CYUSB3014-BZXC [INFINEON]
EZ-USB™ FX3 USB 5 Gbps外设控制器;型号: | CYUSB3014-BZXC |
厂家: | Infineon |
描述: | EZ-USB™ FX3 USB 5 Gbps外设控制器 时钟 数据传输 控制器 外围集成电路 |
文件: | 总82页 (文件大小:719K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CYUSB301X, CYUSB201X
EZ-USB FX3
SuperSpeed USB Controller
Features
• Universal serial bus (USB) integration
- USB 3.2, Gen 1 and USB 2.0 peripherals compliant with USB 3.2 Specification Revision 1.0 (TID # 340800007)
- 5-Gbps SuperSpeed PHY compliant with USB 3.2 Gen 1
- High-speed On-The-Go (HS-OTG) host and peripheral compliant with OTG Supplement Version 2.0
- Thirty-two physical endpoints
• General programmable interface (GPIF™ II)
- Programmable 100-MHz GPIF II enables connectivity to a wide range of external devices
- 8-, 16-, 24-, and 32-bit data bus
- Up to 16 configurable control signals
• Fully accessible 32-bit CPU
- ARM926EJ core with 200-MHz operation
- 512-KB or 256-KB embedded SRAM
• Additional connectivity to the following peripherals
- SPI master at up to 33 MHz
- UART support of up to 4 Mbps
- I2C master controller at 1 MHz
- I2S master (transmitter only) at sampling frequencies of 8 kHz, 16 kHz, 32 kHz, 44.1 kHz, 48 kHz, 96 kHz and
192 kHz
• Selectable clock input frequencies
- 19.2, 26, 38.4, and 52 MHz
- 19.2-MHz crystal input support
• Ultra low-power in core power-down mode
- Less than 60 µA with VBATT on and 20 µA with VBATT off
• Independent power domains for core and I/O
- Core operation at 1.2 V
- I2S, UART, and SPI operation at 1.8 to 3.3 V
- I2C operation at 1.2 V to 3.3 V
• Package options
- 121-ball, 10- × 10-mm, 0.8-mm pitch Pb-free ball grid array (BGA)
- See Table 24 for details on the seven FX3 variants
• EZ-USB® software development kit (SDK) for code development of firmware and PC Applications
- Includes RTOS Framework (using ThreadX Version 5)
- Firmware examples covering all I/O modules
- Visual Studio host examples using C++ and C#
• SuperSpeed explorer board available for rapid prototyping
- Several accessory boards also available:
• Adapter boards for Xilinx/Altera FPGA development
• Adapter board for video development
• CPLD board for concept testing and initial development
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
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EZ-USB FX3
SuperSpeed USB Controller
Applications
Applications
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Digital video camcorders
Digital still cameras
Printers
Scanners
Video capture cards
Test and measurement equipment
Surveillance cameras
Personal navigation devices
Medical imaging devices
Video IP phones
Portable media players
Industrial cameras
Data loggers
Data acquisition
High-performance human interface devices (gesture recognition)
Functional description
For a complete list of related documentation, click here.
Errata: For information on silicon errata, see “Errata” on page 70. Details include trigger conditions, devices affected, and proposed workaround.
Datasheet
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EZ-USB FX3
SuperSpeed USB Controller
Logic block diagram
Logic block diagram
Datasheet
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EZ-USB FX3
SuperSpeed USB Controller
More information
1
More information
Infineon provides a wealth of data at www.infineon.com to help you to select the right USB SuperSpeed device
for your design, and to help you to quickly and effectively integrate the device into your design.
• Overview: USB Portfolio, USB Roadmap
• USB 3.0 Product Selectors: FX3, FX3S, CX3, HX3, SX3
• Application notes: Infineon offers a large number of USB application notes covering a broad range of topics,
from basic to advanced level. Recommended application notes for getting started with FX3 are:
- AN75705 - Getting Started with EZ-USB FX3
- AN76405 - EZ-USB FX3 Boot Options
- AN70707 - EZ-USB FX3/FX3S/SX3 Hardware Design Guidelines and Schematic Checklist
- AN65974 - Designing with the EZ-USB FX3 Slave FIFO Interface
- AN75779 - How to Implement an Image Sensor Interface with EZ-USB FX3 in a USB Video Class (UVC)
Framework
- AN86947 - Optimizing USB 3.0 Throughput with EZ-USB FX3
- AN84868 - Configuring an FPGA over USB Using Cypress EZ-USB FX3
- AN68829 - Slave FIFO Interface for EZ-USB FX3: 5-Bit Address Mode
- AN73609 - EZ-USB FX2LP/ FX3 Developing Bulk-Loop Example on Linux
- AN77960 - Introduction to EZ-USB FX3 High-Speed USB Host Controller
- AN76348 - Differences in Implementation of EZ-USB FX2LP and EZ-USB FX3 Applications
- AN89661 - USB RAID 1 Disk Design Using EZ-USB FX3S
• Code Examples:
- USB Hi-Speed
- USB Full-Speed
- USB SuperSpeed
• Knowledge Base Articles (KBA):
- FX3 FAQs - KBA224051
- Trouble Shooting Guide for the FX3/FX3S/CX3 Enumeration - KBA222372
- EZ-USB™ FX3 Explorer kit as 16-channel 100 MHz logic analyzer with sigrok PulseView - KBA233652
- EZ-USB™ FX3-based HDMI-to-USB3 Vision solution demo kit - KBA235421
- EZ-USB™ FX3: Open source KiCad based schematic and BOM for FX3 camera kit - KBA236085
• Technical Reference Manual (TRM):
- EZ-USB FX3 Technical Reference Manual
• Development Kits:
- CYUSB3KIT-003, EZ-USB FX3 SuperSpeed Explorer Kit
• Models: IBIS
Datasheet
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EZ-USB FX3
SuperSpeed USB Controller
More information
1.1
EZ-USB FX3 Software Development Kit
Cypress delivers the complete software and firmware stack for FX3, in order to easily integrate SuperSpeed USB
into any embedded application. The Software Development Kit (SDK) comes with tools, drivers and application
examples, which help accelerate application development.
1.2
GPIF™ II Designer
The GPIF II Designer is a graphical software that allows designers to configure the GPIF II interface of the EZ-USB
FX3 USB 3.0 Device Controller.
The tool allows users the ability to select from one of five Cypress supplied interfaces, or choose to create their
own GPIF II interface from scratch. Cypress has supplied industry standard interfaces such as Asynchronous and
Synchronous Slave FIFO, Asynchronous and Synchronous SRAM, and Asynchronous SRAM. Designers who
already have one of these pre-defined interfaces in their system can simply select the interface of choice, choose
from a set of standard parameters such as bus width (x8, 16, x32) endianess, clock settings, and compile the
interface. The tool has a streamlined three step GPIF interface development process for users who need a
customized interface. Users are able to first select their pin configuration and standard parameters. Secondly,
they can design a virtual state machine using configurable actions. Finally, users can view output timing to verify
that it matches the expected timing. Once the three step process is complete, the interface can be compiled and
integrated with FX3.
Datasheet
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EZ-USB FX3
SuperSpeed USB Controller
Table of contents
Table of contents
Features ...........................................................................................................................................1
Applications......................................................................................................................................2
Functional description.......................................................................................................................2
Logic block diagram ..........................................................................................................................3
1 More information............................................................................................................................4
1.1 EZ-USB FX3 Software Development Kit .................................................................................................................5
1.2 GPIF™ II Designer.....................................................................................................................................................5
Table of contents...............................................................................................................................6
2 Functional overview .......................................................................................................................8
2.1 Application examples .............................................................................................................................................8
3 USB interface ...............................................................................................................................10
3.1 OTG ........................................................................................................................................................................10
3.1.1 OTG connectivity................................................................................................................................................10
3.2 ReNumeration.......................................................................................................................................................11
3.3 VBUS overvoltage protection...............................................................................................................................11
3.4 Carkit UART Mode .................................................................................................................................................11
4 GPIF II ..........................................................................................................................................12
4.0.1 Slave FIFO interface ...........................................................................................................................................12
5 CPU .............................................................................................................................................13
6 JTAG interface ..............................................................................................................................14
7 Other interfaces............................................................................................................................15
7.1 SPI interface ..........................................................................................................................................................15
7.2 UART interface ......................................................................................................................................................15
7.3 I2C interface ..........................................................................................................................................................15
7.4 I2S interface ..........................................................................................................................................................16
8 Boot options.................................................................................................................................17
9 Reset ...........................................................................................................................................18
9.1 Hard reset..............................................................................................................................................................18
9.2 Soft reset ...............................................................................................................................................................18
10 Clocking .....................................................................................................................................19
10.1 32-kHz watchdog timer clock input ...................................................................................................................20
11 Power ........................................................................................................................................21
11.1 Power Modes.......................................................................................................................................................21
12 Digital I/Os .................................................................................................................................24
13 GPIOs.........................................................................................................................................25
14 System-level ESD ........................................................................................................................26
15 Pin configurations.......................................................................................................................27
16 Pin description ...........................................................................................................................28
17 Electrical specifications...............................................................................................................32
17.1 Absolute maximum ratings ................................................................................................................................32
17.2 Operating conditions..........................................................................................................................................32
17.3 DC specifications.................................................................................................................................................33
18 Thermal characteristics...............................................................................................................36
19 AC timing parameters..................................................................................................................37
19.1 GPIF II lines AC characteristics at 100 MHz ........................................................................................................37
19.2 GPIF II PCLK jitter characteristics.......................................................................................................................37
19.3 GPIF II timing.......................................................................................................................................................38
19.4 Slave FIFO interface ............................................................................................................................................41
19.4.1 Synchronous Slave FIFO Read sequence description....................................................................................41
19.4.2 Synchronous Slave FIFO Write sequence description ...................................................................................43
19.4.3 Asynchronous Slave FIFO Read sequence description ..................................................................................46
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EZ-USB FX3
SuperSpeed USB Controller
Table of contents
19.4.4 Asynchronous Slave FIFO Write sequence description..................................................................................47
19.5 Host Processor Interface (P-Port) timing...........................................................................................................50
19.5.1 Asynchronous SRAM timing.............................................................................................................................50
19.5.2 ADMux timing for Asynchronous Access .........................................................................................................54
19.5.3 Synchronous ADMux timing ............................................................................................................................56
19.6 Serial Peripherals timing ....................................................................................................................................59
19.6.1 I2C timing .........................................................................................................................................................59
19.6.2 I2S timing diagram...........................................................................................................................................62
19.6.3 SPI timing specification...................................................................................................................................63
19.7 Reset sequence ...................................................................................................................................................65
20 Package diagram ........................................................................................................................66
21 Ordering information ..................................................................................................................67
21.1 Ordering code definitions...................................................................................................................................67
22 Acronyms ...................................................................................................................................68
23 Document conventions................................................................................................................69
23.1 Units of measure .................................................................................................................................................69
24 Errata ........................................................................................................................................70
24.1 Qualification status.............................................................................................................................................70
24.2 Errata summary ..................................................................................................................................................70
Revision history ..............................................................................................................................75
Datasheet
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EZ-USB FX3
SuperSpeed USB Controller
Functional overview
2
Functional overview
Infineon’s EZ-USB FX3 is a SuperSpeed peripheral controller, providing integrated and flexible features.
FX3 has a fully configurable, parallel, general programmable interface called GPIF II, which can connect to any
processor, ASIC, or FPGA. GPIF II is an enhanced version of the GPIF in FX2LP, Infineon’s flagship USB 2.0 product.
It provides easy and glueless connectivity to popular interfaces, such as asynchronous SRAM, asynchronous and
synchronous address data multiplexed interfaces, and parallel ATA.
FX3 has integrated the USB 3.2 Gen 1 and USB 2.0 physical layers (PHYs) along with a 32-bit ARM926EJ-S
microprocessor for powerful data processing and for building custom applications. It implements an architecture
that enables 375-MBps data transfer from GPIF II to the USB interface.
An integrated USB 2.0 OTG controller enables applications in which FX3 may serve dual roles; for example,
EZ-USB FX3 may function as an OTG Host to MSC as well as HID-class devices.
FX3 contains 512 KB or 256 KB of on-chip SRAM (see “Ordering information” on page 67) for code and data.
EZ-USB FX3 also provides interfaces to connect to serial peripherals such as UART, SPI, I2C, and I2S.
FX3 comes with application development tools. The software development kit comes with firmware and host
application examples for accelerating time to market.
FX3 complies with the USB 3.2, Gen 1.0 specification and is also backward compatible with USB 2.0. It also
complies with USB 2.0 OTG Specification v2.0.
2.1
Application examples
In a typical application (see Figure 1), the FX3 functions as the main processor running the application software
that connects external hardware to the SuperSpeed USB connection. Additionally, FX3 can function as a
coprocessor connecting via the GPIF II interface to an application processor (see Figure 2) and operates as a
subsystem providing SuperSpeed USB connectivity to the application processor.
Crystal*
Clock
External Slave
Device
(e.g. Image
Sensor)
EZ-USB™ FX3
GPIF II
USB
USB Host
I2C
*A clock input may be provided on the CLKIN
pin instead of a crystal input
EEPROM
Figure 1
EZ-USB FX3 as main processor
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EZ-USB FX3
SuperSpeed USB Controller
Functional overview
Crystal*
Clock
External Master
(e.g. MCU/CPU/
FPGA/ASIC)
EZ-USB™ FX3
GPIF II
USB
USB Host
I2C
* A clock input may be provided on the
CLKIN pin instead of a crystal input
EEPROM
Figure 2
EZ-USB FX3 as a coprocessor
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EZ-USB FX3
SuperSpeed USB Controller
USB interface
3
USB interface
FX3 complies with the following specifications and supports the following features:
• Supports USB peripheral functionality compliant with USB 3.2 Specification Revision 1.0 and is also backward
compatible with the USB 2.0 Specification.
• FX3 Hi-Speed parts (CYUSB201X) only support USB 2.0.
• Complies with OTG Supplement Revision 2.0. It supports high-speed, full-speed, and low-speed OTG dual-role
device capability. As a peripheral, FX3 is capable of SuperSpeed, high-speed, and full-speed. As a host, it is
capable of high-speed, full-speed, and low-speed.
• Supports Carkit Pass-Through UART functionality on USB D+/D– lines based on the CEA-936A specification.
• Supports 16 IN and 16 OUT endpoints.
• Supports USB Attached SCSI (UAS) device-class to optimize mass-storage access performance.
• As a USB peripheral, application examples show that the FX3 supports UAS, USB Video Class (UVC), and Mass
Storage Class (MSC) USB peripheral classes. All other device classes can be supported by customer firmware; a
template example is provided as a starting point.
• As an OTG host, application examples show that FX3 supports MSC and HID device classes.
Note When the USB port is not in use, disable the PHY and transceiver to save power.
3.1
OTG
FX3 is compliant with the OTG Specification Revision 2.0. In OTG mode, FX3 supports both A and B device modes
and supports Control, Interrupt, Bulk, and Isochronous data transfers.
FX3 requires an external charge pump (either standalone or integrated into a PMIC) to power VBUS in the OTG
A-device mode.
The Target Peripheral List for OTG host implementation consists of MSC- and HID-class devices.
FX3 does not support Attach Detection Protocol (ADP).
3.1.1
OTG connectivity
In OTG mode, FX3 can be configured to be an A, B, or dual-role device. It can connect to the following:
• ACA device
• Targeted USB peripheral
• SRP-capable USB peripheral
• HNP-capable USB peripheral
• OTG host
• HNP-capable host
• OTG device
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EZ-USB FX3
SuperSpeed USB Controller
USB interface
3.2
ReNumeration
Because of FX3’s soft configuration, one chip can take on the identities of multiple distinct USB devices.
When first plugged into USB, FX3 enumerates automatically with the Infineon Vendor ID (0x04B4) and downloads
firmware and USB descriptors over the USB interface. The downloaded firmware executes an electrical
disconnect and connect. FX3 enumerates again, this time as a device defined by the downloaded information.
This patented two-step process, called ReNumeration, happens instantly when the device is plugged in.
3.3
VBUS overvoltage protection
The maximum input voltage on FX3’s VBUS pin is 6 V. A charger can supply up to 9 V on VBUS. In this case, an
external overvoltage protection (OVP) device is required to protect FX3 from damage on VBUS. Figure 3 shows
the system application diagram with an OVP device connected on VBUS. Refer to Table 8 for the operating range
of VBUS and VBATT.
POWER SUBSYSTEM
EZ-USB FX3
VBUS
1
OVP device
OTG_ID
2
3
4
5
6
7
8
9
SSRX-
SSRX+
SSTX-
SSTX+
D-
D+
GND
Figure 3
System diagram with OVP device for VBUS
3.4
Carkit UART Mode
The USB interface supports the Carkit UART mode (UART over D+/D–) for non-USB serial data transfer. This mode
is based on the CEA-936A specification.
In the Carkit UART mode, the output signaling voltage is 3.3 V. When configured for the Carkit UART mode, TXD
of UART (output) is mapped to the D– line, and RXD of UART (input) is mapped to the D+ line.
In the Carkit UART mode, FX3 disables the USB transceiver and D+ and D– pins serve as pass-through pins to
connect to the UART of the host processor. The Carkit UART signals may be routed to the GPIF II interface or to
GPIO[48] and GPIO[49], as shown in Figure 4.
In this mode, FX3 supports a rate of up to 9600 bps.
Carkit UART Pass-through
UART_TXD
UART_RXD
TXD
RXD
(DP)
RXD
(
)
Carkit UART Pass-through
Interface on GPIF II
DP
USB PHY
DM
GPIO[48]
TXD(DM)
(UART_TX)
Carkit UART Pass-through
Interface on GPIOs
GPIO[49]
(UART_RX)
Figure 4
Carkit UART Pass-through block diagram
Datasheet
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EZ-USB FX3
SuperSpeed USB Controller
GPIF II
4
GPIF II
The high-performance GPIF II interface enables functionality similar to, but more advanced than, FX2LP’s GPIF
and Slave FIFO interfaces.
The GPIF II is a programmable state machine that enables a flexible interface that may function either as a master
or slave in industry-standard or proprietary interfaces. Both parallel and serial interfaces may be implemented
with GPIF II.
Here is a list of GPIF II features:
• Functions as master or slave
• Provides 256 firmware programmable states
• Supports 8-bit, 16-bit, 24-bit, and 32-bit parallel data bus
• Enables interface frequencies up to 100 MHz
• Supports 14 configurable control pins when a 32- bit data bus is used. All control pins can be either input/output
or bidirectional.
• Supports 16 configurable control pins when a 16/8 data bus is used. All control pins can be either input/output
or bi-directional.
GPIF II state transitions are based on control input signals. The control output signals are driven as a result of the
GPIF II state transitions. The INT# output signal can be controlled by GPIF II. Refer to the GPIFII Designer tool. The
GPIF II state machine’s behavior is defined by a GPIF II descriptor. The GPIF II descriptor is designed such that the
required interface specifications are met. 8 KB of memory (separate from the 256/512 KB of embedded SRAM) is
dedicated to the GPIF II waveform where the GPIF II descriptor is stored in a specific format.
Infineon’s GPIFII Designer Tool enables fast development of GPIF II descriptors and includes examples for
common interfaces.
Example implementations of GPIF II are the asynchronous slave FIFO and synchronous slave FIFO interfaces.
4.0.1
Slave FIFO interface
The Slave FIFO interface signals are shown in Figure 5. This interface allows an external processor to directly
access up to four buffers internal to FX3. Further details of the Slave FIFO interface are described on page 41.
Note Access to all 32 buffers is also supported over the slave FIFO interface. For details, contact Infineon
applications support.
SLCS#
PKTEND
FLAGB
FLAGA
External Master
(For example,
A[1:0]
D[31:0]
MCU/CPU/
EZ-USB FX3
FPGA/ASIC)
SLWR#
SLRD#
SLOE#
Note: Multiple Flags may be configured.
Figure 5
Slave FIFO interface
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EZ-USB FX3
SuperSpeed USB Controller
CPU
5
CPU
FX3 has an on-chip 32-bit, 200-MHz ARM926EJ-S core CPU. The core has direct access to 16 KB of instruction
tightly coupled memory (TCM) and 8 KB of Data TCM. The ARM926EJ-S core provides a JTAG interface for
firmware debugging.
FX3 offers the following advantages:
• Integrates 256/512 KB of embedded SRAM for code and data and 8 KB of instruction cache and data cache.
• Implements efficient and flexible DMA connectivity between the various peripherals (such as, USB, GPIF II, I2S,
SPI, UART, I2C), requiring firmware only to configure data accesses between peripherals, which are then
managed by the DMA fabric.
• Allows easy application development using industry-standard development tools for ARM926EJ-S.
Examples of the FX3 firmware are available with the Infineon EZ-USB FX3 Development Kit.
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EZ-USB FX3
SuperSpeed USB Controller
JTAG interface
6
JTAG interface
FX3’s JTAG interface has a standard five-pin interface to connect to a JTAG debugger in order to debug firmware
through the CPU-core’s on-chip-debug circuitry.
Industry-standard debugging tools for the ARM926EJ-S core can be used for the FX3 application development.
For ARM JTAG access, TCK frequency should not be more than 1/6 of the CPU clock frequency.
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EZ-USB FX3
SuperSpeed USB Controller
Other interfaces
7
Other interfaces
FX3 supports the following serial peripherals:
• SPI
• UART
• I2C
• I2S
The SPI, UART, and I2S interfaces are multiplexed on the serial peripheral port.
Table 7 shows details of how these interfaces are multiplexed. Note that when GPIF II is configured for a 32-bit
data bus width (CYUSB3012 and CYUSB3014), then the SPI interface is not available.
7.1
SPI interface
FX3 supports an SPI Master interface on the Serial Peripherals port. The maximum operation frequency is 33 MHz.
The SPI controller supports four modes of SPI communication (see “SPI timing specification” on page 63 for
details on the modes) with the Start-Stop clock. This controller is a single-master controller with a single
automated SSN control. It supports transaction sizes ranging from four bits to 32 bits.
7.2
UART interface
The UART interface of FX3 supports full-duplex communication. It includes the signals noted in Table 1.
Table 1
Signal
UART interface signals
Description
TX
RX
CTS
RTS
Output signal
Input signal
Flow control
Flow control
The UART is capable of generating a range of baud rates, from 300 bps to 4608 Kbps, selectable by the firmware.
If flow control is enabled, then FX3’s UART only transmits data when the CTS input is asserted. In addition to this,
FX3’s UART asserts the RTS output signal, when it is ready to receive data.
7.3
I2C interface
FX3’s I2C interface is compatible with the I2C Bus Specification Revision 3. This I2C interface is capable of
operating only as I2C master; therefore, it may be used to communicate with other I2C slave devices. For example,
FX3 may boot from an EEPROM connected to the I2C interface, as a selectable boot option.
FX3’s I2C Master Controller also supports multi-master mode functionality.
The power supply for the I2C interface is VIO5, which is a separate power domain from the other serial peripherals.
This gives the I2C interface the flexibility to operate at a different voltage than the other serial interfaces.
The I2C controller supports bus frequencies of 100 kHz, 400 kHz, and 1 MHz. When VIO5 is 1.2 V, the maximum
operating frequency supported is 100 kHz. When VIO5 is 1.8 V, 2.5 V, or 3.3 V, the operating frequencies supported
are 400 kHz and 1 MHz. The I2C controller supports clock-stretching to enable slower devices to exercise flow
control.
The I2C interface’s SCL and SDA signals require external pull-up resistors. The pull-up resistors must be
connected to VIO5.
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EZ-USB FX3
SuperSpeed USB Controller
Other interfaces
7.4
I2S interface
FX3 has an I2S port to support external audio codec devices. FX3 functions as I2S Master as transmitter only. The
I2S interface consists of four signals: clock line (I2S_CLK), serial data line (I2S_SD), word select line (I2S_WS), and
master system clock (I2S_MCLK). FX3 can generate the system clock as an output on I2S_MCLK or accept an
external system clock input on I2S_MCLK.
The sampling frequencies supported by the I2S interface are 8 kHz, 16 kHz, 32 kHz, 44.1 kHz, 48 kHz, 96 kHz and
192 kHz.
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EZ-USB FX3
SuperSpeed USB Controller
Boot options
8
Boot options
FX3 can load boot images from various sources, selected by the configuration of the PMODE pins. Following are
the FX3 boot options:
• Boot from USB
• Boot from I2C
• Boot from SPI
- Infineon SPI Flash parts supported are S25FS064S (64-Mbit), S25FS128S (128-Mbit) and S25LFL064L (64-Mbit).
- W25Q32FW (32-Mbit) is also supported.
• Boot from GPIF II Sync ADMux mode
Table 2
FX3 booting options
PMODE[2:0][1]
Boot from
F00
F11
F1F
1FF
0F1
Sync ADMux (16-bit)
USB boot
I2C, On failure, USB boot is enabled
I2C only
SPI, On failure, USB boot is enabled
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EZ-USB FX3
SuperSpeed USB Controller
Reset
9
Reset
9.1
Hard reset
A hard reset is initiated by asserting the Reset# pin on FX3. The specific reset sequence and timing requirements
are detailed in Figure 29 and Table 23. All I/Os are tristated during a hard reset. Note however, that the on-chip
bootloader has control after a hard reset and it will configure I/O signals depending on the selected boot mode;
see AN76405 - EZ-USB® FX3™ Boot Options for more details.
9.2
Soft reset
In a soft reset, the processor sets the appropriate bits in the PP_INIT control register. There are two types of soft
reset:
• CPU reset – The CPU program counter is reset. Firmware does not need to be reloaded following a CPU reset.
• Whole device reset – This reset is identical to hard reset.
• The firmware must be reloaded following a whole device reset.
Note
1. F indicates floating.
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EZ-USB FX3
SuperSpeed USB Controller
Clocking
10
Clocking
FX3 allows either a crystal to be connected between the XTALIN and XTALOUT pins or an external clock to be
connected at the CLKIN pin. The XTALIN, XTALOUT, CLKIN, and CLKIN_32 pins can be left unconnected if they are
not used.
Crystal frequency supported is 19.2 MHz, while the external clock frequencies supported are 19.2, 26, 38.4, and
52 MHz.
FX3 has an on-chip oscillator circuit that uses an external 19.2-MHz (±100 ppm) crystal (when the crystal option
is used). An appropriate load capacitance is required with a crystal. Refer to the specification of the crystal used
to determine the appropriate load capacitance. The FSLC[2:0] pins must be configured appropriately to select
the crystal- or clock-frequency option. The configuration options are shown in Table 3.
Clock inputs to FX3 must meet the phase noise and jitter requirements specified in Table 4.
The input clock frequency is independent of the clock and data rate of the FX3 core or any of the device interfaces.
The internal PLL applies the appropriate clock multiply option depending on the input frequency.
Table 3
FSLC[2]
Crystal/clock frequency selection
FSLC[1]
FSLC[0]
Crystal/clock frequency
19.2-MHz crystal
0
1
1
1
1
0
0
0
1
1
0
0
1
0
1
19.2-MHz input CLK
26-MHz input CLK
38.4-MHz input CLK
52-MHz input CLK
Table 4
FX3 input clock specifications
Parameter Description
Specification
Units
Min
–
–
–
–
Max
–75
100-Hz offset
1-kHz offset
10-kHz offset
100-kHz offset
1-MHz offset
–104
–120
–128
–130
Phase noise
dB
–
Maximum frequency
deviation
–
–
150
ppm
Duty cycle
Overshoot
Undershoot
Rise time/fall time
–
–
–
–
30
–
–
70
3
–3
3
%
–
ns
Datasheet
19
001-52136 Rev. *Z
2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
Clocking
10.1
32-kHz watchdog timer clock input
FX3 includes a watchdog timer. The watchdog timer can be used to interrupt the ARM926EJ-S core, automatically
wake up the FX3 in Standby mode, and reset the ARM926EJ-S core. The watchdog timer runs a 32-kHz clock,
which may be optionally supplied from an external source on a dedicated FX3 pin.
The firmware can disable the watchdog timer. Requirements for the optional 32-kHz clock input are listed in
Table 5.
Table 5
32-kHz clock input requirements
Parameter
Min
40
–
Max
60
±200
200
Units
%
ppm
ns
Duty cycle
Frequency deviation
Rise time/fall time
–
Datasheet
20
001-52136 Rev. *Z
2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
Power
11
Power
FX3 has the following power supply domains:
• IO_VDDQ: This is a group of independent supply domains for digital I/Os. The voltage level on these supplies is
1.8 V to 3.3 V. FX3 provides six independent supply domains for digital I/Os listed as follows (see Table 7 for
details on each of the power domain signals):
- VIO1: GPIF II I/O
- VIO2: IO2
- VIO3: IO3
- VIO4: UART-/SPI/I2S
- VIO5: I2C and JTAG (supports 1.2 V to 3.3 V)
- CVDDQ: This is the supply voltage for clock and reset I/O. It should be either 1.8 V or 3.3 V based on the voltage
level of the CLKIN signal.
- VDD: This is the supply voltage for the logic core. The nominal supply-voltage level is 1.2 V. This supplies the
core logic circuits. The same supply must also be used for the following:
• AVDD: This is the 1.2-V supply for the PLL, crystal oscillator, and other core analog circuits.
• U3TXVDDQ/U3RXVDDQ: These are the 1.2-V supply voltages for the USB 3.0 interface.
• VBATT/VBUS: This is the 3.2-V to 6-V battery power supply for the USB I/O and analog circuits. This supply powers
the USB transceiver through FX3’s internal voltage regulator. VBATT is internally regulated to 3.3 V.
Note:
No specific power-up sequence for FX3 power domains. Minimum power on reset time of 1 ms should be met and
the power domains must be stable for FX3 operation.
11.1
Power Modes
FX3 supports the following power modes:
• Normal mode: This is the full-functional operating mode. The internal CPU clock and the internal PLLs are
enabled in this mode.
- Normal operating power consumption does not exceed the sum of ICC Core max and ICC USB max (see Table 8
for current consumption specifications).
- The I/O power supplies VIO2, VIO3, VIO4, and VIO5 can be turned off when the corresponding interface is not
in use. VIO1 cannot be turned off at any time if the GPIF II interface is used in the application.
• Low-power modes (see Table 6):
- Suspend mode with USB 3.0 PHY enabled (L1)
- Suspend mode with USB 3.0 PHY disabled (L2)
- Standby mode (L3)
- Core power-down mode (L4)
Datasheet
21
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2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
Power
Table 6
Entry and Exit methods for Low-Power Modes
Low-Power
Characteristics
Methods of Entry
Methods of Exit
Mode
• The power consumption in this mode
does not exceed ISB1
• Firmware executing on ARM926EJ-S core • D+ transitioning to low or
can put FX3 into suspend mode. For
example, on USB suspend condition,
firmware may decide to put FX3 into
suspend mode
high
• USB 3.0 PHY is enabled and is in U3 mode
(one of the suspend modes defined by
the USB 3.0 specification). Thisone block
alone is operational with its internal
clock while all other clocks are shut down
• D– transitioning to low or
high
• Impedance change on
OTG_ID pin
• External Processor, through the use of
mailbox registers, can put FX3 into
suspend mode
• Resume condition on
SSRX±
• All I/Os maintain their previous state
• Power supply for the wakeup source and
core power must be retained. All other
power domains can be turned on/off
individually
• Detection of VBUS
Suspend Mode
with USB 3.0
PHY Enabled
(L1)
• Level detect on
UART_CTS
(programmable polarity)
• The states of the configuration registers,
buffer memory, and all internal RAM are
maintained
• GPIF II interface assertion
of CTL[0]
• All transactions must be completed
before FX3 enters Suspend mode (state
of outstanding transactions are not
preserved)
• Assertion of RESET#
• The firmware resumes operation from
where it was suspended (except when
woken up by RESET# assertion) because
the program counter does not reset
• The power consumption in this mode
does not exceed ISB2
• Firmware executing on ARM926EJ-S core • D+ transitioning to low or
can put FX3 into suspend mode. For
example, on USB suspend condition,
firmware may decide to put FX3 into
suspend mode
high
• USB 3.0 PHY is disabled and the USB
interface is in suspend mode
• D– transitioning to low or
high
• The clocks are shut off. The PLLs are
disabled
• Impedance change on
OTG_ID pin
• External Processor, through the use of
mailbox registers can put FX3 into
suspend mode
• All I/Os maintain their previous state
• Detection of VBUS
• USB interface maintains the previous
• Level detect on
state
UART_CTS
(programmable polarity)
• Power supply for the wakeup source and
core power must be retained. All other
power domains can be turned on/off
individually
Suspend Mode
with USB 3.0
PHY Disabled
(L2)
• GPIF II interface assertion
of CTL[0]
• Assertion of RESET#
• The states of the configuration registers,
buffer memory and all internal RAM are
maintained
• All transactions must be completed
before FX3 enters Suspend mode (state
of outstanding transactions are not
preserved)
• The firmware resumes operation from
where it was suspended (except when
woken up by RESET# assertion) because
the program counter does not reset
Datasheet
22
001-52136 Rev. *Z
2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
Power
Table 6
Entry and Exit methods for Low-Power Modes (continued)
Low-Power
Characteristics
Methods of Entry
Methods of Exit
Mode
• The power consumption in this mode
does not exceed ISB3
• Firmware executing on ARM926EJ-S core • Detection of VBUS
or external processor configures the
• Level detect on
appropriate register
• All configuration register settings and
UART_CTS
program/data RAM contents are
(Programmable Polarity)
preserved. However, data in the buffers
or other parts of the data path, if any, is
not guaranteed. Therefore, the external
processor should take care that the data
needed is read before putting FX3 into
this Standby Mode
• GPIF II interface assertion
of CTL[0]
• Assertion of RESET#
• The program counter is reset after
waking up from Standby
Standby Mode
(L3)
• GPIO pins maintain their configuration
• Crystal oscillator is turned off
• Internal PLL is turned off
• USB transceiver is turned off
• ARM926EJ-S core is powered down.
Upon wakeup, the core re-starts and runs
the program stored in the program/data
RAM
• Power supply for the wakeup source and
core power must be retained. All other
power domains can be turned on/off
individually
• The power consumption in this mode
does not exceed ISB4
• Turn off VDD
• Reapply VDD
• Assertion of RESET#
• Core power is turned off
Core Power
Down Mode
(L4)
• All buffer memory, configuration
registers, and the program RAM do not
maintain state. After exiting this mode,
reload the firmware
• In this mode, all other power domains
can be turned on/off individually
Note: The power consumption depends on how the FX3 IOs are utilized in the application. Refer to KBA85505 to
estimate the current consumption by different power domains (VIO1–VIO5).
Datasheet
23
001-52136 Rev. *Z
2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
Digital I/Os
12
Digital I/Os
FX3 has internal firmware-controlled pull-up or pull-down resistors on all digital I/O pins. An internal
50-k resistor pulls the pins high, while an internal 10-k resistor pulls the pins low to prevent them from
floating. The I/O pins may have the following states:
• Tristated (High-Z)
• Weak pull-up (via internal 50 k)
• Pull-down (via internal 10 k)
• Hold (I/O hold its value) when in low-power modes
• The JTAG TDI, TMS, and TRST# signals have fixed 50-kinternal pull-ups, and the TCK signal has a fixed 10-k
pull-down resistor.
All unused I/Os should be pulled high by using the internal pull-up resistors. All unused outputs should be left
floating. All I/Os can be driven at full-strength, three-quarter strength, half-strength, or quarter-strength. These
drive strengths are configured separately for each interface.
Datasheet
24
001-52136 Rev. *Z
2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
GPIOs
13
GPIOs
EZ-USB enables a flexible pin configuration both on the GPIF II and the serial peripheral interfaces. Any unused
control pins (except CTL[15]) on the GPIF II interface can be used as GPIOs. Similarly, any unused pins on the serial
peripheral interfaces may be configured as GPIOs. See “Pin configurations” on page 27 for pin configuration
options.
All GPIF II and GPIO pins support an external load of up to 16 pF for every pin.
EMI
FX3 meets EMI requirements outlined by FCC 15B (USA) and EN55022 (Europe) for consumer electronics. FX3 can
tolerate EMI, conducted by the aggressor, outlined by these specifications and continue to function as expected.
Datasheet
25
001-52136 Rev. *Z
2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
System-level ESD
14
System-level ESD
FX3 has built-in ESD protection on the D+, D–, and GND pins on the USB interface. The ESD protection levels
provided on these ports are:
• ±2.2-kV human body model (HBM) based on JESD22-A114 Specification
• ±6-kV contact discharge and ±8-kV air gap discharge based on IEC61000-4-2 level 3A
• ± 8-kV Contact Discharge and ±15-kV Air Gap Discharge based on IEC61000-4-2 level 4C.
This protection ensures the device continues to function after ESD events up to the levels stated in this section.
The SSRX+, SSRX–, SSTX+, and SSTX– pins only have up to ±2.2-kV HBM internal ESD protection.
Datasheet
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2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
Pin configurations
15
Pin configurations
1
2
3
4
5
6
7
8
9
10
11
U3VSSQ
U3RXVDDQ
SSRXM
SSRXP
SSTXP
SSTXM
AVDD
VSS
DP
DM
NC
A
B
C
D
E
F
G
H
J
VIO4
GPIO[54]
GPIO[50]
GPIO[47]
VIO2
FSLC[0]
GPIO[55]
GPIO[51]
VSS
R_USB3
VDD
FSLC[1]
GPIO[57]
GPIO[53]
GPIO[49]
GPIO[41]
GPIO[30]
GPIO[31]
GPIO[34]
VSS
U3TXVDDQ
RESET#
CVDDQ
XTALIN
CLKIN_32
FSLC[2]
TCK
AVSS
XTALOUT
CLKIN
VSS
R_USB2
VSS
VSS
VDD
TDO
TRST#
VIO5
OTG_ID
GPIO[52]
VIO3
GPIO[56]
GPIO[48]
GPIO[46]
GPIO[25]
GPIO[29]
GPIO[28]
GPIO[27]
VDD
I2C_GPIO[58] I2C_GPIO[59]
NC
TDI
TMS
VDD
GPIO[1]
GPIO[4]
GPIO[7]
GPIO[9]
GPIO[13]
VIO1
VBATT
GPIO[0]
GPIO[3]
GPIO[6]
GPIO[8]
GPIO[12]
GPIO[11]
VBUS
VDD
GPIO[45]
GPIO[42]
GPIO[39]
GPIO[36]
GPIO[33]
VSS
GPIO[44]
GPIO[43]
GPIO[40]
GPIO[37]
VSS
GPIO[2]
GPIO[21]
GPIO[20]
GPIO[19]
GPIO[18]
VDD
GPIO[5]
GPIO[15]
GPIO[24]
GPIO[14]
GPIO[17]
INT#
VSS
GPIO[22]
GPIO[26]
GPIO[16]
GPIO[23]
VSS
VSS
VDD
VIO1
VDD
GPIO[38]
GPIO[35]
VSS
GPIO[10]
VSS
K
L
VSS
GPIO[32]
Figure 6
FX3 121-ball BGA ball map (Top view)
1
2
3
4
5
6
7
8
9
10
11
VSS
VIO4
VDD
NC
NC
NC
NC
AVDD
VSS
DP
DM
NC
A
B
C
D
E
F
G
H
J
FSLC[0]
GPIO[55]
GPIO[51]
VSS
NC
FSLC[1]
GPIO[57]
GPIO[53]
GPIO[49]
GPIO[41]
GPIO[30]
GPIO[31]
GPIO[34]
VSS
VDD
CVDDQ
XTALIN
CLKIN_32
FSLC[2]
TCK
AVSS
XTALOUT
CLKIN
VSS
R_USB2
VSS
VSS
VDD
TDO
TRST#
VIO5
GPIO[54]
GPIO[50]
GPIO[47]
VIO2
VDD
RESET#
GPIO[56]
GPIO[48]
GPIO[46]
GPIO[25]
GPIO[29]
GPIO[28]
GPIO[27]
VDD
OTG_ID
GPIO[52]
VIO3
I2C_GPIO[58] I2C_GPIO[59]
NC
TDI
TMS
VDD
GPIO[1]
GPIO[4]
GPIO[7]
GPIO[9]
GPIO[13]
VIO1
VBATT
GPIO[0]
GPIO[3]
GPIO[6]
GPIO[8]
GPIO[12]
GPIO[11]
VBUS
VDD
GPIO[45]
GPIO[42]
GPIO[39]
GPIO[36]
GPIO[33]
VSS
GPIO[44]
GPIO[43]
GPIO[40]
GPIO[37]
VSS
GPIO[2]
GPIO[21]
GPIO[20]
GPIO[19]
GPIO[18]
VDD
GPIO[5]
GPIO[15]
GPIO[24]
GPIO[14]
GPIO[17]
INT#
VSS
GPIO[22]
GPIO[26]
GPIO[16]
GPIO[23]
VSS
VSS
VDD
VIO1
VDD
GPIO[38]
GPIO[35]
VSS
GPIO[10]
VSS
K
L
VSS
GPIO[32]
Figure 7
FX3 Hi-Speed 121-ball BGA ball map (Top view)
Note: A2 and C3 need not be connected for FX3 Hi-Speed part.
Datasheet
27
001-52136 Rev. *Z
2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
Pin description
16
Pin description
Table 7
CYUSB3011, CYUSB3012, CYUSB3013, CYUSB3014 and CYUSB2014 pin list
BGA
Power domain
I/O
Name
Description
GPIF II interface
DQ[0]
Slave FIFO interface [2]
DQ[0]
F10
F9
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[7]
GPIO[8]
GPIO[9]
GPIO[10]
GPIO[11]
GPIO[12]
GPIO[13]
GPIO[14]
GPIO[15]
GPIO[16]
GPIO[17]
GPIO[18]
GPIO[19]
GPIO[20]
GPIO[21]
GPIO[22]
GPIO[23]
GPIO[24]
GPIO[25]
GPIO[26]
GPIO[27]
GPIO[28]
GPIO[29]
GPIO[30]
GPIO[31]
GPIO[32]
INT#
DQ[1]
DQ[1]
F7
DQ[2]
DQ[2]
G10
G9
F8
DQ[3]
DQ[3]
DQ[4]
DQ[4]
DQ[5]
DQ[5]
H10
H9
J10
J9
DQ[6]
DQ[6]
DQ[7]
DQ[7]
DQ[8]/A0 [3]
DQ[9]/A1 [3]
DQ[10]
DQ[8]/A0 [3]
DQ[9]/A1 [3]
DQ[10]
DQ[11]
DQ[12]
DQ[13]
DQ[14] [4]
DQ[15] [4]
CLK
K11
L10
K10
K9
J8
DQ[11]
DQ[12]
DQ[13]
DQ[14] [4]
DQ[15] [4]
PCLK
G8
J6
K8
K7
J7
CTL[0]
SLCS#
CTL[1]
SLWR#
SLOE#
CTL[2]
H7
G7
G6
K6
H8
G5
H6
K5
J5
CTL[3]
SLRD#
CTL[4]
FLAGA
CTL[5]
FLAGB
CTL[6]
GPIO
CTL[7]
PKTEND#
GPIO
CTL[8]
CTL[9]
GPIO
CTL[10]
CTL[11]
CTL[12]
PMODE[0]
PMODE[1]
PMODE[2]
INT#/CTL[15]
GPIO
A1
H5
G4
H4
L4
A0
PMODE[0]
PMODE[1]
PMODE[2]
CTL[15]
L8
Notes
2. Slave FIFO is an example configuration of GPIF II Interface. The Slave FIFO control signal assignments can be
modified using GPIF-II designer tool.
3. For 8-bit data bus configuration, GPIO[8] and GPIO[9] act as address lines.
4. GPIF II can also be configured as a serial interface. The DQ[15] pin becomes a serial output and DQ[14]
becomes a serial input in this mode.
Datasheet
28
001-52136 Rev. *Z
2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
Pin description
Table 7
CYUSB3011, CYUSB3012, CYUSB3013, CYUSB3014 and CYUSB2014 pin list (continued)
BGA
Power domain
I/O
Name
Description
CYUSB3014
and
CYUSB3011, CYUSB3012, CYUSB3013, CYUSB3014 and
CYUSB2014
CYUSB2014
16-bit
16-bitDataBus
+ UART + SPI +
I2S
16-bit
16-bit
32-bit
Data Bus +
UART +
GPIO
GPIO
only
Data Bus + Data Bus +
SPI + GPIO I2S + GPIO
Data Bus
K2
J4
K1
J2
J3
J1
H2
H3
F4
G2
G3
F3
F2
F5
E1
E5
E4
D1
D2
D3
D4
C1
C2
D5
C4
VIO2
VIO2
VIO2
VIO2
VIO2
VIO2
VIO2
VIO2
VIO2
VIO2
VIO2
VIO2
VIO2
VIO3
VIO3
VIO3
VIO3
VIO3
VIO3
VIO3
VIO4
VIO4
VIO4
VIO4
VIO4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO[33]
GPIO[34]
GPIO[35]
GPIO[36]
GPIO[37]
GPIO[38]
GPIO[39]
GPIO[40]
DQ[16]
DQ[17]
DQ[18]
DQ[19]
DQ[20]
DQ[21]
DQ[22]
DQ[23]
DQ[24]
DQ[25]
DQ[26]
DQ[27]
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
I2S_CLK
I2S_SD
I2S_WS
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
I/O GPIO[41]/A0 [5]
I/O GPIO[42]/A1 [5]
GPIO
GPIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO[43]
GPIO[44]
GPIO[45]
GPIO[46]
GPIO[47]
GPIO[48]
GPIO[49]
GPIO[50]
GPIO[51]
GPIO[52]
GPIO[53]
GPIO[54]
GPIO[55]
GPIO[56]
GPIO[57]
GPIO
GPIO
GPIO
DQ[28]
DQ[29]
DQ[30]
DQ[31]
I2S_CLK
I2S_SD
I2S_WS
UART_RTS
UART_CTS
UART_TX
UART_RX
I2S_MCLK
UART_RT S
UART_CT S
UART_TX
UART_R X
I2S_CLK
I2S_SD
I2S_WS
SPI_SCK
SPI_SSN
SPI_MIS O
SPI_MOS I
I2S_MCL K
UART_RTS SPI_SCK
UART_CTS SPI_SSN
UART_TX SPI_MISO
UART_RX SPI_MOSI
GPIO
GPIO
I2S_MCLK GPIO
USB Port
CYUSB301X
SSRX-
CYUSB201X
A3
A4
A6
A5
B3
U3RXVDDQ
U3RXVDDQ
U3TXVDDQ
U3TXVDDQ
U3TXVDDQ
I
I
SSRXM
SSRXP
SSTXM
SSTXP
R_usb3
NC
NC
NC
NC
NC
SSRX+
O
O
I/O
SSTX-
SSTX+
Precision resistor for USB 3.0
(Connect a 200 ±1% resistor
between this pin and GND)
C9
A9
VBUS/VBATT
VBUS/VBATT
VBUS/VBATT
VBUS/VBATT
I
OTG_ID
DP
OTG_ID
D+
I/O
I/O
I/O
A10
C8
DM
D–
R_usb2
Precision resistor for USB 2.0
(Connect a 6.04 k ±1% resistor between this pin and GND)
Note
5. For 24-bit data bus configuration, GPIO[41] and GPIO[42] act as address lines.
Datasheet
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2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
Pin description
Table 7
CYUSB3011, CYUSB3012, CYUSB3013, CYUSB3014 and CYUSB2014 pin list (continued)
BGA
Power domain
I/O
Name
Description
Clock and Reset
FSLC[0]
XTALIN
B2
C6
C7
B4
E6
D7
D6
C5
CVDDQ
AVDD
I
FSLC[0]
XTALIN
I/O
AVDD
I/O
XTALOUT
FSLC[1]
FSLC[2]
CLKIN
XTALOUT
FSLC[1]
FSLC[2]
CLKIN
CVDDQ
CVDDQ
CVDDQ
CVDDQ
CVDDQ
I
I
I
I
I
CLKIN_32
RESET#
CLKIN_32
RESET#
I2C and JTAG
I2C_SCL
I2C_SDA
TDI
D9
D10
E7
VIO5
VIO5
VIO5
VIO5
VIO5
VIO5
VIO5
VIO5
I/O
I2C_GPIO[58]
I2C_GPIO[59]
TDI
I/O
I
O
I
C10
B11
E8
TDO
TDO
TRST#
TMS
TRST#
I
TMS
F6
I
TCK
TCK
D11
O
O[60]
GPIO
Power
E10
B10
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
VBATT
VDD
VDD
A1
E11
D8
U3VSSQ
VBUS
VSS
H11
E2
VIO1
VSS
L9
VIO1
G1
VSS
VIO1
VSS
F1
VIO2
G11
VSS
VIO2
E3
L1
B1
L6
VIO3
VSS
VIO4
VSS
VSS
B6
B5
CVDDQ
U3TXVDDQ
U3RXVDDQ
VIO5
A2
C11
L11
A7
VSS
AVDD
Datasheet
30
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2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
Pin description
Table 7
BGA
B7
CYUSB3011, CYUSB3012, CYUSB3013, CYUSB3014 and CYUSB2014 pin list (continued)
Power domain
I/O
Name
AVSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VSS
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
NC
Description
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
C3
B8
E9
B9
F11
GND
GND
GND
H1
L7
J11
L5
K4
L3
K3
L2
A8
No Connect
No Connect
A11
NC
Datasheet
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EZ-USB FX3
SuperSpeed USB Controller
Electrical specifications
17
Electrical specifications
17.1
Absolute maximum ratings
Exceeding maximum ratings may shorten the useful life of the device.
Storage temperature ......................... –65°C to +150°C
Ambient temperature with
power supplied (Industrial) ................ –40°C to +85°C
Ambient temperature with
power supplied (Commercial) ................ 0°C to +70°C
Supply voltage to ground potential
VDD, AVDDQ ...........................................................1.25 V
VIO1,VIO2, VIO3, VIO4, VIO5 .......................................3.6 V
U3TXVDDQ, U3RXVDDQ .........................................1.25 V
DC input voltage to any input pin ...............VCC + 0.3 V
DC voltage applied to
outputs in high Z state ............................... VCC + 0.3 V
(VCC is the corresponding I/O voltage)
Static discharge voltage ESD protection levels:
• ± 2.2-kV HBM based on JESD22-A114
• Additional ESD protection levels on D+, D–, and GND pins, and serial peripheral pins
• ± 6-kV contact discharge, ± 8-kV air gap discharge based on IEC61000-4-2 level 3A, ± 8-kV contact discharge, and
± 15-kV air gap discharge based on IEC61000-4-2 level 4C
Latch-up current ............................................ 180 mA
Maximum output short-circuit current
for all I/Os (cumulative) ................................ –100 mA
Maximum output current per I/O
(source or sink) .................................................. 20 mA
17.2
Operating conditions
TA (ambient temperature under bias)
Industrial ............................................. –40°C to +85°C
Commercial ............................................ 0°C to +70°C
VDD, AVDDQ, U3TXVDDQ, U3RXVDDQ
Supply voltage .....................................1.15 V to 1.25 V
VBATT supply voltage ..................................3.2 V to 6 V
VIO1, VIO2, VIO3, VIO4, CVDDQ
Supply voltage .........................................1.7 V to 3.6 V
VIO5 supply voltage ............................... 1.15 V to 3.6 V
Datasheet
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2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
Electrical specifications
17.3
DC specifications
Table 8
Parameter
VDD
DC specifications
Description
Core voltage supply
Analog voltage supply
Min
1.15
1.15
Max
1.25
1.25
Units
Notes
V
V
1.2-V typical
1.2-V typical
AVDD
GPIF II I/O power supply
domain
VIO1
1.7
3.6
V
1.8-, 2.5-, and 3.3-V typical
VIO2
VIO3
IO2 power supply domain
IO3 power supply domain
1.7
1.7
3.6
3.6
V
V
1.8-, 2.5-, and 3.3-V typical
1.8-, 2.5-, and 3.3-V typical
UART/SPI/I2S power supply
domain
VIO4
1.7
3.6
V
1.8-, 2.5-, and 3.3-V typical
VBATT
VBUS
USB voltage supply
USB voltage supply
3.2
4.0
6
6
V
V
3.7-V typical
5-V typical
1.2-V typical. A 22-µF bypass
capacitor is required on this power
supply.
U3TXVDDQ
U3RXVDDQ
USB 3.0 1.2-V supply
USB 3.0 1.2-V supply
1.15
1.15
1.25
1.25
V
V
N/A for CYUSB201X
1.2-V typical. A 22-µF bypass
capacitor is required on this power
supply.
N/A for CYUSB201X
CVDDQ
VIO5
Clock voltage supply
I2C and JTAG voltage supply
1.7
1.15
3.6
3.6
V
V
1.8-, 3.3-V typical
1.2-, 1.8-, 2.5-, and 3.3-V typical
For 2.0 V VCC 3.6 V
VIH1
Input HIGH voltage 1
0.625 × VCC VCC + 0.3
VCC – 0.4 VCC + 0.3
V
(except USB port). VCC is the
corresponding I/O voltage supply.
For 1.7 V VCC 2.0 V
(except USB port). VCC is the
corresponding I/O voltage supply.
VCC is the corresponding I/O
voltage supply.
VIH2
VIL
Input HIGH voltage 2
Input LOW voltage
V
V
–0.3
0.25 × VCC
IOH (max) = –100 µA tested at
quarter drive strength. VCC is the
corresponding I/O voltage supply.
Refer toTable 9 for values of IOH at
various drive strength and VCC.
IOL (min) = +100 µA tested at
quarter drive strength. VCC is the
corresponding I/O voltage supply.
Refer to Table 9 for values of IOL
measured at various drive strength
and VCC.
VOH
Output HIGH voltage
Output LOW voltage
0.9 × VCC
–
V
V
VOL
–
0.1 × VCC
All I/O signals held at VDDQ
(For I/Os with a pull-up or
Input leakage current for all
pins except
SSTXP/SSXM/SSRXP/SSRXM
IIX
–1
1
µA pull-down resistor connected, the
leakage current increases by
VDDQ/Rpu or VDDQ/RPD
)
Datasheet
33
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2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
Electrical specifications
Table 8
DC specifications (continued)
Parameter
Description
Min
Max
Units
Notes
Output High-Z leakage
current for all pins except
SSTXP/ SSXM/
IOZ
–1
1
µA All I/O signals held at VDDQ
SSRXP/SSRXM
Core and analog voltage
operating current
USB voltage supply
operating current
ICC Core
–
–
200
mA Total current through AVDD, VDD
ICC USB [6]
60 [6]
mA
–
Core current: 1.5 mA
I/O current: 20 µA
Total suspend current
USB current: 2 mA
ISB1
ISB2
ISB3
ISB4
during suspend mode with
USB 3.0 PHY enabled (L1)
–
–
–
–
–
–
–
–
mA
For typical PVT (typical silicon, all
power supplies at their respective
nominal levels at 25°C)
Core current: 250 µA
I/O current: 20 µA
Total suspend current
during suspend mode with
USB 3.0 PHY disabled (L2)
USB current: 1.2 mA
mA
µA
µA
For typical PVT (Typical silicon, all
power supplies at their respective
nominal levels at 25°C)
Core current: 60 µA
I/O current: 20 µA
Total standby current
during standby mode (L3)
USB current: 40 µA
For typical PVT (typical silicon, all
power supplies at their respective
nominal levels at 25°C)
Core current: 0 µA
I/O current: 20 µA
Total standby current
during core power-down
mode (L4)
USB current: 40 µA
For typical PVT (typical silicon, all
power supplies at their respective
nominal levels at 25°C)
Voltage ramp rate on core
and I/O supplies
Noise level permitted on VDD
and I/O supplies
Noise level permitted on
AVDD supply
VRAMP
VN
0.2
–
50
100
20
V/ms Voltage ramp must be monotonic
Max p-p noise level permitted on all
supplies except AVDD
mV
Max p-p noise level permitted on
AVDD
VN_AVDD
–
mV
Note
6. For CYUSB2014 ICC USB is typically 22 mA–23 mA.
Datasheet
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2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
Electrical specifications
Table 9
VDDIO (V)
IOH/IOL values for different drive strength and VDDIO values
VOH (V)
VOL (V)
Drive strength
Quarter
Half
Three-quarters
Full
IOH max (mA)
1.02
IOL min (mA)
2.21
1.51
1.83
2.28
3.28
3.85
4.73
1.7
2.5
3.6
1.53
0.17
Quarter
Half
Three-quarters
Full
Quarter
Half
Three-quarters
Full
5.03
7.38
8.89
11.07
7.80
11.36
13.64
16.92
3.96
5.84
6.89
8.61
5.74
8.64
10.15
12.67
2.25
3.24
0.25
0.36
Datasheet
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2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
Thermal characteristics
18
Thermal characteristics
Table 10
Thermal characteristics
Description
Value
125
34.66
27.03
13.57
Unit
°C
°C/W
°C/W
°C/W
Parameter
TJ MAX
JA
JB
JC
Maximum junction temperature
Thermal resistance (Junction to ambient)
Thermal resistance (Junction to board)
Thermal resistance (Junction to case)
Datasheet
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2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
AC timing parameters
19
AC timing parameters
19.1
GPIF II lines AC characteristics at 100 MHz
Table 11
GPIF II lines AC characteristics at 100 MHz
Symbol
Parameter
Rise time
Fall time
Overshoot
Undershoot
Min
–
–
–
–
Typ
–
–
–
–
Max
2.5
2.5
3
Unit
ns
ns
%
%
Tr
Tf
Tov
Tun
3
19.2
GPIF II PCLK jitter characteristics
Table 12
GPIF II PCLK jitter characteristics
Clk Freq (MHz)
Period jitter (ps)
354.44
C-C min (ps)
–187.92
C-C max (ps)
204.55
10.08
25.2
205.97
–153.54
126.53
50.4
144.62
–100.16
85.769
100.8
171.43
–155.13
157.14
Note
7. The clock jitter is measured using internally generated PCLK. ie. PCLK is configured as an output from GPIF.
The data is measured over 10,000 clock cycles.
Datasheet
37
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2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
AC timing parameters
19.3
GPIF II timing
tCLKH tCLKL
CLK
tCLK
tLZ
tCO
tHZ
tCOE
tDS tDH
tDOH
tDOH
tLZ
Data1
( OUT)
Data2
( OUT)
DQ- [31:0]
Data(IN)
tS tH
CTL(IN)
tCTLO
tCOH
CTL( OUT)
Figure 8
GPIF II timing in Synchronous Mode
Table 13
Parameter
Frequency
tCLK
tCLKH
tCLKL
tS
tH
tDS
tDH
GPIF II timing parameters in Synchronous Mode [8]
Description
Interface clock frequency
Interface clock period
Clock high time
Clock low time
CTL input to clock setup time
CTL input to clock hold time
Data in to clock setup time
Data in to clock hold time
Min
Max
100
–
–
–
–
–
–
–
Units
MHz
ns
ns
ns
ns
ns
ns
ns
–
10
4
4
2
0.5
2
0.5
Clock to data out propagation delay when DQ bus is already in
output direction
Clock to data out propagation delay when DQ lines change to
output from tristate and valid data is available on the DQ bus
tCO
–
–
7
9
ns
ns
tCOE
tCTLO
tDOH
tCOH
tHZ
Clock to CTL out propagation delay
Clock to data out hold
Clock to CTL out hold
Clock to high-Z
–
2
0
–
0
8
–
–
8
–
ns
ns
ns
ns
ns
tLZ
Clock to low-Z
Note
8. All parameters guaranteed by design and validated through characterization.
Datasheet
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2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
AC timing parameters
tAH
tDH/
tDS/ tAS
DATA/ ADDR
DATA IN
tCHZ
tCTLassert_DQlatch
tCTLdeassert_DQlatch
CTL#
(I/P, ALE/ DLE)
tAA/tDO
tCHZ/tOEHZ
tCLZ/ tOELZ
DATA OUT
DATA OUT
CTL#
(I/P, non ALE/ DLE
tCTLdeassert
tCTLassert
tCTLalpha
tCTLbeta
ALPHA
O/P
BETA
O/P
1
1
tCTLassert
tCTLdeassert
tCTL#
(O/P)
1. n is an integer >= 0
tDST
tDHT
DATA/
ADDR
tCTLdeassert_DQassert
tCTLassert_DQassert
CTL#
I/P (non DLE/ALE)
Figure 9
GPIF II timing in Asynchronous Mode
tDS
tCTLdeassert_DqlatchDDR
tCTLassert_DQlatchDDR
CTL#
(I/P)
tDS
tDH
tDH
DATA IN
Figure 10
GPIF II timing in Asynchronous DDR Mode
Datasheet
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2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
AC timing parameters
Table 14
GPIF II timing in Asynchronous Mode[9, 10]
Note The following parameters assume one state transition
Parameter
Description
Min
2.3
2
2.3
2
Max
Units
ns
ns
ns
ns
tDS
tDH
tAS
tAH
Data In to DLE setup time. Valid in DDR async mode.
Data In to DLE hold time. Valid in DDR async mode.
Address In to ALE setup time
–
–
–
–
Address In to ALE hold time
CTL I/O asserted width for CTRL inputs without DQ
input association and for outputs.
CTL I/O deasserted width for CTRL inputs without DQ
input association and for outputs.
tCTLassert
7
7
–
–
ns
ns
tCTLdeassert
CTL asserted pulse width for CTL inputs that signify DQ
inputs valid at the asserting edge but do not employ
in-built latches (ALE/DLE) for those DQ inputs.
tCTLassert_DQassert
20
7
–
–
–
–
ns
ns
ns
ns
CTL deasserted pulse width for CTL inputs that signify
tCTLdeassert_DQassert DQ input valid at the asserting edge but do not employ
in-built latches (ALE/DLE) for those DQ inputs.
CTL asserted pulse width for CTL inputs that signify DQ
tCTLassert_DQdeassert inputs valid at the deasserting edge but do not employ
in-built latches (ALE/DLE) for those DQ inputs.
7
CTL deasserted pulse width for CTL inputs that signify
tCTLdeassert_
DQ inputs valid at the deasserting edge but do not
DQdeassert
20
employ in-built latches (ALE/DLE) for those DQ inputs.
CTL asserted pulse width for CTL inputs that employ
in-built latches (ALE/DLE) to latch the DQ inputs. In this
tCTLassert_DQlatch
7
–
–
ns
ns
non-DDR case, in-built latches are always close at the
deasserting edge.
CTL deasserted pulse width for CTL inputs that employ
in-built latches (ALE/DLE) to latch the DQ inputs. In this
tCTLdeassert_DQlatch
10
non-DDR case, in-built latches always close at the
deasserting edge.
CTL asserted pulse width for CTL inputs that employ
tCTLassert_
in-built latches (DLE) to latch the DQ inputs in DDR
10
10
–
–
–
ns
ns
ns
ns
DQlatchDDR
mode.
CTL deasserted pulse width for CTL inputs that employ
tCTLdeassert_
DQlatchDDR
in-built latches (DLE) to latch the DQ inputs in DDR
mode.
DQ/CTL input to DQ output time when DQ change or
CTL change needs to be detected and affects internal
updates of input and output DQ lines.
CTL to data out when the CTL change merely enables
the output flop update whose data was already
established.
tAA
30
25
tDO
–
Notes
9. All parameters guaranteed by design and validated through characterization.
10.“alpha” output corresponds to “early output” and “beta” corresponds to “delayed output”. Please refer to
the GPIFII Designer Tool for the use of these outputs.
Datasheet
40
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2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
AC timing parameters
Table 14
GPIF II timing in Asynchronous Mode[9, 10] (continued)
Note The following parameters assume one state transition
Parameter
Description
Min
0
Max
Units
ns
CTL designated as OE to low-Z. Time when external
devices should stop driving data.
CTL designated as OE to high-Z
CTL (non-OE) to low-Z. Time when external devices
should stop driving data.
tOELZ
tOEHZ
tCLZ
–
8
–
8
ns
0
ns
tCHZ
CTL (non-OE) to high-Z
CTL to alpha change at output
CTL to beta change at output
Addr/data setup when DLE/ALE not used
Addr/data hold when DLE/ALE not used
30
–
–
2
20
30
25
30
–
ns
ns
ns
ns
ns
tCTLalpha
tCTLbeta
tDST
tDHT
–
19.4
Slave FIFO interface
Synchronous Slave FIFO Read sequence description
19.4.1
• FIFO address is stable and SLCS is asserted
• FLAG indicates FIFO not empty status
• SLOE is asserted. SLOE is an output-enable only, whose sole function is to drive the data bus.
• SLRD is asserted
The FIFO pointer is updated on the rising edge of the PCLK, while the SLRD is asserted. This starts the propagation
of data from the newly addressed location to the data bus. After a propagation delay of tco (measured from the
rising edge of PCLK), the new data value is present. N is the first data value read from the FIFO. To have data on
the FIFO data bus, SLOE must also be asserted.
The same sequence of events is applicable for a burst read.
FLAG Usage:
The FLAG signals are monitored for flow control by the external processor. FLAG signals are outputs from FX3 that
may be configured to show empty, full, or partial status for a dedicated thread or the current thread that is
addressed.
Socket Switching Delay (Tssd):
The socket-switching delay is measured from the time EPSWITCH# is asserted by the master, with the new socket
address on the address bus, to the time the Current_Thread_DMA_Ready flag is asserted. For the Producer
socket, the flag is asserted when it is ready to receive data in the DMA buffer. For the Consumer socket, the flag
is asserted when it is ready to drive data out of the DMA buffer. For a synchronous slave FIFO interface, the
switching delay is measured in the number of GPIF interface clock cycles; for an asynchronous slave FIFO
interface, in PIB clock cycles. This is applicable only for the 5-bit Slave FIFO interface; there is no socket-switching
delay in FX3’s 2-bit Slave FIFO interface, which makes use of thread switching in the GPIF™ II state machine.
Note For burst mode, the SLRD# and SLOE# are asserted during the entire duration of the read. When SLOE# is
asserted, the data bus is driven (with data from the previously addressed FIFO). For each subsequent rising edge
of PCLK, while the SLRD# is asserted, the FIFO pointer is incremented and the next data value is placed on the
data bus.
Datasheet
41
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2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
AC timing parameters
Synchronous Read Cycle Timing
tCYC
PCLK
SLCS
tCH tCL
ACCD
t
tAS
tAH
FIFO ADDR
An
Am
tRDH
tRDS
SLRD
SLOE
Tssd
ACCD
t
Tssd
tCFLG
FLAGA
(dedicated thread Flag for An )
( 1 = Not Empty 0 = Empty )
tCFLG
FLAGB
(dedicated thread Flag for Am )
( 1 = Not Empty 0 = Empty )
tCDH
tOELZ
tOEZ
tCO
tOEZ
High-Z
High-Z
High-Z
Data
driven:DN(An
DN (An)
D ( Am)
N
Data Out
DN+2 (Am)
DN+1 (Am)
)
SLWR( HIGH)
Figure 11
Synchronous Slave FIFO Read Mode
Datasheet
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2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
AC timing parameters
19.4.2
Synchronous Slave FIFO Write sequence description
• FIFO address is stable and the signal SLCS# is asserted
• External master or peripheral outputs the data to the data bus
• SLWR# is asserted
• While the SLWR# is asserted, data is written to the FIFO and on the rising edge of the PCLK, the FIFO pointer is
incremented
• The FIFO flag is updated after a delay of t WFLG from the rising edge of the clock
The same sequence of events is also applicable for burst write
Note For the burst mode, SLWR# and SLCS# are asserted for the entire duration, during which all the required
data values are written. In this burst write mode, after the SLWR# is asserted, the data on the FIFO data bus is
written to the FIFO on every rising edge of PCLK. The FIFO pointer is updated on each rising edge of PCLK.
Short Packet: A short packet can be committed to the USB host by using the PKTEND#. The external device or
processor should be designed to assert the PKTEND# along with the last word of data and SLWR# pulse
corresponding to the last word. The FIFOADDR lines must be held constant during the PKTEND# assertion.
Zero-Length Packet: The external device or processor can signal a Zero-Length Packet (ZLP) to FX3 simply by
asserting PKTEND#, without asserting SLWR#. SLCS# and address must be driven as shown in Figure 12.
Synchronous Write Cycle Timing
tCYC
PCLK
tCH tCL
SLCS
tAH
tAS
Am
An
FIFO ADDR
SLWR
Tssd
tWRS
tWRH
tCFLG
tFAD
FLAGA
dedicated thread FLAG for An
( 1 = Not Full0= Full)
Tssd
tCFLG
tFAD
FLAGB
current thread FLAG for Am
( 1 = Not Full0= Full)
tDS tDH
tDS tDH
tDH
DN(Am)
DN+1(Am) DN+2(Am)
DN(An)
DataIN
High-Z
t
PES tPEH
PKTEND
SLOE
(HIGH)
Figure 12
Synchronous Slave FIFO Write Mode
Datasheet
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001-52136 Rev. *Z
2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
AC timing parameters
Synchronous ZLP Write Cycle Timing
tCYC
PCLK
tCH tCL
SLCS
tAH
tAS
An
FIFO ADDR
SLWR
(HIGH)
t
PES tPEH
PKTEND
tCFLG
FLAGA
dedicated thread FLAG for An
(1 = Not Full 0= Full)
FLAGB
current thread FLAG for Am
(1 = Not Full 0= Full)
High-Z
Data IN
SLOE
(HIGH)
Figure 13
Synchronous Slave FIFO ZLP Write Cycle timing
Datasheet
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001-52136 Rev. *Z
2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
AC timing parameters
Table 15
Parameter
FREQ
tCYC
Synchronous Slave FIFO parameters[11]
Description
Interface clock frequency
Clock period
Min
–
10
4
Max
100
–
Units
MHz
ns
tCH
Clock HIGH time
–
ns
tCL
Clock LOW time
4
–
ns
tRDS
tRDH
tWRS
tWRH
tCO
SLRD# to CLK setup time
SLRD# to CLK hold time
SLWR# to CLK setup time
SLWR# to CLK hold time
Clock to valid data
2
0.5
2
0.5
–
–
–
–
–
ns
ns
ns
ns
7
ns
tDS
tDH
tAS
tAH
tOELZ
tCFLG
tOEZ
tPES
tPEH
tCDH
Data input setup time
CLK to data input hold
Address to CLK setup time
CLK to address hold time
SLOE# to data low-Z
CLK to flag output propagation delay
SLOE# deassert to Data Hi Z
PKTEND# to CLK setup
2
0.5
2
0.5
0
–
–
2
0.5
2
–
–
–
–
–
8
8
–
ns
ns
ns
ns
ns
ns
ns
ns
CLK to PKTEND# hold
CLK to data output hold
–
–
ns
ns
Clock
cycles
Clock
cycles
Clock
cycles
tSSD
tACCD
tFAD
Socket switching delay
2
2
3
68
2
Latency from SLRD# to Data
Latency from SLWR# to FLAG
3
Note Three-cycle latency from ADDR to DATA/FLAGS.
Note
11.All parameters guaranteed by design and validated through characterization.
Datasheet
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001-52136 Rev. *Z
2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
AC timing parameters
19.4.3
Asynchronous Slave FIFO Read sequence description
• FIFO address is stable and the SLCS# signal is asserted.
• SLOE# is asserted. This results in driving the data bus.
• SLRD # is asserted.
• Data from the FIFO is driven after assertion of SLRD#. This data is valid after a propagation delay of tRDO from
the falling edge of SLRD#.
• FIFO pointer is incremented on deassertion of SLRD#
In Figure 14, data N is the first valid data read from the FIFO. For data to appear on the data bus during the read
cycle, SLOE# must be in an asserted state. SLRD# and SLOE# can also be tied.
The same sequence of events is also shown for a burst read.
Note In the burst read mode, during SLOE# assertion, the data bus is in a driven state (data is driven from a
previously addressed FIFO). After assertion of SLRD# data from the FIFO is driven on the data bus (SLOE# must
also be asserted). The FIFO pointer is incremented after deassertion of SLRD#.
Asynchronous Read Cycle Timing
SLCS
tAS
tAH
An
tRDl tRDh
Am
FIFO ADDR
SLRD
SLOE
tFLG
tRFLG
FLAGA
dedicated thread Flag for An
(1=Not empty 0 = Empty)
FLAGB
dedicated thread Flag for Am
(1=Not empty 0 = Empty)
tRDO
tRDO
tOH
tOE
tLZ
tOE
tRDO
tOH
DN(An)
DN(An)
DN(Am)
DN+1(Am)
DN+2(Am)
Data Out
High-Z
SLWR
(HIGH)
Figure 14
Asynchronous Slave FIFO Read Mode
Datasheet
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2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
AC timing parameters
19.4.4
Asynchronous Slave FIFO Write sequence description
• FIFO address is driven and SLCS# is asserted
• SLWR# is asserted. SLCS# must be asserted with SLWR# or before SLWR# is asserted
• Data must be present on the tWRS bus before the deasserting edge of SLWR#
• Deassertion of SLWR# causes the data to be written from the data bus to the FIFO, and then the FIFO pointer is
incremented
• The FIFO flag is updated after the tWFLG from the deasserting edge of SLWR.
The same sequence of events is shown for a burst write.
Note that in the burst write mode, after SLWR# deassertion, the data is written to the FIFO, and then the FIFO
pointer is incremented.
Short Packet: A short packet can be committed to the USB host by using the PKTEND#. The external device or
processor should be designed to assert the PKTEND# along with the last word of data and SLWR# pulse
corresponding to the last word. The FIFOADDR lines must be held constant during the PKTEND# assertion.
Zero-Length Packet: The external device or processor can signal a zero-length packet (ZLP) to FX3 simply by
asserting PKTEND#, without asserting SLWR#. SLCS# and the address must be driven as shown in Figure 16.
FLAG Usage: The FLAG signals are monitored by the external processor for flow control. FLAG signals are FX3
outputs that can be configured to show empty, full, and partial status for a dedicated address or the current
address.
SLCS
tAS
tAH
An
Am
FIFO ADDR
SLWR
tWRl
tWRh
tFLG
tWFLG
FLAGA
dedicated thread Flag for An
(1= Not Full0 = Full)
tWFLG
FLAGB
dedicated thread Flag for Am
(1= Not Full0 = Full)
tWR
tWR
tWRH
tWRH
S
S
High-Z
DN(An)
DN(Am)
DN+1(Am)
DN+2(Am)
DATA In
tWRPE
tPEh
PKTEND
SLOE
(HIGH)
Figure 15
Asynchronous Slave FIFO Write Mode
Datasheet
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001-52136 Rev. *Z
2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
AC timing parameters
SLCS
tAS
tAH
An
FIFO ADDR
SLWR
(HIGH)
tPEl
tPEh
PKTEND
tWFLG
FLAGA
dedicated thread Flag for An
(1= Not Full0 = Full)
FLAGB
dedicated thread Flag for Am
(1= Not Full0 = Full)
High-Z
DATA In
SLOE
(HIGH)
Figure 16
Asynchronous ZLP Write Cycle timing
Datasheet
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2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
AC timing parameters
Table 16
Parameter
tRDI
tRDh
tAS
Asynchronous Slave FIFO parameters[12]
Description
SLRD# LOW
SLRD# HIGH
Address to SLRD#/SLWR# setup time
SLRD#/SLWR#/PKTEND to address hold time
SLRD# to FLAGS output propagation delay
ADDR to FLAGS output propagation delay
SLRD# to data valid
OE# low to data valid
OE# low to data low-Z
SLOE# deassert data output hold
SLWR# LOW
SLWR# HIGH
Data to SLWR# setup time
SLWR# to Data Hold time
SLWR#/PKTEND to Flags output propagation delay
PKTEND LOW
PKTEND HIGH
SLWR# deassert to PKTEND deassert
Min
20
10
7
Max
–
–
–
–
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAH
2
tRFLG
tFLG
tRDO
tOE
tLZ
tOH
–
–
–
–
0
–
20
10
7
2
–
20
7.5
2
35
22.5
25
25
–
22.5
–
–
–
–
35
–
–
tWRI
tWRh
tWRS
tWRH
tWFLG
tPEI
tPEh
tWRPE
–
Note
12.All parameters guaranteed by design and validated through characterization.
Datasheet
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001-52136 Rev. *Z
2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
AC timing parameters
19.5
Host Processor Interface (P-Port) timing
19.5.1
Asynchronous SRAM timing
Socket Read – Address Transition Controlledtiming (OE# is asserted)
A[0]
tAA
tAH
tOH
HIGH
DATA
IMPEDANCE
OUT
DATA VALID
DATA VALID
DATA VALID
tOE
OE#
OE# Controlled timing
ADDRESS
WE# (HIGH)
CE#
tAOS
tOHC
tRC
OE#
tOHH
tOE
t
OEZ
tOLZ
HIGH
IMPEDANCE
HIGH
IMPEDANCE
HIGH
IMPEDANCE
DATA OUT
DATA
VALID
DATA
VALID
Figure 17
Non-multiplexed Asynchronous SRAM Read timing
Datasheet
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2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
AC timing parameters
Write Cycle 1 WE# Controlled, OE# HIGH during Write
tWC
ADDRESS
tCW
CE#
tAW
tAH
tDH
tWP
WE#
tAS
tWPH
OE#
tDS
VALID DATA
DATA I/O
VALID DATA
tWHZ
Write Cycle 2 CE# Controlled, OE# HIGH during Write
tWC
ADDRESS
tAS
tCW
tCPH
CE#
tAW
tAH
tDH
tWP
WE#
OE#
tDS
VALID DATA
DATA I/O
VALID DATA
tWHZ
Figure 18
Non-multiplexed Asynchronous SRAM Write timing (WE# and CE# Controlled)
Datasheet
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2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
AC timing parameters
Write Cycle 3 WE# Controlled. OE# LOW
tWC
tCW
CE#
tAW
tAH
tAS
tWP
WE#
tDS
tDH
DATA I/O
VALID DATA
tOW
tWHZ
Note: tWP must be adjusted such that tWP > tWHZ + tDS
Figure 19
Non-multiplexed Asynchronous SRAM Write timing (WE# Controlled, OE# LOW)
Datasheet
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2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
AC timing parameters
Table 17
Parameter
–
tRC
tAA
tAOS
tOH
tOHH
tOHC
tOE
tOLZ
tWC
tCW
tAW
tAS
tAH
tWP
tWPH
tCPH
tDS
Asynchronous SRAM timing parameters[13]
Description
SRAM interface bandwidth
Read cycle time
Min
–
32.5
–
Max
61.5
–
30
–
Units
Mbps
ns
ns
ns
Address to data valid
Address to OE# LOW setup time
Data output hold from address change
OE# HIGH hold time
OE# HIGH to CE# HIGH
OE# LOW to data valid
OE# LOW to Low-Z
Write cycle time
CE# LOW to write end
Address valid to write end
Address setup to write start
Address hold time from CE# or WE#
WE# pulse width
7
3
7.5
2
–
0
30
30
30
7
–
–
–
25
–
–
–
–
–
–
–
–
–
–
–
22.5
22.5
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
20
10
10
7
2
–
WE# HIGH time
CE# HIGH time
Data setup to write end
Data hold to write end
Write to DQ High-Z output
OE# HIGH to DQ High-Z output
End of write to Low-Z output
tDH
tWHZ
tOEZ
tOW
–
0
ns
ns
Note
13.All parameters guaranteed by design and validated through characterization.
Datasheet
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2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
AC timing parameters
19.5.2
ADMux timing for Asynchronous Access
tRC
tACC
Valid Address
tAVS
tVP
Valid
Addr
Valid Data
A[0:7]/DQ[0:15]
ADV#
tAVH
WE# (HIGH)
CE#
tCEAV
tCPH
tHZ
tCO
tHZ
tOLZ
tOE
OE#
tAVOE
Note:
1. Multiple read cycles can be executed while keeping CE# low.
2. Read operation ends with either de-assertion of either OE# or CE#, whichever comes earlier.
Figure 20
ADMux Asynchronous Random Read
tWC
Valid
Addr
Address Valid
Data Valid
tDS
A[0:7]/DQ[0:15]
ADV#
tAW
tAVH
tAVS
tVP
tDH
tVPH
tCEAV
CE#
tCPH
tCW
tWP
tWPH
WE#
tAVWE
Note:
1. Multiple write cycles can be executed while keeping CE# low.
2. Write operation ends with de-assertion of either WE# or CE#, whichever comes earlier.
Figure 21
ADMux Asynchronous Random Write
Datasheet
54
001-52136 Rev. *Z
2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
AC timing parameters
Table 18
Asynchronous ADMux timing parameters[14]
Description Min
Parameter
Max
Units
Notes
ADMux Asynchronous READ Access timing parameters
This parameter is dependent
ns on when the P-port processors
deasserts OE#
Read cycle time (address valid to
address valid)
tRC
54.5
–
tACC
tCO
tAVOE
tOLZ
tOE
Address valid to data valid
CE# assert to data valid
ADV# deassert to OE# assert
OE# assert to data Low-Z
OE# assert to data valid
–
–
2
0
–
–
32
34.5
–
–
25
ns
ns
ns
ns
ns
ns
–
–
–
–
–
–
tHZ
Read cycle end to data High-Z
22.5
ADMux Asynchronous WRITE Access timing parameters
Write cycle time (Address Valid to
Address Valid)
tWC
–
52.5
ns
–
tAW
tCW
tAVWE
tWP
tWPH
tDS
Address valid to write end
CE# assert to write end
ADV# deassert to WE# assert
WE# LOW pulse width
WE# HIGH pulse width
Data valid setup to WE# deassert
Data valid hold from WE# deassert
30
30
2
20
10
18
2
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
–
–
–
–
–
–
–
tDH
ADMux Asynchronous Common READ/WRITE Access timing parameters
Address valid setup to ADV#
tAVS
tAVH
5
2
–
–
ns
ns
–
–
deassert
Address valid hold from ADV#
deassert
tVP
ADV# LOW pulse width
CE# HIGH pulse width
ADV# HIGH pulse width
CE# assert to ADV# assert
7.5
10
15
0
–
–
–
–
ns
ns
ns
ns
–
–
–
–
tCPH
tVPH
tCEAV
Note
14.All parameters guaranteed by design and validated through characterization.
Datasheet
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001-52136 Rev. *Z
2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
AC timing parameters
19.5.3
Synchronous ADMux timing
tCLK
tCLKL
2- cycle latency from OE# to DATA
tCLKH
CLK
tCO
tS
tH
Valid Data
Valid Address
A[0:7]/DQ[0:31]
tS
tH
tOHZ
ADV#
CE#
tS
tAVOE
tOLZ
OE#
RDY
tKW
tKW
tCH
WE# (HIGH)
Note:
1) External P-Port processor and FX3 operate on the same clock edge
2) External processor sees RDY assert 2 cycles after OE # asserts andand sees RDY deassert a cycle after the data appears on the output
3) Valid output data appears 2 cycle after OE # asserted. The data is held until OE # deasserts
4) Two cycle latency is shown for 0-100 MHz operation. Latency can be reduced by 1 cycle for operations at less than 50 MHz (this 1 cycle latency is not supported by the bootloader)
Figure 22
Synchronous ADMux Interface – Read Cycle timing
2-cycle latency between
WE# and data being latched
2-cycle latency between this clk edge and RDY deassertion seen by
the host
CLK
tCLK
tDS
tDH
tS
tH
Valid Address
Valid Data
A[0:7]/DQ[0:31]
tS
tH
ADV#
tS
CE#
tAVWE
tS
tH
WE#
RDY
tKW
tKW
Note:
1) External P-Port processor and FX3 operate on the same clock edge
2) External processor sees RDY assert 2 cycles after WE # asserts and deassert 3 cycles after the edge sampling the data.
3) Two cycle latency is shown for 0-100 MHz operation. Latency can be reduced by 1 cycle for operations at less than 50 MHz (this 1 cycle latency is not supported by the bootloader)
Figure 23
Synchronous ADMux Interface – Write Cycle timing
Datasheet
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2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
AC timing parameters
2-cycle latency fromOE# to Data
tCLK
tCLKH
tCLKL
CLK
tCO
tCH
tS
tH
ValidAddress
D0
D1
D2
D3
A[0:7]/DQ[0:31]
tS
tH
ADV#
CE#
tHZ
tS
tAVOE
tOLZ
OE#
RDY
tKW
tKW
Note:
1) External P-Port processor and FX3 work operate on the same clock edge
2) External processor sees RDY assert 2 cycles after OE # asserts andand sees RDY deassert a cycle after the last burst data appears on the output
3) Valid output data appears 2 cycle after OE # asserted. The last burst data is held until OE# deasserts
4) Burst size of 4 is shown. Transfer size for the operation must be amultiple of burst size. Burst size is usually power of2. RDYwill not deassert in the middle of the burst.
5) External processor cannot deassert OE in the middle of a burst. If it does so, any bytes remaining in the burst packet could get lost.
6) Two cycle latency is shown for 0-100 MHz operation. Latency can be reduced by1 cycle for operations at less than 50 MHz (this 1 cycle latency is not supported by the bootloader)
Figure 24
Synchronous ADMux Interface – Burst Read timing
2-cycle latency between
WE# and data being latched
2-cycle latency between this clk edge and RDY
deassertion seen by the host
tCLKH
tCLKL
CLK
tCLK
tDS
tDH
tDH
tS
tH
D0
Valid Address
D1
D2
D3
A[0:7]/DQ[0:31]
tS
tH
ADV#
CE#
tS
tAVWE
WE#
RDY
tKW
tKW
Note:
1) External P-Port processor and FX3 operate on the same clock edge
2) External processor sees RDY assert 2 cycles after WE # asserts and deasserts 3 cycles after the edge sampling the last burst data.
3) Transfer size for the operation must be a multiple of burst size. Burst size is usually power of 2. RDY will not deassert in the middle of the burst. Burst size of 4 is shown
4) External processor cannot deassert WE in the middle of a burst. If it does so, any bytes remaining in the burst packet could get lost.
5)Two cycle latency is shown for 0-100 MHz operation. Latency can be reduced by 1 cycle for operations at less than 50 MHz (this 1 cycle latency is not supported by the bootloader)
Figure 25
Sync ADMux Interface – Burst Write timing
Datasheet
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EZ-USB FX3
SuperSpeed USB Controller
AC timing parameters
Table 19
Parameter
FREQ
tCLK
tCLKH
tCLKL
tS
tH
tCH
tDS
tDH
tAVDOE
tAVDWE
tHZ
tOHZ
tOLZ
Synchronous ADMux timing parameters[15]
Description
Interface clock frequency
Clock period
Clock HIGH time
Clock LOW time
Min
–
10
4
Max
100
–
–
–
Unit
MHz
ns
ns
ns
4
CE#/WE#/DQ setup time
CE#/WE#/DQ hold time
2
0.5
0
2
0.5
0
0
–
–
0
–
–
–
–
–
–
–
8
ns
ns
ns
ns
ns
ns
ns
ns
Clock to data output hold time
Data input setup time
Clock to data input hold
ADV# HIGH to OE# LOW
ADV# HIGH to WE# LOW
CE# HIGH to Data High-Z
OE# HIGH to Data High-Z
OE# LOW to Data Low-Z
Clock to RDY valid
8
–
8
ns
ns
ns
tKW
–
Note
15.All parameters guaranteed by design and validated through characterization.
Datasheet
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EZ-USB FX3
SuperSpeed USB Controller
AC timing parameters
19.6
Serial Peripherals timing
19.6.1
I2C timing
Figure 26
I2C timing definition
Datasheet
59
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EZ-USB FX3
SuperSpeed USB Controller
AC timing parameters
Table 20
I2C timing parameters[16]
Parameter
I2C Standard Mode parameters
Description
Min
Max
Units
fSCL
tHD:STA
tLOW
SCL clock frequency
0
4
4.7
4
4.7
0
250
–
–
4
4.7
–
–
100
–
–
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
µs
µs
Hold time START condition
LOW period of the SCL
HIGH period of the SCL
Setup time for a repeated START condition
Data hold time
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tr
–
–
–
–
Data setup time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Setup time for STOP condition
Bus free time between a STOP and START condition
Data valid time
1000
300
–
tf
tSU:STO
tBUF
tVD:DAT
tVD:ACK
tSP
–
3.45
3.45
n/a
Data valid ACK
Pulse width of spikes that must be suppressed by input filter
n/a
I2C Fast Mode parameters
fSCL
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tr
SCL clock frequency
Hold time START condition
LOW period of the SCL
HIGH period of the SCL
Setup time for a repeated START condition
Data hold time
Data setup time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Setup time for STOP condition
Bus free time between a STOP and START condition
Data valid time
0
0.6
1.3
0.6
0.6
0
100
–
–
0.6
1.3
–
–
0
400
–
–
–
–
–
–
300
300
–
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
µs
µs
ns
tf
tSU:STO
tBUF
tVD:DAT
tVD:ACK
tSP
–
0.9
0.9
50
Data valid ACK
Pulse width of spikes that must be suppressed by input filter
Note
16.All parameters guaranteed by design and validated through characterization.
Datasheet
60
001-52136 Rev. *Z
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EZ-USB FX3
SuperSpeed USB Controller
AC timing parameters
Table 20
I2C timing parameters[16] (continued)
Description
Parameter
Min
Max
Units
I2C Fast Mode Plus Parameters (Not supported at I2C_VDDQ = 1.2 V)
fSCL
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tr
SCL clock frequency
Hold time START condition
LOW period of the SCL
HIGH period of the SCL
Setup time for a repeated START condition
Data hold time
0
0.26
0.5
0.26
0.26
0
50
–
–
0.26
0.5
–
–
0
1000
–
–
–
–
–
–
120
120
–
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
µs
µs
ns
Data setup time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Setup time for STOP condition
Bus-free time between a STOP and START condition
Data valid time
tf
tSU:STO
tBUF
tVD:DAT
tVD:ACK
tSP
–
0.45
0.55
50
Data valid ACK
Pulse width of spikes that must be suppressed by input filter
Datasheet
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EZ-USB FX3
SuperSpeed USB Controller
AC timing parameters
19.6.2
I2S timing diagram
tT
tTR
tTF
tTH
tTL
SCK
tThd
SA,
WS (output)
tTd
Figure 27
I2S transmit cycle
Table 21
Parameter
tT
tTL
tTH
tTR
tTF
tThd
tTd
I2S timing parameters[17]
Description
Min
Ttr
0.35 × Ttr
0.35 × Ttr
Max
Units
ns
ns
I2S transmitter clock cycle
–
–
–
I2S transmitter cycle LOW period
I2S transmitter cycle HIGH period
I2S transmitter rise time
ns
–
–
0
–
0.15 × Ttr ns
0.15 × Ttr ns
I2S transmitter fall time
I2S transmitter data hold time
I2S transmitter delay time
–
ns
ns
0.8tT
Note tT is selectable through clock gears. Max Ttr is designed for 96-kHz codec at 32 bits to be 326 ns (3.072 MHz).
Note
17.All parameters guaranteed by design and validated through characterization.
Datasheet
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EZ-USB FX3
SuperSpeed USB Controller
AC timing parameters
19.6.3
SPI timing specification
SSN
(output)
tssnh
tsck
tlag
tlead
SCK
(CPOL=0,
Output)
trf
twsck
twsck
SCK
(CPOL=1,
Output)
tsdi
thoi
LSB
MISO
(input)
MSB
MSB
td
tdis
tsdd
tdi
v
MOSI
(output)
LSB
SPI Master Timing for CPHA = 0
SSN
(output)
tssnh
tsck
tlag
tlead
trf
SCK
(CPOL=0,
Output)
twsck
twsck
SCK
(CPOL=1,
Output)
thoi
LSB
tsdi
MISO
(input)
MSB
MSB
tdis
tdi
tdv
MOSI
(output)
LSB
SPI Master Timing for CPHA = 1
Figure 28
SPI timing
Datasheet
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EZ-USB FX3
SuperSpeed USB Controller
AC timing parameters
Table 22
Parameter
fop
SPI timing parameters[18]
Description
Operating frequency
Cycle time
Min
0
30
Max
33
–
Units
MHz
ns
tsck
twsck
tlead
tlag
trf
tsdd
tdv
tdi
tssnh
tsdi
thoi
tdis
Clock high/low time
SSN-SCK lead time
Enable lag time
Rise/fall time
Output SSN to valid data delay time
Output data valid time
Output data invalid
Minimum SSN high time
Data setup time input
13.5
–
ns
ns
1/2 tsck[19] – 5 1.5 tsck[19] + 5
0.5
–
–
–
0
10
8
0
1.5 tsck[19] + 5
ns
ns
ns
ns
ns
ns
ns
ns
8
5
5
–
–
–
–
–
Data hold time input
Disable data output on SSN high
0
ns
Notes
18.All parameters guaranteed by design and validated through characterization.
19.Depends on LAG and LEAD setting in the SPI_CONFIG register.
Datasheet
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EZ-USB FX3
SuperSpeed USB Controller
AC timing parameters
19.7
Reset sequence
FX3’s hard reset sequence requirements are specified in this section.
Table 23
Reset and Standby timing parameters
Definition
Parameter
Conditions
Clock input
Crystal input
–
Clock input
Crystal input
Min (ms) Max (ms)
1
1
5
1
5
–
–
–
–
tRPW
tRH
Minimum RESET# pulse width
Minimum HIGH on RESET#
Reset recovery time (after which Boot loader begins
firmware download)
tRR
Time to enter standby/suspend (from the time
MAIN_CLOCK_EN/ MAIN_POWER_EN bit is set)
tSBY
tWU
tWH
–
–
1
Clock input
Crystal input
1
5
–
–
Time to wakeup from standby
Minimum time before Standby/Suspend source may
be reasserted
–
5
–
VDD
( core )
xVDDQ
XTALIN/
CLKIN
XTALIN/ CLKIN must be stable
before exiting Standby/Suspend
tRh
tRR
Mandatory
Reset Pulse
Hard Reset
RESET #
tWH
tWU
tRPW
tSBY
Standby/
Suspend
Source
Standby/Suspend source Is asserted
(MAIN_POWER_EN/ MAIN_CLK_EN bit
is set)
Standby/Suspend
source Is deasserted
Figure 29
Reset sequence
Datasheet
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EZ-USB FX3
SuperSpeed USB Controller
Package diagram
20
Package diagram
2X
0.10 C
E1
6
E
B
(datum B)
A1 CORNER
A
11 10
9
8
7
5
4
3
2
1
7
A1 CORNER
A
B
C
D
E
F
6
SD
D1
D
(datum A)
G
H
J
K
eD
L
2X
0.10 C
6
eE
TOP VIEW
SE
BOTTOM VIEW
0.20 C
DETAIL A
A1
0.08 C
C
121XØb
5
A
Ø0.15 M C A B
Ø0.08 M C
SIDE VIEW
DETAIL A
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS
SYMBOL
2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
3. "e" REPRESENTS THE SOLDER BALL GRID PITCH.
MIN.
-
NOM.
MAX.
1.20
-
A
-
4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
SIZE MD X ME.
A1
D
0.15
-
10.00 BSC
E
10.00 BSC
8.00 BSC
8.00 BSC
11
D1
E1
MD
ME
N
5.
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A
PLANE PARALLEL TO DATUM C.
6.
"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
11
121
0.30
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" OR "SE" = 0.
b
0.25
0.35
eD
eE
SD
SE
0.80 BSC
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" = eD/2 AND "SE" = eE/2.
0.80 BSC
0.00
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK
METALIZED MARK, INDENTATION OR OTHER MEANS.
7.
0.00
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER
BALLS.
001-54471 *F
CAE
O T
SHEET
OF
Figure 30
121-ball BGA package diagram
Datasheet
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EZ-USB FX3
SuperSpeed USB Controller
Ordering information
21
Ordering information
Table 24
Ordering information
GPIF II data bus
width
Operating
Ordering code
USB
SRAM (kB)
Package type
temperature
CYUSB3011-BZXC
CYUSB3012-BZXC
CYUSB3013-BZXC
CYUSB3014-BZXC
CYUSB3014-BZXI
CYUSB2014-BZXC
CYUSB2014-BZXI
USB 3.0
USB 3.0
USB 3.0
USB 3.0
USB 3.0
USB 2.0
USB 2.0
256
256
512
512
512
512
512
16-bit
32-bit
16-bit
32-bit
32-bit
32-bit
32-bit
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
121-ball BGA
121-ball BGA
121-ball BGA
121-ball BGA
121-ball BGA
121-ball BGA
121-ball BGA
21.1
Ordering code definitions
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EZ-USB FX3
SuperSpeed USB Controller
Acronyms
22
Acronyms
Table 25
Acronyms
Acronym
Description
DMA
FIFO
GPIF
HNP
I2C
direct memory access
first in, first out
general programmable interface
host negotiation protocol
inter-integrated circuit
inter IC sound
I2S
MISO
MOSI
MMC
MSC
MTP
OTG
OVP
PHY
PLL
PMIC
PVT
RTOS
SCL
master in, slave out
master out, slave in
multimedia card
mass storage class
media transfer protocol
on-the-go
overvoltage protection
physical layer
phase locked loop
power management IC
process voltage temperature
real-time operating system
serial clock line
SCLK
SD
serial clock
secure digital
SD
secure digital
SDA
SDIO
SLC
serial data clock
secure digital input / output
single-level cell
SLCS
SLOE
SLRD
SLWR
SPI
SRP
SSN
UART
UVC
USB
Slave Chip Select
Slave Output Enable
Slave Read
Slave Write
serial peripheral interface
session request protocol
SPI slave select (Active low)
universal asynchronous receiver transmitter
USB Video Class
universal serial bus
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EZ-USB FX3
SuperSpeed USB Controller
Document conventions
23
Document conventions
23.1
Units of measure
Table 26
Units of measure
Symbol
Unit of measure
°C
µA
µs
mA
Mbps
MBps
MHz
ms
ns
degree Celsius
microamperes
microseconds
milliamperes
Megabits per second
Megabytes per second
mega hertz
milliseconds
nanoseconds
ohms
pF
pico Farad
V
volts
Datasheet
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EZ-USB FX3
SuperSpeed USB Controller
Errata
24
Errata
This section describes the errata for Revision D, C and B of the FX3. Details include errata trigger conditions, scope
of impact, available workaround, and silicon revision applicability. Contact your local Infineon Sales
Representative if you have questions.
Part numbers affected
Part number
CYUSB301x-xxxx
CYUSB201x-xxxx
Device characteristics
All variants
All variants
24.1
Qualification status
Product Status: Production
24.2
Errata summary
The following table defines the errata applicability to available Rev. D EZ-USB FX3 SuperSpeed USB Controller
family devices.
Silicon
Items
Part number
Fix status
Revision
1. Turning off VIO1 during Normal, Suspend, and
CYUSB301x-xxxx
CYUSB201x-xxxx
Workaround
provided
Rev. D, C, B
Standby modes causes the FX3 to stop working.
2. USB enumeration failure in USB boot mode when
CYUSB301x-xxxx
CYUSB201x-xxxx
CYUSB301x-xxxx
CYUSB201x-xxxx
CYUSB301x-xxxx
CYUSB201x-xxxx
CYUSB301x-xxxx
CYUSB201x-xxxx
Workaround
provided
Workaround
provided
Workaround
provided
Workaround
provided
Rev. D, C, B
Rev. D, C, B
Rev. D, C, B
Rev. D, C, B
FX3 is self-powered.
3. Extra ZLP is generated by the COMMIT action in the
GPIF II state.
4. Invalid PID Sequence in USB 2.0 ISOC data transfer.
5. USB data transfer errors are seen when ZLP is
followed by data packet within same microframe.
Use FX3 in
6. Bus collision is seen when the I2C block is used as a CYUSB301x-xxxx
Rev. D, C, B single-master
configuration
master in the I2C Multi-master configuration.
CYUSB201x-xxxx
CYUSB301x-xxxx
CYUSB301x-xxxx
CYUSB301x-xxxx
7. Low Power U1 Fast-Exit Issue with USB3.0 host
Workaround
provided
Workaround
provided
Workaround
provided
Rev. D, C, B
controller.
8. USB data corruption when operating on hosts with
Rev. D, C, B
poor link quality.
9. Device treats Rx Detect sequence from the USB 3.0
Rev. D, C, B
host as a valid U1 exit LFPS burst.
No
Rev. D, C, B workaround
needed
10. I2C Data Valid (tVD:DAT) specification violation at
CYUSB301x-xxxx
CYUSB201x-xxxx
400 kHz with a 40/60 duty cycle.
11. FX3 Device does not respond correctly to Port
Workaround
Rev. D, C, B
Capability Request from Host after multiple power CYUSB301x-xxxx
provided
cycles.
Datasheet
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EZ-USB FX3
SuperSpeed USB Controller
Errata
1. Turning off VIO1 during Normal, Suspend, and Standby modes causes the FX3 to stop working.
Problem definition
Turning off the VIO1 during Normal, Suspend, and Standby modes will cause the FX3
to stop working.
Parameters affected NA
Trigger condition(s) This condition is triggered when the VIO1 is turned off during Normal, Suspend, and
Standby modes.
Scope of impact
Workaround
Fix status
FX3 stops working.
VIO1 must stay on during Normal, Suspend, and Standby modes.
No fix. Workaround is required.
2.USB enumeration failure in USB boot mode when FX3 is self-powered.
When FX3 is self-powered and not connected to the USB host, it enters low-power
mode and does not wake up when connected to USB host afterwards. This is because
the bootloader does not check the VBUS pin on the connector to detect USB
connection. It expects that the USB bus is connected to the host when it is powered on.
Problem definition
Parameters affected NA
Trigger condition(s) This condition is triggered when FX3 is self-powered in USB boot mode.
Scope of impact
Workaround
Fix status
Device does not enumerate
Reset the device after connecting to USB host.
No fix. Workaround is required.
3.Extra ZLP is generated by the COMMIT action in the GPIF II state.
When COMMIT action is used in a GPIF-II state without IN_DATA action then an extra
zero length packet (ZLP) is committed along with the data packets.
Parameters affected NA
Problem definition
This condition is triggered when COMMIT action is used in a state without IN_DATA
action.
Trigger condition(s)
Scope of impact
Workaround
Fix status
Extra ZLP is generated.
Use IN_DATA action along with COMMIT action in the same state.
No fix. Workaround is required.
Datasheet
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EZ-USB FX3
SuperSpeed USB Controller
Errata
4.Invalid PID Sequence in USB 2.0 ISOC data transfer.
When the FX3 device is functioning as a high speed USB device with high bandwidth
isochronous endpoints, the PID sequence of the ISO data packets is governed solely by
the isomult setting. The length of the data packet is not considered while generating
the PID sequence during each microframe. For example, even if a short packet is being
sent on an endpoint with MULT set to 2; the PID used will be DATA2.
Problem definition
Parameters affected NA
Trigger condition(s) This condition is triggered when high bandwidth ISOC transfer endpoints are used.
Scope of impact
Workaround
Fix status
ISOC data transfers failure.
This problem can be worked around by reconfiguring the endpoint with a lower
isomult setting prior to sending short packets, and then switching back to the original
value.
No fix. Workaround is required.
5.USB data transfer errors are seen when ZLP is followed by data packet within same microframe.
Some data transfer errors may be seen if a ZLP is followed very quickly (within one
microframe or 125 µs) by another data packet on a burst enabled USB IN endpoint
operating at super speed.
Problem definition
Parameters affected NA
Trigger condition(s) This condition is triggered in SuperSpeed transfer with ZLPs
Scope of impact
Workaround
Fix status
Data failure and lower data speed.
The solution is to ensure that some time is allowed to elapse between a ZLP and the
next data packet on burst enabled USB IN endpoints. If this cannot be ensured at the
data source, the CyU3PDmaChannelSetSuspend() API can be used to suspend the
corresponding USB DMA socket on seeing the EOP condition. The channel operation
can then be resumed as soon as the suspend callback is received.
No fix. Workaround is required.
6.Bus collision is seen when the I2C block is used as a master in the I2C Multi-master configuration.
When FX3 is used as a master in the I2C multi-master configuration, there can be
occasional bus collisions.
Problem definition
Parameters affected NA
This condition is triggered only when the FX3 I2C block operates in Multi-master
Trigger condition(s)
configuration.
Scope of impact
Workaround
Fix status
The FX3 I2C block can transmit data when the I2C bus is not idle leading to bus collision.
Use FX3 as a single master.
No fix.
Datasheet
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EZ-USB FX3
SuperSpeed USB Controller
Errata
7.Low Power U1 Fast-Exit Issue with USB3.0 host controller.
When FX3 device transitions from Low power U1 state to U0 state within 5 µs after
entering U1 state, the device sometimes fails to transition back to U0 state, resulting
in USB Reset.
Problem definition
Parameters affected NA
Trigger condition(s) This condition is triggered during low power transition mode.
Scope of impact
Workaround
Fix status
Unexpected USB warm reset during data transfer.
This problem can be worked around in the FW by disabling LPM (Link Power
Management) during data transfer.
FW workaround is proven and reliable.
8.USB data corruption when operating on hosts with poor link quality.
If FX3 is operating on a USB 3.0 link with poor signal quality, the device could send
corrupted data on any of the IN endpoints (including the control endpoint).
Problem definition
Parameters affected NA
Trigger condition(s) This condition is triggered when the USB3.0 link signal quality is very poor.
Scope of impact
Workaround
Fix status
Data corruption in any of the IN endpoints (including the control endpoint).
The application firmware should perform an error recovery by stalling the endpoint on
receiving CYU3P_USBEPSS_RESET_EVT event, and then stop and restart DMA path
when the CLEAR_FEATURE request is received.
Note: SDK versions 1.3.3 and above internally manages the DMA transfers and
performs the endpoint reset when potential error conditions are seen. For more details
in application firmware, please refer to GpiftoUsb example available with SDK.
FW Work-around is proven and reliable.
9.Device treats Rx Detect sequence from the USB 3.0 host as a valid U1 exit LFPS burst.
The USB 3.0 PHY in the FX3 device uses an electrical idle detector to determine whether
LFPS is being received. The duration for which the receiver does not see an electrical
Problem definition
idle condition is timed to detect various LFPS bursts. This implementation causes the
device to treat an Rx Detect sequence from the USB host as a valid U1 exit LFPS burst.
Parameters affected NA
This condition is triggered when the USB host is initiating an Rx Detect sequence while
the USB 3.0 Link State Machine on the FX3 is in the U1 state. Since the host will only
Trigger condition(s) perform Rx Detect sequence in the RX Detect and U2 states, the error condition is seen
only in cases where the USB link on the host has moved into the U2 state while the link
on FX3 is in the U1 state.
FX3 moves into Recovery prematurely leading to a Recovery failure followed by Warm
Reset and USB re-enumeration. This sequence can repeat multiple times resulting in
data transfer failures.
Scope of impact
FX3 can be configured to transition from U1 to U2 a few microseconds before the host
does so. This will ensure that the link will be in U2 on the device side before the host
attempts any Rx Detect sequence; thereby preventing a false detection of U1 exit.
Workaround
Fix status
Workaround is implemented in FX3 SDK library 1.3.4 and above.
Datasheet
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EZ-USB FX3
SuperSpeed USB Controller
Errata
10. I2C Data Valid (tVD:DAT) specification violation at 400 kHz with a 40/60 duty cycle.
I2C Data Valid (tVD:DAT) parameter at 400 kHz with a 40/60 duty cycle is 1.0625 µs,
Problem definition
which exceeds the I2C specification limit of 0.9 µs.
Parameters affected NA
Trigger condition(s) This violation occurs only at 400 kHz with a 40/60 duty cycle of the I2C clock.
Setup time (tSUDAT) is met with a huge margin for the transmitted data for 400 kHz and
so tvd:DAT violation will not cause any data integrity issues.
Scope of impact
Workaround
Fix status
No workaround needed.
No fix needed.
11.FX3 Device does not respond correctly to Port Capability Request from Host after multiple power
cycles.
During multiple power cycles, sometimes the FX3 device does not respond correctly
to the Port Capability request (Link Packet) from the USB Controller. In view of this,
FX3 does not get the subsequent Port Configuration request from the USB controller,
resulting in SS.Disabled state. The device fails to recover from this state and finally
results in enumeration failure.
Problem definition
Parameters affected NA
This condition is triggered when the FX3 provides an incorrect response to the Port
Trigger condition(s)
Scope of impact
Capability request from the host.
Device fails to enumerate after multiple retries.
Since the host does not send the Port Configuration request to the FX3 device, it causes
a Port Configuration request timeout interrupt to be triggered in the device. This
interrupt is handled in the FX3 SDK 1.3.4 onwards to generate and signal
CY_U3P_USB_EVENT_LMP_EXCH_FAIL event to the application. This event should be
handled in the user application such that it does a USB Interface Block Restart. Refer
the Knowledge Base Article (KBA225778) for more details and the firmware
workaround example project.
Workaround
Fix status
Suggested firmware work-around is proven and reliable.
Datasheet
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EZ-USB FX3
SuperSpeed USB Controller
Revision history
Revision history
Document
Date
Description of changes
revision
**
2009-03-06
New data sheet.
Updated the part# from CYX01XXBB to CYUSB3011-BZXI
Changed status from “ADVANCE” to “ADVANCE INFORMATION”
In page 1, the second bullet (Flexible Host Interface), add “32-bit, 100 MHz”
to first sub bullet.
In page 1, changed the second bullet “Flexible Host Interface” to General
Programmable Interface”.
In page 1, the second bullet (Flexible Host Interface), removed “DMA Slave
Support” and “MMC Slave support with Pass through Boot” sub bullets.
In page 1, third bullet, changed “50 A with Core Power” to “60 A with Core
Power”
In page 1, fifth bullet, added “at 1 MHz”
In page 1, seventh bullet, added “up to 4 MHz” to UART
In page 1, Applications Section, move “Digital Still Cameras” to second line.
In page 1, Applications Section, added “Machine Vision” and Industrial
Cameras”
*A
2009-09-01
Added ™ to GPIF and FX3.
In page 1, updated Logic Block Diagram.
In page 2, section of “Functional Overview”, updated the whole section.
In page 2, removed the section of “Product Interface”
In page 2, removed the section of “Processor Interface (P-Port)”
In page 2, removed the section of “USB Interface (U-Port)”
In page 2, removed the section of “Other Interfaces”
In page 2, added a section of “GPIF II”
In page 2, added a section of “CPU”
In page 2, added a section of “JTAG Interface”
In page 2, added a section of “Boot Options”
In page 2, added a section of “ReNumeration”
In page 2, added a section of “Power”
In the section of “Package”, replaced “West Bridge USB 3.0 Platform” by FX3.
In the section of “Package”, added 0.8 mm pitch in front of BGA.
Added Pin List (Table 1)
Changed title to EZ-USB™ FX3: SuperSpeed USB Controller
Features:
Added the thrid bullet “Fully accessible 32-bit ARM9 core with 512kB of
embedded SRAM”
*B
*C
2009-09-29
2009-12-08
Added the thrid line “EZ USB™ Software and DVK for easy code
development”
Table 1: Pin 74, corrected to NC - No Connect.
Added data sheet to the USB 3.0 EROS spec 001-51884. No technical
updates.
Datasheet
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2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
Revision history
Document
Date
Description of changes
revision
Changed status from Advance to Preliminary.
Changed part number from CYUSB3011 to CYUSB3014
Added the following sections: Power, Digital I/Os, Digital I/Os,
System-level ESD, DC specifications, AC timing parameters, Reset
sequence, Package diagram
Added DC specifications table
*D
2010-11-08
Updated feature list
Updated Pin List
Added support for selectable clock input frequencies.
Updated block diagram
Updated part number
Updated package diagram
Updated Slave FIFO protocol and added ZLP signaling protocol
Changed GPIFII asynchronous tDO parameter
Changed Async Slave FIFO tOE parameter
Changed Async Slave FIFO tRDO parameter
Added tCOE parameter to GPIFII Sync mode timing parameters
Renamed GPIFII Sync mode tDO to tCO and tDO_ss0 to tCO_ss0
Modified description of GPIFII Sync tCO (previously tDO) parameter
Changed tAH(address hold time) parameter in Async Slave FIFO modes to
be with respect to rising edge of SLWR#/SLRD# instead of falling edge.
Correspondingly, changed the tAH number.
*E
2011-03-24
Removed 24 bit data bus support for GPIFII.
*F
2011-04-07
2011-04-20
Minor ECN - Release to web. No content changes.
Minor updates in Features.
*G
Updated GPIFII Synchronous Timing diagram. Added SPI Boot option.
Corrected values of R_USB2 and R_USB3. Corrected TCK and TRST#
pull-up/pull-down configuration. Minor updates to block diagrams.
Corrected Synchronous Slave FIFO tDH parameter.
*H
*I
2011-04-06
2011-07-07
Minor ECN - Correct ECN number in revision *F. No content changes.
Changed datasheet status from Preliminary to Final.
Changed tWRPE parameter to 2 ns
Updated tRR and tRPW for crystal input
Added clarification regarding IOZ and IIX
Updated Sync SLave FIFO Read timing diagram
Updated SPI timing diagram
Removed tGRANULARITY parameter
Updated I2S Timing diagram and tTd parameter
Updated 121-ball BGA package diagram.
*J
2011-12-06
2012-02-24
Added clarification regarding VCC in DC Specifications table
In Power Modes description, stated that VIO1 cannot be turned off at any
time if the GPIFII is used in the application
Updated Absolute Maximum Ratings
Added requirement for by-pass capacitor on U3RXVDDQ and U3TXVDDQ
Updated tPEI parameter in Async Slave FIFO timing table
Updated Sync Slave FIFO write and read timing diagrams
Updated I2C interface tVD:ACK parameter for 1MHz operation
Clarified that CTL[15] is not usable as a GPIO
*K
Corrected typo in the block diagram.
Datasheet
76
001-52136 Rev. *Z
2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
Revision history
Document
Date
Description of changes
revision
Changed part number to CYUSB301X.
Added 256 KB range for embedded SRAM.
Updated Functional Overview, Other Interfaces, and Clocking sections.
Added Pin List for CYUSB3011 and CYUSB3013 parts.
Updated Ordering information:
*L
2012-08-16
2012-12-20
Updated part numbers.
*M
Updated 121-ball BGA package diagram to current revision.
Included Commercial Temperature Range related information in all
instances across the document.
Included 131-ball WLCSP Package related information in all instances
across the document.
Updated Pin description:
*N
2013-05-31
Updated Table 7.
Updated Package diagram:
Added 131-ball WLCSP Package Diagram.
Updated Ordering information:
Updated part numbers.
Updated Package diagram:
spec 001-62221 – Changed revision from *B to *C.
Updated to new template.
*O
*P
2014-05-02
2014-08-14
Completing Sunset Review.
Added CYUSB201x MPNs, ball map, and pin list to the datasheet.
Datasheet
77
001-52136 Rev. *Z
2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
Revision history
Document
Date
Description of changes
revision
Updated Features:
Updated description.
Updated Logic block diagram.
Updated Functional description:
Added “
For a complete list of related documentation, click here.” at the end.
Added More information.
Updated Functional overview:
Updated Application examples:
Updated Figure 1.
Updated Figure 2.
Updated USB interface:
Updated description.
Removed Figure “USB Interface Signals”.
Updated Reset:
Updated Hard reset:
Updated description.
Updated Pin configurations:
Updated Figure 6.
Updated Pin description:
*Q
2015-02-24
Updated Table 7:
Updated entire table.
Modified CVDDQ power domain description.
Removed Table “CYUSB3011 and CYUSB3013 Pin List (GPIF II with 16-bit
Data Bus Width)”.
Removed Table “CYUSB2014 Pin List (GPIF II with 32-bit Data Bus Width)”.
Updated DC specifications:
Added ISS parameter and its details.
Updated Slave FIFO interface:
Updated Synchronous Slave FIFO Read sequence description:
Updated Figure 11.
Updated Synchronous Slave FIFO Write sequence description:
Updated Figure 12.
Updated Table 15.
Updated AC timing parameters:
Added Host Processor Interface (P-Port) timing.
Updated Acronyms.
Added Errata.
Replaced West Bridge Benicia with FX3.
Updated Slave FIFO interface:
Updated Synchronous Slave FIFO Read sequence description:
Updated Figure 11.
Updated Synchronous Slave FIFO Write sequence description:
Updated Figure 12.
*R
2015-03-27
Updated Table 15:
Updated minimum value of tSSD parameter.
Added tACCD, tFAD parameters and their details.
Datasheet
78
001-52136 Rev. *Z
2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
Revision history
Document
Date
Description of changes
revision
Updated Electrical specifications:
Updated DC specifications:
Updated Table 8 (Removed ISS parameter and its corresponding details).
Updated Errata:
*S
*T
2016-04-07
2016-06-29
Updated Errata summary:
Updated description.
Added item “Bus collision is seen when the I2C block is used as a master in
the I2C Multi-master configuration.” and its corresponding details in the
table.
Updated AC timing parameters:
Updated GPIF II timing:
Updated Table 13:
Changed maximum value of tCO parameter from 8 ns to 7 ns.
Updated Slave FIFO interface:
Updated Synchronous Slave FIFO Write sequence description:
Updated Table 15:
Changed maximum value of tCO parameter from 8 ns to 7 ns.
Updated to new template.
*U
*V
2017-04-20
2018-02-19
Updated Cypress Logo and Copyright.
Removed 131-ball WLCSP Package related information in all instances
across the document.
Updated Package diagram:
spec 001-54471 – Changed revision from *E to *F.
Updated to new template.
Datasheet
79
001-52136 Rev. *Z
2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
Revision history
Document
Date
Description of changes
revision
Updated Features:
Updated description.
Updated More information:
Updated description.
Updated Functional overview:
Updated description.
Updated USB interface:
Removed “EZ-Dtect”.
Updated JTAG interface:
Updated description.
Updated Other interfaces:
Updated I2S interface:
Updated description.
Updated Boot options:
Updated description.
Updated Power:
Updated description.
Updated Table 6.
Updated Pin configurations:
Updated Figure 6.
*W
2018-09-25
Updated Figure 7.
Updated Pin description:
Updated Table 7.
Updated Electrical specifications:
Updated DC specifications:
Updated Table 8.
Added Table 9.
Added Thermal characteristics.
Updated AC timing parameters:
Added GPIF II lines AC characteristics at 100 MHz.
Added GPIF II PCLK jitter characteristics.
Updated Errata:
Updated description.
Updated Errata summary:
Updated description.
Updated details in “Silicon Revision” column for all items in the table.
Added items “Low Power U1 Fast-Exit Issue with USB3.0 host controller.”,
“USB data corruption when operating on hosts with poor link quality.”,
“Device treats Rx Detect sequence from the USB 3.0 host as a valid U1 exit
LFPS burst.”, “I2C Data Valid (tVD:DAT) specification violation at 400 kHz
with a 40/60 duty cycle.” and their corresponding details in the table.
Updated Pin description:
Updated Table 7.
Updated Errata:
Updated Errata summary:
Updated description.
*X
2018-12-17
Added item “FX3 Device does not respond correctly to Port Capability
Request from Host after multiple power cycles.” and its corresponding
details in the table.
Datasheet
80
001-52136 Rev. *Z
2022-09-29
EZ-USB FX3
SuperSpeed USB Controller
Revision history
Document
Date
Description of changes
revision
Updated Document Title to read as “CYUSB301X, CYUSB201X, EZ-USB FX3
SuperSpeed USB Controller”.
Added a note on Errata in page 2.
Updated More information:
Updated description.
Added hyperlink in required places.
Updated Functional overview:
Updated Application examples:
Updated Figure 1.
*Y
2022-08-11
Updated Figure 2.
Updated USB interface:
Updated description.
Updated Boot options:
Updated description.
Updated Errata:
Updated Errata summary:
Updated details in “[Part Number]” column for Errata items 7, 8, 9, and 11.
Migrated to Infineon template.
Updated Features:
Updated description.
Updated More information:
Updated description.
Updated hyperlinks.
Updated Functional overview:
Updated description.
Updated USB interface:
Updated description.
*Z
2022-09-29
Updated Boot options:
Updated description.
Updated Table 2.
Updated Electrical specifications:
Updated Absolute maximum ratings:
Updated details corresponding to “Latch-up current”.
Updated Pin description:
Updated Table 7.
Datasheet
81
001-52136 Rev. *Z
2022-09-29
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Edition 2022-09-29
Published by
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001-52136 Rev. *Z
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