EIB-TP-UART-IC_技术文档

TECHNICAL DATA

EIB-TP-UART-IC

Features

VB -

Tx0

11

12

13

14

15

16

17

18

19

20

VB +

VSP

CSA

VCC

DIV

10

9

8

7

6

5

4

3

2

1

· Signaling for standard UART (LSB-First,

Idle is 1)

· Baud rate 9600 or 19200 baud for the

communication:

Rx IN

MODE 0

MODE 1

TEST MODE

X 1

TP - UART <--> Host - Controller

· Direct coupling to host controller (TxD,

RxD), or via optical couplers (optional)

SAVE

TSTIN

VIF

· 2 - wire protocol with software handshake

· Buffering of send frames

X 2

TSTOUT

RxD

RESn

TxD

· No critical timing during transmission

· 64 Byte telegram buffer

· Operating temperature range:

-25°C to 85°C

· Supervision of EIB bus voltage

GENERAL DESCRIPTION

The TP - UART - IC (Twisted Pair - Universal Asynchronous Receive Transmit - IC) is a

transceiver which supports the connection of microcontrollers of sensors, actuators, or other

applications to the EIB (European - Installation - Bus).

This module supports every transmit- and receive - function and also the high ohmic decoupling

of energy from bus line. It generates further a stabilized 3.3V or 5V supply to use by a host

controller. Up to 256 subscribers can be connected to one bus line.

An UART interface is realized for communication with a host controller. The coupling can be

realized directly or via optical couplers.

The TP - UART - IC consists of two main parts: the digital part (UART - Interface) and the analog

part ( analog circuit part).

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TP-UART-IC

GENERAL DRAWING

A - Bus

B - Bus

+

-

Power

Supply

230V / 50Hz

30V

TP-UART-

IC

TP-UART-

IC

TP-UART-

IC

Optional

RxD

TxD

RxD

TxD

RxD

TxD

Electrical Isolation

(Optocoupler)

Application

...

Optional Power Supply

Bus Device 1

Bus Device 2

Bus Device n

STRUCTURE of TP - UART - IC

(Block Diagram:)

Host-Controller

RESn

RxD

TxD

TSTIN_BDS

(Baud rate)

UART-Receiver

UART-Transmitter

64 Byte

Telegram-

Sendbuffer

Digital - Part

TSTout

Mode 0

1 Bytebuffer

(receive)

State-Byte

ACK-Flags

Controll-Logic

Mode 1

EIB-Receiver

Filter

4,9152 MHz

0,05 %

EIB-Transmitter

EIB-Transmit RxD3

EIB-ReceiveTxD3

Analog - Part

Transmit

Receive

Power Supply

5 V Regulator

EIB

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TP-UART-IC

1

The ANALOG - PART

1.1 General Device Specification

1.1.1 Absolute Maximum Ratings

All voltages are referring to VB-. Currents are declared positive in case of flowing into pin.

Symbol

VB+

V_CC

Parameter

positive line voltage

positive voltage supply (internal or external supply)

positive external voltage supply

interstate voltage (generated by on-chip regulator)

voltage on pin Tx0

voltage on pin RxIN

voltage on low voltage pins MODE0, MODE1, TSTIN,

TESTMODE

Min

-0.5

-15

Max

45

7

13

45

V_CC+0.5

Unit Note

V

1)

2)

1)

1) 4)

V_IF

V_VSP

V_TxO

V_RxIN

V_LV1

-0.5

V_LV2

voltage on low voltage pins TxD, RESn, TSTOUT, X1,

X2, RxD

junction temperature

-0.5

-65

V_IF+0.5

V

o

170

J _j

J _S

C

o

storage temperature

V_ESD

max. ESD stress voltage

± 1000

V

3)

I_LATCHUPstatic current for latchup initialization

± 50

58.5

mA

K/W

W

R_th

P_V

thermal resistance of the SOIC-20 package

maximum power dissipation

71.5

1

1) During surge impulse is allowed and guaranteed by ext. elements:

-20 V for

2 µsec and

65 V for 150 µsec

2) Allowed voltage relations: (a) V_CCand V_VSPnormal / VB+ and V_IFcan be 0 V

(b) V_VSPnormal / V_CC, VB+ and V_IFcan be 0 V

(c) V_IFnormal / V_CC, VB+ and V_VSPcan be 0 V

The combination: V_CCnormal and V_VSP= 0 V is not allowed!

3) Human body model: 100 pF, 1.5 kW

4) Dynamic via C_REC= 47 nF in case of switching-on the bus voltage

1.1.2 Recommended Operating Conditions

Symbol

VB+

Parameter

positive line voltage

positive voltage supply for external supply

(digital test modes with SHB = 0)

positive external supply voltage

ambient temperature

Min

20

4.75

Max

33

5.25

Unit Note

V

1)

V_CC

V_IF

J _amb

3.0

-25

5.25

85

V

o

C

f_clk

clock frequency (external quartz)

4.9152

MHz

1) DC voltage of bus, with signal and compensation pulse 11 V ... 45 V

1.1.3 Humidity Level

The valid susceptibility against humidity is described by JEDEC JESD22-A112, table 1, level

5.

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TP-UART-IC

1.2 DC and AC Characteristics

o

The following parameters are valid in the ambient temperature range J _amb= -25 C to 85 C

and for bus voltage VB+ = 20 to 33 V if it is not otherwise declared. When the bus voltage is

lower than 20 V and no RESET is active then the normal functionality must be fulfilled, but

the parameters may be outside the limits.

1.2.1 Bus Pins VB+ and VB- (Pins 10, 11)

Via these pins the ASIC is connected to the bus line. VB- represents the reference potential.

Symbol Parameter

Min

-0.5

Max

45

1

Unit Note

V_VB+

I_normal

positive line voltage

current consumption in analog mode (without clock)

current consumption in normal mode (with clock)

V

1)

mA

1.6

mA 4,9152 MHz

1) during surge impulse is allowed and guaranteed by ext. Elements: -20 V for 2 µs and 65 V for 150 µs

1.2.2 Buffer Voltage VSP (Pin 9)

The ASIC delivers a supply voltage of 5 volts to external loads. In order to prevent a rapid

change of bus current as a result of a rapid change of the load an external capacitor at the

pin VSP is used for energy storage. The static voltage is adjusted to app. 8,8 V (8,2 ...9,2)

by an internal regulator.

Symbol Parameter

Min

5.76

80

Max

13

Unit

V

µF

Note

1)

2)

V_VSP

C_VSP

Energy buffer voltage

External storage capacitor

1) due to the limited current changing rate an overshoot of V_VSPafter load change may occur

2) recommended 100 mF; must be larger than the capacitor at VCC

1.2.3 Current Controlling Pin CSA (Pin 8)

An external capacitor at this pin prevents a quick change of ASIC current in case of quick

changing bus voltage VB+ or load current IVCC. The ASIC current changes with a rate of

max. 0,5 mA/ms (CCSA = 47 nF).

Symbol

CCR

Parameter

Min

0.2

Max

0.5

Unit

mA/ms

Note

1)

max. current changing rate (ext. Start, C_CSA= 47 nF)

1)tolerance of capacitor C_CSA= 47nF/50V +/- 5%

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TP-UART-IC

1.2.4 Supply Pin VCC (Pin 7)

The pin VCC delivers the internal generated voltage supply to external loads. An external

short-circuit from the VCC pin to GND will not cause a destruction of the ASIC.

Symbol Parameter

Min

Max

Unit

Note

V_VCC

Voltage supply (generated by the ASIC or external

4.75

5.25

V

1)

source in case of digital test modes)

External storage capacitor

External load at VCC

C_VCC

I_VCC

6,8

10

µF

mA

+/-20 %

2)

1) VB+ ³ 11 V

2) If there is a current leap I_Leapwith a slope greater than 1 mA/ms the following formulas have to be

applied:

I_Statis the static current, i.e. slope not greater than 1 mA/ms

I

_Stat£ 3 mA;

I_Leap£ (3 mA – I_Stat) + 5 mA

I_Leap£ 8 mA - I_Stat

I_Leap£ 3 mA

3mA < I_Stat£ 5 mA;

I_Stat> 5 mA;

1.2.5 Receive Pin RxIN (Pin 13)

The Receive Pin RxIN is coupled to the EIB bus by an external capacitor.

Symbol Parameter

Min

44.5

Max

49.5

Unit

Note

nF typ.47 nF¹⁾

C_REC

external coupling capacitor

¹⁾external capacitor 47 nF/50V ± 5%

1.2.6 Transmit Pin TxO (Pin 12)

The transmit pin is connected to EIB via external resistor of typ. 68W/1W (see Typical

Application Circuits).

Symbol Parameter

Min

-6

Max

-9

Unit Note

1)

V_TRANS

transmit voltage

V

1) related to VB+

1.2.7 Supply Pin VIF (Pin 3)

The Pin VIF is used as supply voltage for the pins TxD, RxD, RESn, TSTOUT, X1, X2 and

determines their high input or output level.

Symbol Parameter

Min

3

10

Max

5.5

Unit

V

nF

Note

1)

2)

V_IF

external supply voltage for interface

external storage capacitor

C_VIF

1) Typical supply voltages: 3.3 V or 5 V

2) Recommended

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TP-UART-IC

1.2.8 Oscillator Pins X1 and X2 (Pins 17, 18)

The oscillator pins X1 and X2 are used to connect directly a quartz of 4.9152 MHz without

additional external capacitors. These pins are ESD protected to VB - and VIF.

Symbol Parameter

Min

-0.5

0

Max

Unit

V

Note

V_X1/2

V_IL

Oscillator voltage at X1 and X2

VIF + 0.5

0.25 * VIF

1.0 * VIF

4,9152

Voltage range for input low level

Voltage range for input high level

Clock frequency

V_IH

f_clk

0.75 * VIF

2,4576

MHz

1)

1) 4,9152 MHz (DIV = VCC) or 2.4576 MHz (DIV = VB -); Tolerance: ±0,05 %; no other clock frequencies

Operation

Mode

Normal Mode with

external Clock

Analog Mode

X1

Clock

VB-

X2

open

1.2.9 Internal Clock Divider Pin DIV (Pin 6)

This input pin activates an internal 2:1 clock divider. If a 4.9152 MHz clock is used (quartz or

external clock) then pin DIV must be connected to VCC. If an 2.4576 MHz clock is used (only

external clock) then this pin must be connected to VB -.

Symbol Parameter

Min

Max

Unit

Note

V_IL

V_IH

voltage range for input low level

voltage range for input high level

0

0.2 * VCC

1.0 * VCC

0.8 * VCC

1.2.10 Interface Pin RxD (Pin 20)

The UART interface input pin RxD receives the information from host controller to

control the transmitter of the ASIC. This pin is an input pin with pull-down resistor. The

switching levels are derived from external voltage supply VIF. This pin is ESD protected to

VB- and VIF.

In normal mode: RxD = LOW à RxD3 = HIGH à transmitter switches on

In analog mode: RxD = HIGH à RxD3 = HIGH à transmitter switches on

Symbol Parameter

Min

Max

0.2 * VIF

1.0 * VIF

0.4 * VIF

450

Unit

Note

V_IL

V_ICH

V_hyst

voltage range for input low level

voltage range for input high level

hysteresis for switching level

0

0.8 * VIF

0.1 * VIF

150

1)

value of internal pull-down resistor

R_PullDown

kW

typ.220 kW

1) switching level appr. VIF/2, i.e. VIF/2 ± V_hyst/2

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TP-UART-IC

1.2.11 Interface Pin TxD (Pin 1)

The UART interface output pin TxD transmits the information to host controller. The high

output level is derived from external voltage supply VIF. This pin is ESD protected to VB-

and VIF.

In normal mode: LOW pulse at EIB bus à TxD3 = HIGH à TxD = LOW

In analog mode: LOW pulse at EIB bus à TxD3 = HIGH à TxD = HIGH

Symbol Parameter

Min

VIF - 0.8

Max

Unit

V

Note

V_OH

V_OL

t_r,t_f

output voltage high

output voltage low

rise time, fall time (10 % « 90 %)

I_OH= -5 mA

I_OL= 5 mA

C_L= 150 pF

0.5

100

V

ns

1.2.12 Reset Pin RESn (Pin 2)

This pin is an I / O pin with internal pull - up resistor to VIF.

In case of a reset the reset pin RESn delivers an active LOW signal to external host

controller. The output driver is realized as open drain (NMOS - transistor). The reset state

RESn = LOW can be caused by an internal RESET or by an external RESET due to forcing

an active LOW to the pin RESn. The switching levels are derived from external voltage

supply VIF. This pin is ESD protected to VB - and VIF.

Symbol Parameter

R_PullUpvalue of internal pull-up resistor to VIF

V_RESmaxmaximum voltage at RES pin

Min

10

Max

25

Unit

kW

V

Note

VIF + 0.5

0.2 * VIF

1.0 * VIF

0.4 * VIF

0.2

V_IL

V_IH

V_hyst

V_OL

voltage range for input low level

voltage range for input high level

hysteresis for switching level

output low voltage at 1V <= VCC < 4 V, I_OL= 1 mA

output low voltage at VCC <= 1V, VIF > 3 V,

I_OL= 1 mA

0

0.8 * VIF

0.1 * VIF

1)

V

0.2

V_OL

output low voltage at VCC >= 4 V, I_OL= 3 mA

0.4

V

1) Switching level appr. VIF/2, i.e. VIF/2 ±V_hyst/2

1.2.13 Save PIN SAVE (Pin 5)

This pin is an NMOS open drain output with internal pullup resistor to VIF.

In case of break-down of the bus voltage for more than typ. 1.5 ms (save condition) this pin

delivers an active LOW signal to external host electronic. This pin is ESD protected to VB-

and VIF.

Symbol Parameter

Min

10

Max

25

VIF + 0.5

0.4

Unit

kW

V

ms

Note

R_PullUp

V_max

V_OL

Value of internal pull-up resistor to VIF

maximum voltage at SAVE pin

Output LOW voltage at VCC >= 4V

Delay from VB+ break-down to SAVE= LOW

I_OL= 3 mA

Typ. 1.5 ms

t_FRG2

0.7

3

In order to reach a Buffertime of at least 60 ms for VCC (I_VCC£ 10 mA) the capacitor at VSP has to

be 470 mF ±20 %

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TP-UART-IC

2

Modes of Operation

2.1 Interface to the HOST Controller

TP - UART - IC

Analog -

Part

TxD

RxD

Digital -

Part

HOST -

Controller

EIB

TxD3

RxD3

Normal Mode:

IDLE = HIGH

IDLE = LOW

IDLE = HIGH

IDLE = LOW

Bus Coupler

Mode:

2.2 Selection of Different Modes of Operation

It is possible to choose two different modes of operation: the normal mode and the analog

mode. To work in one of those modes you have to adjust the mode control pins as it is

shown in following table, in which is also demonstrated the usage of other pins:

Operating

Modes

Mode Control Pins

Other Pins

Mode0

(Pin 14)

Mode1

(Pin 15)

1

Testmode

(Pin 16)

TSTin_BDS

TSTout_TW

(Pin 19)

(Pin 4)

1

0

= 1: 9.600 Baud

= 0: 19.200 Baud

= 1: Temp. Warning¹⁾

--> TxO disabled

= 0: Temp. is OK

= 1: Temp. warning¹⁾²⁾

--> TxO disabled

= 0: Temp. is OK

Normal Mode

Analog Mode

1

0

do not care!

(à 19.200 Baud)

¹⁾After a Temperature Warning was recognized, a second must at least be maintained until the next

telegram is sent.

²⁾Transmission is stopped immediately by the TP_UART_IC.

2.2.1 Normal Mode

In the ‘normal’ operation mode both parts, digital and analog part, are working. The Idle-level

on the UART-interface is 1.

(As it is shown in the above standing figure, in chapter 2.1)

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TP-UART-IC

2.2.2 Analog / Bus Coupler Mode

In the ‘analog’ operation mode the analog part just works. The Idle-level on the UART-

interface is 0.

(As it is shown in the above standing figure, in chapter 2.1)

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TP-UART-IC

3

The DIGITAL - PART

3.1 Relationship to ISO-Reference-Model

ISO - Layer

EIB - UART - Layer

Applikation - Layer

Host -

Contoller

Transport - Layer

Network - Layer

Logical Link -

Link -

Layer

Control

TP-

UART - Digital - Part

UART - Analog - Part

Media - Access

Control

UART-

IC

Physical - Layer

Tasks of the Logical Link - Control in:

TP - UART - IC :

Host - Controller :

Checksum, Parity, Immediate Acknowledge, Repetition, Timing

Checksum, Parity, Addressing, Length

3.2 UART - Interface

3.2.1 Configuration and Timing

The TP-UART-IC has an UART-interface to transmit received EIB-telegrams. The baud rate

is as it was mentioned before 19.2 or 9.6 kbaud.

The UART-interface has the following firm telegram structure:

1 start bit (= 0) / 8 data bits (LSB first) / 1 parity bit / 1 stop bit (= 1).

The signals can be transmit without a break and the Idle-level is 1.

The parity bit of every signal is checked while down loading and faults, which can appear,

are transmitted to the host controller. The check mechanism runs also while receiving of

telegrams from the EIB, but here isn’t any possibility to transmit a fault to the host controller.

In those cases the host controller has to recognize the parity faults in the transmitted

telegrams by its own.

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TP-UART-IC

The UART-interface works with a clock frequency of 307,2 kHz, if it is chosen 9.6 kbaud (32

sample spots per bit), or 614,4 kHz, if it is chosen 19.2 kbaud (32 sample spots per bit).

3.2.2 Resetbehavior

After connecting the operating voltage the TP-UART-IC generates an active reset

(level 0 V) at pin RESn. This is valid for all modes. If Normal Mode is activated the following

will happen at the UART-interface.

TxD will be 0 as long as there was no bus signal on the EIB for 40 Tbit (1 Tbit = 1/9600 s;

Attention: The bittime of RxD/TxD depends on the adjusted baudrate at the UART-interface,

for example 1 Tbit or 0,5 Tbit). This results in a complete time of 40 Tbit + 12 Tbit = 5,42 ms.

Then TxD changes for 1 Tbit to 1 and following the service TPUART-Reset.Indication is

transmitted. This signal behavior on TxD appears after each reset.

3.2.3 UART-Protocol Definition

The protocol between TP-UART-IC and the application controller is a two wire protocol with

software handshake. Each data byte transmitted to the TP-UART-IC is started with a control

byte. Each data byte received on the EIB is transparently transmitted through the TP-UART-

IC and is therefore started with the EIB control field. Additional Information from the TP-

UART-IC is transmitted with an ESC code on the EIB control field. The host controller which

is connected to the TP-UART-IC needs to detect a receive time-out of 2 to 2,5 ms to detect

an end of Packet.

3.2.3.1 Services to UART

The following Services are supported from the TP-UART-IC.

· U_Reset.request

· U_State.request

· U_Activate Busmonitor

· U_AckInformation (Nack, Busy, Addressed)

· U_L_DataStart

+ CTRL-Byte

· U_L_DataContinue (index)

· U_L_DataEnd

+ Data-Byte

+ Checksum

· U_PollingState (Slotnumber)

+ PollAddrHigh + PollAddrLow + State

UART-Control Field

7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 1

0 0 0 0 0 0 1 0

0 0 0 0 0 1 0 1

0 0 0 1 0 X X X

1 0 0 0 0 0 0 0

Servicename

Hexadecimal

U_Reset.request

U_State.request

U_ActivateBusmon

U_AckInformation

U_L_DataStart

01

02

05

xxx:

10 - 17

80

Nack,Busy,Addressed

1 0 i

0 1 l

i

l

i

l

i

l

i

l

i

l

i = Index

U_L_DataContinue

U_L_DataEnd

81 - BE

47 - 7F

E0 - EF

1 .. 62

7 .. 63

l = last index + 1

s = Slotnumber

0 .. 14

1 1 1 0 s s s s

U_PollingState

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TP-UART-IC

3.2.3.1.1 U_Reset.request-Service

Resets the TP-UART-IC to the initial state. At start-up the TP-UART-IC waits for a bus free

time-out before sending a U_Reset.indication-Service to the host controller. To be sure that

TP-UART-IC is in reset state the host controller has to wait for 50 ms and after that the

U_Reset.request-Service can be send.

UART-Control Field (01_hex

)

7

0

6

0

5

0

4

0

3

0

2

0

1

0

1

3.2.3.1.2 U_State.request-Service

Requests the internal communication state from TP-UART-IC. The TP-UART-IC answers

with the communication state.

UART-Control Field (02_hex

)

7

0

6

0

5

0

4

0

3

0

2

0

1

0

3.2.3.1.3 U_ActiveBusmon-Service

Activates the busmonitor mode. That means each byte which is received on the EIB is sent

through the TP-UART-IC as well as illegal control bytes and not used immediate ACK. The

TP-UART-IC is absolute quiet (not sending) on the EIB. The busmonitor mode can only left

by using the U_Reset.request-Service.

UART-Control Field (05_hex

)

7

0

6

0

5

0

4

0

3

0

2

1

0

1

3.2.3.1.4 U_AckInformation-Service

The U_AckInformation-Service is to indicate if the device is addressed. This service must be

send latest 1,7 ms (9600 Baud) after receiving the address type octet of an addressed

frame. The nack- / busy- / addressed-bits set internal flags in the TP-UART-IC. The internal

NACK flag is also be set by the TP-UART-IC itself if it is detecting any frame error.

If the TP-UART-IC receive this service and the addressed bit is set it will generate an ACK-,

NACK- or BUSY-frame on the EIB depending on the settings of the NACK- / BUSY-flags.

UART-Control Field

7

0

6

0

5

0

4

1

3

0

2

x

1

x

0

X

1: Nack 1: Busy 1: Addr

AckInformation

0: NotAddr

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page12

TP-UART-IC

Receive frame

Ack / Nack / Busy Generation

of the TP- UART:

No

Addr.

Yes

Nack

No

Send NACK

Yes

Busy

No

Send BUSY

Send ACK

Timing for sending U_AckInformation (9600 Baud):

Interchargap (2Bit)

Parity 1 Startbit

1 Stopbit

8 Datenbits

15 Bit Pause

Addresstype

s 0 1 2 3 4 5 6 7 p s

TPCI

Checksum

s 0 1 2 3 4 5 6 7 p s

Ack

Receive from Bus

6 7 p s

s 0 1 2 3 4 5 6 7 p s

Addresstype

TPCI

Checksum

Send to Host-Con. p s

Rec. fr. Host-Con.

Send to Bus

s 0 1 2 3 4 5 6 7 p s

Ack-Information

s 0 1 2 3 4 5 6 7 p s

Time for Addresssearch (17 Bit)

1 Bit Buffertime

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25.15.10.41.33a

25.10.01

page13

TP-UART-IC

3.2.3.1.5 U_L_Data-Service

The U_L_Data-Services are used to transfer the complete EIB-Link-Layer-Frame to the TP-

UART-IC.

TP-UART-IC sending telegram:

HOST-

Controller

E I B

U_L_DATA_Start

U_L_DATA_Cont(1)

U_L_DATA_Cont(2)

U_L_DATA_End

TP-

UART

Ctrl-Byte

1. Databyte

2. Databyte

1. Databyte

2. Databyte

Chksum

immediate Ack

L_DATA_Confirm

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25.15.10.41.33a

25.10.01

page14

TP-UART-IC

TP-UART-IC receiving telegram:

HOST-

Controller

E I B

Ctrl-Byte

1. Databyte

2. Databyte

Ctrl-Byte

1. Databyte

2. Databyte

TP-

UART

immediate Ack-Info

Chksum

immediate Ack

3.2.3.1.5.1U_L_DataStart-Service

The U_L_DataStart-Service initialize the TP-UART-IC to receive a complete EIB-Link-Layer-

Frame from Host Controller. As additional data the EIB control byte is transmitted which is

the control field of the L_Data-frame or L_Polldata-frame. If the repetition flag in the control

byte is just cleared the TP-UART-IC transmits the frame only once with repetition flag set.

UART-Control Field (80_hex

)

Additional Information

7

1

6

0

5

0

4

0

3

0

2

0

1

0

7

F

6

F

5

R

4

1

3

c

2

c

1

0

L-Data

Data-Index 00 = Start

EIB control field

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25.15.10.41.33a

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page15

TP-UART-IC

FF = Frame Format

10 Standard Length L_DATA-EIB-Frame

00 Long L_DATA-Frames

11 Polling Frame

R = Repeat-flag (on the EIB 1 = not repeated, 0 = repeated)

1 = repeat the telegram on the EIB 3 times

send first time with repeat flag = 1 and repeat with repeat flag = 0

0 = don’t repeat the telegram on the EIB; send only once with repeat flag = 1

CC = Class:

control field data link frame type

class

repeat flag

FFR1 cc00

FFR1 0000

FFR1 1000

FFR1 0100

FFR1 1100

1111 0000

(0 = repeated)

set by TP-UART-IC

= 1

L_DATA request

L_POLLDATA request

system

alarm

high

normal

system priority

3.2.3.1.5.2U_L_DataContinue-Service

The U_L_DataContinue-Service transmits one byte containing an EIB-L_Data-Frame to the

TP-UART-IC. The index starts with 1 and the maximum value is 62 depending on the length

of the frame. But the EIB confirms just the length of 22 Bytes.

UART-Control Field

Additional Information

7

1

6

0

5

i

4

i

3

i

2

i

1

i

0

i

7

d

6

d

5

d

4

d

3

d

2

d

1

d

0

d

L-Data

Index

EIB-Data Byte for L-Data-Frame

3.2.3.1.5.3U_L_DataEnd-Service

The U_L_DataEnd-Service marks the end of the transmission of the EIB frame. After

receiving this service the TP - UART controls the checksum and in case of correctness it

starts the transmission on the EIB, else the UART returns a state indication with receive-

error flag is set.

UART-Control Field(40_hex

)

Additional Information

7

0

6

1

5

l

4

l

3

l

2

l

1

l

0

l

7

c

6

c

5

c

4

c

3

c

2

c

1

c

0

c

L-Data

last index + 1

Checksum

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reserved.

25.15.10.41.33a

25.10.01

page16

TP-UART-IC

3.2.3.1.6 U_Polling-State

This service must be send to the TP-UART-IC if a polling-frame-control-byte is received. If

the TP-UART-IC detects a collision during sending the slave slot to the EIB TP - UART

generates a state indication with the slave collision flag set.

UART-Control Field

Polling Address High

7

1

6

1

5

1

4

0

3

s

2

s

1

s

0

s

7

c

6

c

5

c

4

c

3

c

2

c

1

c

0

c

Slotnumber

Polling Address Low

Polling State

7

c

6

c

5

c

4

c

3

c

2

c

1

c

0

c

7

c

6

c

5

c

4

c

3

c

2

c

1

c

0

c

Timing for U_PollingState-Service (9600 Baud):

Ctrl-Byte

Src-Addr

PollAddr

Receive from Bus

Send to Controller

s 0 1 2 3 4 5 6 7 p s

s 0 1 2 3 4 5

Ctrl-Byte

s 0 1 2 3 4 5 6 7 p s

X 1

PollCtrl+Slotnr

PollAddr

Rec from Controller

Send to Bus

s 0 1 2 3 4 5 6 7 p s

s 0 1 2 3 4 5 6 7

continuos ...

PollAddr

5 6 7 p s

Slotcount

s 0 1 2 3 4 5 6 7 p s

Checksum

s 0 1 2 3 4 5 6 7 p s

Slot 0

s 0 1 2 3 4 5 6 7 p s

Slot 1

s 0 1 2 3 4 5 6 7

Receive from Bus

Send to Controller

X1

PollAddr

7 p s

Pollingstate

s 0 1 2 3 4 5 6 7 p s

Rec From Controller

Send to Bus

Slot 0

s 0 1 2 3 4 5 6 7 p s

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25.15.10.41.33a

25.10.01

page17

TP-UART-IC

Timing for U_PollingState-Service for a Master (9600 Baud):

Ctrl-Byte

Src-Addr

PollAddr

Send to Bus

s 0 1 2 3 4 5 6 7 p s

s 0 1 2 3 4

Ctrl-Byte

Src-Addr

PollAddr

Receive from Bus

s 0 1 2 3 4 5 6 7 p s

s 0 1 2 3 4

X2

Poll Addr

Ctrl-Byte

Src-Addr

Send to Host-Con.

Rec. f. Host-Con.

s 0 1 2 3 4 5 6 7 p s

s 0 1 2 3 4 5

PollCtrl+Slotnr

s 0 1 2 3 4 5 6 7 p s

PollAddr

s 0 1 2 3 4 5 6 7 p s

PollAddr

s 0 1 2 3 4 5 6

PollAddr

Slotcount

Checksum

Fillbyte for Slot0

Send to Bus

5 6 7 p s

s 0 1 2 3 4 5 6 7 p s

PollAddr

Slotcount

Checksum

Slot 0

Slot 1

Receive from Bus

5 6 7 p s

s 0 1 2 3 4 5 6 7 p s

X2

PollAddr

7 p s

PollAddr

s 0 1 2 3 4 5 6 7 p s

Slotcount

s 0 1 2 3 4 5 6 7 p s

Checksum

s 0 1 2 3 4 5 6 7 p s

Slot 0

s 0 1 2 3 4 5 6 7 p s

Send to Host-Con.

Rec. f. Host-Con.

PollAddr

7 p s

Pollingstate

s 0 1 2 3 4 5 6 7 p s

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reserved.

25.15.10.41.33a

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page18

TP-UART-IC

3.2.3.2 Services from UART

The first character of each service which is sent to the host controller is the control field. The

control field contains the information about the TP - UART-Service. There are 3 types of

services which can be send to the host controller: the EIB-Layer-2-Services, the Immediate-

Acknowledge-Services and the special TP – UART - Services. The EIB-Layer-2-Services

contain information about their class and also a flag which contains the information whether

the LPDU is a repeated one, or not. The Immediate-Acknowledge-Services include

information about a successful sending. The TP – UART - Services are to inform the host

controller about the communication state or to reset the communication.

Control Field

7 6 5 4 3 2 1 0

Layer-2 Services

repeat flag = 0: repeated L_DATA frame

repeat flag = 1: not repeated

1 0 r 1 c1 c0 0 0

0 0 r 1 c1 c0 0 0

1 1 1 1 0 0 0 0

c1

0

c0

0

L_DATA.ind

L_LONG_DATA.ind

L_Poll_Data.ind

system priority

alarm priority

high priority

low priority

1

0

1

Immediate Acknowledge Services

1 1 0 0 1 1 0 0

0 0 0 0 1 1 0 0

1 1 0 0 0 0 0 0

1

Acknowledge frame

NotAcknowledge frame

Busy frame

EIBUART-Control-Services

0 0 0 0 0 0 1 1

x x x x x 1 1 1

x 0 0 0 1 0 1 1

Reset-Indication

State-Response/Indication

L_DATA.confirm

x = 1 Positive Confirm x = 0 Negative Confirm

3.2.3.2.1 Layer-2-Services

The Layer-2-Services include all standard EIB Link-Layer-Services. The control fields are

followed by the data of the EIB frame. All bytes received on the EIB are immediately sent to

the host controller. The host controller has to detect a end of packet time out by supervising

the EOP gap of 2 to 2.5 bittimes.

control field Hexadecimal data link frame type

class

Repeat flag

FFR1 cc00

FF11 0000

FF01 0000

FF11 1000

FF01 1000

FF11 0100

FF01 0100

FF11 1100

FF01 1100

1111 0000

(0 = repeated)

Not repeated

Repeated

Not repeated

Repeated

Not repeated

Repeated

long/normal

30/B0_Hex

10/90_Hex

38/B8_Hex

18/98_Hex

34/B4_Hex

14/94_Hex

3C/BC_Hex

1C/9C_Hex

F0_Hex

L_DATA request

L_POLLDATA request

system

alarm

high

normal

system

Not repeated

Repeated

The frame format 01 is not supported.

For a complete description of the Link-Layer service see the EIB - Handbook.

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reserved.

25.15.10.41.33a

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page19

TP-UART-IC

Each L_Data-request is transmitted completely to the host controller. If TP - UART is polling

master the complete polling frame is transmitted to the host controller and regardless of

whether a collision is detected while sending the polling frame, or not. In case TP - UART is

polling slave just the control byte out of L_PollData-request is transmitted to the host

controller.

3.2.3.2.2 Acknowledge-Services

Acknowledge-Services are just transmitted to the host controller in busmonitor mode.

The short acknowledgment frame format consists of 15 Tbit (1 Tbit = 1/9600 s) idle time

followed by a single character which is used to acknowledge a L_Data.req frame. The

following figure shows the corresponding codes of the short acknowledgment.

Octet 0

Short ACK

8

1

0

1

7

1

0

1

6

0

5

0

4

1

0

3

1

0

2

0

1

0

ACK

NACK

BUSY

3.2.3.2.3 TP-UART-Control-Services

The TP-UART-Control-Services are services which exist only on this interface. They have to

reset the communication or to inform the host controller about the actual state.

3.2.3.2.3.1TP-UART-Reset.indication-Service

The Reset.indication-Service is sent after each reset (e.g. TP_UART_Reset.requ).

TP-UART-Control Field

7

0

6

0

5

0

4

0

3

0

2

0

1

0

1

3.2.3.2.3.2TP-UART-State.indication/response-Service

The TP-UART-State.response-Service is sent if an U_State.request-Service was received

from the host controller. In case of a slave collision, receive error, checksum error or

protocol error the TP-UART-IC sends a State.indication-Service.

TP-UART-Control Field

7

6

5

4

PE

3

TW

2

1

0

1

SC RE TE

SC = Slave Collision

RE = Receive Error (checksum, parity or bit error)

TE

PE

= Transmitter Error (send 0 receive 1)

= Protocol Error (e.g. illegal control byte)

TW = Temperature Warning¹⁾

¹⁾After a temperature warning was received, a second must at least be maintained until the next

telegram is sent.

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rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes

reserved.

25.15.10.41.33a

25.10.01

page20

TP-UART-IC

Attention: A received L_Data frame can follow the State-Indication without any delay.

3.2.3.2.3.3TP-UART-L_Data.confirm Service

The L_DATA.confirm service is transmitted to the host controller if an acknowledge was

received or the last repetition is transmitted and no acknowledge was received.

TP-UART-Control Field

7

x

6

0

5

0

4

0

3

1

2

0

1

0

1

X = 1 à The transmission of the L_DATA frame was successful

X = 0 à The transmission of the L_DATA frame was not successful

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reserved.

25.15.10.41.33a

25.10.01

page21

TP-UART-IC

4

INTERFACE BLOCK DIAGRAM

PIN Description

(The drawing of the pins is shown on first page)

Pin #

Name

Type

OUT

IO_HYST

SUPPLY

IO

Description

data transmit to host controller

reset pin

external supply (5V or 3.3V)

input for digital test / baud rate select; output

for analog test

1

2

3

4

TxD

RESn

VIF

TSTIN_BDS

5

6

7

8

9

SAVE

DIV

VCC

CSA

VSP

OUT

IN

save pin

internal clock divider 2:1 active

external power supply 5 V

current changing rate control

interstate voltage blocking capacitor

positive bus pin

POWER

ANALOG

POWER

ANALOG

IN

10 VB+

11 VB-

12 TXO

13 RxIN

14 MODE0

15 MODE1

16 TESTMODE

17 X1

negative bus pin

transmit output current (bus signal)

capacitive coupling of bus signal

mode control pin 1

mode control pin 2

mode control pin 3

crystal oscillator pin 1, external clock

crystal oscillator pin 2

18 X2

19 TSTOUT_TW

20 RxD

OUT

IN_HYST

digital test / temperature signal

data receive from host controller

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reserved.

25.15.10.41.33a

25.10.01

page22

TP-UART-IC

5

MECHANICAL SPECIFICATION

SOIC 20 (300 MIL)

Dimensions (mm)

min.

2.46

0.127

2.29

0.35

0.23

12.70

7.42

nom.

2.56

0.22

2.34

0.41

0.25

12.83

7.52

Max.

2.64

0.29

2.39

0.48

0.32

12.95

7.59

A

A1

A2

B

C

D

E

e

H

h

L

a

1.27 BSC

10.31

0.33

10.16

0.25

0.61

0^o

10.41

0.41

1.02

8^o

0.81

5^o

h x 45^o

a

C

L

E

H

e

B

D

A1

A2

A

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rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes

reserved.

25.15.10.41.33a

25.10.01

page23

TP-UART-IC

6

APPENDIX

6.1 Typical Application Circuits

6.1.1 Normal Mode

RESn

D1

A

BYG21M

VCC

SAVE

TxD

U1

1

2

3

20

19

18

17

16

15

14

13

12

11

RxD

TxD

RxD

TSTOUT

X2

VCC

RESn

VIF

Y1

U2

4

5

C1

R1

TSTIN

SAVE

DIV

X1

SMAJ43CA

68/1W

TEST MODE

MODE1

MODE0

RxIN

4,915MHz

6

47n/50V

7

VCC

CSA

VSP

C2

8

47n/50V

9

TxO

10

VB+

VB-

TP-UART-01

3)

+

2)

+

C5

10n

C3

6,8u

C4

C6

100u/16V 10n

GND

B

TSTIN = Low => 19200 Baud

²⁾recommended (close to Pins VSP and VCC)

³⁾Buffertime of VCC after SAVE active, see 1.2.13

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25.15.10.41.33a

25.10.01

page24

TP-UART-IC

6.1.2 Analogmode

RESn

D1

A

BYG21M

VCC

SAVE

TxD

U1

1

2

20

19

18

17

16

15

14

13

12

11

RxD

TxD

RxD

TSTOUT

X2

VCC

RESn

VIF

3

1)

U2

4

C1

R1

TSTIN

SAVE

DIV

X1

SMAJ43CA

5

68/1W

TEST MODE

MODE1

MODE0

RxIN

6

7

VCC

CSA

VSP

C2

8

47n/50V

9

TxO

10

47n/50V

VB+

VB-

TP-UART-01

2)

+

3)

C4

100u/16V

C5

10n

C3

6,8u

C6

10n

GND

B

¹⁾The maximum average powerdissipation of the transmitting resistance of 1 W is valid for an

active telegramrate of 50 %

²⁾recommended (close to Pins VSP and VCC)

³⁾Buffertime of VCC after SAVE active, see 1.2.13

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25.15.10.41.33a

25.10.01

page25

TP-UART-IC

6.1.3 PART LIST *)

No.

Component

Type/Value

Remarks

U1

IC

TP-UART-IC

U2

Suppressor Diode SMAJ43CA

Manufacturer: General Semiconductor

Fast rectifier, Manufaturer: Vishay, Temic

Ceramic

D1

Rectifier Diode

Capacitor

Resistor

BYG21M

C1, C2

C3

47nF/50V/ ±5%

6,8uF/6.3V/ ±20%

100uF/16V/ ±20%

10nF/50V/ ±10%

68/±5%

Electrolytic, useful life at 105°C : 2000h

Ceramic

C4

C5, C6

R1

1W

Y1

Quarz

4.9152MHz/50ppm/30pF

*)additional components may be required because of EMC

6.2 Galvanic Isolation

The interface pins TxD, RxD and TSTOUT_TW are prepared for galvanic isolation with

optocouplers. The interface output pins TxD and TSTOUT_TW provide a driver current of

5 mA, thus the transmitting diode of an optocoupler can be connected directly. The interface

input pin RxD is implemented as a Schmitt Trigger. There are no additional level shifters

after the output of the optocoupler necessary.

In Normal Mode it is possible to recognize a reset via TxD without an additional optocoupler.

Please refer to 3.2.2. A busvoltage breakdown can also be monitored if in quiescent state

the transmitting diode belonging to TxD is active.

The data contained herein are subject to change without notice. Siemens does not warrant

for correctness or completeness of the documentation or that the products described are

qualified for certification.

The reproduction, transmission or use of this document or it‘s contents is not permitted without express written authority. All

rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes

reserved.

25.15.10.41.33a

25.10.01

page26


型号：	EIB-TP-UART-IC
厂家：	Infineon
描述：	TP-UART-IC TP -UART -IC
文件：	总26页 (文件大小：377K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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