IAUC120N04S6N006 [INFINEON]

A portfolio of 18 products (RDS (on) max from 0,5 mΩ to 4.4 mΩ which enables the best product fit in the applications.;
IAUC120N04S6N006
型号: IAUC120N04S6N006
厂家: Infineon    Infineon
描述:

A portfolio of 18 products (RDS (on) max from 0,5 mΩ to 4.4 mΩ which enables the best product fit in the applications.

文件: 总10页 (文件大小:936K)
中文:  中文翻译
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IAUC120N04S6N006  
OptiMOS- 6 Power-Transistor  
Product Summary  
VDS  
40  
0.6  
120  
V
RDS(on),max  
ID  
mW  
A
Features  
PG-TDSON-8-53  
• OptiMOS™ - power MOSFET for automotive applications  
• N-channel - Enhancement mode - Normal Level  
• AEC Q101 qualified  
1
• MSL1 up to 260°C peak reflow  
• 175°C operating temperature  
• Green Product (RoHS compliant)  
• 100% Avalanche tested  
1
Type  
Package  
Marking  
IAUC120N04S6N006  
PG-TDSON-8-53 6N04N006  
Maximum ratings, at T j=25 °C, unless otherwise specified  
Value  
Parameter  
Symbol  
Conditions  
VGS=10V,  
Chip Limitation1,2)  
VGS=10V,  
DC current3)  
Unit  
I D  
Drain current  
405  
120  
55  
A
Ta=85°C, VGS=10V,  
RthJA on 2s2p4,5)  
Pulsed drain current5)  
I D,pulse  
EAS  
T C=25°C, t p =100µs  
1500  
750  
Avalanche energy, single pulse2)  
Avalanche current, single pulse  
Gate source voltage  
I D=60A, R G=25W  
mJ  
A
I AS  
R G=25W  
120  
VGS  
-
±20  
V
Ptot  
T C=25°C  
Power dissipation  
187  
W
°C  
T j, T stg  
Operating and storage temperature  
-
-55 ... +175  
Rev. 1.0  
page 1  
2020-06-05  
IAUC120N04S6N006  
Values  
typ.  
Parameter  
Symbol  
Conditions  
Unit  
min.  
max.  
Thermal characteristics5)  
R thJC  
Thermal resistance, junction - case  
-
-
-
-
-
0.8  
-
K/W  
Thermal resistance,  
junction - ambient4)  
R thJA  
26  
Electrical characteristics, at T j=25 °C, unless otherwise specified  
Static characteristics  
V(BR)DSS VGS=0V, I D= 1mA  
VGS(th) VDS=VGS, I D=130µA  
Drain-source breakdown voltage  
Gate threshold voltage  
40  
-
-
V
2.2  
2.6  
3.0  
VDS=40V, VGS=0V,  
T j=25°C  
I DSS  
Zero gate voltage drain current  
-
-
-
-
1
µA  
VDS=40V, VGS=0V,  
T j=125°C2)  
33  
I GSS  
VGS=20V, VDS=0V  
Gate-source leakage current  
-
-
-
-
100 nA  
R DS(on) VGS=7V, I D=60A  
VGS=10V, I D=60A  
Drain-source on-state resistance  
0.54  
0.46  
0.85  
0.60  
mW  
Rev. 1.0  
page 2  
2020-06-05  
IAUC120N04S6N006  
Values  
typ.  
Parameter  
Symbol  
Conditions  
Unit  
min.  
max.  
Dynamic characteristics2)  
Input capacitance  
Output capacitance  
Reverse transfer capacitance  
Turn-on delay time  
Rise time  
C iss  
C oss  
Crss  
t d(on)  
t r  
-
-
-
-
-
-
-
7607  
2249  
100  
13  
10117 pF  
2991  
VGS=0V, VDS=25V,  
f =1MHz  
150  
-
-
-
-
ns  
8
VDD=20V, VGS=10V,  
I D=120A, R G=3.5W  
t d(off)  
t f  
Turn-off delay time  
Fall time  
33  
16  
Gate Charge Characteristics2)  
Gate to source charge  
Gate to drain charge  
Gate charge total  
Q gs  
-
-
-
-
31  
22  
40  
32  
151  
-
nC  
Q gd  
VDD=32V, I D=120A,  
VGS=0 to 10V  
Q g  
116  
4.0  
Vplateau  
Gate plateau voltage  
V
A
Reverse Diode  
Diode continous forward current5)  
Diode pulse current5)  
I S  
-
-
-
-
256  
T C=25°C  
I S,pulse  
1780  
VGS=0V, I F=60A,  
T j=25°C  
VSD  
Diode forward voltage  
Reverse recovery time2)  
-
-
0.8  
66  
1.1  
-
V
VR=20V, I F=50A,  
diF/dt =100A/µs  
t rr  
ns  
Reverse recovery charge2)  
Q rr  
-
83  
-
nC  
1)  
Practically the current is limited by overall system design including customer specific PCB.  
2) The parameter is not subject to production test - verified by characterization.  
3) The product can operate at specified current based on best practice to minimize electromigration at the solder joint.  
For rare events and inrush currents the value may be exceeded.  
4) Device on 2s2p FR4 PCB defined in accordance with JEDEC standards (JESD51-5, -7). PCB is vertical in still air.  
5) The parameter is not subject to production test - verified by design.  
Rev. 1.0  
page 3  
2020-06-05  
IAUC120N04S6N006  
1 Power dissipation  
2 Drain current  
Ptot = f(T C); VGS = 10 V  
I D = f(T C); VGS = 10 V  
250  
200  
150  
100  
50  
500  
450  
400  
350  
300  
250  
200  
150  
Chip limit  
DC current  
100  
50  
0
0
0
50  
100  
150  
200  
0
50  
100  
150  
200  
TC [°C]  
TC [°C]  
3 Safe operating area  
4 Max. transient thermal impedance  
Z thJC = f(t p)  
I D = f(VDS); T C = 25 °C; D = 0  
parameter: t p  
parameter: D =t p/T  
101  
10000  
1000  
100  
10  
1 µs  
100  
10 µs  
0.5  
0.1  
10-1  
100 µs  
0.05  
0.01  
10-2  
150 µs  
single pulse  
10-3  
1
0.1  
1
10  
100  
10-6  
10-5  
10-4  
10-3  
10-2  
10-1  
100  
VDS [V]  
tp [s]  
Rev. 1.0  
page 4  
2020-06-05  
IAUC120N04S6N006  
5 Typ. output characteristics  
I D = f(VDS); T j = 25 °C  
parameter: VGS  
6 Typ. drain-source on-state resistance  
R DS(on) = f(I D); T j = 25 °C  
parameter: VGS  
1200  
4
3
2
1
0
10 V  
7 V  
1100  
5.5 V  
1000  
4.5 V  
900  
800  
700  
600  
500  
400  
300  
200  
100  
0
5 V  
5 V  
4.5 V  
5.5 V  
7 V  
10 V  
0
1
2
3
0
50 100 150 200 250 300 350 400  
VDS [V]  
ID [A]  
7 Typ. transfer characteristics  
I D = f(VGS); VDS = 6V  
parameter: T j  
8 Typ. drain-source on-state resistance  
R DS(on) = f(T j); I D = 60 A; VGS = 10 V  
1
0.75  
0.5  
1400  
1200  
1000  
800  
600  
175 °C  
400  
25 °C  
200  
-55 °C  
0
0.25  
3
3.5  
4
4.5  
VGS [V]  
5
5.5  
-60  
-20  
20  
60  
100  
140  
180  
Tj [°C]  
Rev. 1.0  
page 5  
2020-06-05  
IAUC120N04S6N006  
9 Typ. gate threshold voltage  
VGS(th) = f(T j); VGS = VDS  
parameter: I D  
10 Typ. capacitances  
C = f(VDS); VGS = 0 V; f = 1 MHz  
105  
4
3.5  
3
104  
Ciss  
1300 µA  
Coss  
2.5  
130 µA  
103  
2
1.5  
1
Crss  
102  
0.5  
0
101  
0
10  
20  
30  
-60  
-20  
20  
60  
Tj [°C]  
100  
140  
180  
VDS [V]  
11 Typical forward diode characteristicis  
12 Avalanche characteristics  
I A S= f(t AV  
IF = f(VSD)  
)
parameter: T j  
parameter: Tj(start) >25°C  
103  
1000  
102  
100  
10  
1
25 °C  
100 °C  
25 °C  
150 °C  
175 °C  
101  
100  
0
0.2  
0.4  
0.6  
0.8  
1
1.2  
1.4  
1
10  
100  
1000  
VSD [V]  
tAV [µs]  
Rev. 1.0  
page 6  
2020-06-05  
IAUC120N04S6N006  
13 Avalanche energy  
14 Drain-source breakdown voltage  
EAS = f(T j)  
VBR(DSS) = f(T j); I D = 1 mA  
44  
2000  
1500  
1000  
42  
40  
38  
30 A  
60 A  
500  
120 A  
0
-60  
-20  
20  
60  
100  
140  
180  
25  
75  
125  
175  
Tj [°C]  
Tj [°C]  
15 Typ. gate charge  
16 Gate charge waveforms  
VGS = f(Q gate); I D = 120 A pulsed  
parameter: VDD  
10  
V GS  
8 V  
9
8
7
6
5
4
3
2
1
0
Qg  
32 V  
V gs(th)  
Qg(th)  
Qsw  
Qgd  
Qgate  
Qgs  
0
50  
100  
150  
Qgate [nC]  
Rev. 1.0  
page 7  
2020-06-05  
IAUC120N04S6N006  
PG-TDSON-8: Outline  
Footprint  
Dimensions in mm  
Packaging  
Rev. 1.0  
page 8  
2020-06-05  
IAUC120N04S6N006  
Published by  
Infineon Technologies AG  
81726 Munich, Germany  
© Infineon Technologies AG 2020  
All Rights Reserved.  
Legal Disclaimer  
The information given in this document shall in no event be regarded as a guarantee of conditions  
or characteristics. With respect to any examples or hints given herein, any typical values stated  
herein and/or any information regarding the application of the device, Infineon Technologies hereby  
disclaims any and all warranties and liabilities of any kind, including without limitation, warranties  
of non-infringement of intellectual property rights of any third party.  
Information  
For further information on technology, delivery terms and conditions and prices, please contact  
the nearest Infineon Technologies Office (www.infineon.com).  
Warnings  
Due to technical requirements, components may contain dangerous substances.  
For information on the types in question, please contact the nearest Infineon Technologies Office.  
Infineon Technologies components may be used in life-support devices or systems only with the  
express written approval of Infineon Technologies, if a failure of such components can reasonably be  
expected to cause the failure of that life-support device or system or to affect the safety or  
effectiveness of that device or system. Life support devices or systems are intended to be implanted  
in the human body or to support and/or maintain and sustain and/or protect human life.  
If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.  
Rev. 1.0  
page 9  
2020-06-05  
IAUC120N04S6N006  
Revision History  
Version  
Date  
Changes  
05.06.2020 Final Data Sheet  
Revision 1.0  
Rev. 1.0  
page 10  
2020-06-05  

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