IAUC41N06S5L100 [INFINEON]

车规级MOSFET;
IAUC41N06S5L100
型号: IAUC41N06S5L100
厂家: Infineon    Infineon
描述:

车规级MOSFET

文件: 总10页 (文件大小:1007K)
中文:  中文翻译
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IAUC41N06S5L100  
OptiMOS-5 Power Transistor  
Product Summary  
VDS  
60  
10  
41  
V
Features  
RDS(on),max  
ID  
mW  
A
• OptiMOS™ power MOSFET for automotive applications  
• N-channel - Enhancement mode - Logic Level  
• MSL1 up to 260°C peak reflow  
• 175 °C operating temperature  
• Green product (RoHS compliant)  
• 100% Avalanche tested  
PG-TDSON-8-33  
Type  
Package  
Marking  
IAUC41N06S5L100  
PG-TDSON-8-33 5N06L100  
Maximum ratings, at T j=25 °C, unless otherwise specified  
Value  
Parameter  
Symbol  
Conditions  
Unit  
VGS=10 V, Chip  
limitation1,2)  
I D  
Drain current  
41  
A
VGS=10V, DC current  
41  
12  
T a=85 °C, VGS=10 V,  
R thJA on 2s2p 2,3)  
Pulsed drain current2)  
I D,pulse  
EAS  
T C=25 °C, tp= 100 µs  
115  
Avalanche energy, single pulse2)  
Avalanche current, single pulse  
Gate source voltage  
I D=20 A  
37  
41  
mJ  
A
I AS  
-
VGS  
-
±16  
V
Ptot  
T C=25 °C  
Power dissipation  
42  
W
°C  
T j, T stg  
Operating and storage temperature  
-
-55 ... +175  
Rev. 1.0  
page 1  
2020-05-05  
IAUC41N06S5L100  
Values  
Parameter  
Symbol  
Conditions  
Unit  
min.  
typ.  
max.  
Thermal characteristics2)  
R thJC  
Thermal resistance, junction - case  
-
-
-
-
-
3.6  
-
K/W  
Thermal resistance, junction -  
ambient3)  
R thJA  
25.5  
Electrical characteristics, at T j=25 °C, unless otherwise specified  
Static characteristics  
V(BR)DSS VGS=0V, I D=1mA  
VGS(th) VDS=VGS, I D=13µA  
Drain-source breakdown voltage  
Gate threshold voltage  
60  
-
-
V
1.2  
1.7  
2.2  
VDS=60V, VGS=0V,  
T j=25°C  
I DSS  
Zero gate voltage drain current  
-
-
-
-
1
µA  
VDS=60V, VGS=0V,  
T j=125°C1)  
100  
I GSS  
VGS=16V, VDS=0V  
Gate-source leakage current  
-
-
-
-
-
100 nA  
R DS(on) VGS=4.5V, I D=20A  
VGS=10V, I D=20A  
Drain-source on-state resistance  
11.6  
7.9  
1.1  
13.9  
10  
-
mW  
Gate resistance2)  
R G  
-
W
Rev. 1.0  
page 2  
2020-05-05  
IAUC41N06S5L100  
Values  
Parameter  
Symbol  
Conditions  
Unit  
min.  
typ.  
max.  
Dynamic characteristics2)  
Input capacitance  
Output capacitance  
Reverse transfer capacitance  
Turn-on delay time  
Turn-off delay time  
Rise time  
C iss  
C oss  
Crss  
t d(on)  
t d(off)  
t r  
-
-
-
-
-
-
-
927  
183  
12  
1205 pF  
238  
VGS=0V, VDS=30V,  
f =1MHz  
18  
2.4  
6.7  
1.0  
2.2  
-
-
-
-
ns  
VDD=30V, VGS=10V,  
I D=20A, R G,ext=3.5W  
t f  
Fall time  
Gate Charge Characteristics2)  
Gate to source charge  
Gate to drain charge  
Gate charge total  
Q gs  
-
-
-
-
3.0  
2.1  
4.0  
3.1  
16.4  
-
nC  
Q gd  
VDD=30V, I D=20A,  
VGS=0 to 10V  
Q g  
12.7  
3.3  
Vplateau  
Gate plateau voltage  
V
A
Reverse Diode  
Diode continous forward current2)  
Diode pulse current2)  
I S  
T C=25°C  
-
-
-
-
41  
I S,pulse  
T C=25 °C, tp= 100 µs  
115  
VGS=0V, I F=20A,  
T j=25°C  
VSD  
Diode forward voltage  
-
0.8  
1.1  
V
Reverse recovery time2)  
t rr  
-
-
26  
16  
-
-
ns  
VR=30V, I F=41A,  
diF/dt =100A/µs  
Reverse recovery charge2)  
Q rr  
nC  
1) Practically the current is limited by the overall system design including the customer-specific PCB.  
2) The parameter is not subject to production test - verified by design/characterization.  
3) Device on a four-layer 2s2p FR4 PCB defined in accordance with JEDEC standards (JESD51-5-7). PCB is vertical  
in still air.  
Rev. 1.0  
page 3  
2020-05-05  
IAUC41N06S5L100  
1 Power dissipation  
2 Drain current  
Ptot = f(T C); VGS = 10 V  
I D = f(T C); VGS = 10 V  
50  
40  
30  
20  
10  
0
40  
20  
0
0
50  
100  
150  
200  
0
50  
100  
150  
200  
TC [°C]  
TC [°C]  
3 Safe operating area  
4 Max. transient thermal impedance  
Z thJC = f(t p)  
I D = f(VDS); T C = 25 °C; D = 0  
parameter: t p  
parameter: D =t p/T  
101  
1000  
100  
10  
0.5  
100  
1 µs  
0.1  
0.05  
10 µs  
10-1  
0.01  
100 µs  
150 µs  
single pulse  
10-2  
10-3  
1
0.1  
1
10  
100  
10-6  
10-5  
10-4  
10-3  
10-2  
10-1  
100  
VDS [V]  
tp [s]  
Rev. 1.0  
page 4  
2020-05-05  
IAUC41N06S5L100  
5 Typ. output characteristics  
I D = f(VDS); T j = 25 °C  
parameter: VGS  
6 Typ. drain-source on-state resistance  
R DS(on) = f(I D); T j = 25 °C  
parameter: VGS  
160  
50  
45  
40  
35  
30  
25  
20  
15  
10  
5 V  
6 V  
10 V  
120  
4 V  
4.5 V  
4.5 V  
80  
4 V  
40  
5 V  
6 V  
10 V  
0
5
0
0
1
2
3
4
5
6
40  
80  
VDS [V]  
ID [A]  
7 Typ. transfer characteristics  
I D = f(VGS); VDS = 6V  
parameter: T j  
8 Typ. drain-source on-state resistance  
R DS(on) = f(T j);  
parameter: ID, VGS  
100  
-55 °C  
21  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
25 °C  
19  
VGS=4.5V, ID=20A  
17  
15  
13  
11  
9
175 °C  
VGS=10V, ID=20A  
7
5
1
1.5  
2
2.5  
3
3.5  
4
4.5  
5
5.5  
6
-60  
-20  
20  
60  
100  
140  
180  
VGS [V]  
Tj [°C]  
Rev. 1.0  
page 5  
2020-05-05  
IAUC41N06S5L100  
9 Typ. gate threshold voltage  
VGS(th) = f(T j); VGS = VDS  
parameter: I D  
10 Typ. capacitances  
C = f(VDS); VGS = 0 V; f = 1 MHz  
104  
2.5  
2
103  
Ciss  
130 µA  
Coss  
1.5  
1
13 µA  
102  
Crss  
0.5  
0
101  
0
10  
20  
30  
40  
50  
60  
-60  
-20  
20  
60  
Tj [°C]  
100  
140  
180  
VDS [V]  
11 Typical forward diode characteristics  
12 Avalanche characteristics  
I AS= f(t AV  
IF = f(VSD)  
)
parameter: T j  
parameter: Tj(start)  
103  
102  
101  
100  
25 °C  
100 °C  
150 °C  
10  
25 °C  
175 °C  
100  
1
0
0.2  
0.4  
0.6  
0.8  
1
1.2  
1.4  
0.1  
1
10  
100  
1000  
VSD [V]  
tAV [µs]  
Rev. 1.0  
page 6  
2020-05-05  
IAUC41N06S5L100  
13 Avalanche energy  
EAS = f(T j)  
14 Drain-source breakdown voltage  
VBR(DSS) = f(T j); I D = 1 mA  
parameter: I D  
66  
80  
64  
62  
60  
58  
56  
10 A  
60  
40  
20 A  
20  
41 A  
0
-55  
-15  
25  
65  
105  
145  
25  
75  
125  
175  
Tj [°C]  
Tj [°C]  
15 Typ. gate charge  
16 Gate charge waveforms  
VGS = f(Q gate); I D = 20 A pulsed  
parameter: VDD  
10  
9
8
7
6
5
4
3
2
1
0
V GS  
12 V  
Qg  
30 V  
48V  
V gs(th)  
Qg(th)  
Qsw  
Qgd  
Qgate  
Qgs  
0
2
4
6
8
10  
12  
Qgate [nC]  
Rev. 1.0  
page 7  
2020-05-05  
IAUC41N06S5L100  
Package Outline  
Footprint  
Packaging  
Rev. 1.0  
page 8  
2020-05-05  
IAUC41N06S5L100  
Published by  
Infineon Technologies AG  
81726 Munich, Germany  
© Infineon Technologies AG 2020  
All Rights Reserved.  
Legal Disclaimer  
The information given in this document shall in no event be regarded as a guarantee of conditions  
or characteristics. With respect to any examples or hints given herein, any typical values stated  
herein and/or any information regarding the application of the device, Infineon Technologies hereby  
disclaims any and all warranties and liabilities of any kind, including without limitation, warranties  
of non-infringement of intellectual property rights of any third party.  
Information  
For further information on technology, delivery terms and conditions and prices, please contact  
the nearest Infineon Technologies Office (www.infineon.com).  
Warnings  
Due to technical requirements, components may contain dangerous substances.  
For information on the types in question, please contact the nearest Infineon Technologies Office.  
Infineon Technologies components may be used in life-support devices or systems only with the  
express written approval of Infineon Technologies, if a failure of such components can reasonably be  
expected to cause the failure of that life-support device or system or to affect the safety or  
effectiveness of that device or system. Life support devices or systems are intended to be implanted  
in the human body or to support and/or maintain and sustain and/or protect human life.  
If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.  
Rev. 1.0  
page 9  
2020-05-05  
IAUC41N06S5L100  
Revision History  
Version  
Date  
Changes  
Final Data Sheet  
Revision 1.0  
05.05.2020  
Rev. 1.0  
page 10  
2020-05-05  

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