IPD50N06S3L06ATMA1 [INFINEON]
Power Field-Effect Transistor, 50A I(D), 55V, 0.006ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252, GREEN, PLASTIC PACKAGE-3;
| 型号： | IPD50N06S3L06ATMA1 |
| 厂家： | 
Infineon |
| 描述： | Power Field-Effect Transistor, 50A I(D), 55V, 0.006ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252, GREEN, PLASTIC PACKAGE-3 脉冲 晶体管 |
| 文件： | 总9页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IPD50N06S3L-06
OptiMOS®-T Power-Transistor
Product Summary
VDS
55
6.0
50
V
R DS(on),max
I D
mΩ
A
Features
• N-channel - Logic Level - Enhancement mode
• Automotive AEC Q101 qualified
• MSL1 up to 260°C peak reflow
• 175°C operating temperature
• Green package (RoHS compliant)
• Ultra low Rds(on)
PG-TO252-3-11
• 100% Avalanche tested
Type
Package
Marking
IPD50N06S3L-06
PG-TO252-3-11 3N06L06
Maximum ratings, at T j=25 °C, unless otherwise specified
Value
Parameter
Symbol
Conditions
Unit
Continuous drain current1)
I D
T C=25 °C, VGS=10 V
T C=100 °C,
50
50
A
V
GS=10 V2)
Pulsed drain current2)
Avalanche energy, single pulse2)
I D,pulse
EAS
T C=25 °C
I D=25 A
200
710
mJ
A
I AS
Avalanche current, single pulse
50
Gate source voltage3)
VGS
±16
V
Ptot
T C=25 °C
Power dissipation
136
W
°C
T j, T stg
Operating and storage temperature
IEC climatic category; DIN IEC 68-1
-55 ... +175
55/175/56
Rev. 1.2
page 1
2009-05-20
IPD50N06S3L-06
Values
Parameter
Symbol
Conditions
Unit
min.
typ.
max.
Thermal characteristics2)
R thJC
R thJA
Thermal resistance, junction - case
SMD version, device on PCB
-
-
-
-
-
-
1.1
62
40
K/W
minimal footprint
6 cm2 cooling area4)
Electrical characteristics, at T j=25 °C, unless otherwise specified
Static characteristics
V(BR)DSS
VGS(th)
V
V
GS=0 V, I D= 1 mA
DS=VGS, I D=80 µA
Drain-source breakdown voltage
Gate threshold voltage
55
-
-
V
1.2
1.7
2.2
V
DS=55 V, VGS=0 V,
I DSS
Zero gate voltage drain current
-
-
0.01
1
1
µA
T j=25 °C
V
DS=55 V, VGS=0 V,
100
T j=125 °C2)
I GSS
V
V
V
GS=16 V, VDS=0 V
GS=5 V, I D=37 A
GS=10 V, I D=50 A
Gate-source leakage current
-
-
-
1
100 nA
R DS(on)
Drain-source on-state resistance
8.4
5.1
11
6
mΩ
Rev. 1.2
page 2
2009-05-20
IPD50N06S3L-06
Values
Parameter
Symbol
Conditions
Unit
min.
typ.
max.
Dynamic characteristics2)
Input capacitance
Output capacitance
Reverse transfer capacitance
Turn-on delay time
Rise time
C iss
C oss
Crss
t d(on)
t r
-
-
-
-
-
-
-
9400
1200
1130
20
11750 pF
1800
V
GS=0 V, VDS=25 V,
f =1 MHz
1700
-
-
-
-
ns
V
V
DD=27.5 V,
GS=10 V, I D=50 A,
57
t d(off)
t f
Turn-off delay time
Fall time
75
R G=7 Ω
115
Gate Charge Characteristics2)
Gate to source charge
Gate to drain charge
Gate charge total
Q gs
-
-
-
-
37
27
50
40
145
-
nC
Q gd
V
V
DD=11 V, I D=50 A,
GS=0 to 10 V
Q g
129
3.9
Vplateau
Gate plateau voltage
V
A
Reverse Diode
Diode continous forward current2)
Diode pulse current2)
I S
-
-
-
-
50
T C=25 °C
I S,pulse
200
V
GS=0 V, I F=50 A,
VSD
Diode forward voltage
0.6
0.9
1.3
V
T j=25 °C
Reverse recovery time2)
Reverse recovery charge2)
t rr
-
-
47
62
-
-
ns
VR=27.5 V, I F=I S,
diF/dt =100 A/µs
Q rr
nC
1) Current is limited by bondwire; with an R thJC = 1.1 K/W the chip is able to carry 112 A at 25°C. For detailed
information see Application Note ANPS071E.
2) Defined by design. Not subject to production test.
3) Qualified at -5V and +20V.
4) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
Rev. 1.2
page 3
2009-05-20
IPD50N06S3L-06
1 Power dissipation
2 Drain current
P
tot = f(T C); VGS ≥ 4 V
I D = f(T C); VGS ≥ 4 V
160
140
120
100
80
60
40
20
0
60
40
20
0
0
50
100
150
200
0
50
100
150
200
T
C [°C]
T
C [°C]
3 Safe operating area
4 Max. transient thermal impedance
thJC = f(t p)
I D = f(VDS); T C = 25 °C; D = 0
parameter: t p
Z
parameter: D =t p/T
101
1000
100
10
1 µs
100
0.5
10 µs
100 µs
0.1
1 ms
10-1
0.05
0.01
10-2
single pulse
10-3
1
10-7
10-6
10-5
10-4
10-3
10-2
10-1
100
0.1
1
10
100
t p [s]
V
DS [V]
Rev. 1.2
page 4
2009-05-20
IPD50N06S3L-06
5 Typ. output characteristics
I D = f(VDS); T j = 25 °C
parameter: VGS
6 Typ. drain-source on-state resistance
DS(on) = f(I D); T j = 25 °C
R
parameter: VGS
200
10
10 V
6 V
5 V
6 V
175
150
125
100
75
8
6
5 V
4.5 V
8 V
9 V
4 V
50
10 V
3.5 V
25
0
4
0
0
2
4
6
8
10
50
100
150
200
V
DS [V]
I
D [A]
7 Typ. transfer characteristics
I D = f(VGS); VDS = 4 V
parameter: T j
8 Typ. drain-source on-state resistance
R
DS(on) = f(T j); I D = 50 A; VGS = 10 V
150
100
50
10
-55 °C
25 °C
175 °C
8
6
4
2
0
0
2
4
6
-60
-20
20
60
100
140
180
V
GS [V]
T j [°C]
Rev. 1.2
page 5
2009-05-20
IPD50N06S3L-06
9 Typ. gate threshold voltage
GS(th) = f(T j); VGS = VDS
10 Typ. capacitances
V
C = f(VDS); VGS = 0 V; f = 1 MHz
parameter: I D
2.5
2.25
2
Ciss
104
Coss
800µA
1.75
1.5
1.25
1
Crss
80µA
103
0.75
102
0.5
-60
0
5
10
15
DS [V]
20
25
-20
20
60
T j [°C]
100
140
180
V
11 Typical forward diode characteristicis
12 Typ. avalanche characteristics
AV = f(t AV
IF = f(VSD)
I
)
parameter: T j
parameter: Tj(start)
103
102
101
100
25°C
100°C
150°C
10
25 °C
175 °C
100
1
1
0
0.2
0.4
0.6
0.8
1
1.2
1.4
10
100
1000
V
SD [V]
t AV [µs]
Rev. 1.2
page 6
2009-05-20
IPD50N06S3L-06
13 Typical avalanche Energy
AS = f(T j)
14 Drain-source breakdown voltage
E
V
BR(DSS) = f(T j); I D = 1 mA
parameter: I D
65
1500
12.5 A
1200
60
55
50
45
900
25 A
600
50 A
300
0
0
-60
-20
20
60
100
140
180
50
100
150
200
T j [°C]
T j [°C]
15 Typ. gate charge
GS = f(Q gate); I D = 50 A pulsed
16 Gate charge waveforms
V
parameter: VDD
12
V GS
44 V
11 V
Q g
10
8
Vplateau
6
V gs(th)
4
2
Q g(th)
Q sw
Q gd
Q gate
Q gs
0
0
50
100
150
200
Q
gate [nC]
Rev. 1.2
page 7
2009-05-20
IPD50N06S3L-06
Published by
Infineon Technologies AG
81726 Munich, Germany
© Infineon Technologies AG 2009
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions
or characteristics. With respect to any examples or hints given herein, any typical values stated
herein and/or any information regarding the application of the device, Infineon Technologies hereby
disclaims any and all warranties and liabilities of any kind, including without limitation, warranties
of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact
the nearest Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances.
For information on the types in question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the
express written approval of Infineon Technologies, if a failure of such components can reasonably be
expected to cause the failure of that life-support device or system or to affect the safety or
effectiveness of that device or system. Life support devices or systems are intended to be implanted
in the human body or to support and/or maintain and sustain and/or protect human life.
If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Rev. 1.2
page 8
2009-05-20
IPD50N06S3L-06
Revision History
Version
Date
Changes
Implementation of avalanche
07.11.2007 current single pulse
Data Sheet version 1.1
Data Sheet version 1.1
Data Sheet version 1.1
Data Sheet version 1.1
Data Sheet version 1.2
Data Sheet version 1.2
07.11.2007 Update of package drawing
Update of avalanche diagram 12
07.11.2007 and 13
implementation of footnote 2 for
07.11.2007 Eas specification
Correction of marking and update
15.06.2009 of disclaimer
15.06.2009 Correction of package name
Rev. 1.2
page 9
2009-05-20
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