IRDC3640 [INFINEON]

USER GUIDE FOR IR3640 EVALUATION BOARD; 用户指南IR3640评估板


型号：	IRDC3640
厂家：	Infineon
描述：	USER GUIDE FOR IR3640 EVALUATION BOARD 用户指南IR3640评估板
文件：	总17页 (文件大小：748K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IRDC3640

USER GUIDE FOR IR3640 EVALUATION BOARD

DESCRIPTION

An output over-current protection function is

implemented by sensing the voltage developed

across the on-resistance of the synchronous

rectifier MOSFET for optimum cost and

performance.

The IR3640 is a PWM controller for use in

high performance synchronous Buck DC/DC

applications. This is designed to drive a pair

of external NFETs using a programmable

switching frequency up to 1.5MHz in voltage

mode. It is housed in a in 20 Lead 3x4

MLPQ package.

This user guide contains the schematic and bill

of materials for the IR3640 evaluation board.

The guide describes operation and use of the

evaluation board itself. Detailed application

information for IR3640 is available in the

IR3640 data sheet.

Key features offered by the IR3640 include

programmable soft-start ramp, Power Good,

thermal protection, over voltage and over

current protection, programmable switching

frequency, tracking input, enable input, input

under-voltage lockout for proper start-up,

and pre-bias start-up.

BOARD FEATURES

• V_in= +12V (13.2V Max)

• V_cc= +5V (5.5V Max)

• V_out= +1.8V @ 0- 25A

• F_s= 600kHz

• L = 0.33uH

• C_in= 4x10uF (ceramic 1210) + 2x330uF (electrolytic)

• C_out= 10x47uF (ceramic 0805)

IRDC3640

CONNECTIONS and OPERATING INSTRUCTIONS

A well regulated +12V input supply should be connected to VIN+ and VIN-. A maximum 25A load should be

connected to VOUT+ and VOUT-. The connection diagram is shown in Fig. 1 and inputs and outputs of the

board are listed in Table I.

IR3640 has two input supplies, one for biasing (Vcc) and the other as input voltage (Vin). Separate supplies

should be applied to these inputs. Vcc input should be a well regulated 4.5V-5.5V supply and it would be

connected to Vcc+ and Vcc-.

Table I. Connections

Connection

VIN+

Signal Name

V_in(+12V)

VIN-

Ground of V_in

Vcc input

Vcc+

Vcc-

Ground for Vcc input

VOUT+

V_out(+1.8V)

VOUT-

Sync

Ground of Vout

Synchronous input

Power Good Signal

PGood

LAYOUT

The PCB is a 6-layer board. All of layers are 2 Oz. copper. The IR3640 and other components are

mounted on the top and bottom side of the board.

Power supply decoupling capacitors, the Bootstrap capacitor and feedback components are located

close to IR3640. The feedback resistors are connected to the output voltage at the point of regulation

and are located close to IR3640. To improve efficiency, the circuit board is designed to minimize the

length of the on-board power ground current path.

IRDC3640

Connection Diagram

V = +12V

V_OUT= +1.8V

GROUND

Vcc = +5V

Fig. 1: Connection diagram of IR3640 evaluation board (top and bottom)

IRDC3640

Fig. 2: Board layout, top layer

Fig. 3: Board layout, bottom layer

IRDC3640

Single point

connection

between AGND

and PGND.

Fig. 4: Board layout, mid-layer I

Fig. 5: Board layout, mid-layer II

IRDC3640

Fig. 6: Board layout, mid-layer III

Fig. 7: Board layout, mid-layer IV

IRDC3640

o o B t

F b

m p C o

n c S y

1 0

1 2

1 8

1 3

N C 1

N C 6

e l

E n a b

L G n d

P V c

2 0

IRDC3640

Bill of Materials

Item Quantity

Reference

10 VOUT-,VOUT+,VIN-,VIN+,

Sync,PVcc,PGood,PGND,B,A _TestPoint

Value

Description

Manufacturer

Part Number

0.075" SQ_SMT SMT 0.075" Test Point

4 C2,C3,C4,C5

5 C7,C8,C20,C27,C28

10 C9,C10,C11,C12,C13,

10uF

0.1uF

47uF

Ceramic,25V,1210,X5R,10%

Ceramic,50V,0603,X7R,10%

Ceramic,4V,0805,X5R,10%

Taiyo-Yuden

Panasonic

Murata Electronics

TMK325BJ106MN-T

ECJ-1VB1H104K

GRM21BR60G476ME15L

C14,C15,C16,C31,C32

1 C17

1 C21

1 C22

1 C23

2 C25,C26

1 L1

1.0uF

5.6nF

160pF

2200pF

330uF

0.33uH

Ceramic,25V,0603,X5R,10%

Ceramic,25V,0603,C0G,5%

Ceramic,50V,0603,C0G,5%

SMD Elecrolytic, 25V,F-size,20%

Murata Electronics

Panasonic-ECG

Murata Electronics

TDK Corporation

Panasonic

GRM188R61E105KA12D

C1608C0G1E562J

GRM1885C1H161JA01D

C1608C0G1H222J

EEE-FK1E331P

SMT-Inductor,1.5mOhms,10x11mm,20% Delta

MPL104-R33IR

1 Q1

1 Q2

3 R5,R21,R22

2 R3,R6

1 R4

1 R8

1 R9

2 R11,R19

1 R12

1 R13

IRF6710S2TRPbF IRF6710 SQ 25V

International Rectifier IRF6710S2TRPbF

International Rectifier IRF6795MPbF

IRF6795MPbF

IRF6795 MX 25V

Thick-film,0603,1/10 W,5%

Thick-film,0603,1/10W,1%

Thick-film,0603,1/10 W,1%

Thick-film,0603,1/10W,1%

Thick-film,0603,1/10 W,1%

Thick-film,0603,1/10W,1%

Thick-film,0603,1/10 W,1%

0.250" x 0.300" test pad area

IR3640,Controller,MLPQ,3x4mm

Vishay/Dale

Rohm

Vishey/Dale

Rohm

CRCW06030000Z0EA

4.99K

681

MCR03EZPFX4991

CRCW0603681RFKEA

MCR03EZPFX2261

MCR03EZPFX2372

MCR03EZPFX2551

MCR03EZPFX4121

MCR03EZPFX3241

MCR03EZPFX1300

MCR03EZPFX4021

CRCW060320R0FKEA

2.26K

23.7K

2.55K

4.12K

3.24K

130

1 R14

1 R17

1 R18

4.02K

Label TP

IR3640

Vishey/Dale

4 TP11,TP12,TP13,TP14

1 U1

International Rectifier IR3640

IRDC3640

TYPICAL OPERATING WAVEFORMS

Vin=12.0V, Vcc=5V, Vo=1.8V, Io=0- 25A, Room Temperature, No Air Flow

Fig. 9: Start up at 0A Load (Note 1)

Ch₁:V_o, Ch₂:PGood Ch₃:V_SSCh₄: V_in

Fig. 10: Start up at 25A Load (Note 1)

Ch₁:V_o, Ch₂:PGood Ch₃:V_SSCh₄: V_in

Fig. 12: Output Voltage Ripple, 25A load

Ch₃: V_out

Fig. 11: Start up with 1.5V Prebias,

0A Load, Ch₂:V_outCh₃:V_SSCh₄: PGood

Fig. 14: Short (Hiccup) Recovery

Ch₂:V_out, Ch₃:V_SS, Ch₄:Io

Fig. 13: Inductor node at 25A load

Ch₂:SW

IRDC3640

TYPICAL OPERATING WAVEFORMS

Vin=12V, Vcc=5V, Vo=1.8V, Room Temperature, No Air Flow

Fig. 15: Transient Response

0A-12.5A load Ch₂:V_out, Ch₄:I_o

Note1: Enable is tied to Vin via a resistor divider and triggered when Vin is exceeding above 10V.

IRDC3640

TYPICAL OPERATING WAVEFORMS

Vin=12V, Vcc=5V, Vo=1.8V, Io=0-25A, Room Temperature, No Air Flow

Fig.16: Bode Plot at 25A load shows a bandwidth of 113.6kHz and phase margin of 50.4 degrees

IRDC3640

TYPICAL OPERATING WAVEFORMS

Vin=12V, Vo=1.8V, Io=0-25A, Room Temperature, No Air Flow

IR3640_IRF6710_IRF6795_0.33uH Efficiency vs. Io

Io(A)

IR3640_IRF6710_IRF6795_0.33uH Power Loss vs. Io

Io(A)

Fig.17: Efficiency and power loss vs. load current

IRDC3640

THERMAL IMAGES

Vin=12V, Vo=1.8V, Io=25A, Room Temperature, No Air Flow

Fig.18: Thermal Image at 25A load

Test Point 1: Ctrl FET IRF6710, Test Point 2: Sync FET IRF6795

Test Point 3: Inductor

IRDC3640

PCB Metal and Components Placement

Lead land width should be equal to nominal part lead width. The minimum lead to lead

spacing should be ≥ 0.2mm to minimize shorting.

Lead land length should be equal to maximum part lead length + 0.3 mm outboard

extension +0.05mm inboard extension. The outboard extension ensures a large and

inspectable toe fillet, and the inboard extension will accommodate any part misalignment and

ensure a fillet.

Center pad land length and width should be equal to maximum part pad length and width.

However, the minimum metal to metal spacing should be ≥ 0.17mm for 2 oz. Copper (≥

0.1mm for 1 oz. Copper and ≥ 0.23mm for 3 oz. Copper).

Four 0.30mm diameter via shall be placed in the center of the pad land and connected to

ground to minimize the noise effect on the IC.

IRDC3640

Solder Resist

The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm.

The solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead

lands are all Non Solder Mask Defined (NSMD). Therefore pulling the S/R 0.06mm will always

ensure NSMD pads.

The minimum solder resist width is 0.13mm. At the inside corner of the solder resist where

the lead land groups meet, it is recommended to provide a fillet so a solder resist width of ≥

0.17mm remains.

The land pad should be Non Solder Mask Defined (NSMD), with a minimum pullback of the

solder resist off the copper of 0.06mm to accommodate solder resist mis-alignment.

Ensure that the solder resist in-between the lead lands and the pad land is ≥ 0.15mm due to

the high aspect ratio of the solder resist strip separating the lead lands from the pad land.

Each via in the land pad should be tented or plugged from bottom boardside with solder resist.

IRDC3640

Stencil Design

•

The stencil apertures for the lead lands should be approximately 80% of the area of the

lead lands. Reducing the amount of solder deposited will minimize the occurrence of lead

shorts. Since for 0.5mmpitch devices the leads are only 0.25mm wide, the stencil

apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult

to maintain repeatable solder release.

•

The stencil lead land apertures should therefore be shortened in length by 80% and

centered on the lead land.

The land pad aperture should deposit approximately 50% area of solder on the center

pad. If too much solder is deposited on the center pad the part will float and the lead

lands will be open.

•

The maximum length and width of the land pad stencil aperture should be equal to the

solder resist opening minus an annular 0.2mm pull back to decrease the incidence of

shorting the center land to the lead lands when the part is pushed into the solder paste.

IRDC3640

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

This product has been designed and qualified for the Consumer market.

Visit us at www.irf.com for sales contact information

Data and specifications subject to change without notice. 11/07

IRDC3640 [INFINEON]

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