IRDC3802 [INFINEON]

USER GUIDE FOR IR3802 EVALUATION BOARD; 用户指南IR3802评估板
IRDC3802
型号: IRDC3802
厂家: Infineon    Infineon
描述:

USER GUIDE FOR IR3802 EVALUATION BOARD
用户指南IR3802评估板

文件: 总16页 (文件大小:1186K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
IRDC3802  
TM  
SupIRBuck  
USER GUIDE FOR IR3802 EVALUATION BOARD  
DESCRIPTION  
An output over-current protection function is  
implemented by sensing the voltage  
developed across the on-resistance of the  
synchronous rectifier MOSFET for optimum  
cost and performance.  
The IR3802 is a synchronous buck  
converter, providing a compact, high  
performance and flexible solution in a  
small 5mmx6mm Power QFN package.  
Key features offered by the IR3802  
include programmable soft-start ramp,  
precision 0.6V reference voltage, thermal  
protection, fixed 600kHz switching  
This user guide contains the schematic and  
bill of materials for the IR3802 evaluation  
board. The guide describes operation and  
use of the evaluation board itself. Detailed  
application information for IR3802 is  
available in the IR3802 data sheet.  
frequency requiring  
no external  
component, input under-voltage lockout  
for proper start-up, and pre-bias start-up.  
BOARD FEATURES  
Vin = +12V (13.2V Max)  
Vout = +3.3V @ 0- 4A  
L = 3.3uH  
Cin= 1x10uF (ceramic 1206)  
Cout= 1x22uF (ceramic 0805), 1x220uF/6.3V (SP-Cap)  
Rev 0.1  
6/16/2008  
1
IRDC3802  
CONNECTIONS and OPERATING INSTRUCTIONS  
A well regulated +12V input supply should be connected to VIN+ and VIN-. A maximum 4A load  
should be connected to VOUT+ and VOUT-. The connection diagram is shown in Fig. 1 and inputs  
and outputs of the board are listed in Table I.  
IR3802 has two input supplies, one for biasing (Vcc) and the other as input voltage (Vin). These  
inputs are connected on the board with a 330 ohm resistor (R13). Separate supplies can be applied  
to these inputs. Vcc input cannot be connected unless R13 is removed. Vcc input should be a well  
regulated 5V-12V supply and it would be connected to Vcc+ and Vcc-.  
Table I. Connections  
Connection  
VIN+  
Signal Name  
Vin (+12V)  
VIN-  
Ground of Vin  
Vcc+  
Optional Vcc input  
Ground for Optional Vcc input  
Ground of Vout  
Vcc-  
VOUT-  
VOUT+  
Vout (+3.3V)  
LAYOUT  
The PCB is a 4-layer board. All of layers are 2 Oz. copper. The IR3802A SupIRBuck and all of  
the passive components are mounted on the bottom side of the board. The Inductor, Input and  
Output Bulk Capacitors are located on the top side of the board.  
Power supply decoupling capacitors, the charge-pump capacitor and feedback components are  
located close to IR3802A. The feedback resistors are connected to the output voltage at the point  
of regulation and are located close to the SupIRBuck.  
To improve efficiency, the circuit board is designed to minimize the length of the on-board power  
ground current path.  
Rev 0.1  
2
6/16/2008  
IRDC3802  
Connection Diagram  
Vcc+  
Vcc-  
Vout+  
Vin+  
Vin-  
Vout-  
20mm/787mil’s  
Front  
Vcc- Vcc+  
Vout+  
Vin+  
Vout-  
Vin-  
20mm/787mil’s  
Back  
Fig. 1: Connection diagram of IR3802A evaluation board  
Rev 0.1  
3
6/16/2008  
IRDC3802  
Fig. 2: Board layout, top overlay  
Single point  
connection  
between  
AGND and  
PGND.  
PGND  
Plain  
PGND  
Plain  
Fig. 3: Board layout, bottom overlay (rear  
view)  
Rev 0.1  
4
6/16/2008  
IRDC3802  
Fig. 4: Board layout, mid-layer I.  
Fig. 5: Board layout, mid-layer II.  
Rev 0.1  
5
6/16/2008  
IRDC3802  
Rev 0.1  
6
6/16/2008  
IRDC3802  
Bill of Materials  
Item  
Number Quantity Part Reference  
Value  
Description  
Manufacturer  
Part Number  
1
2
3
4
5
6
7
8
1
1
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
B1  
C1  
ESDB016,Rev A ESDB016,Rev A, PCB  
International Rectifier  
TDK Corporation  
Panasonic - ECG  
Sanyo  
Panasonic - ECG  
Kemet  
Murata  
Murata  
Panasonic - ECG  
Panasonic - ECG  
TDK  
Panasonic  
International Rectifier  
ACT  
Panasonic - ECG  
Rohm  
Rohm  
Rohm  
Vishey/Dale  
Rohm  
Rohm  
International Rectifier  
ESDB016,Rev A  
10uF  
0.1uF  
47uF  
Ceramic,16V,1206,X7R,10%  
Ceramic,25V,0603,X7R,10%  
Poscap,16V,D2,Polomer-Aluminum  
Ceramic,50V,0603,NPO,5%  
Ceramic,50V,0603,C0G,10%  
Ceramic,50V,0603,X7R,10%  
Ceramic,50V,0603,X7R,10%  
Ceramic,10V,0603,X5R,10%  
Ceramic,16V,0603,X5R,10%  
Ceramic,6.3V,0805,X5R,20%  
SP-Cap,4.0V,D4,Polymer-Aluminum  
Diode,Schotky,40V,SOD323,200mA  
SMT-Inductor,18mOhms,7.5x7.5mm,20%  
Thick-film,0603,1/10W,1%  
Thick-film,0603,1/10W,1%  
Thick-film,0603,1/10W,1%  
Thick-film,0603,1/10W,1%  
Thick-film,0603,1/10 W,1%  
Thick-film,0603,1/10 W,1%  
Thick-film,0805,1/8W,1%  
C3216X7R1C106K  
ECJ-1VB1E104K  
16TQC47M  
C2 C12 C14  
C3  
C6  
C7  
C8  
22pF  
ECJ-1VC1H220J  
C0603C102J5GACTU  
GRM188R71H821KA01D  
GRM188R71H561KA01D  
ECJ-1VB1A224K  
ECJ-BVB1C105K  
C2012X5R0J226M  
EEFUE0G221XE  
BAT54WS  
1000pF  
820pF  
560pF  
0.22uF  
1uF  
C9  
9
C10  
C13  
C15  
C16  
D2  
L1  
R1  
R2  
R3  
R4  
R6  
R12  
R13  
U1  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
22uF  
220uF  
BAT54WS  
3.3uH  
36.0K  
28.7K  
6.34K  
1.8K  
20  
8.06K  
330  
STS704-3R3M  
ERJ-3EKF3602V  
MCR03EZPFX2872  
MCR03EZPFX6341  
MCR03EZPFX1801  
CRCW060320R0FKEA  
MCR03EZPFX8061  
MCR10EZPF3300  
IR3802  
IR3802  
IR3802, Controller,PQFN,5x6mm  
Rev 0.1  
7
6/16/2008  
IRDC3802  
TYPICAL OPERATING WAVEFORMS  
Vin=12.0V, Vcc = 6.3V, Vo=3.3V, Io=0- 4A, Room Temperature, No Air Flow  
Fig. 7: Start up at 4A Load  
Fig. 8: Pre-Bias Start up, 0A Load  
Ch1:Vin, Ch2:VSS, Ch3:Vout  
Ch1:Vin, Ch2:VSS, Ch3:Vout, Ch4:Iout  
Fig. 9: Output Voltage Ripple, 4A load  
Ch1: Vout ,Ch4: Iout  
Fig. 10: Inductor node at 4A load  
Ch1:LX, Ch4:Iout  
Fig. 11: Short (Hiccup) Recovery  
Ch1:VSS , Ch2:Vout  
Rev 0.1  
8
6/16/2008  
IRDC3802  
TYPICAL OPERATING WAVEFORMS  
Vin=12.0V, Vcc = 6.3V, Vo=3.3V, Io=0- 4A, Room Temperature, No Air Flow  
Fig. 12: Transient Response, 2A to 4A step  
Ch1:Vout, Ch4:Iout  
Rev 0.1  
9
6/16/2008  
IRDC3802  
TYPICAL OPERATING WAVEFORMS  
Vin=12.0V, Vcc = 6.3V, Vo=3.3V, Io=0- 4A, Room Temperature, No Air Flow  
Fig. 13: Bode Plot at 4A load shows a bandwidth of 32+kHz and phase margin of  
52+degrees  
Rev 0.1  
6/16/2008  
10  
IRDC3802  
TYPICAL OPERATING WAVEFORMS  
Vin=12.0V, Vcc = 6.3V, Vo=3.3V, Io=0- 4A, Room Temperature, No Air Flow  
Efficiency for IR3802 at 12.0Vin, 3.3Vout and R13  
= 330  
92  
90  
88  
86  
84  
82  
80  
78  
76  
74  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
4.0  
4.5  
Iout (A)  
Fig.14: Efficiency versus load current  
Power Loss for IR3802 at 12.0Vin, 3.3Vout, and  
R13 = 330  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0.0  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
4.0  
4.5  
Iout (A)  
Fig.15: Power loss versus load  
current  
Rev 0.1  
11  
6/16/2008  
IRDC3802  
TYPICAL OPERATING WAVEFORMS  
Vin=12.0V, Vcc = 6.3V, Vo=3.3V, Io=0- 4A, Room Temperature, No Air Flow  
Fig. 16: Thermal Image at 4A load at 50.4o C  
Test point (square) 1 is IR3802  
Rev 0.1  
12  
6/16/2008  
IRDC3802  
PCB Metal and Components Placement  
The lead lands (the 11 IC pins) width should be equal to the nominal part lead width. The  
minimum lead to lead spacing should be 0.2mm to minimize shorting.  
Lead land length should be equal to the maximum part lead length + 0.3 mm outboard  
extension. The outboard extension ensures a large and inspectable toe fillet.  
The pad lands (the 4 big pads other than the 11 IC pins) length and width should be equal to  
maximum part pad length and width. However, the minimum metal to metal spacing should be  
no less than 0.17mm for 2 oz. Copper; no less than 0.1mm for 1 oz. Copper and no less than  
0.23mm for 3 oz. Copper.  
Rev 0.1  
6/16/2008  
IRDC3802  
Solder Resist  
It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder  
resist should be pulled away from the metal lead lands by a minimum of 0.025mm to  
ensure NSMD pads.  
The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder  
resist onto the copper of 0.05mm to accommodate solder resist mis-alignment.  
Ensure that the solder resist in between the lead lands and the pad land is 0.15mm due  
to the high aspect ratio of the solder resist strip separating the lead lands from the pad  
land.  
Rev 0.1  
6/16/2008  
IRDC3802  
Stencil Design  
The Stencil apertures for the lead lands should be approximately 80% of the area  
of the lead lads. Reducing the amount of solder deposited will minimize the  
occurrences of lead shorts. If too much solder is deposited on the center pad the  
part will float and the lead lands will be open.  
The maximum length and width of the land pad stencil aperture should be equal to  
the solder resist opening minus an annular 0.2mm pull back to decrease the  
incidence of shorting the center land to the lead lands when the part is pushed into  
the solder paste.  
Rev 0.1  
6/16/2008  
IRDC3802  
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105  
TAC Fax: (310) 252-7903  
This product has been designed and qualified for the Consumer market.  
Visit us at www.irf.com for sales contact information  
Data and specifications subject to change without notice. 11/07  
Rev 0.1  
6/16/2008  

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