IRF2903ZS [INFINEON]
HEXFET Power MOSFET; HEXFET功率MOSFET型号: | IRF2903ZS |
厂家: | Infineon |
描述: | HEXFET Power MOSFET |
文件: | 总12页 (文件大小:415K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PD - 96988A
IRF2903Z
IRF2903ZS
AUTOMOTIVE MOSFET
IRF2903ZL
HEXFET® Power MOSFET
Features
D
l
Advanced Process Technology
Ultra Low On-Resistance
175°C Operating Temperature
Fast Switching
VDSS = 30V
l
l
l
l
RDS(on) = 2.4mΩ
G
Repetitive Avalanche Allowed up to Tjmax
ID = 75A
S
Description
Specifically designed for Automotive applications,
this HEXFET® Power MOSFET utilizes the latest
processingtechniquestoachieveextremelylowon-
resistance per silicon area. Additional features of
thisdesign area175°Cjunctionoperatingtempera-
ture, fast switching speed and improved repetitive
avalanche rating . These features combine to make
thisdesignanextremelyefficientandreliabledevice
foruseinAutomotiveapplicationsandawidevariety
of other applications.
D
D
D
S
S
S
D
D
D
G
G
G
D2Pak
TO-262
TO-220AB
IRF2903Z
IRF2903ZS
IRF2903ZL
G
Gate
D
S
Drain
Source
Absolute Maximum Ratings
Parameter
Max.
260
180
75
Units
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Package Limited)
Pulsed Drain Current
I
I
I
I
@ T = 25°C
C
D
D
D
@ T = 100°C
C
A
@ T = 25°C
C
1020
290
2.0
DM
P
@T = 25°C Power Dissipation
C
W
W/°C
V
D
Linear Derating Factor
± 20
290
820
V
Gate-to-Source Voltage
GS
EAS (Thermally limited)
Single Pulse Avalanche Energy
Single Pulse Avalanche Energy Tested Value
Avalanche Current
mJ
EAS (Tested )
IAR
See Fig.12a, 12b, 15, 16
A
EAR
Repetitive Avalanche Energy
Operating Junction and
mJ
-55 to + 175
T
T
J
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting Torque, 6-32 or M3 screw
°C
STG
300 (1.6mm from case )
10 lbf in (1.1N m)
Thermal Resistance
Parameter
Typ.
–––
Max.
0.51
–––
62
Units
RθJC
RθCS
RθJA
RθJA
Junction-to-Case
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
0.50
–––
°C/W
Junction-to-Ambient (PCB Mount, steady state)
–––
40
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1
8/26/05
IRF2903Z/S/L
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
Min. Typ. Max. Units
30 ––– –––
Conditions
VGS = 0V, ID = 250µA
Reference to 25°C, ID = 1mA
VGS = 10V, ID = 75A
V(BR)DSS
∆V(BR)DSS/∆TJ
RDS(on)
VGS(th)
V
Breakdown Voltage Temp. Coefficient ––– 0.021 ––– V/°C
mΩ
V
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
–––
2.0
1.9
–––
–––
–––
–––
–––
2.4
4.0
–––
20
VDS = VGS, ID = 150µA
VDS = 10V, ID = 75A
gfs
IDSS
Forward Transconductance
120
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
S
V
DS = 30V, VGS = 0V
VDS = 30V, VGS = 0V, TJ = 125°C
GS = 20V
Drain-to-Source Leakage Current
µA
250
200
V
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
nA
nC
VGS = -20V
ID = 75A
––– -200
Qg
Qgs
Qgd
td(on)
tr
160
51
240
–––
–––
–––
–––
–––
–––
–––
VDS = 24V
VGS = 10V
VDD = 15V
ID = 75A
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
58
24
Rise Time
100
48
RG = 3.2 Ω
VGS = 10V
Between lead,
td(off)
tf
Turn-Off Delay Time
ns
Fall Time
37
LD
Internal Drain Inductance
4.5
nH 6mm (0.25in.)
from package
LS
Internal Source Inductance
–––
7.5
–––
and center of die contact
VGS = 0V
Ciss
Input Capacitance
––– 6320 –––
––– 1980 –––
––– 1100 –––
––– 5930 –––
––– 2010 –––
––– 3050 –––
VDS = 25V
Coss
Output Capacitance
Crss
ƒ = 1.0MHz
Reverse Transfer Capacitance
Output Capacitance
pF
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 0V, VDS = 24V, ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 24V
Coss
Coss
Output Capacitance
Coss eff.
Effective Output Capacitance
Source-Drain Ratings and Characteristics
Parameter
Min. Typ. Max. Units
Conditions
MOSFET symbol
I
Continuous Source Current
–––
–––
75
S
showing the
(Body Diode)
A
integral reverse
I
Pulsed Source Current
(Body Diode)
–––
––– 1020
SM
p-n junction diode.
T = 25°C, I = 75A, V = 0V
V
t
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
–––
–––
–––
–––
34
1.3
51
44
V
J
S
GS
SD
T = 25°C, I = 75A, VDD = 15V
ns
nC
J
F
rr
di/dt = 100A/µs
Q
29
rr
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
t
on
2
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IRF2903Z/S/L
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
TOP
TOP
BOTTOM
BOTTOM
4.5V
4.5V
≤ 60µs PULSE WIDTH
≤ 60µs PULSE WIDTH
Tj = 25°C
Tj = 175°C
1
0.1
1
10
100
1000
0.1
1
10
100
1000
V
, Drain-to-Source Voltage (V)
V
DS
, Drain-to-Source Voltage (V)
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000.0
240
T
= 25°C
J
200
160
120
80
100.0
10.0
1.0
T
= 175°C
J
T
= 175°C
J
T
= 25°C
J
V
= 25V
DS
40
V
= 10V
DS
380µs PULSE WIDTH
≤ 60µs PULSE WIDTH
0.1
0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0 10.0
0
20 40 60 80 100 120 140 160 180
Drain-to-Source Current (A)
V
, Gate-to-Source Voltage (V)
GS
I
D,
Fig 3. Typical Transfer Characteristics
Fig 4. Typical Forward Transconductance
Vs. Drain Current
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3
IRF2903Z/S/L
12000
20
16
12
8
V
C
= 0V,
f = 1 MHZ
GS
I = 75A
D
V
= 24V
= C + C , C SHORTED
DS
VDS= 15V
iss
gs
gd ds
C
= C
10000
8000
6000
4000
2000
0
rss
gd
C
= C + C
oss
ds
gd
Ciss
Coss
Crss
4
0
0
40
80
120
160
200
240
1
10
100
Q
Total Gate Charge (nC)
G
V
, Drain-to-Source Voltage (V)
DS
Fig 6. Typical Gate Charge Vs.
Fig 5. Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
1000.0
100.0
10.0
1.0
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
T
= 175°C
J
1msec
100µsec
10msec
DC
LIMITED BY PACKAGE
T
= 25°C
J
1
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
GS
0.1
0.1
0.0
0.4
0.8
1.2
1.6
2.0
2.4
0.1
1.0
10.0
100.0
V
, Drain-toSource Voltage (V)
V
, Source-to-Drain Voltage (V)
DS
SD
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
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IRF2903Z/S/L
2.0
1.5
1.0
0.5
300
250
200
150
100
50
I
= 75A
LIMITED BY PACKAGE
D
V
= 10V
GS
0
25
50
75
100
125
150
175
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
T
, Case Temperature (°C)
C
T
, Junction Temperature (°C)
J
Fig 10. Normalized On-Resistance
Fig 9. Maximum Drain Current Vs.
Vs. Temperature
Case Temperature
1
D = 0.50
0.20
0.10
0.05
0.1
0.01
R1
R2
R2
R3
R3
Ri (°C/W) τi (sec)
0.08133 0.000044
R1
τ
JτJ
τ
τ
Cτ
τ
1τ1
τ
0.02
0.01
2 τ2
3τ3
0.2408 0.000971
0.18658 0.008723
Ci= τi/Ri
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRF2903Z/S/L
1200
1000
800
600
400
200
0
15V
I
D
TOP
26A
42A
75A
DRIVER
+
L
V
BOTTOM
DS
D.U.T
AS
R
G
V
DD
-
I
A
V
20V
GS
0.01
Ω
t
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
25
50
75
100
125
150
175
Starting T , Junction Temperature (°C)
J
I
AS
Fig 12c. Maximum Avalanche Energy
Fig 12b. Unclamped Inductive Waveforms
Vs. Drain Current
Q
G
10 V
Q
Q
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
GS
GD
I
I
= 1.0A
D
D
= 1.0mA
V
G
ID = 250µA
= 150µA
I
D
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
.2µF
12V
.3µF
+
V
DS
D.U.T.
-
-75 -50 -25
0
J
25 50 75 100 125 150 175
, Temperature ( °C )
V
GS
3mA
T
I
I
D
G
Current Sampling Resistors
Fig 14. Threshold Voltage Vs. Temperature
Fig 13b. Gate Charge Test Circuit
6
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IRF2903Z/S/L
1000
100
10
Duty Cycle = Single Pulse
0.01
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.05
0.10
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
300
250
200
150
100
50
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
TOP
BOTTOM 1% Duty Cycle
= 75A
Single Pulse
I
D
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
0
25
50
75
100
125
150
175
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
Starting T , Junction Temperature (°C)
J
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
Fig 16. Maximum Avalanche Energy
EAS (AR) = PD (ave)·tav
Vs. Temperature
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7
IRF2903Z/S/L
Driver Gate Drive
P.W.
P.W.
Period
D.U.T
Period
D =
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Curent
I
SD
Ripple
≤ 5%
* VGS = 5V for Logic Level Devices
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
RD
VDS
VGS
D.U.T.
RG
+VDD
-
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 18a. Switching Time Test Circuit
V
DS
90%
10%
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 18b. Switching Time Waveforms
8
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IRF2903Z/S/L
TO-220ABPackageOutline
TO-220ABPartMarkingInformation
EXAMPLE: THIS IS AN IRF1010
PART NUMBER
LOT CODE 1789
ASSEMBLED ON WW 19, 2000
IN THE ASSEMBLY LINE "C"
INTERNATIONAL
RECTIFIER
LOGO
DATE CODE
YEAR 0 = 2000
WEEK 19
Note: "P" in assembly lineposition
indicates "L ead - F ree"
ASSEMBLY
LOT CODE
LINE C
TO-220AB package is not recommended for Surface Mount Application.
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9
IRF2903Z/S/L
D2Pak Package Outline (Dimensions are shown in millimeters (inches))
D2PakPartMarkingInformation
THIS IS AN IRF530S WITH
PART NUMBER
LOT CODE 8024
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLED ON WW 02, 2000
IN THE ASSEMBLY LINE "L"
F530S
DATE CODE
YEAR 0 = 2000
WEEK 02
Note: "P" in assembly line
position indicates "Lead-Free"
ASSEMBLY
LOT CODE
LINE L
OR
PART NUMBER
DATE CODE
INTERNATIONAL
RECTIFIER
LOGO
F530S
P = DE S I GNAT E S L E AD-F RE E
PRODUCT (OPTIONAL)
YEAR 0 = 2000
ASSEMBLY
LOT CODE
WEEK 02
A= ASSEMBLY SITE CODE
10
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IRF2903Z/S/L
TO-262 Package Outline (Dimensions are shown in millimeters (inches))
IGBT
1-GATE
2-COLLECTOR
3-EMITTER
4-COLLECTOR
TO-262 Part Marking Information
EXAMPLE: THIS IS AN IRL3103L
LOT CODE 1789
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLED ON WW 19, 1997
IN THE ASSEMBLY LINE "C"
DATE CODE
YEAR 7 = 1997
WE EK 19
Note: "P" in assembly line
pos ition indicates "L ead-F ree"
AS S E MB LY
LOT CODE
LINE C
OR
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
DATE CODE
P = DE S IGNAT E S L E AD-F RE E
PRODUCT (OPTIONAL)
YEAR 7 = 1997
AS S E MBL Y
LOT CODE
WEEK 19
A = AS S E MB L Y S IT E CODE
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11
IRF2903Z/S/L
D2Pak Tape & Reel Information
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
1.85 (.073)
11.60 (.457)
11.40 (.449)
1.65 (.065)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
TRL
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
4
3
Notes:
ꢀ
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Limited by TJmax, starting TJ = 25°C, L = 0.10mH
This value determined from sample failure population. 100%
tested to this value in production.
RG = 25Ω, IAS = 75A, VGS =10V. Part not
recommended for use above this value.
This is only applied to TO-220AB pakcage.
Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the
same charging time as Coss while VDS is rising
This is applied to D2Pak, when mounted on 1" square PCB (FR-
4 or G-10 Material). For recommended footprint and soldering
techniques refer to application note #AN-994.
from 0 to 80% VDSS
.
Rθ is measured at TJ approximately 90°C
Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive [Q101]market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 08/05
12
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