IRFB3307ZPBF [INFINEON]
HEXFET Power MOSFET; HEXFET功率MOSFET
| 型号： | IRFB3307ZPBF |
| 厂家： | 
Infineon |
| 描述： | HEXFET Power MOSFET |
| 文件： | 总11页 (文件大小：836K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 97214B
IRFB3307ZPbF
IRFS3307ZPbF
IRFSL3307ZPbF
Applications
l High Efficiency Synchronous Rectification in
SMPS
HEXFET® Power MOSFET
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
D
S
VDSS
RDS(on) typ.
max.
ID (Silicon Limited)
ID (Package Limited)
75V
4.6m
5.8m
120A
:
:
c
G
Benefits
75A
l Improved Gate, Avalanche and Dynamic
dv/dt Ruggedness
l Fully Characterized Capacitance and
Avalanche SOA
D
D
D
l Enhanced body diode dV/dt and dI/dt
Capability
S
S
D
S
D
G
G
G
D2Pak
TO-262
TO-220AB
IRFB3307ZPbF
IRFS3307ZPbF
IRFSL3307ZPbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
Parameter
Max.
120c
88c
Units
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Package Limited)
Pulsed Drain Current d
ID @ TC = 100°C
ID @ TC = 25°C
IDM
A
75
480
PD @TC = 25°C
230
W
Maximum Power Dissipation
1.5
Linear Derating Factor
W/°C
V
VGS
± 20
Gate-to-Source Voltage
6.7
Peak Diode Recovery f
dv/dt
TJ
V/ns
°C
-55 to + 175
Operating Junction and
TSTG
Storage Temperature Range
300
Soldering Temperature, for 10 seconds
(1.6mm from case)
10lbxin (1.1Nxm)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
Single Pulse Avalanche Energy e
EAS (Thermally limited)
140
75
mJ
A
Avalanche Currentꢀc
IAR
Repetitive Avalanche Energy g
EAR
23
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
0.65
–––
62
Units
RθJC
Junction-to-Case k
RθCS
RθJA
RθJA
0.50
–––
–––
°C/W
Case-to-Sink, Flat Greased Surface , TO-220
Junction-to-Ambient, TO-220 k
Junction-to-Ambient (PCB Mount) , D2Pak jk
40
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1
05/31/07
IRFB/S/SL3307ZPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Min. Typ. Max. Units
75 ––– –––
––– 0.094 ––– V/°C Reference to 25°C, ID = 5mAd
Conditions
VGS = 0V, ID = 250µA
V
∆V(BR)DSS/∆TJ
RDS(on)
–––
2.0
–––
4.6
5.8
4.0
VGS = 10V, ID = 75A g
mΩ
V
VGS(th)
–––
VDS = VGS, ID = 150µA
RG(int)
IDSS
Internal Gate Resistance
Drain-to-Source Leakage Current
0.70 –––
20
Ω
––– –––
µA VDS = 75V, VGS = 0V
––– ––– 250
––– ––– 100
––– ––– -100
V
V
V
DS = 75V, VGS = 0V, TJ = 125°C
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
nA
GS = 20V
GS = -20V
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
320 ––– –––
Conditions
VDS = 50V, ID = 75A
S
–––
–––
–––
–––
–––
–––
–––
–––
79
19
24
55
15
64
38
65
110
–––
–––
–––
–––
–––
–––
–––
nC ID = 75A
VDS = 38V
Qgs
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
Turn-On Delay Time
Qgd
VGS = 10V g
Qsync
ID = 75A, VDS =0V, VGS = 10V
td(on)
ns VDD = 49V
ID = 75A
tr
Rise Time
td(off)
Turn-Off Delay Time
RG = 2.6Ω
VGS = 10V g
tf
Fall Time
Ciss
Input Capacitance
––– 4750 –––
––– 420 –––
––– 190 –––
––– 440 –––
––– 410 –––
pF VGS = 0V
Coss
Output Capacitance
V
DS = 50V
ƒ = 1.0MHz
GS = 0V, VDS = 0V to 60V j
Crss
Reverse Transfer Capacitance
Coss eff. (ER)
Coss eff. (TR)
V
Effective Output Capacitance (Energy Related)
i
VGS = 0V, VDS = 0V to 60V h
Effective Output Capacitance (Time Related)
h
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
Conditions
D
S
IS
Continuous Source Current
––– –––
A
MOSFET symbol
120
c
(Body Diode)
showing the
integral reverse
G
ISM
Pulsed Source Current
(Body Diode)ꢀdi
Diode Forward Voltage
Reverse Recovery Time
––– ––– 480
p-n junction diode.
TJ = 25°C, IS = 75A, VGS = 0V g
VSD
trr
––– –––
1.3
50
V
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
VR = 64V,
–––
–––
–––
–––
–––
33
39
42
56
2.2
ns
IF = 75A
59
di/dt = 100A/µs g
Qrr
Reverse Recovery Charge
63
nC
84
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
–––
A
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Calculated continuous current based on maximum allowable junction
temperature. Package limitation current is 75A.
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.050mH
RG = 25Ω, IAS = 75A, VGS =10V. Part not recommended for use
above this value.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS
.
.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C.
ISD ≤ 75A, di/dt ≤ 1570A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
ꢁ Pulse width ≤ 400µs; duty cycle ≤ 2%.
2
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IRFB/S/SL3307ZPbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
TOP
TOP
BOTTOM
BOTTOM
4.5V
4.5V
60µs PULSE WIDTH
Tj = 175°C
≤
60µs PULSE WIDTH
Tj = 25°C
≤
1
1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
100
10
2.5
2.0
1.5
1.0
0.5
I
= 72A
D
V
= 10V
GS
T
= 175°C
J
T
= 25°C
J
1
V
= 25V
DS
≤
60µs PULSE WIDTH
0.1
2
3
4
5
6
7
8
-60 -40 -20 0 20 40 60 80 100120140160180
, Junction Temperature (°C)
T
J
V
, Gate-to-Source Voltage (V)
GS
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
12.0
100000
10000
1000
V
= 0V,
= C
f = 1 MHZ
GS
I
= 72A
D
C
C
C
+ C , C
SHORTED
iss
gs
gd
ds
= C
10.0
8.0
6.0
4.0
2.0
0.0
rss
oss
gd
V
V
V
= 60V
= 38V
= 15V
DS
DS
DS
= C + C
ds
gd
C
iss
C
oss
C
rss
100
0
10 20 30 40 50 60 70 80 90
1
10
, Drain-to-Source Voltage (V)
100
Q , Total Gate Charge (nC)
G
V
DS
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFB/S/SL3307ZPbF
1000
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
T
= 175°C
J
100
10
1
100µsec
T
= 25°C
J
1msec
10msec
DC
1
Tc = 25°C
Tj = 175°C
V
= 0V
GS
Single Pulse
0.1
0.1
0.0
0.5
1.0
1.5
2.0
1
10
, Drain-to-Source Voltage (V)
100
V
, Source-to-Drain Voltage (V)
V
SD
DS
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode Forward Voltage
120
100
95
90
85
80
75
70
65
Id = 5mA
Limited By Package
100
80
60
40
20
0
25
50
75
100
125
150
175
-60 -40 -20
0
20 40 60 80 100120140160180
T
, Case Temperature (°C)
T , Temperature ( °C )
C
J
Fig 10. Drain-to-Source Breakdown Voltage
Fig 9. Maximum Drain Current vs. Case Temperature
1.2
600
I
D
TOP
15A
26A
1.0
0.8
0.6
0.4
0.2
0.0
500
400
300
200
100
0
BOTTOM 75A
20
30
V
40
50
60
70
80
25
50
75
100
125
150
175
Starting T , Junction Temperature (°C)
J
Drain-to-Source Voltage (V)
DS,
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
Fig 11. Typical COSS Stored Energy
4
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IRFB/S/SL3307ZPbF
1
D = 0.50
0.20
0.10
0.05
0.1
R1
R1
R2
R2
R3
R3
Ri (°C/W) τi (sec)
0.1164 0.000088
τ
JτJ
τ
τ
Cτ
0.02
0.01
τ
1τ1
τ
2 τ2
3τ3
0.3009 0.001312
0.2313 0.009191
0.01
Ci= τi/Ri
Notes:
SINGLE PULSE
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
10
1
Allowed avalanche Current vs avalanche
0.01
∆
pulsewidth, tav, assuming Tj = 150°C and
Tstart =25°C (Single Pulse)
Duty Cycle =
Single Pulse
0.05
0.10
Allowed avalanche Current vs avalanche
∆Τ
pulsewidth, tav, assuming
Tstart = 150°C.
j = 25°C and
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
150
125
100
75
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
TOP
BOTTOM 1.0% Duty Cycle
= 75A
Single Pulse
I
D
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
50
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
25
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
0
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25
50
75
100
125
150
175
Iav = 2DT/ [1.3·BV·Zth]
Starting T , Junction Temperature (°C)
EAS (AR) = PD (ave)·tav
J
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFB/S/SL3307ZPbF
4.5
4.0
3.5
3.0
2.5
20
15
10
5
I
= 48A
= 64V
F
V
R
T = 25°C
J
T = 125°C
J
I
I
I
I
= 150µA
= 250µA
= 1.0mA
= 1.0A
2.0
1.5
1.0
0.5
D
D
D
D
0
-75 -50 -25
0
25 50 75 100 125 150 175 200
, Temperature ( °C )
0
200
400
600
800
1000
T
di /dt (A/µs)
J
F
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
20
420
I = 72A
I = 48A
F
F
V
= 64V
V
= 64V
R
R
340
260
180
100
20
T = 25°C
T = 25°C
J
J
15
10
5
T = 125°C
J
T = 125°C
J
0
0
200
400
600
800
1000
0
200
400
600
800
1000
di /dt (A/µs)
di /dt (A/µs)
F
F
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
420
I
= 72A
= 64V
F
V
R
340
260
180
100
20
T = 25°C
J
T = 125°C
J
0
200
400
600
800
1000
di /dt (A/µs)
F
Fig. 20 - Typical Stored Charge vs. dif/dt
6
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IRFB/S/SL3307ZPbF
Driver Gate Drive
P.W.
P.W.
D =
Period
D.U.T
Period
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Current
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 20. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
V
2
GS
0.01Ω
t
p
I
AS
Fig 21b. Unclamped Inductive Waveforms
Fig 21a. Unclamped Inductive Test Circuit
LD
VDS
VDS
90%
+
-
VDD
10%
VGS
D.U.T
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
td(on)
td(off)
tr
tf
Fig 22a. Switching Time Test Circuit
Fig 22b. Switching Time Waveforms
Id
Vds
Vgs
L
VCC
DUT
Vgs(th)
0
1K
Qgs1
Qgs2
Qgd
Qgodr
Fig 23a. Gate Charge Test Circuit
Fig 23b. Gate Charge Waveform
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7
IRFB/S/SL3307ZPbF
TO-220AB Package Outline (Dimensions are shown in millimeters (inches))
TO-220AB Part Marking Information
Note: "P" in assembly line
position indicates "Lead-Free"
TO-220AB packages are not recommended for Surface Mount Application.
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/pkhexfet.html
8
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IRFB/S/SL3307ZPbF
D2Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)
D2Pak (TO-263AB) Part Marking Information
25
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/pkhexfet.html
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9
IRFB/S/SL3307ZPbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
25
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/pkhexfet.html
10
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IRFB/S/SL3307ZPbF
D2Pak (TO-263AB) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
1.85 (.073)
11.60 (.457)
11.40 (.449)
1.65 (.065)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
TRL
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
4
3
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/pkhexfet.html
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 05/07
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相关型号：
IRFB3607GPBF
Power Field-Effect Transistor, 80A I(D), 75V, 0.009ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-220AB, HALOGEN FREE AND LEAD FREE, PLASTIC PACKAGE-3
INFINEON
IRFB3806
The IR MOSFET™ family of power MOSFETs utilizes proven silicon processes offering designers a wide portfolio of devices to support various applications such as DC motors, inverters, SMPS, lighting, load switches as well as battery powered applications. The devices are available in a variety of surface mount and through-hole packages with industry standard footprints for ease of design. The optimized gate drive options enables designers the flexibility of selecting super, logic or normal level drives.
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