IRFB4019PBF [INFINEON]
DIGITAL AUDIO MOSFET; 数字音频MOSFET
| 型号： | IRFB4019PBF |
| 厂家： | 
Infineon |
| 描述： | DIGITAL AUDIO MOSFET |
| 文件： | 总7页 (文件大小：279K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 97075
IRFB4019PbF
Key Parameters
DIGITAL AUDIO MOSFET
Features
• Key Parameters Optimized for Class-D Audio
Amplifier Applications
VDS
150
V
m:
RDS(ON) typ. @ 10V
Qg typ.
80
• Low RDSON for Improved Efficiency
• Low QG and QSW for Better THD and Improved
Efficiency
13
nC
nC
Ω
Q
sw typ.
5.1
2.4
175
RG(int) typ.
• Low QRR for Better THD and Lower EMI
• 175°C Operating Junction Temperature for
Ruggedness
TJ max
°C
D
S
D
• Can Deliver up to 200W per Channel into 8Ω Load in
Half-Bridge Configuration Amplifier
G
S
D
G
TO-220AB
G
D
S
Gate
Drain
Source
Description
This Digital Audio MOSFET is specifically designed for Class-D audio amplifier applications. This MOSFET utilizes
thelatestprocessingtechniquestoachievelowon-resistancepersiliconarea.Furthermore,Gatecharge,body-diode
reverse recovery and internal Gate resistance are optimized to improve key Class-D audio amplifier performance
factors such as efficiency, THD and EMI. Additional features of this MOSFET are 175°C operating junction
temperature and repetitive avalanche capability. These features combine to make this MOSFET a highly efficient,
robust and reliable device for ClassD audio amplifier applications.
Absolute Maximum Ratings
Parameter
Drain-to-Source Voltage
Max.
150
±20
17
Units
V
VDS
VGS
Gate-to-Source Voltage
ID @ TC = 25°C
ID @ TC = 100°C
IDM
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current c
A
12
51
Power Dissipation f
PD @TC = 25°C
PD @TC = 100°C
80
W
Power Dissipation f
40
Linear Derating Factor
Operating Junction and
0.5
W/°C
°C
TJ
-55 to + 175
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
300
10lbxin (1.1Nxm)
Mounting torque, 6-32 or M3 screw
Thermal Resistance
Parameter
Typ.
Max.
1.88
–––
62
Units
Junction-to-Case f
RθJC
RθCS
RθJA
–––
0.50
–––
Case-to-Sink, Flat, Greased Surface
°C/W
Junction-to-Ambient f
Notes through ꢀare on page 2
www.irf.com
1
3/2/06
IRFB4019PbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
Conditions
VGS = 0V, ID = 250µA
BVDSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
150
–––
–––
3.0
–––
0.19
80
–––
–––
95
V
∆ΒVDSS/∆TJ
RDS(on)
V/°C Reference to 25°C, ID = 1mA
mΩ
VGS = 10V, ID = 10A
VGS(th)
–––
-13
–––
–––
–––
–––
–––
13
4.9
V
VDS = VGS, ID = 50µA
∆VGS(th)/∆TJ
IDSS
Gate Threshold Voltage Coefficient
Drain-to-Source Leakage Current
–––
–––
–––
–––
–––
14
––– mV/°C
20
250
100
-100
–––
20
µA
nA
S
V
V
V
V
DS = 150V, VGS = 0V
DS = 150V, VGS = 0V, TJ = 125°C
GS = 20V
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Forward Transconductance
Total Gate Charge
GS = -20V
gfs
VDS = 10V, ID = 10A
Qg
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Qgs1
Qgs2
Qgd
Qgodr
Qsw
RG(int)
td(on)
tr
Pre-Vth Gate-to-Source Charge
Post-Vth Gate-to-Source Charge
Gate-to-Drain Charge
3.3
0.95
4.1
4.7
5.1
2.4
7.0
13
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
VDS = 75V
nC
VGS = 10V
ID = 10A
Gate Charge Overdrive
See Fig. 6 and 19
Switch Charge (Qgs2 + Qgd
Internal Gate Resistance
Turn-On Delay Time
Rise Time
)
Ω
V
DD = 75V, VGS = 10V
ID = 10A
td(off)
tf
Turn-Off Delay Time
Fall Time
12
ns RG = 2.4Ω
7.8
800
74
Ciss
Coss
Crss
Coss
LD
Input Capacitance
Output Capacitance
VGS = 0V
pF
V
DS = 50V
Reverse Transfer Capacitance
Effective Output Capacitance
Internal Drain Inductance
19
ƒ = 1.0MHz,
See Fig.5
99
VGS = 0V, VDS = 0V to 120V
Between lead,
4.5
D
S
nH 6mm (0.25in.)
from package
G
LS
Internal Source Inductance
–––
7.5
–––
and center of die contact
Avalanche Characteristics
Parameter
Typ.
Max.
Units
Single Pulse Avalanche Energy
Avalanche Current
EAS
IAR
–––
73
mJ
See Fig. 14, 15, 17a, 17b
A
Repetitive Avalanche Energy
EAR
mJ
Diode Characteristics
Parameter
Min. Typ. Max. Units
Conditions
MOSFET symbol
IS @ TC = 25°C
Continuous Source Current
–––
–––
17
(Body Diode)
A
showing the
ISM
Pulsed Source Current
–––
–––
51
integral reverse
(Body Diode)
p-n junction diode.
VSD
trr
Diode Forward Voltage
–––
–––
–––
–––
64
1.3
96
V
TJ = 25°C, IS = 10A, VGS = 0V
Reverse Recovery Time
Reverse Recovery Charge
ns TJ = 25°C, IF = 10A
di/dt = 100A/µs
nC
Qrr
160
240
Notes:
Repetitive rating; pulse width limited by max. junction temperature.
Starting TJ = 25°C, L = 1.46mH, RG = 25Ω, IAS = 10A.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
R is measured at TJ of approximately 90°C.
ꢀ Limited by Tjmax. See Figs. 14, 15, 17a, 17b for repetitive
avalanche information
θ
2
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IRFB4019PbF
100
10
100
10
1
VGS
15V
12V
VGS
15V
12V
TOP
TOP
10V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM
BOTTOM
1
5.0V
0.1
0.01
5.0V
≤ 60µs PULSE WIDTH
Tj = 25°C
≤ 60µs PULSE WIDTH
Tj = 175°C
0.1
0.1
1
10
100
0.1
1
10
, Drain-to-Source Voltage (V)
DS
100
V
, Drain-to-Source Voltage (V)
V
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
3.0
2.5
2.0
1.5
1.0
0.5
100.0
10.0
1.0
I
= 10A
V
= 25V
D
DS
≤ 60µs PULSE WIDTH
V
= 10V
GS
T
= 175°C
J
T
= 25°C
J
0.1
2
4
6
8
10
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
V
, Gate-to-Source Voltage (V)
GS
T , Junction Temperature (°C)
J
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance vs. Temperature
10000
20
V
C
= 0V,
f = 1 MHZ
I = 10A
D
GS
= C + C , C SHORTED
iss
gs
gd ds
V
= 120V
DS
C
= C
rss
gd
16
12
8
VDS= 75V
VDS= 30V
C
= C + C
ds
oss
gd
1000
100
10
Ciss
Coss
Crss
4
0
0
5
10
15
20
1
10
100
1000
Q
Total Gate Charge (nC)
G
V
, Drain-to-Source Voltage (V)
DS
Fig 5. Typical Capacitance vs.Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs.Gate-to-Source Voltage
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3
IRFB4019PbF
100
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
10
100µsec
1msec
T
= 175°C
J
10msec
1
T
= 25°C
J
1
Tc = 25°C
Tj = 175°C
Single Pulse
DC
V
= 0V
GS
0.1
0.1
1
10
100
1000
0.0
0.5
1.0
1.5
V
, Drain-toSource Voltage (V)
V
, Source-to-Drain Voltage (V)
DS
SD
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
5.0
4.0
3.0
2.0
1.0
20
16
12
8
I
= 50µA
D
4
0
-75 -50 -25
0
25 50 75 100 125 150 175
, Temperature ( °C )
25
50
75
100
125
150
175
T
T
, Junction Temperature (°C)
J
J
Fig 9. Maximum Drain Current vs. Case Temperature
Fig 10. Threshold Voltage vs. Temperature
10
1
D = 0.50
0.20
0.10
0.05
0.1
R1
R1
R2
R2
R3
R3
Ri (°C/W) τι (sec)
0.535592 0.000222
0.913763 0.001027
0.432454 0.006058
τ
J τJ
τ
Cτ
0.02
0.01
τ
τ
1 τ1
τ
2 τ2
3τ3
Ci= τi/Ri
Ci= τi/Ri
0.01
Notes:
SINGLE PULSE
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
4
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IRFB4019PbF
300
250
200
150
100
50
0.5
0.4
0.3
0.2
0.1
0.0
I
= 10A
I
D
D
TOP
1.3A
2.3A
10A
BOTTOM
T
T
= 125°C
= 25°C
J
J
0
4
6
8
10
12
14
16
25
50
75
100
125
150
175
V
, Gate-to-Source Voltage (V)
GS
Starting T , Junction Temperature (°C)
J
Fig 12. On-Resistance Vs. Gate Voltage
Fig 13. Maximum Avalanche Energy Vs. Drain Current
100
Allowed avalanche Current vs avalanche
Duty Cycle = Single Pulse
pulsewidth, tav, assuming ∆Tj = 150°C and
Tstart =25°C (Single Pulse)
10
0.01
0.05
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current Vs.Pulsewidth
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
80
60
40
20
0
TOP
BOTTOM 1% Duty Cycle
= 10A
Single Pulse
I
D
2. Safe operation in Avalanche is allowed as long as neither
Tjmax nor Iav (max) is exceeded
3. Equation below based on circuit and waveforms shown in
Figures 17a, 17b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
25
50
75
100
125
150
175
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
Starting T , Junction Temperature (°C)
J
EAS (AR) = PD (ave)·tav
Fig 15. Maximum Avalanche Energy Vs. Temperature
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5
IRFB4019PbF
Driver Gate Drive
P.W.
P.W.
Period
Period
D =
D.U.T
+
V***
=10V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
*
VDD
**
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Curent
I
SD
Ripple
≤ 5%
* Use P-Channel Driver for P-Channel Measurements
** Reverse Polarity for P-Channel
*** VGS = 5V for Logic Level Devices
Fig 16. Diode Reverse Recovery Test Circuit for HEXFET® Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
V
GS
0.01
Ω
t
p
I
AS
Fig 17b. Unclamped Inductive Waveforms
Fig 17a. Unclamped Inductive Test Circuit
LD
VDS
VDS
90%
+
-
VDD
10%
VGS
D.U.T
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
td(on)
td(off)
tr
tf
Fig 18a. Switching Time Test Circuit
Fig 18b. Switching Time Waveforms
Current Regulator
Same Type as D.U.T.
Id
Vds
Vgs
50KΩ
.2µF
12V
.3µF
+
V
DS
D.U.T.
-
Vgs(th)
V
GS
3mA
I
I
D
G
Current Sampling Resistors
Qgs1
Qgs2
Qgd
Qgodr
Fig 19a. Gate Charge Test Circuit
Fig 19b Gate Charge Waveform
6
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IRFB4019PbF
TO-220AB Package Outline (Dimensions are shown in millimeters (inches))
TO-220AB Part Marking Information
EXAMPLE: THIS IS AN IRF1010
LOT CODE 1789
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLED ON WW 19, 2000
IN THE ASSEMBLY LINE "C"
DATE CODE
YEAR 0 = 2000
WE EK 19
Note: "P" in assembly lineposition
indicates "Lead - F ree"
AS S E MB L Y
LOT CODE
LINE C
TO-220AB packages are not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 03/06
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7
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