IRFH7440TRPBF_技术文档

StrongIRFET

IRFH7440PbF

HEXFET^®Power MOSFET

Applications

l Brushed Motor drive applications

l BLDC Motor drive applications

l PWM Inverterized topologies

l Battery powered circuits

l Half-bridge and full-bridge topologies

l Electronic ballast applications

l Synchronous rectifier applications

l Resonant mode power supplies

l OR-ing and redundant power switches

l DC/DC and AC/DC converters

V_DSS

R_DS(on)typ.

max.

40V

1.8m

2.4m

159A

I_{D (Silicon Limited)}

I_D

85A

(Package Limited)

Benefits

l Improved Gate, Avalanche and Dynamic dV/dt

Ruggedness

l Fully Characterized Capacitance and Avalanche

SOA

l Enhanced body diode dV/dt and dI/dt Capability

l RoHS Compliant containing no Lead, no Bromide,

and no Halogen

PQFN 5X6 mm

Base Part Number

Package Type

Standard Pack

Form

Tape and Reel

Orderable Part Number

Quantity

4000

IRFH7440PBF

PQFN 5mm x 6mm

IRFH7440TRPBF

IRFH7440TR2PBF

400

6.0

5.0

4.0

3.0

2.0

1.0

200

150

100

50

I

= 50A

D

Limited By Package

T

= 125°C

J

T = 25°C

J

0

4

6

8

10

12 14 16

18 20

25

50

T

75

100

125

150

, Case Temperature (°C)

C

V

Gate -to -Source Voltage (V)

GS,

Fig 2. Maximum Drain Current vs. Case Temperature

Fig 1. Typical On-Resistance vs. Gate Voltage

October 11, 2012

1

IRFH7440PbF

Absolute Maximum Ratings

Symbol

Parameter

Max.

159

Units

I_D@ T_C= 25°C

I_D@ T_C= 100°C

I_D@ T_C= 25°C

I_DM

Continuous Drain Current, V_GS@ 10V (Silicon Limited)

Continuous Drain Current, V_GS@ 10V (Package Limited)

Pulsed Drain Current

101

A

85

624

104

P_D@T_C= 25°C

Maximum Power Dissipation

W

0.83

Linear Derating Factor

W/°C

V

± 20

V_GS

Gate-to-Source Voltage

3.0

Peak Diode Recovery

dv/dt

T_J

V/ns

-55 to + 150

Operating Junction and

°C

T_STG

Storage Temperature Range

Avalanche Characteristics

E_{AS (Thermally limited)}

Single Pulse Avalanche Energy

121

273

mJ

E_{AS (tested)}

I_AR

Single Pulse Avalanche Energy Tested Value

Avalanche Current

See Fig. 14, 15, 22a, 22b

A

Repetitive Avalanche Energy

E_AR

mJ

Thermal Resistance

Symbol

Parameter

Typ.

–––

Max.

1.2

31

Units

Junction-to-Case

R__JC(Bottom)

Junction-to-Case

R__JC(Top)

°C/W

Junction-to-Ambient

35

R_

JA

22

R__JA(<10s)

Static @ T_J= 25°C (unless otherwise specified)

Symbol

Parameter

Min. Typ. Max. Units

Conditions

V_(BR)DSS

Drain-to-Source Breakdown Voltage

Breakdown Voltage Temp. Coefficient

Static Drain-to-Source On-Resistance

40

–––

V

V_GS= 0V, I_D= 250μA

V/°C Reference to 25°C, I_D= 1.0mA

m _GS= 10V, I_D= 50A

m V_GS= 6.0V, I_D= 25A

V_DS= V_GS, I_D= 100μA

μA V_DS= 40V, V_GS= 0V

V_(BR)DSS/T_J

R_DS(on)

––– 0.031 –––

–––

2.2

1.8

2.7

2.4

–––

3.9

V

V_GS(th)

I_DSS

Gate Threshold Voltage

–––

2.6

V

Drain-to-Source Leakage Current

–––

1.0

150

100

-100

–––

V

_DS= 40V, V_GS= 0V, T_J= 125°C

_GS= 20V

I_GSS

R_G

Gate-to-Source Forward Leakage

Gate-to-Source Reverse Leakage

Internal Gate Resistance

nA

V_GS= -20V



Notes:

Calculated continuous current based on maximum allowable junction

temperature. Current is limited to 85A by source bond technology.

Note that current limitations arising from heating of the

ꢀ Pulse width  400μs; duty cycle  2%.

C_osseff. (TR) is a fixed capacitance that gives the same charging time

as C_osswhile V_DSis rising from 0 to 80% V_DSS

C_osseff. (ER) is a fixed capacitance that gives the same energy as

C_osswhile V_DSis rising from 0 to 80% V_DSS

.

device leads may occur with some lead mounting arrangements.

(Refer to AN-1140)

.

Repetitive rating; pulse width limited by max. junction

temperature.

When mounted on 1 inch square 2 oz copper pad on 1.5 x 1.5 in. board of

FR-4 material.

R_is measured at T_Japproximately 90°C.

This value determined from sample failure population,

Limited by T_Jmax, starting T_J= 25°C, L = 0.097mH

R_G= 50, I_AS= 50A, V_GS=10V.

I_SD 50A, di/dt  1126A/μs, V_DDV_(BR)DSS, T_J 150°C.

starting T_J= 25°C, L= 0.097mH, R_G= 50, I_AS= 50A, V_GS=10V.

October 11, 2012

2

IRFH7440PbF

Dynamic @ T_J= 25°C (unless otherwise specified)

Symbol

Parameter

Min. Typ. Max. Units

Conditions

gfs

Q_g

Forward Transconductance

149

–––

138

–––

S

V_DS= 10V, I_D= 50A

Total Gate Charge

92

nC I_D= 50A

V_DS=20V

Q_gs

Q_gd

Gate-to-Source Charge

Gate-to-Drain ("Miller") Charge

Total Gate Charge Sync. (Q_g- Q_gd)

Turn-On Delay Time

22

29

V

_GS= 10V

I_D= 50A, V_DS=0V, V_GS= 10V

ns V_DD= 20V

Q_sync

t_d(on)

t_r

63

12

Rise Time

45

I_D= 30A

R_G= 2.7

V_GS= 10V

t_d(off)

t_f

Turn-Off Delay Time

53

Fall Time

42

C_iss

C_oss

C_rss

Input Capacitance

4574

700

466

863

1229

pF V_GS= 0V

V_DS= 25V

Output Capacitance

Reverse Transfer Capacitance

Effective Output Capacitance (Energy Related)

Effective Output Capacitance (Time Related)

ƒ = 1.0 MHz

C

_osseff. (ER)

_osseff. (TR)

V

_GS= 0V, V_DS= 0V to 32V

V_GS= 0V, V_DS= 0V to 32V

Diode Characteristics

Symbol

Parameter

Min. Typ. Max. Units

Conditions

MOSFET symbol

showing the

D

S

I_S

Continuous Source Current

–––

85

A

V

(Body Diode)

G

I_SM

Pulsed Source Current

–––

745

integral reverse

(Body Diode)

p-n junction diode.

T_J= 25°C, I_S= 50A, V_GS= 0V

V_SD

t_rr

Diode Forward Voltage

Reverse Recovery Time

–––

0.9

25

27

16

17

1.2

1.3

–––

ns T_J= 25°C

T_J= 125°C

V_R= 34V,

I_F= 50A

di/dt = 100A/μs

Q_rr

Reverse Recovery Charge

Reverse Recovery Current

nC T_J= 25°C

T_J= 125°C

I_RRM

A

T_J= 25°C

3

October 11, 2012

IRFH7440PbF

1000

100

10

1000

100

10

VGS

15V

10V

8.0V

7.0V

6.0V

5.5V

5.0V

4.5V

VGS

15V

10V

8.0V

7.0V

6.0V

5.5V

5.0V

4.5V

TOP

BOTTOM

4.5V

60μs PULSE WIDTH

Tj = 150°C



4.5V

V

60μs PULSE WIDTH

Tj = 25°C



1

0.1

1

10

100

0.1

1

10

100

, Drain-to-Source Voltage (V)

V

, Drain-to-Source Voltage (V)

DS

Fig 3. Typical Output Characteristics

Fig 4. Typical Output Characteristics

1000

100

10

1.8

1.6

1.4

1.2

1.0

0.8

0.6

I

= 50A

D

V

= 10V

GS

T

= 150°C

J

T

= 25°C

J

V

= 10V

DS



60μs PULSE WIDTH

1.0

3

4

5

6

7

8

9

-60 -40 -20

0

20 40 60 80 100 120140 160

T

J

, Junction Temperature (°C)

V

, Gate-to-Source Voltage (V)

GS

Fig 6. Normalized On-Resistance vs. Temperature

Fig 5. Typical Transfer Characteristics

100000

10000

1000

14.0

V

= 0V,

= C

f = 1 MHZ

GS

I = 50A

D

C

+ C , C

SHORTED

iss

gs

gd

ds

12.0

= C

rss

oss

gd

= C + C

V

= 32V

= 20V

DS

ds

gd

10.0

8.0

6.0

4.0

2.0

0.0

C

iss

C

oss

rss

100

1

10

, Drain-to-Source Voltage (V)

100

0

20

40

60

80

100

120

V

Q

, Total Gate Charge (nC)

G

DS

Fig 7. Typical Capacitance vs. Drain-to-Source Voltage

Fig 8. Typical Gate Charge vs. Gate-to-Source Voltage

October 11, 2012

4

IRFH7440PbF

1000

100

10

10000

1000

100

10

OPERATION IN THIS AREA

LIMITED BY R

(on)

DS

T

= 150°C

J

100μsec

1msec

Limited by

package

T

= 25°C

J

10msec

DC

1

Tc = 25°C

Tj = 150°C

Single Pulse

V

= 0V

GS

0.1

1.0

0.1

1

10

100

0.0

0.5

1.0

1.5

2.0

2.5

V

, Drain-to-Source Voltage (V)

V

, Source-to-Drain Voltage (V)

DS

SD

Fig 10. Maximum Safe Operating Area

Fig 9. Typical Source-Drain Diode

Forward Voltage

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

50

48

46

44

42

40

Id = 1.0mA

-5

0

5

10 15 20 25 30 35 40

Drain-to-Source Voltage (V)

-60 -40 -20

0

20 40 60 80 100 120140 160

T , Temperature ( °C )

J

V

DS,

Fig 11. Drain-to-Source Breakdown Voltage

Fig 12. Typical C_OSSStored Energy

40

V

= 5.0V

GS

= 6.0V

= 7.0V

= 8.0V

=10V

GS

30

20

10

0

100

200

300

400

500

I , Drain Current (A)

D

Fig 13. Typical On-Resistance vs. Drain Current

5

October 11, 2012

IRFH7440PbF

10

1

D = 0.50

0.20

0.10

0.05

0.1

0.02

0.01

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

SINGLE PULSE

( THERMAL RESPONSE )

0.001

1E-006

1E-005

0.0001

0.001

0.01

0.1

t

, Rectangular Pulse Duration (sec)

1

Fig 14. Maximum Effective Transient Thermal Impedance, Junction-to-Case

100

10

1

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming Tj = 125°C and

Tstart =25°C (Single Pulse)

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming  j = 25°C and

Tstart = 125°C.

0.1

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01

tav (sec)

Fig 15. Typical Avalanche Current vs.Pulsewidth

Notes on Repetitive Avalanche Curves , Figures 14, 15:

(For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption:

Purely a thermal phenomenon and failure occurs at a temperature far in

excess of T_jmax. This is validated for every part type.

2. Safe operation in Avalanche is allowed as long asT_jmaxis not exceeded.

3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.

4. P_{D (ave)}= Average power dissipation per single avalanche pulse.

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase

during avalanche).

140

120

100

80

TOP

BOTTOM 1.0% Duty Cycle

= 50A

Single Pulse

I

D

6. I_av= Allowable avalanche current.

60

7. T = Allowable rise in junction temperature, not to exceed T_jmax(assumed as

25°C in Figure 14, 15).

t_{av =}Average time in avalanche.

40

D = Duty cycle in avalanche = t_av·f

Z_thJC(D, t_av) = Transient thermal resistance, see Figures 13)

20

P_{D (ave)}= 1/2 ( 1.3·BV·I_av) = DT/ Z_thJC

I_av= 2DT/ [1.3·BV·Z_th]

0

25

50

75

100

125

150

E_{AS (AR)}= P_{D (ave)}·t_av

Starting T , Junction Temperature (°C)

J

Fig 16. Maximum Avalanche Energy vs. Temperature

October 11, 2012

6

IRFH7440PbF

4.5

4.0

3.5

3.0

2.5

2.0

1.5

10

8

I = 30A

F

V

= 34V

R

T = 25°C

J

T = 125°C

J

6

I

= 100μA

= 1.0mA

= 1.0A

D

4

2

0

-75 -50 -25

0

25 50 75 100 125 150

0

200

400

600

800

1000

T

, Temperature ( °C )

di /dt (A/μs)

J

F

Fig. 18 - Typical Recovery Current vs. di_f/dt

Fig 17. Threshold Voltage vs. Temperature

200

10

I = 30A

F

I = 50A

F

V

= 34V

V

= 34V

R

8

6

4

2

0

T = 25°C

J

150

100

50

T = 125°C

J

T = 125°C

J

0

200

400

600

800

1000

0

200

400

600

800

1000

di /dt (A/μs)

F

Fig. 19 - Typical Recovery Current vs. di_f/dt

Fig. 20 - Typical Stored Charge vs. di_f/dt

200

I = 50A

F

V

= 34V

R

T = 25°C

J

150

100

50

T = 125°C

J

0

200

400

600

800

1000

di /dt (A/μs)

F

Fig. 21 - Typical Stored Charge vs. di_f/dt

7

October 11, 2012

IRFH7440PbF

Driver Gate Drive

P.W.

Period

D.U.T

Period

D =

+

-

*

=10V

V

GS

Circuit Layout Considerations

 Low Stray Inductance

Ground Plane

Low Leakage Inductance

Current Transformer

D.U.T. I Waveform

SD

+

-

Reverse

Recovery

Current

Body Diode Forward

Current

di/dt

-

+

D.U.T. V Waveform

DS

Diode Recovery

dv/dt

V

DD

V_DD

Re-Applied

Voltage

dv/dt controlled by R_G

R_G

+

-

Body Diode

Forward Drop

Driver same type as D.U.T.

I_SDcontrolled by Duty Factor "D"

D.U.T. - Device Under Test

Inductor Current

Inductor Curent

I

SD

Ripple  5%

* V_GS= 5V for Logic Level Devices

Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET^®Power MOSFETs

V

(BR)DSS

15V

t

p

DRIVER

+

L

V

DS

D.U.T

AS

R

G

V

DD

-

I

A

2V0_GV_S



0.01

t

p

I

AS

Fig 22b. Unclamped Inductive Waveforms

Fig 22a. Unclamped Inductive Test Circuit

R_D

V_DS

V

DS

90%

V_GS

D.U.T.

R_G

+

V_DD

-

10V

V_GS

10%

Pulse Width µs

Duty Factor 

V

GS

t

r

t

f

d(on)

d(off)

Fig 23a. Switching Time Test Circuit

Fig 23b. Switching Time Waveforms

Id

Current Regulator

Same Type as D.U.T.

Vds

Vgs

50K

.2F

12V

.3F

+

V

DS

D.U.T.

-

Vgs(th)

V

GS

3mA

I

D

G

Qgs1

Qgs2

Qgd

Qgodr

Current Sampling Resistors

Fig 24a. Gate Charge Test Circuit

Fig 24b. Gate Charge Waveform

October 11, 2012

8

IRFH7440PbF

PQFN 5x6 Outline "E" Package Details

For more information on board mounting, including footprint and stencil recommendation, please refer to application note

AN-1136:http://www.irf.com/technical-info/appnotes/an-1136.pdf

For more information on package inspection techniques, please refer to application note AN-1154:

http://www.irf.com/technical-info/appnotes/an-1154.pdf

PQFN 5x6 Outline "E" Part Marking

INTERNATIONAL

RECTIFIER LOGO

DATE CODE

PART NUMBER

XXXX

XYWWX

XXXXX

(“4 or 5 digits”)

ASSEMBLY

SITE CODE

(Per SCOP 200-002)

MARKING CODE

(Per Marking Spec)

PIN 1

IDENTIFIER

LOT CODE

(Eng Mode - Min last 4 digits of EATI#)

(Prod Mode - 4 digits of SPN code)

Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/

9

October 11, 2012

IRFH7440PbF

PQFN 5x6 Outline "E" Tape and Reel

NOTE: Controlling dimensions in mm Std reel quantity is 4000 parts.

REEL DIMENSIONS

STANDARD OPTION (QTY 4000)

TR1 OPTION (QTY 400)

METRIC

MAX

IMPERIAL

METRIC

MAX

178.5

21.5

13.8

2.3

IMPERIAL

MIN

MAX

7.028

0.846

0.543

0.091

2.598

CODE

MIN

MAX

13.011 177.5

MIN

A

B

C

D

E

F

12.972

0.823

0.504

0.067

3.819

6.988

0.823

0.520

0.075

2.350

329.5 330.5

20.9

12.8

1.7

0.846

0.532

0.091

3.898

20.9

13.2

1.9

21.5

13.5

2.3

97

99

65

66

Ref

13

17.4

14.5

Ref

13

12

G

0.512

0.571

14.5

October 11, 2012

10

IRFH7440PbF

Qualification information^†

Industrial

(per JEDEC JE S D47F guidelines)^††

Qualification level

MS L1

Moisture Sensitivity Level

RoHS compliant

PQFN 5mm x 6mm

(per JE DE C J-S TD-020D^††

)

Yes

Qualification standards can be found at International Rectifiers web site: http://www.irf.com/product-info/reliability/

Applicable version of JEDEC standard at the time of product release.

Data and specifications subject to change without notice.

IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.

11

October 11, 2012


型号：	IRFH7440TRPBF
厂家：	Infineon
描述：	HEXFETPower MOSFET
文件：	总11页 (文件大小：272K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IRFH7440TRPBF [INFINEON]

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