IRFS4310ZPBF [INFINEON]
HEXFET Power MOSFET; HEXFET功率MOSFET
| 型号： | IRFS4310ZPBF |
| 厂家： | 
Infineon |
| 描述： | HEXFET Power MOSFET |
| 文件： | 总11页 (文件大小：427K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 97115A
IRFB4310ZPbF
IRFS4310ZPbF
IRFSL4310ZPbF
HEXFET® Power MOSFET
Applications
D
VDSS
RDS(on) typ.
max.
100V
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
4.8m
6.0m
:
:
G
ID
127A
c
(Silicon Limited)
ID
75A
S
S
(Package Limited)
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
D
Ruggedness
D
D
l Fully Characterized Capacitance and Avalanche
SOA
S
D
S
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
D
D
G
G
G
D2Pak
IRFS4310ZPbF
TO-262
IRFSL4310ZPbF
TO-220AB
IRFB4310ZPbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
ID @ TC = 25°C
IDM
Parameter
Max.
127c
90c
Units
A
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Package Limited)
Pulsed Drain Current d
75
560
PD @TC = 25°C
250
Maximum Power Dissipation
W
1.7
Linear Derating Factor
W/°C
V
VGS
± 20
Gate-to-Source Voltage
18
Peak Diode Recovery f
dv/dt
TJ
V/ns
°C
-55 to + 175
Operating Junction and
TSTG
Storage Temperature Range
300
Soldering Temperature, for 10 seconds
(1.6mm from case)
10lbxin (1.1Nxm)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
Single Pulse Avalanche Energy e
EAS (Thermally limited)
130
mJ
A
Avalanche Currentꢀc
IAR
See Fig. 14, 15, 22a, 22b,
Repetitive Avalanche Energy g
EAR
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
0.6
Units
RθJC
Junction-to-Case k
RθCS
Case-to-Sink, Flat Greased Surface , TO-220
Junction-to-Ambient, TO-220 k
0.50
–––
–––
62
°C/W
RθJA
Junction-to-Ambient (PCB Mount) , D2Pak jk
RθJA
–––
40
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1
4/27/07
IRFB/S/SL4310ZPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Min. Typ. Max. Units
100 ––– –––
––– 0.11 ––– V/°C Reference to 25°C, ID = 5mAd
Conditions
VGS = 0V, ID = 250μA
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
V
ΔV(BR)DSS/ΔTJ
RDS(on)
–––
2.0
4.8
6.0
4.0
20
mΩ VGS = 10V, ID = 75A g
VDS = VGS, ID = 150μA
VGS(th)
–––
V
IDSS
Drain-to-Source Leakage Current
––– –––
μA VDS = 100V, VGS = 0V
VDS = 80V, VGS = 0V, TJ = 125°C
nA VGS = 20V
––– ––– 250
––– ––– 100
––– ––– -100
IGSS
RG
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
VGS = -20V
–––
0.7
–––
Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
Conditions
VDS = 50V, ID = 75A
150 ––– –––
S
Qg
––– 120 170
nC ID = 75A
VDS =50V
Qgs
Gate-to-Source Charge
–––
–––
–––
–––
–––
–––
–––
29
35
85
20
60
55
57
–––
Qgd
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
Turn-On Delay Time
V
GS = 10V g
ID = 75A, VDS =0V, VGS = 10V
VDD = 65V
Qsync
–––
–––
–––
–––
–––
td(on)
ns
tr
Rise Time
ID = 75A
td(off)
Turn-Off Delay Time
RG = 2.7Ω
VGS = 10V g
tf
Fall Time
Ciss
Input Capacitance
––– 6860 –––
––– 490 –––
––– 220 –––
––– 570 –––
––– 920 –––
pF VGS = 0V
VDS = 50V
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)h
ƒ = 1.0MHz, See Fig. 5
Coss eff. (ER)
Coss eff. (TR)
VGS = 0V, VDS = 0V to 80V i, See Fig. 11
VGS = 0V, VDS = 0V to 80V h
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
Conditions
IS
Continuous Source Current
––– –––
A
MOSFET symbol
127c
D
(Body Diode)
Pulsed Source Current
showing the
integral reverse
G
ISM
––– ––– 560
A
S
(Body Diode)ꢀd
p-n junction diode.
VSD
trr
Diode Forward Voltage
––– –––
1.3
V
TJ = 25°C, IS = 75A, VGS = 0V g
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
VR = 85V,
Reverse Recovery Time
Reverse Recovery Charge
–––
–––
–––
–––
–––
40
49
58
89
2.5
ns
IF = 75A
di/dt = 100A/μs g
Qrr
nC
A
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
–––
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Calculated continuous current based on maximum allowable junction
Coss eff. (TR) is a fixed capacitance that gives the same charging time
temperature. Package limitation current is 75A
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.047mH
RG = 25Ω, IAS = 75A, VGS =10V. Part not recommended for use
above this value.
as Coss while VDS is rising from 0 to 80% VDSS
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C
.
.
ISD ≤ 75A, di/dt ≤ 600A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
ꢁ Pulse width ≤ 400μs; duty cycle ≤ 2%.
2
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IRFB/S/SL4310ZPbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
TOP
TOP
BOTTOM
BOTTOM
4.5V
4.5V
≤ 60μs PULSE WIDTH
Tj = 25°C
≤ 60μs PULSE WIDTH
Tj = 175°C
1
0.1
1
10
100
0.1
1
10
, Drain-to-Source Voltage (V)
DS
100
V
, Drain-to-Source Voltage (V)
V
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
2.5
2.0
1.5
1.0
0.5
1000
100
10
I
= 75A
D
V
= 10V
GS
T
= 175°C
J
T
= 25°C
= 50V
J
1
V
DS
≤ 60μs PULSE WIDTH
0.1
2.0
3.0
V
4.0
5.0
6.0
7.0
8.0
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
, Gate-to-Source Voltage (V)
GS
T
, Junction Temperature (°C)
J
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
12000
10000
8000
6000
4000
2000
0
20
V
C
= 0V,
f = 1 MHZ
I = 75A
D
GS
= C + C , C SHORTED
iss
gs
gd ds
V
= 80V
DS
C
= C
rss
gd
16
12
8
VDS= 50V
VDS= 20V
C
= C + C
oss
ds
gd
Ciss
4
Coss
Crss
0
0
40
80
120
160
200
1
10
100
Q
Total Gate Charge (nC)
G
V
, Drain-to-Source Voltage (V)
DS
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFB/S/SL4310ZPbF
1000
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
T
= 175°C
J
100
10
1
1msec
100μsec
T
= 25°C
J
10msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
GS
DC
0.1
0.1
0.1
1
10
100
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
, Source-to-Drain Voltage (V)
V
, Drain-toSource Voltage (V)
V
DS
SD
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
130
120
110
100
90
140
120
100
80
I
= 5mA
LIMITED BY PACKAGE
D
60
40
20
0
25
50
75
100
125
150
175
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
T , Case Temperature (°C)
C
T
, Junction Temperature (°C)
J
Fig 9. Maximum Drain Current vs.
Fig 10. Drain-to-Source Breakdown Voltage
Case Temperature
3.0
2.5
2.0
1.5
1.0
0.5
0.0
600
I
D
TOP
11A
19A
75A
500
400
300
200
100
0
BOTTOM
0
20
40
60
80
100
25
50
75
100
125
150
175
V
Drain-to-Source Voltage (V)
Starting T , Junction Temperature (°C)
J
DS,
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
4
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IRFB/S/SL4310ZPbF
1
D = 0.50
0.20
0.10
0.1
R1
R1
R2
R2
R3
R3
0.05
R4
R4
Ri (°C/W) τι (sec)
0.018756 0.000373
0.159425 0.000734
0.320725 0.005665
0.101282 0.115865
τJ
τC
0.02
0.01
τJ
τ1
τ
τ
τ
3 τ3
τ4
2τ2
τ1
τ4
0.01
Ci= τi/Ri
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔTj = 150°C and
Tstart =25°C (Single Pulse)
Duty Cycle = Single Pulse
0.01
0.05
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
140
120
100
80
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
TOP
BOTTOM 1% Duty Cycle
= 75A
Single Pulse
I
D
60
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14).
40
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
20
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
0
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25
50
75
100
125
150
175
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Starting T , Junction Temperature (°C)
J
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFB/S/SL4310ZPbF
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
24
20
16
12
8
I
I
I
= 1.0A
D
D
D
= 1.0mA
= 250μA
ID = 150μA
I
= 30A
= 85V
F
V
R
4
T
= 125°C
= 25°C
J
T
J
0
-75 -50 -25
0
25 50 75 100 125 150 175
, Temperature ( °C )
100 200 300 400 500 600 700 800 900 1000
T
di / dt - (A / μs)
J
f
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage Vs. Temperature
600
500
400
300
200
24
20
16
12
8
I
= 30A
= 85V
I
= 45A
= 85V
F
F
V
T
V
T
R
R
100
0
4
0
= 125°C
= 25°C
= 125°C
= 25°C
J
J
T
T
J
J
100 200 300 400 500 600 700 800 900 1000
100 200 300 400 500 600 700 800 900 1000
di / dt - (A / μs)
di / dt - (A / μs)
f
f
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
600
500
400
300
200
100
0
I
= 45A
F
V
= 85V
R
T
= 125°C
= 25°C
J
J
T
100 200 300 400 500 600 700 800 900 1000
di / dt - (A / μs)
f
Fig. 20 - Typical Stored Charge vs. dif/dt
6
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IRFB/S/SL4310ZPbF
Driver Gate Drive
P.W.
P.W.
D =
Period
D.U.T
Period
+
V***
=10V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
-
+
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
*
VDD
**
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Curent
I
SD
Ripple
≤ 5%
* Use P-Channel Driver for P-Channel Measurements
** Reverse Polarity for P-Channel
*** VGS = 5V for Logic Level Devices
Fig 21. Diode Reverse Recovery Test Circuit for HEXFET® Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
V
20
GS
0.01
Ω
t
p
I
AS
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
RD
VDS
VDS
90%
VGS
D.U.T.
RG
+VDD
-
10%
VGS
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
td(on)
td(off)
tr
tf
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Id
Vds
Vgs
L
VCC
DUT
0
Vgs(th)
20K
Qgs1
Qgs2
Qgodr
Qgd
Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
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7
IRFB/S/SL4310ZPbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
EXAMPLE: THIS IS AN IRF1010
LOT CODE 1789
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLED ON WW 19, 2000
IN THE ASSEMBLY LINE "C"
DATE CODE
YEAR 0 = 2000
WE E K 19
Note: "P" in assembly lineposition
indicates "Lead- Free"
ASSEMBLY
LOT CODE
LINE C
TO-220AB packages are not recommended for Surface Mount Application.
8
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IRFB/S/SL4310ZPbF
TO-262 Package Outline (Dimensions are shown in millimeters (inches))
TO-262 Part Marking Information
EXAMPLE: THIS IS AN IRL3103L
LOT CODE 1789
PART NUMBER
INTERNATIONAL
ASSEMBLED ON WW 19, 1997
RECTIFIER
IN THE ASSEMBLY LINE "C"
LOGO
DATE CODE
YEAR 7 = 1997
WEEK 19
ASSEMBLY
LOT CODE
LINE C
OR
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
DATE CODE
P = DE S IGNAT E S L E AD-F R E E
PRODUCT (OPTIONAL)
YEAR 7 = 1997
ASSEMBLY
LOT CODE
WEE K 19
A = AS S E MB L Y S IT E CODE
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9
IRFB/S/SL4310ZPbF
D2Pak Package Outline (Dimensions are shown in millimeters (inches))
D2Pak Part Marking Information
THIS IS AN IRF530S WITH
PART NUMBER
LOT CODE 8024
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLED ON WW 02, 2000
IN THE ASSEMBLY LINE "L"
F530S
DATE CODE
YEAR 0 = 2000
WEEK 02
ASSEMBLY
LOT CODE
LINE L
THIS IS AN IRF530S WITH
LOT CODE 8024
PART NUMBER
DATE CODE
INTERNATIONAL
RECTIFIER
LOGO
For GB Production
ASSEMBLED ON WW 02, 2000
IN THE ASSEMBLY LINE "L"
F530S
LOT CODE
10
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IRFB/S/SL4310ZPbF
D2Pak Tape & Reel Information
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
TRL
11.60 (.457)
11.40 (.449)
1.85 (.073)
1.65 (.065)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
4
3
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 04/07
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11
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