IRLR8743 [INFINEON]

The StrongIRFET™ power MOSFET family is optimized for low RDS(on) and high current capability. The devices are ideal for low frequency applications requiring performance and ruggedness. The comprehensive portfolio addresses a broad range of applications including DC motors, battery management systems, inverters, and DC-DC converters. ;


型号：	IRLR8743
厂家：	Infineon
描述：	The StrongIRFET™ power MOSFET family is optimized for low RDS(on) and high current capability. The devices are ideal for low frequency applications requiring performance and ruggedness. The comprehensive portfolio addresses a broad range of applications including DC motors, battery management systems, inverters, and DC-DC converters.
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PD - 96123

IRLR8743PbF

IRLU8743PbF

HEXFET^®Power MOSFET

Applications

l High Frequency Synchronous Buck

Converters for Computer Processor Power

l High Frequency Isolated DC-DC

Converters with Synchronous Rectification

for Telecom and Industrial Use

l Lead-Free

V_DSSR_DS(on)max

39nC

3.1m

30V

Benefits

l Very Low RDS(on) at 4.5V V_GS

l Ultra-Low Gate Impedance

l Fully Characterized Avalanche Voltage

and Current

D-Pak

I-Pak

IRLR8743PbF

IRLU8743PbF

Gate

Drain

Source

Absolute Maximum Ratings

Parameter

Max.

Units

V_DS

Drain-to-Source Voltage

Gate-to-Source Voltage

± 20

160

113

Continuous Drain Current, V_GS@ 10V

Pulsed Drain Current

@ T_C= 25°C

@ T_C= 100°C

640

135

Maximum Power Dissipation

@T_C= 25°C

@T_C= 100°C

Linear Derating Factor

Operating Junction and

0.90

-55 to + 175

W/°C

°C

Storage Temperature Range

STG

Soldering Temperature, for 10 seconds

300 (1.6mm from case)

Thermal Resistance

Parameter

Junction-to-Case

Typ.

–––

Max.

1.11

Units

R_θJC

R_θJA

Junction-to-Ambient (PCB Mount)

°C/W

Junction-to-Ambient

110

Notes through ꢀ are on page 11

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08/15/07

IRLR/U8743PbF

Static @ T_J= 25°C (unless otherwise specified)

Parameter

Min. Typ. Max. Units

Conditions

V_GS= 0V, I_D= 250µA

BV_DSS

∆Β

R_DS(on)

–––

1.35

–––

Drain-to-Source Breakdown Voltage

Breakdown Voltage Temp. Coefficient

Static Drain-to-Source On-Resistance

∆

_DSS/ T_J

––– mV/°C Reference to 25°C, I_D= 1mA

2.4

3.0

1.9

-6.4

–––

3.1

3.9

V_GS= 10V, I_D= 25A

V_GS= 4.5V, I_D= 20A

V_DS= V_GS, I_D= 100µA

Ω

V_GS(th)

2.35

Gate Threshold Voltage

∆

_GS(th)/ T_J

––– mV/°C

Gate Threshold Voltage Coefficient

Drain-to-Source Leakage Current

I_DSS

1.0

µA

V_DS= 24V, V_GS= 0V

V_DS= 24V, V_GS= 0V, T_J= 125°C

V_GS= 20V

150

I_GSS

100

Gate-to-Source Forward Leakage

Gate-to-Source Reverse Leakage

Forward Transconductance

Total Gate Charge

-100

V_GS= -20V

gfs

Q_g

–––

_DS= 15V, I_D= 20A

–––

Q_gs1

–––

_DS= 15V

_GS= 4.5V

Pre-Vth Gate-to-Source Charge

Post-Vth Gate-to-Source Charge

Gate-to-Drain Charge

Gate Charge Overdrive

Switch Charge (Q_gs2+ Q_gd)

Output Charge

Q_gs2

Q_gd

3.9

I_D= 20A

Q_godr

See Fig. 16

Q_sw

Q_oss

nC V_DS= 16V, V_GS= 0V

R_G

t_d(on)

t_r

Gate Resistance

–––

0.85

1.5

–––

Ω

V_DD= 15V, V_GS= 4.5V

Turn-On Delay Time

I_D= 20A

Rise Time

t_d(off)

t_f

R = 1.8

Ω

Turn-Off Delay Time

See Fig. 14

Fall Time

C_iss

C_oss

C_rss

––– 4880 –––

V_GS= 0V

Input Capacitance

–––

950

470

–––

V_DS= 15V

ƒ = 1.0MHz

Output Capacitance

Reverse Transfer Capacitance

Avalanche Characteristics

Parameter

Typ.

–––

Max.

250

Units

E_AS

Single Pulse Avalanche Energy

I_AR

Avalanche Current

E_AR

13.5

Repetitive Avalanche Energy

Diode Characteristics

Parameter

Min. Typ. Max. Units

Conditions

I_S

–––

MOSFET symbol

Continuous Source Current

160

(Body Diode)

showing the

integral reverse

I_SM

–––

Pulsed Source Current

640

(Body Diode)

p-n junction diode.

V_SD

–––

1.0

T = 25°C, I = 20A, V = 0V

J S GS

Diode Forward Voltage

t_rr

ns T = 25°C, I = 20A, V_DD= 15V

Reverse Recovery Time

Q_rr

di/dt = 300A/µs

Reverse Recovery Charge

t_on

Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Forward Turn-On Time

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IRLR/U8743PbF

1000

100

1000

100

VGS

10V

VGS

10V

TOP

4.5V

3.7V

3.5V

3.3V

3.0V

2.7V

2.5V

4.5V

3.7V

3.5V

3.3V

3.0V

2.7V

2.5V

BOTTOM

2.5V

60µs PULSE WIDTH

Tj = 175°C

≤

60µs PULSE WIDTH

Tj = 25°C

≤

0.1

100

0.1

100

, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics

Fig 2. Typical Output Characteristics

1000

2.0

1.5

1.0

0.5

= 25A

= 10V

100

= 175°C

= 25°C

= 15V

≤

60µs PULSE WIDTH

0.1

-60 -40 -20 0 20 40 60 80 100120140160180

, Junction Temperature (°C)

, Gate-to-Source Voltage (V)

Fig 3. Typical Transfer Characteristics

Fig 4. Normalized On-Resistance

vs. Temperature

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IRLR/U8743PbF

5.0

4.0

3.0

2.0

1.0

0.0

100000

= 0V,

= C

f = 1 MHZ

I = 20A

= 24V

= 15V

+ C , C

SHORTED

iss

= C

rss

oss

= C + C

10000

1000

100

iss

oss

rss

10 15 20 25 30 35 40 45 50

, Drain-to-Source Voltage (V)

100

Q , Total Gate Charge (nC)

Fig 6. Typical Gate Charge vs.

Fig 5. Typical Capacitance vs.

Gate-to-Source Voltage

Drain-to-Source Voltage

10000

1000

100

1000

100

OPERATION IN THIS AREA

LIMITED BY R

(on)

= 175°C

100µsec

1msec

10msec

= 25°C

Tc = 25°C

Tj = 175°C

Single Pulse

= 0V

0.1

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

, Source-to-Drain Voltage (V)

100

, Drain-to-Source Voltage (V)

Fig 8. Maximum Safe Operating Area

Fig 7. Typical Source-Drain Diode

Forward Voltage

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IRLR/U8743PbF

180

160

140

120

100

2.5

2.0

1.5

1.0

0.5

Limited By Package

= 100µA

-75 -50 -25

25 50 75 100 125 150175 200

100

125

150

175

T , Temperature ( °C )

, Case Temperature (°C)

Fig 9. Maximum Drain Current vs.

Fig 10. Threshold Voltage vs. Temperature

Case Temperature

0.1

D = 0.50

0.20

0.10

0.05

Ri (°C/W) τi (sec)

R₁

R₂

R₃

R₄

0.02879

0.000017

^Jτ_J

^Cτ

0.25773

0.000143

0.02

0.01

¹τ₁

Ci= τi/Ri

²τ₂

³τ₃

⁴τ₄

0.48255 0.001411

0.34135 0.010617

0.01

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

SINGLE PULSE

( THERMAL RESPONSE )

0.001

1E-006

1E-005

0.0001

0.001

0.01

0.1

, Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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IRLR/U8743PbF

15V

1200

1000

800

600

400

200

TOP

2.7A

3.7A

DRIVER

BOTTOM 20A

D.U.T

V0_GV_S

Ω

0.01

Fig 12a. Unclamped Inductive Test Circuit

(BR)DSS

100

125

150

175

Starting T , Junction Temperature (°C)

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current

R_D

Fig 12b. Unclamped Inductive Waveforms

V_DS

V_GS

D.U.T.

R_G

⁺V_DD

Current Regulator

Same Type as D.U.T.

V_GS

PulseWidth ≤ 1 µs

Duty Factor ≤ 0.1 %

50KΩ

.2µF

12V

.3µF

Fig 14a. Switching Time Test Circuit

D.U.T.

90%

3mA

10%

Current Sampling Resistors

d(on)

d(off)

Fig 13. Gate Charge Test Circuit

Fig 14b. Switching Time Waveforms

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IRLR/U8743PbF

Driver Gate Drive

P.W.

Period

D.U.T

Period

D =

P.W.

=10V

Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer

D.U.T. I Waveform

Reverse

Recovery

Current

Body Diode Forward

Current

di/dt

D.U.T. V Waveform

Diode Recovery

dv/dt

V_DD

Re-Applied

Voltage

• dv/dt controlled by R_G

R_G

Body Diode

Forward Drop

• Driver same type as D.U.T.

• I_SDcontrolled by Duty Factor "D"

• D.U.T. - Device Under Test

Inductor Curent

Ripple ≤ 5%

* V_GS= 5V for Logic Level Devices

Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET^®Power MOSFETs

Vds

Vgs

Vgs(th)

Qgs1

Qgs2

Qgodr

Qgd

Fig 16. Gate Charge Waveform

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IRLR/U8743PbF

Power MOSFET Selection for Non-Isolated DC/DC Converters

Synchronous FET

Control FET

The power loss equation for Q2 is approximated

by;

Special attention has been given to the power losses

in the switching elements of the circuit - Q1 and Q2.

Power losses in the high side switch Q1, also called

the Control FET, are impacted by the R_ds(on)of the

MOSFET, but these conduction losses are only about

one half of the total losses.

P = P

+ P + P^*

loss

conduction

drive

output

P = I_rms²× R_ds(on)

loss ( )

Power losses in the control switch Q1 are given

by;

+ Q × V × f

(

)

⎛

⎜

Q_oss

⎞

⎠

P_loss= P_conduction+ P_switching+ P_drive+ P_output

×V × f + Q × V × f

(

)

⎝ 2

This can be expanded and approximated by;

*dissipated primarily in Q1.

= I ²× R_{ds(on )}

(

)

loss

rms

For the synchronous MOSFET Q2, R_ds(on)is an im-

portant characteristic; however, once again the im-

portance of gate charge must not be overlooked since

it impacts three critical areas. Under light load the

MOSFET must still be turned on and off by the con-

trol IC so the gate drive losses become much more

significant. Secondly, the output charge Q_ossand re-

verse recovery charge Q_rrboth generate losses that

are transfered to Q1 and increase the dissipation in

that device. Thirdly, gate charge will impact the

MOSFETs’ susceptibility to Cdv/dt turn on.

⎛

Q_gd

i_g

⎞

Q_gs2

i_g

⎞

⎟

⎜

⎟

⎜

+ I ×

× V × f + I ×

× V × f

⎝

⎠

⎝

⎠

+ Q × V × f

(

)

⎛ Q_oss

⎞

⎠

×V × f

⎝

This simplified loss equation includes the terms Q_gs2

The drain of Q2 is connected to the switching node

of the converter and therefore sees transitions be-

tween ground and V_in. As Q1 turns on and off there is

a rate of change of drain voltage dV/dt which is ca-

pacitively coupled to the gate of Q2 and can induce

a voltage spike on the gate that is sufficient to turn

the MOSFET on, resulting in shoot-through current .

The ratio of Q_gd/Q_gs1must be minimized to reduce the

potential for Cdv/dt turn on.

and Q_osswhich are new to Power MOSFETdata sheets.

Q_gs2is a sub element of traditional gate-source

charge that is included in all MOSFET data sheets.

The importance of splitting this gate-source charge

into two sub elements, Q_gs1and Q_gs2, can be seen from

Fig 16.

Q_gs2indicates the charge that must be supplied by

the gate driver between the time that the threshold

voltage has been reached and the time the drain cur-

rent rises to I_dmaxat which time the drain voltage be-

gins to change. Minimizing Q_gs2is a critical factor in

reducing switching losses in Q1.

Q_ossis the charge that must be supplied to the out-

put capacitance of the MOSFET during every switch-

ing cycle. Figure A shows how Q_ossis formed by the

parallel combination of the voltage dependant (non-

linear) capacitances C_dsand C_dgwhen multiplied by

the power supply input buss voltage.

Figure A: Q_ossCharacteristic

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IRLR/U8743PbF

D-Pak (TO-252AA) Package Outline

Dimensions are shown in millimeters (inches)

D-Pak (TO-252AA) Part Marking Information

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

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IRLR/U8743PbF

I-Pak (TO-251AA) Package Outline

Dimensions are shown in millimeters (inches)

I-Pak (TO-251AA) Part Marking Information

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

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IRLR/U8743PbF

D-Pak (TO-252AA) Tape & Reel Information

Dimensions are shown in millimeters (inches)

TRL

TRR

16.3 ( .641 )

15.7 ( .619 )

16.3 ( .641 )

15.7 ( .619 )

12.1 ( .476 )

11.9 ( .469 )

8.1 ( .318 )

7.9 ( .312 )

FEED DIRECTION

NOTES :

1. CONTROLLING DIMENSION : MILLIMETER.

2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).

3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

16 mm

NOTES :

1. OUTLINE CONFORMS TO EIA-481.

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

Notes:

Calculated continuous current based on maximum allowable

Repetitive rating; pulse width limited by

max. junction temperature.

junction temperature. Package limitation current is 50A.

Starting T_J= 25°C, L = 1.252mH, R_G= 25Ω,

I_AS= 20A.

Pulse width ≤ 400µs; duty cycle ≤ 2%.

ꢀ When mounted on 1" square PCB (FR-4 or G-10 Material).

For recommended footprint and soldering techniques refer to

application note #AN-994.

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.08/2007

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IMPORTANT NOTICE

The information given in this document shall in no For further information on the product, technology,

event be regarded as a guarantee of conditions or delivery terms and conditions and prices please

characteristics (“Beschaffenheitsgarantie”) .

contact your nearest Infineon Technologies office

(www.infineon.com).

With respect to any examples, hints or any typical

values stated herein and/or any information

regarding the application of the product, Infineon

Technologies hereby disclaims any and all

warranties and liabilities of any kind, including

without limitation warranties of non-infringement

of intellectual property rights of any third party.

WARNINGS

Due to technical requirements products may

contain dangerous substances. For information on

the types in question please contact your nearest

Infineon Technologies office.

In addition, any information given in this document

is subject to customer’s compliance with its

obligations stated in this document and any

applicable legal requirements, norms and

standards concerning customer’s products and any

use of the product of Infineon Technologies in

customer’s applications.

Except as otherwise explicitly approved by Infineon

Technologies in a written document signed by

authorized

representatives

Infineon

Technologies, Infineon Technologies’ products may

not be used in any applications where a failure of

the product or any consequences of the use thereof

can reasonably be expected to result in personal

injury.

The data contained in this document is exclusively

intended for technically trained staff. It is the

responsibility of customer’s technical departments

to evaluate the suitability of the product for the

intended application and the completeness of the

product information given in this document with

respect to such application.

IRLR8743 [INFINEON]

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