S6BT112A01SSBB202 [INFINEON]
S6BT112A CXPI Transceiver;
| 型号： | S6BT112A01SSBB202 |
| 厂家： | 
Infineon |
| 描述： | S6BT112A CXPI Transceiver |
| 文件： | 总38页 (文件大小：1053K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
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S6BT112A01/S6BT112A02
ASSP CXPI Transceiver IC for
Automotive Network
The S6BT112A01 and S6BT112A02 are integrated transceiver ICs for automotive communication network with Clock Extension
Peripheral Interface (CXPI). It has a flexible bit rate ranging from 2.4 kbps to 20 kbps and is JASO and ISO CXPI compliant. This
CXPI transceiver IC connects the CXPI data link controller and the CXPI Bus line, and enables direct connection to the vehicle
battery with a high surge protection. Additionally, S6BT112A01 have an optional Spread Spectrum Clock Generator (SSCG)
function, which is effective at master node. During Sleep mode, S6BT112A01 and S6BT112A02 reduce power consumption. The
CXPI transceiver IC supports master node and slave node, which is set by SELMS pins.
Features
◼Compliant with the JASO CXPI (JASO D 015-3: 2015)
standard
◼Overtemperature protection
◼Low-voltage detection
◼Compliant with the SAE CXPI (J3076_201510) standard
◼Compliant with the ISO CXPI (ISO 20794-4: 2020) standard
◼Supports 2.4 kbps to 20 kbps bitrate
◼Supports Sleep and Wakeup modes
◼Sleep mode current: 6 µA (typical at Slave)
◼Halogen-free 8-pin SOIC package
◼Waveshaping for low Electromagnetic Interference (EMI)
◼Operating voltage range: 5.3 V to 18 V
◼ESD protection HBM (1.5 kΩ, 100 pF) ±8 kV (BUS pin, BAT
pin)
◼Direct battery operation with protection against load dump,
◼Voltage tolerance ±40 V (BUS pin)
jump start, and transients
◼S6BT112A01: With SSCG
S6BT112A02: Without SSCG
◼BUS short to VBAT overcurrent protection
◼Loss of ground protection; BUS pin leakage is lower than
◼AEC-Q100 compliant (Grade-1)
±1 mA
◼Application Notes: AN227376 - Getting Started with CXPI
Transceiver S6BT112A
◼Easy selection of master node or slave node
S6BT112A Block Diagram
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Document Number: 002-10203 Rev. *H
Revised March 3, 2021
S6BT112A01/S6BT112A02
Table of Contents
1. Applications
............................................................................................................................................................. 3
............................................................................................................................................................. 4
2. Pin Assignment
3. Pin Descriptions ............................................................................................................................................................. 5
4. Block Diagram ............................................................................................................................................................. 6
5. Function Description.......................................................................................................................................................... 7
5.1 Operation Modes........................................................................................................................................................... 7
5.2 Master Node.................................................................................................................................................................. 8
5.3 Slave Node.................................................................................................................................................................. 11
5.4 Common Functions ..................................................................................................................................................... 15
6. Absolute Maximum Ratings............................................................................................................................................. 21
7. Recommended Operating Conditions ............................................................................................................................ 22
8. Electrical Characteristics................................................................................................................................................. 23
9. Ordering Information........................................................................................................................................................ 34
10. Package Dimensions...................................................................................................................................................... 34
Document History
........................................................................................................................................................... 35
Sales, Solutions, and Legal Information............................................................................................................................. 37
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S6BT112A01/S6BT112A02
1. Applications
Figure 1-1 and Figure 1-2 illustrate the typical applications of S6BT112A01 or S6BT112A02.
Figure 1-1 Typical Application as Master
S6BT112A AS MASTER
12V Battery
CXPI BUS LINE
BAT
Regulator
S6BT112A: CXPI Transceiver IC
RC
LDO Regulator
OSC
5 V
VCC
Thermal Shutdown
Low Voltage Detection
Over Current Protection
SELMS
MCU
CLK
TXD
CXPI
Control
Logic
UART
RXD
NSLP
VSS
BUS
CXPI
PHY
GND
Figure 1-2 Typical Application as Slave
S6BT112A AS SLAVE
12V Battery
CXPI BUS LINE
BAT
Regulator
S6BT112A: CXPI Transceiver IC
RC
LDO Regulator
OSC
5 V
VCC
Thermal Shutdown
Low Voltage Detection
Over Current Protection
SELMS
MCU
CLK
TXD
CXPI
Control
Logic
UART
RXD
NSLP
VSS
BUS
CXPI
PHY
GND
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S6BT112A01/S6BT112A02
2. Pin Assignment
Figure 2-1. Pin Assignment
(TOP VIEW)
RXD
SELMS
1
2
3
4
8
7
6
5
BAT
BUS
GND
NSLP
CLK
TXD
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S6BT112A01/S6BT112A02
3. Pin Descriptions
Table 3-1. Pin Descriptions
Pin
Symbol
Number
Direction
Description
Receive data output (open-drain)
1
2
RXD
Output
Requires external pull-up resistor (refer to Table 7-1)
Sleep control input
Low: Sleep mode
NSLP
Input
High: Normal mode or Standby mode
Refer to section 5.2.2 or section 5.3.2
When the SELMS pin is low level, the CLK pin is the baud rate clock input
Input clock signal with baud rate frequency
(When the input clock frequency is 20 kHz, the bit rate is 20 kbps)
When the SELMS pin is high level, the CLK pin is baud rate clock output
Outputs clock signal with baud rate frequency
(When the output clock frequency is 20 kHz , the bit rate is 20 kbps)
Open drain output
3
CLK
I/O
Requires external pull-up resistor (refer to Table 7-1)
Transmit data input
4
5
6
7
TXD
GND
BUS
BAT
Input
Ground
-
I/O
-
CXPI BUS line Input/Output
Battery (voltage source) supply
Master / slave node select input
Low: Master
8
SELMS
Input
High: Slave
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S6BT112A01/S6BT112A02
4. Block Diagram
Figure 4-1. Block Diagram
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S6BT112A01/S6BT112A02
5. Function Description
5.1 Operation Modes
Figure 5-1. State Transition Diagram
Notes
[1] : “Hi-z” means high-impedance.
[2] : Switching of the master / slave during transmitting is prohibited. Refer to section 5.4.5.
[3] : The operation mode, after the transceiver powers on, has to start from sleep mode.
[4] : If TXD is low level when releasing the thermal shutdown, TXD has to toggle "High" before transmitting TXD.
For details, refer to section 5.4.7.
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S6BT112A01/S6BT112A02
5.2 Master Node
◼There is only one node in a system, which functions as a schedule manager and a primary clock master.
◼The transceiver works in Master mode when low-level is applied on SELMS. See Table 5-1.
◼The baud rate clock is applied on the CLK pin in the Master state. See Figure 5-2.
◼The transceiver is usually used as the "Master" or "Slave", except for the “Secondary Clock master function”.
◼The SELMS input should not be changed in normal mode.
◼The SELMS input should not be changed during wakeup pulse transmission in Sleep mode.
◼The CLK pin inputs for the baud rate clock in Master state.
Table 5-1. SELMS Pin State for Master
Pin
Input Signal
Master/Slave
SELMS
Low
Master
Figure 5-2. CLK Input -> BUS Signal (Master)
5.2.1
Normal Mode
The Normal mode denotes the state to which communication is possible. The master node transmits the clock to the CXPI BUS,
which means that the clock is the master. During the Normal mode, the transmitted signal is encoded and the received signal is
decoded. When the transmitting node transmits data to the CXPI BUS, it transmits to the TXD pin after converting the data to a UART
format by 1 byte. The data is transmitted to the CXPI BUS as LSB first.
When the receiving node receives data from the CXPI BUS, it receives from the RXD pin in the UART format by 1 byte. The UART
format is listed in Table 5-2. Refer to the JASO or ISO CXPI (JASO D 015-3: 2015, ISO 20794-4: 2020) standard for details of the
operation.
Table 5-2. UART Format
Start bit bit 0 (LSB) bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7(MSB) Stop bit
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S6BT112A01/S6BT112A02
5.2.2
Sleep Mode
The Sleep mode denotes a power-saving state during which each node stops transmitting and receiving data. All nodes transitions
to Sleep mode immediately after power-on. The nodes also transition to Sleep mode after the Sleep processing is executed from the
Normal mode and transition from Standby mode or Normal mode due to CXPI BUS error.
When each node receives the Wakeup condition during the Sleep mode, it transitions to the Standby mode. The Wakeup condition
(for example, detecting that the ignition has been turned on) of each node is different for each application and the external factor that
receives the Wakeup pulse from the CXPI BUS. During the Sleep mode, the reception signal is received without decoding. The MCU
can detect a wakeup pulse width by monitoring the RXD signal.
The sleep mode is initiated by a falling edge on the NSLP pin while TXD is already set high level. The CXPI BUS transmitter output
driver is immediately disabled when the NSLP pin goes low level. The transceiver becomes the normal mode with input high level.
When the input level is switched from low to high, the BUS pin and RXD pin output Hi-Z level during the mode transition time
(TMODE_CHG in Table 8-7).
Stopping the clock input at high level of CLK is recommended. Then turn the NSLP pin to low level after TSLP_WT as shown in Figure
5-3.
The “Pin State” of Table 5-3 indicates before the falling edge in the NSLP pin.
Table 5-3. Transition from Normal to Sleep mode
Pin
TXD
Pin State
High
Description
No data transmitting
CLK
High
No clock receiving
NSLP
RXD
High to Low
High impedance
High impedance
Low
-
High level with external pull-up resistor.
BUS
High level with external pull-up resistor.
-
SELMS
The “Pin State” of Table 5-4 indicates the state before the rising edge in the NSLP pin.
Table 5-4. Transition from Sleep to Normal mode
Pin
TXD
Pin State
High
Description
No data transmitting
CLK
High
No clock receiving
NSLP
RXD
Low to High
High impedance
High impedance
Low
-
High level with external pull-up resistor.
BUS
High level with external pull-up resistor.
-
SELMS
Figure 5-3. Transition Sequence Between Sleep and Normal Mode
NSLPꢀHigh
Low
TSLP_WT
TMODE_CHG
Note:
[1] “Hi-Z” means high-impedance.
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S6BT112A01/S6BT112A02
5.2.3
Standby Mode
The Standby mode denotes the state of standing by the transition to the Normal mode. The standby mode shall transit only from the
sleep mode. The standby mode is not allowed message transition and reception after releasing the Sleep mode. During this mode,
the RXD pin and the BUS pin are in a high-impedance state. After TMODE_CHG, the state changes to the Normal mode. Then, the BUS
pin activates after a clock input of 33 periods.
5.2.4
Power-on Sequence
The power-on sequence occurs at power-up while setting up Sleep mode. When VBAT is above 5.3 V, the NSLP pin can be set to
high level. After the transition to the normal mode, the BUS pin activates after a clock input of 33 periods. See Figure 5-4.
Figure 5-4. Power-on Sequence of Master Node
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S6BT112A01/S6BT112A02
5.3 Slave Node
All the nodes, except the master node, are connected as slave in the system. The transceiver works as Slave when high level is
applied on SELMS pin. See Table 5-5. The CLK pin outputs the baud rate clock during the Slave state.
The transceiver is usually used as the "Master" or "Slave", except for the “Secondary Clock master function”.
Table 5-5. SELMS Pin State for Slave
Pin
Input Signal
Master/Slave
SELMS
High
Slave
The SELMS input should not be changed during the Normal mode or during wakeup pulse transmission in the Sleep mode. The
CLK pin outputs the baud rate clock in Slave node. See Figure 5-5.
Figure 5-5. CLK Pin Clock Output (Slave)
5.3.1
Normal Mode
The Normal mode can perform data transmit and receive. During the Normal mode, the signal that is transmitted is encoded and the
signal that is received is decoded. When the transmitting node transmits data to the CXPI BUS, it transmits to the TXD pin after
converting the data to a UART format by 1 byte. The data is transmitted to the CXPI BUS by LSB first. When the receiving node
receives data from the CXPI BUS, it revises from the RXD pin in the UART format by 1 byte. The UART format is shown in Table 5-6.
Refer to the JASO or ISO CXPI (JASO D 015-3: 2015, ISO 20794-4: 2020) standard for details of the operation.
Table 5-6. UART Format
Start bit bit 0 (LSB) bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7(MSB) Stop bit
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S6BT112A01/S6BT112A02
5.3.2
Sleep Mode
The Sleep mode denotes a state of power saving during which each node stops transmitting and receive data. All nodes transitions
to the Sleep mode immediately after power-on. They are also transitioning to the Sleep mode after the sleep processing is executed
from the Normal mode and transition from the Standby mode or the Normal mode due to CXPI BUS error.
During the Sleep mode, when each node receives the Wakeup factor, it transitions to the Standby mode. The Wakeup factor is
different from each application and is composed of the internal factor (for example, detecting that the ignition has been turned on)
and the external factor that receives the Wakeup pulse from the CXPI BUS.
During the Sleep mode, the reception signal is received without decoding. The sleep mode is initiated by a falling edge on the NSLP
pin while the TXD pin is already set high level. See Figure 5-6. The CXPI BUS transmits path is immediately disabled when the NSLP
pin goes low level.
All wake-up events must be maintained for a specific period (refer to TMODE_CHG in Table 8-7).
Figure 5-6. Transition Sequence Between Sleep and Normal Mode
NSLPꢀHigh
High
TMODE_CHG
Wakeup pulse
The “Pin State” of Table 5-7 indicates the state before the falling edge of the NSLP pin.
Table 5-7. Transition from Normal to Sleep Mode
Pin
TXD
Pin State
High
Description
No data transmitting
CLK
High impedance
High to Low
High impedance
High impedance
High
High level with external pull-up resistor.
NSLP
RXD
-
High level with external pull-up resistor.
BUS
High level with external pull-up resistor.
-
SELMS
The “Pin State” of Table 5-8 indicates the state before the rising edge of the NSLP pin.
Table 5-8. Transition from Sleep to Normal Mode
Pin
TXD
Pin State
High
Description
No data transmitting
CLK
High impedance
Low to High
High impedance
High impedance
High
High level with external pull-up resistor.
NSLP
RXD
-
High level with external pull-up resistor.
BUS
High level with external pull-up resistor.
-
SELMS
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S6BT112A01/S6BT112A02
◼Receiver Function in Sleep Mode
During the Sleep mode, the received signal will be output from the CLK pin without decoding a received signal. The RXD pin outputs
at a high level. When the Master node wake-up, it transmits clock signal to the CXPI BUS. During a wake-up sequence, the slave
transceiver does not decode the received signal. So, if the transceiver outputs this signal to RXD, slave MCUs receive shorter low-
level width signals than the UART communication period and it possibly gets errors. This is because the Slave node is received
without decoding. To avoid these errors, S6BT112A01 or S6BT112A02 CXPI transceiver IC outputs receive signals on the CLK pin
in the Sleep mode.
The MCU can detect a wake-up pulse width by monitoring the CLK signal. (Figure 5-7).
Figure 5-7. CLK Output of Receive Signal, RXD Stays High (for Slave Node)
◼Wakeup Function
The WakeupPulseOutput state transmits out the wakeup pulse in the Slave node. When the slave device returns from the Sleep
mode, it must transmit a wake-up pulse. As the NSLP pin is in a low level, the TXD pin transmits a low level. The TXD signal is
transmitted to the BUS pin without encode. The TXD pin outputs the signal width, which is a value obtained by subtracting the TTXD_BT
:
Signal width ꢀ TXD signal (“L”) – TTXD_BT(“L”)
See Figure 5-8. Refer to Table 8-7 for TTXD_BT(“L”).
Figure 5-8. Wake-Up Pulse Transmission
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S6BT112A01/S6BT112A02
As shown in Table 5-9, in case of 19.2 kbps bitrate, 9 bits (start bit plus 8 bits data) of low level in the TXD signal transmites a 402
µs (min) width wakeup pulse to the BUS. In case of 20 kbps bitrate (50 µs/Bit), to transmit over 400 µs wakeup pulse, over 466 µs
TXD low signal is needed, which can be output by a GPIO port with a timer.
Table 5-9. Bitrate of 19.2 kbps (52 µs/Bit)
UART Transmission Data
Number of Bits of L Level
TXD signal (“L”)
Wakeup Pulse Width (min)
FCH
3-bit
156 µs
90 µs
F8H
F0H
E0H
C0H
80H
00H
4-bit
5-bit
6-bit
7-bit
8-bit
9-bit
208 µs
260 µs
312 µs
364 µs
416 µs
468 µs
142 µs
194 µs
246 µs
298 µs
350 µs
402 µs
5.3.3
Standby Mode
The Standby mode denotes the state of standing by the transition to the Normal mode. The standby mode shall transit only from the
sleep mode. The standby mode is not allowed message transition and reception after releasing the Sleep mode. During this mode,
the CLK pin, the RXD pin and the BUS pin are in a high-impedance state. After TMODE_CHG, the state changes to the Normal mode.
5.3.4
Power-on Sequence
This transceiver should be powered up from Sleep mode with the NSLP pin being set to low level. Sleep mode must be released
after VBAT is above 5.3 V with the NSLP pin being set to high level. See Figure 5-9.
Figure 5-9. Power-on Sequence of Slave Node
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S6BT112A01/S6BT112A02
5.4 Common Functions
5.4.1 Overtemperature Protection
The overtemperature protection (OTP) monitors the die temperature. If the junction temperature exceeds the shutdown junction
temperature, TSD_H, the thermal protection circuit disables the output driver.
The driver is enabled again when the junction temperature falls below TSD_L and theTXD pin is toggled. (see Table 5-10 and
Figure 5-10).
5.4.2
WP_ThermalShutdown
The WP_ThermalShutdown state detects the "shutdown temperature" during the WakeupPulseOutput mode. See Table 5-11. The
overtemperature protection is inactive during the Sleep mode.
Table 5-10. Input Signal Change after Recovery from Thermal Shutdown
Master/Slave
Master
Pin
TXD
TXD
Toggle of Input Signal
Required
Required
Slave
Table 5-11. State Under Thermal Shutdown
Master/Slave
Pin
Description
Normal function
TXD
High: Normal mode / Low: Sleep mode (Thermal protection inactive)
NSLP
CLK(input)
RXD
Normal function
Master
Normal function
High impedance
BUS
Normal function
TXD
High: Normal mode / Low: Sleep mode (Thermal protection inactive)
NSLP
CLK
Normal function
Normal function
High impedance
Slave
RXD
BUS
Figure 5-10. Sequence of Thermal Shutdown
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S6BT112A01/S6BT112A02
5.4.3
Low-voltage Reset
The low-voltage reset state denotes detecting the low voltage of the BAT pin. See Figure 5-11, Table 5-12, and Table 5-13.This device
has an integrated power-on reset and low-voltage detection at the supply BAT.
If the supply voltage, VBAT, is dropping below the power-on reset level (that is, VBAT<VPOR_L), then the transceiver changes to the
LowVoltageReset mode. In the LowVoltageReset mode, the output driver is disabled and communication to the CXPI BUS is not
possible.
If the power supply reaches a higher level than the low-voltage reset level, VBAT> VPOR_H, then transceiver changes to the Standby
mode (the NSLP pin is high level) or Sleep mode (the NSLP pin is low level).
After releasing LowVoltageRest mode, transceiver starts the Power-on sequence.
Table 5-12. Input Signal Change after Recovery from Low Voltage Reset
Toggle of Input
Master/Slave
Master
Pin
TXD
TXD
Signal
Required
Required
Slave
Table 5-13. State Under Low Voltage Reset
Master/Slave
Pin
SELMS
TXD
Description
Reset
Reset
Reset
NSLP
CLK
Master
Reset(High impedance)
High impedance
RXD
High impedance
BUS
Reset
SELMS
TXD
Reset
Reset
NSLP
Slave
Reset(High impedance)
High impedance
CLK
RXD
BUS
High impedance
Figure 5-11. Low-Voltage Detection
33 periods
After releasing the low-voltage reset mode, the logical value high is output to the BUS pin after a clock input of 33 periods. The
TXD data is valid from the falling edge on the TXD pin.
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S6BT112A01/S6BT112A02
5.4.4
Overcurrent Protection
The current in the transmitter output driver is limited to protect the transmitter against short-circuit to BAT or GND pins. See
Table 5-14.
Table 5-14. State Under Overcurrent Protection
Master/Slave
Pin
Description
Normal function
TXD
Normal function
NSLP
CLK
Normal function
Master
Normal function
RXD
BUS
TXD
NSLP
CLK
Output current limited by IBUS_LIM
Normal function
Normal function
Normal function
Slave
Normal function
RXD
BUS
Output current limited by IBUS_LIM
5.4.5
Secondary Clock Master
The node that detects the wakeup event transmits the wakeup pulse on to the CXPI BUS. If the primary clock master cannot transmit
the clock to the CXPI BUS due to failure, the wakeup pulse is retransmitted. If the clock is not transmitted to the CXPI BUS, each
node detects the CXPI BUS error.
The secondary clock master may transmit the clock to the CXPI BUS instead of the primary clock master if it detects that the clock
does not exist, for a certain period after it transitions from the Sleep mode.
■Operation sequence from master to slave
After setting the TXD input pin to high level and the CLK pin is high-impedance, set the transceiver to sleep mode by setting the
NSLP pin to low level. After confirming no data receiving (the RXD pin is high level), set the SELMS pin from low level to high level.
Table 5-15 shows the pin states just before the SELMS pin input signal change. See Figure 5-12 for an application example secondary
clock master, and see Figure 5-13 for transition sequence from master to slave.
Table 5-15. Pin State Table (from Master to Slave)
Pin
TXD
Pin State
High
Description
No data transmitting
CLK
High impedance
Low
High level with external pull-up resistor.
NSLP
SELMS
RXD
Sleep mode
Low to High
High
-
No data receiving
BUS
High
No wakeup signal receiving preferred
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S6BT112A01/S6BT112A02
Figure 5-12. Application Example Secondary Clock Master
S6BT112A AS SLAVE (SECONDARY CLOCK MASTER )
12V Battery
CXPI BUS LINE
BAT
Regulator
S6BT112A: CXPI Transceiver IC
RC
LDO Regulator
OSC
5 V
VCC
Thermal Shutdown
Low Voltage Detection
Over Current Protection
SELMS
MCU
CLK
TXD
CXPI
Control
Logic
UART
RXD
NSLP
VSS
BUS
CXPI
PHY
GND
Figure 5-13. Transition Sequence from Master to Slave
TSLP_WT
RXDꢀHigh
■Operation sequence from slave to master
After setting the TXD pin to high level and the CLK pin is high level, set the transceiver to the Sleep mode by setting NSLP tpin to
low level. After confirming no data receiving (the CLK pin is high level), set the SELMS pin from high level to low level.
See Table 5-16 and Figure 5-14.
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S6BT112A01/S6BT112A02
Table 5-16. Pin State Table (from Slave to Master)
Pin Pin State Description
TXD High No data transmitting
CLK
High impedance
Low
No wakeup signal receiving
NSLP
SELMS
RXD
Sleep mode
High to Low
High
-
-
BUS
High
No wakeup signal receiving preferred
Note: The pin states just before the SELMS input signal change.
Figure 5-14. Transition Sequence from Slave to Master
CLKꢀHigh
Master node stops transmitting
5.4.6
Arbitration
Transceivers arbitrate bit-by-bit. Arbitration in bytes is done in the MCU.
In the Normal mode, each node always compares the received bit from the CXPI BUS with the transmitted bit to the CXPI BUS.
When the value of the bit is corresponding, the node may continuously transmit to the CXPI BUS. When the value of the bit is not
corresponding, the loss of arbitration is detected, and the transmission of the bit after that shall discontinue. If the transmitting node
detects the arbitration loss, it behaves as the receiving node. The data of each bit transmitted on the CXPI BUS performs arbitration
from the start by the bit. Moreover, arbitration is targeted at the entire field of the frame. When two or more nodes begin transmitting
at the same time, by arbitration only the node that transmits the highest priority frame can complete the transmission.
The MCU compares between the transmitted data (TXD) and received data (RXD). If the data difference is detected, MCU has to
stop data transmission until finding IFS.
5.4.7
TXD Toggle
The TXD toggle is an operation in which the TXD pin is first raised to high level and then lowered to low level.
The toggle function of the transceiver initiates a TXD dominant check after the transition to the Normal mode. If the TXD pin is
forced permanently low level by a hardware and/or software application failure, transceiver doesn't recognize the TXD pin as low
level. See Figure 5-15 and Figure 5-16.
As a result, even if the TXD pin is stuck to low level, the BUS pin does not continue to output a logical value of 0 in normal mode.
Therefore, even if the TXD pin is fixed to low level, it does not interfere with the communication of other devices on the BUS.
If the TXD pin is low level, the transmitter output driver remains disabled and is only enabled once the TXD pin goes high level.
A TXD toggle is required in the following cases.
Data transmission after recovery from low-voltage reset. See Figure 5-17.
Data transmission after recovery from thermal shutdown.
First TXD data transmission in the Normal mode.
First wake-up pulse transmission in sleep mode.
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S6BT112A01/S6BT112A02
Figure 5-15. Normal Transmission Sequence of Master
Figure 5-16. TXD Toggle of Master after Transition to Normal mode
Figure 5-17. Slave TXD Toggle after Recovery from Low voltage State
5.4.8
Short-circuit from the TXD pin to ground.(failure detect)
In Normal mode, If the low level input to TXD pin continues for over 10Tbit, the low level TXD input after the 10th Tbit will not be
output to the bus.
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Page 20 of 37
S6BT112A01/S6BT112A02
6. Absolute Maximum Ratings
Semiconductor devices may be permanently damaged by an application of stress (including, without limitation, voltage, current or
temperature) in excess of the absolute maximum ratings. Do not exceed any of these ratings.
Rating
Parameters
Symbol
Conditions
Unit
V
Min
Max
-0.3
40
Power supply voltage
VBAT
BAT pin
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-40
6.9
18
V
VNSLP
VSELMS
VCLK
NSLP pin
SELMS pin
CLK pin
TXD pin
RXD pin
CLK pin
BUS pin
V
Input voltage
6.9
6.9
6.9
6.9
40
V
V
VTXD
VRXD
VCLK
V
Output voltage
V
V
BUS pin voltage
VBUS
BUS pin ESD
-8
-8
8
8
kV
kV
VESDBUS
BUS pin
BAT pin
(1.5 kΩ, 100 pF)
BAT pin ESD
VESDBAT
(1.5 kΩ, 100 pF)
NSLP pin
SELMS pin
CLK pin
ESD
-2
2
kV
VESD
(1.5 kΩ, 100 pF)
TXD pin
RXD pin
-55
-40
150
150
°C
°C
Storage temperature
TSTG
-
-
Maximum
TJMAX
junction temperature
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S6BT112A01/S6BT112A02
7. Recommended Operating Conditions
Table 7-1. Recommended Condition
Value
Unit
Parameters
Symbol
Conditions
Min
Typ
Max
Power supply voltage
BAT pin [1]
VBAT
TA
5.3
-
18
V
Operating ambient temperature
BUS pin pull-up resistance
RXD pin pull-up resistance
CLK pin pull-up resistance
-
－40
+25
1000
10
+125
°C
Ω
RMASTER
RRXD
RCLK
BUS pin (Master node：VSELMSꢀ0V)
RXD pin
900
2.4
2.4
1100
-
-
kΩ
kΩ
CLK pin (VSELMS ꢀ5V)
10
Note:
[1]: (18 V < VBAT ≤ 27 V) less than 2 minutes.
WARNING:
1. The recommended operating conditions are required to ensure the normal operation of the semiconductor device. All of the
device's electrical characteristics are warranted when the device operates under these conditions.
2. Any use of semiconductor devices will be under their recommended operating condition.
3. Operation under any conditions other than these conditions may adversely affect the reliability of the device and could result in
device failure.
4. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you
are considering application under any conditions other than listed herein, please contact sales representatives beforehand.
Document Number: 002-10203 Rev. *H
Page 22 of 37
S6BT112A01/S6BT112A02
8. Electrical Characteristics
Table 8-1. DC Characteristics
VBAT ꢀ 5.3 V~27 V[1], TA ꢀ -40~125 °C; All voltages are referenced to Pin 8 (GND); Positive currents flow into the IC; unless
otherwise specified.
Pin
Name
Parameters
Symbol
Conditions
Normal mode
Min
Typ
Max
Unit
-
1.4
2.9
mA
VTXDꢀ5 V
fCLK ꢀ20 kHz, Duty 50%
Normal mode
-
-
2.0
4.0
10
mA
µA
VTXD ꢀ0 V
fCLKꢀ20 kHz, Duty 50%
Sleep mode
VBAT ꢀ12 V
VTXD ꢀ5 V
VSELMSꢀ5 V
VBUSꢀ VBAT
TAꢀ25 °C
6
Sleep mode
VBAT ꢀ12 V
VTXD ꢀ5 V
Power supply current
IBAT
BAT
-
16
-
µA
VSELMS ꢀ0 V
VBUS ꢀ VBAT
TAꢀ25 °C
Sleep mode
VBAT ꢀ12 V
VTXD ꢀ5 V
-
-
-
-
50
60
µA
µA
VSELMS ꢀ5 V
VBUS ꢀ VBAT
Sleep mode
VBAT ꢀ12 V
VTXD ꢀ5 V
VSELMS ꢀ0 V
VBUS ꢀ VBAT
BUS pin pull-up resistance
BUS short circuit current
RBUSpu
BUS
BUS
20
40
30
-
47
kΩ
-
IBUS_LIM
200
mA
VBUSꢀ18 V
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Page 23 of 37
S6BT112A01/S6BT112A02
Pin
Name
Parameters
Symbol
Conditions
VBUS ꢀ18 V
Min
Typ
Max
Unit
VBAT ꢀ5.3 V
VTXD ꢀ5 V
TAꢀ25 °C
BUS input leak current (HIGH)
IBUS_PAS_rec
BUS
BUS
-
-
20
µA
VBUS ꢀ0 V
VBAT ꢀ12 V
VTXD ꢀ5 V
BUS input leak current (LOW)
IBUS_PAS_dom
-1
-
-
mA
VBAT ꢀGNDꢀ18 V
VBUS ꢀ0 V
loss of ground BUS leak current
loss of battery BUS leak current
BUS drop voltage
IBUS_NO_GND
IBUS_NO_BAT
VBUSDR
BUS
BUS
BUS
-1
-
-
-
-
1
mA
µA
V
VBAT ꢀ0 V
VBUS ꢀ18 V
TAꢀ25 °C
30
5.7
VBAT ꢀ13.5 V
IBUSsourceꢀ-100 µA
2.4
VTXD ꢀ0 V
VBAT ꢀ7 V
BUS pull-up
resistanceꢀ 500 Ω
VO_dom
BUS
BUS
-
-
-
1.4
2
V
V
BUS low level output voltage
VTXD ꢀ0 V
VBAT ꢀ18 V
BUS pull-up
resistanceꢀ 500 Ω
VO_dom
-
-
0.423
VBAT
Receiver low level threshold voltage
Receiver high level threshold voltage
Receiver hysteresis voltage
VBUSdom
VBUSrec
VHYS
BUS
BUS
BUS
BAT
BAT
BAT
-
-
V
V
VBAT ꢀ12V, TAꢀ25 °C
0.556
VBAT
-
-
VBAT ꢀ12V, TAꢀ25 °C
0.133
VBAT
-
-
V
VBAT ꢀ12V, TAꢀ25°C
Low level power-on reset threshold voltage
High level power-on reset threshold voltage
power-on reset hysteresis voltage
Temperature shutdown threshold
Temperature shutdown release threshold
VPOR_L
VPOR_H
VPOR_HYS
TSD_H
3.1
3.3
0.2
156
151
3.8
4.1
0.3
165
159
4.7
4.9
V
-
V
-
0.5
V
-
174
168
°C
°C
[2]
[2]
TSD_L
-
Notes:
[1]: (18 V < VBAT ≤ 27 V) less than 2 minutes.
[2]: Guaranteed by design.
Document Number: 002-10203 Rev. *H
Page 24 of 37
S6BT112A01/S6BT112A02
Table 8-2. DC Characteristics CLK Pin
(If SELMS ꢀ 5 V, this pin operates as Open Drain Output Pin. If SELMS ꢀ 0 V, this pin operates as an input pin).
VBAT ꢀ 5.3 V~27 V[1], TA ꢀ -40~125 °C; all voltages are referenced to Pin 8 (GND). Positive current flow into the IC; unless
otherwise specified.
Parameters
Symbol
Pin Name
Conditions
Min
Typ
Max
Unit
VIH_CLK
CLK
2
-
6
V
High level input voltage
VSELMS ꢀ 0 V
VIL_CLK
CLK
CLK
-0.3
-
-
0.8
0.5
V
V
Low level input voltage
VSELMS ꢀ 0 V
VSELMS ꢀ 0 V
VHYS_CLK
0.03
Hysteresis range of input voltage
ICLK ꢀ 2.2 mA
VSELMS ꢀ 5 V
VOL_CLK
IOL_CLK
IILH_CLK
IILL_CLK
CLK
CLK
CLK
CLK
-
-
3
-
0.6
-
V
Low level output voltage
Low level current
VSELMS ꢀ 5 V,
VCLK ꢀ 0.4 V
1.3
-3
mA
µA
µA
VSELMS ꢀ 5 V
VCLK ꢀ 5 V
3
High level leak current
Low level leak current
VSELMS ꢀ 5 V
VCLK ꢀ 0 V
-3
-
3
Note:
[1]: (18 V < VBAT ≤ 27 V) less than 2 minutes.
Table 8-3. DC Characteristics NSLP Pin
VBAT ꢀ 5.3 V~27 V[1], TA ꢀ -40~125 °C; all voltages are referenced to Pin 8 (GND). Positive current flow into the IC; unless
otherwise specified.
Parameters
Symbol
Pin Name
Conditions
Min
Typ
Max
Unit
High level input voltage
VIH_NSLP
NSLP
2
-
6
V
-
-
-
NSLP
NSLP
NSLP
NSLP
Low level input voltage
VIL_NSLP
VHYS_NSLP
RPD_NSLP
IILL_NSLP
-0.3
0.03
100
-3
-
0.8
0.5
650
3
V
V
Hysteresis range of input voltage
Internal pull-down resistance
Low level leak current
-
250
-
kΩ
µA
VNSLP ꢀ 5 V
VNSLP ꢀ 0 V
Note:
[1]: (18 V < VBAT ≤ 27 V) less than 2 minutes.
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S6BT112A01/S6BT112A02
Table 8-4. TXD Pin
VBAT ꢀ 5.3 V~27 V[1], TA ꢀ -40~125 °C; all voltages are referenced to Pin 8 (GND). Positive current flow into the IC; unless
otherwise specified.
Parameters
Symbol
Pin Name
Conditions
Min
Typ
Max
Unit
VIH_TXD
TXD
2
-
6
V
High level input voltage
-
VIL_TXD
VHYS_TXD
RPU_TXD
IILH_TXD
TXD
TXD
TXD
TXD
-0.3
0.03
50
-
0.8
0.5
325
3
V
V
Low level input voltage
-
-
125
-
Hysteresis range of input voltage
Internal pull-up resistance
High level leak current
-
kΩ
µA
VTXD ꢀ 0 V
VTXD ꢀ 5 V
-3
Note:
[1]: (18V < VBAT ≤ 27V) less than 2 minutes.
Table 8-5. SELMS Pin
VBAT ꢀ 5.3 V~27 V[1], TA ꢀ -40~125 °C; all voltages are referenced to Pin 8 (GND). Positive current flow into the IC; unless
otherwise specified.
Parameters
Symbol
Pin Name
Conditions
Min
Typ
Max
Unit
VIH_SELMS
SELMS
2
-
6
V
High level input voltage
-
-
-
SELMS
SELMS
SELMS
SELMS
VIL_SELMS
VHYS_SELMS
RPU_SELMS
IILH_SELMS
-0.3
0.03
200
-3
-
0.8
0.5
1300
3
V
V
Low level input voltage
-
500
-
Hysteresis range of input voltage
Internal pull-up resistance
High level leak current
kΩ
µA
VSELMS ꢀ 0 V
VSELMS ꢀ 5 V
Note:
[1]: (18 V < VBAT ≤ 27 V) less than 2 minutes.
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Page 26 of 37
S6BT112A01/S6BT112A02
Table 8-6. RXD Pin (Open Drain Output)
VBAT ꢀ 5.3 V~27 V[1], TA ꢀ -40~125 °C; all voltages are referenced to Pin 8 (GND). Positive current flow into the IC; unless
otherwise specified.
Parameters
Symbol
Pin Name
Conditions
Min
Typ
Max
Unit
Low level output voltage
VOL_RXD
RXD
-
-
0.6
V
IRXD ꢀ 2.2 mA
Low level current
IOL_RXD
IOLH_RXD
IOLL_RXD
RXD
RXD
RXD
1.3
-3
3
-
-
mA
µA
µA
RXD ꢀ 0.4 V
RXD ꢀ 5 V
RXD ꢀ 0 V
High level leak current
Low level leak current
3
3
-3
-
Note:
[1]: (18 V < VBAT≦ 27 V) less than 2 minutes.
Table 8-7. AC Characteristics
VBAT ꢀ 5.3 V~27 V[1], TA ꢀ -40~125 °C BUS Load 1 kΩ /1 nF; unless otherwise specified.
Parameters
Symbol
Pin Name
Conditions
Min
Typ
Max
Unit
Bitrate (see Figure
8-1)
TBUAD
BUS
2.4
-
20
kbps
VTH(BUS) [3] ꢀ 0.5VBAT
Mode transition time
(Sleep to Normal or
TMODE_CHG
NSLP
-
-
1
ms
VTH(5 V)[4] ꢀ 50%
Normal to Sleep.) (see
Figure 8-2)
CLK
NSLP wait time (see
Figure 8-3)
VTH(5 V) [4] ꢀ 50%
-
TSLP_WT
TSLP_MN
100
1
-
-
-
-
µs
NSLP
Minimum sleep time
(see Figure 8-4)
NSLP
ms
VBUT ꢀ 7V~27V
VNSLP ꢀ 0 V
Driver boot time under
sleep mode. [2] (see
Figure 8-5)
TTXD_BT
TXD
-
-
66
µs
VSELMS ꢀ 5 V
VTH(5 V)[4]ꢀ50%
VTH(BUS)[3]ꢀ0.3VBAT
VNSLP ꢀ 5 V
VSELMS ꢀ 0 V
CLK transmission
delay time (see Figure
8-6)
CLKꢀinput clock
VTXD ꢀ5 V
TCLK_PD
CLK
-
-
0.9
Tbit[5]
VTH(5 V)[4]ꢀ50%
VTH(BUS)[3]ꢀ0.3VBAT
Document Number: 002-10203 Rev. *H
Page 27 of 37
S6BT112A01/S6BT112A02
Parameters
Symbol
Pin Name
Conditions
VNSLP ꢀ 5 V
Min
Typ
Max
Unit
VSELMS ꢀ 0 V
Time of Low level of
logic value '1' (see
Figure 8-7)
0.39Tbit
+0.6τ
Ttx_1_lo_rec
BUS
-
-
-
CLKꢀinput clock
VTXD ꢀ5 V
VTH(BUS)[3] ꢀ 0.7VBAT
VNSLP ꢀ 5 V
VSELMS ꢀ 0 V
Time of Low level of
logic value '1' (see
Figure 8-7)
Ttx_1_lo_dom
BUS
0.11
-
-
Tbit
CLKꢀinput clock
VTXD ꢀ5 V
VTH(BUS)[3] ꢀ 0.3 VBAT
VNSLP ꢀ 5 V
Time of Low level of
logic value '0' (see
Figure 8-7)
Ttx_1_lo_rec
+0.06Tbit
Ttx_0_lo_rec
BUS
BUS
-
-
-
-
-
-
VTXD ꢀ 0 V
VTH(BUS) [3] ꢀ 0.7 VBAT
VNSLP ꢀ 5 V
Time of Low level of
logic value '0' (see
Figure 8-7)
Ttx_1_lo_dom
+0.06Tbit
Ttx_0_lo_dom
VTXD ꢀ0 V
VTH(BUS) [3] ꢀ 0.3 VBAT
VNSLP ꢀ 5 V
VTXD ꢀ 0 V
VTH(BUS)[3]
High level time at
receiving node. (see
Figure 8-7)
Ttx_0_hi
BUS
0.06
-
-
Tbit
ꢀ
0.556
VBAT
VNSLP ꢀ 5 V
VTH(BUS)[3]
VBUSdom
Receiver delay time
(see Figure 8-8)
TRXD_PD
RXD
TXD
-
-
-
-
1.0
2.0
Tbit
Tbit
ꢀ
Delay time of
transmission if logic
value '0'. (see Figure
8-9)
VNSLP ꢀ 5 V
VTH(BUS) [3]ꢀ0.3 VBAT
TTXD_PD
VSELMS ꢀ 0 V
VTH(5 V)[4] ꢀ 50%
Input clock duty
TICLK_DY
CLK
CLK
30
14
-
-
70
50
%
%
VSELMS ꢀ 5 V
VTH(5 V)[4] ꢀ 50%
Output clock duty[6]
TOCLK_DY
VNSLP ꢀ 0 V
Wakeup pulse filter
constant(Master)[7]
(see Figure 8-10)
Trx_wakeup_mast
BUS
30
-
150
µs
VSELMS ꢀ 0 V
VTH(BUS) [3]ꢀ42.3%
er
Document Number: 002-10203 Rev. *H
Page 28 of 37
S6BT112A01/S6BT112A02
Parameters
Symbol
Pin Name
Conditions
VNSLP ꢀ 0 V
Min
Typ
Max
Unit
Wakeup pulse filter
constant(Slave) [7]
(see Figure 8-10)
Trx_wakeup_slave
BUS
0.5
-
5
µs
VSELMS ꢀ 5 V
VTH(BUS) [3] ꢀ 42.3%
VNSLP ꢀ 5 V
Time of bus slope from
minimum (see Figure
8-7)
VSELMS ꢀ 0 V
Ttx_1_dom_m
BUS
BUS
-
-
-
0.16
-
Tbit
VBAT ꢀ 7V
VTH(BUS) [3] ꢀ 0.3 VBAT
Recessive level of
logical value ‘0’.
V_rec_0
0.93
V_rec_1
VNSLP ꢀ 5 V
Notes:
[1]: (18 V < VBAT ≤ 27 V) less than 2 minutes.
RXD pin load: 20 pF.
[2]: CXPI BUS load (Figure 8-11) : 10 nF/500 Ω.
[3]: VTH(BUS)：threshold of BUS pin.
[4]: VTH(5 V)：threshold of NSLP,CLK,TXD,SELMS,RXD pins.
[5]: Tbit stands for 1bit time.(Figure 8-1)
[6]: logic '0/1' threshold clock.
[7]: Pulse widths greater than Max are output to RXD, pulse widths less than Min are excluded.
Figure 8-1. Definition of Tbit
Figure 8-2. Mode Transition Time
Document Number: 002-10203 Rev. *H
Page 29 of 37
S6BT112A01/S6BT112A02
Figure 8-3. NSLP Wait Time
Figure 8-4. Minimum Sleep Time
Figure 8-5. Driver Boot Time Under Sleep Mode
Figure 8-6. CLK Transmission Delay Time
Document Number: 002-10203 Rev. *H
Page 30 of 37
S6BT112A01/S6BT112A02
Figure 8-7. Logic Low and High CXPI BUS Waveform
Figure 8-8. Receiver Delay Time
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S6BT112A01/S6BT112A02
Figure 8-9. Logic Low Transmission Delay Time
Figure 8-10. Wakeup Pulse Waveform
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Page 32 of 37
S6BT112A01/S6BT112A02
Figure 8-11. CXPI BUS Load Connection
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Page 33 of 37
S6BT112A01/S6BT112A02
9. Ordering Information
Part Number
Package
S6BT112A01SSBB002
8-pin 150-mil SOIC Tape and Reel (SOA008)
8-pin 150-mil SOIC Tape and Reel (SOA008)
S6BT112A02SSBB002
10.Package Dimensions
Package Type
Package Code
SOP 8
SOA 008
NOTES:
DIMENSIONS
SYMBOL
1. ALL DIMENSIONS ARE IN MILLIMETERS.
MIN.
-
NOM.
MAX.
1.75
2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.
-
A
A1
A2
b
3. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER
END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 mm PER SIDE.
D AND E1 DIMENSIONS ARE DETERMINED AT DATUM H.
-
0.10
0.25
-
-
1.32
-
0.51
0.48
0.25
0.23
0.31
0.28
0.17
0.17
4. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS
D AND E1 ARE DETERMINED AT THE OUTMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUSIVE OF ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF
THE PLASTIC BODY.
-
-
b1
c
c1
-
5. DATUMS A AND B TO BE DETERMINED AT DATUM H.
D
E
4.90 BSC
6.00 BSC
3.90 BSC
6. "N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR THE SPECIFIED
PACKAGE LENGTH.
E1
e
7. THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 TO
0.25 mm FROM THE LEAD TIP.
1.27 BSC
-
8. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.10 mm TOTAL IN EXCESS OF THE "b" DIMENSION AT
L
0.89
0.40
MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OF THE LEAD FOOT.
L1
L2
N
1.04 REF
0.25 BSC
8
9. THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT, THEN A PIN 1
IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED.
10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE
SEATING PLANE.
h
-
0.25
0°
0.50
8°
0
-
-
002-18754 **
0 1
0 2
5°
15°
0° REF
Document Number: 002-10203 Rev. *H
Page 34 of 37
S6BT112A01/S6BT112A02
Document History
Document Title: S6BT112A01/S6BT112A02 ASSP CXPI Transceiver IC for Automotive Network
Document Number: 002-10203
Revision
ECN
Submission Date
Description of Change
Initial release
New Spec.
**
5046456
12/11/2015
Revised the sentence style of the cover page
Changed all section 5 for easy to understand.
Changed figure of application.
*A
5208207
04/06/2016
Changed Figure 4-1 and Figure 5-1.
Removed “Driver recovery time when over-temperature detection is released.”
Changed figure of application.
Changed Figure 4-1 Block Diagram
Changed Figure 5-12 Application example Secondary clock master
Added the conditions of VBUSdom/VBUSrec/ VHYS/Ttx_1_dom_m.
Removed the prameter of Receiver center level voltage (VBUS_CNT).
Changed Figure 8-11 CXPI BUS Load Connection
Changed Ordering Information.
*B
5528948
11/24/2016
Changed Package Dimensions.
Updated Introduction.
Updated Note [3] (Page 8).
Updated 5.2 Master Node.
Updated 5.2.2 Sleep Mode.
*C
5547736
12/09/2016
Changed figure of 1. Applications
*D
*E
5757034
6397891
06/20/2017
12/04/2018
Changed Figure 5-12 Application example Secondary Clock Master
Changed SOA 008 figure in Package Demensions
Added recommendation when stopping clock (Page 9).
Corrected Figure 5-2, 5-3, 5-5, 5-6, 5-7, 5-10, 5-11, 5-13, 5-14
Changed Table 5-5 to Table 5-9, 20 kbps to 19.2 kbps. Added explanation (Page 10, 13).
Added max. value for IBAT at Sleep mode, SELMS=5V, and TA=25 °C (Page 23).
Changed max. value of TTXD_BT to 66 (Page 27).
*F
6748976
12/23/2019
Changed max. value of Ttx_1_lo_rec to 0.39Tbit+0.6τ (Page 28).
Changed max. value of TRXD_PD to 1.0 (Page 28).
Changed max. value of TTXD_PD to 2.0 (Page 28).
Document Number: 002-10203 Rev. *H
Page 35 of 37
S6BT112A01/S6BT112A02
Document Title: S6BT112A01/S6BT112A02 ASSP CXPI Transceiver IC for Automotive Network
Document Number: 002-10203
Revision
ECN
Submission Date
Description of Change
Updated Introduction.
Updated Features.
Added title of Figure 1-1 and Figure 1-2.
Changed NSLP pin description of Table 3-1.
Updated block diagram of figure 4-1.
Updated State Transition Diagram of Figure 5-1 and Notes.
Updated 5.2 Master Node.
*G
6906561
06/28/2020
Updated 5.3 Slave Node.
Updated 5.4 Common functions.
Updated style of 7 Recommended Operating Conditions.
Updated style of 8 Electrical Characteristics.
Added conditons of IOL_CLK ; VCLK = 0.4 V.
Added conditons of IILH_CLK ; VCLK = 5 V.
Added conditons of IILL_CLK ; VCLK = 0 V.
Added ISO compliance in the Features.
*H
7097866
03/03/2021
Updated the Short-circuit from the TXD pin to ground.(failure detect) in 5.4.8.
Document Number: 002-10203 Rev. *H
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S6BT112A01/S6BT112A02
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Document Number: 002-10203 Rev. *H
March 3, 2021
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