TDA5211XUMA1 [INFINEON]
Telecom Circuit, 1-Func, PDSO28, PLASTIC, TSSOP-28;
| 型号： | TDA5211XUMA1 |
| 厂家： | 
Infineon |
| 描述： | Telecom Circuit, 1-Func, PDSO28, PLASTIC, TSSOP-28 电信 光电二极管 电信集成电路 |
| 文件： | 总52页 (文件大小：1217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Wireless Components
ASK/FSK Single Conversion Receiver
TDA 5211 Version 2.0
Specification May 2001
Revision History
Current Version: 2.0 as of 18.05.01
Previous Version: 1.1, Dec. 2000
Page
Page
Subjects (major changes since last revision)
(in previ-
ous Ver-
sion)
(in current
Version)
3-12
4-4
3-12
4-4
Sec. 3.4.8: max. datarate changed, Sec. 3.4.9: max. output current changed
value of a changed to 1.414
4-13
4-13
value for C2 changed to 22nF according to bill of materials, τ2 and T2 changed
5-3
5-4
5-5
5-6
5-3
5-4
5-5
5-6
min. supply current limits added, max. limits changed
supply current max. limit changed, min. limit added
3VOUT min. & max. limits changed, TAGC typ. & max. values changed
Section “SLICER” reworked, max. datarate at given load capacitance quoted,
high output voltage limits changed, precharge current: min., max. limits changed
5-7
5-9
5-7
5-9
PDO load and leakage currents limits and typ. values changed, FSK demodula-
tion gain min. limit changed
PDWN-current max. limit changed, supply currents min. limits added, max. limits
changed, 3VOUT min. & max. limits changed, ITAGC_out limits changed
5-10
5-15
5-10
5-15
Section “SLICER” reworked, max. datarate at given load capacitance quoted,
high output voltage limits changed, precharge current: min., max. limits changed,
PDO output voltage removed
C18 value changed
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Edition 05.01
Published by Infineon Technologies AG,
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81541 München
© Infineon Technologies AG May 2001.
All Rights Reserved.
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TDA 5211
Product Info
Product Info
Package
General Description The IC is a very low power consump-
tion single chip FSK/ASK Superhet-
erodyne Receiver (SHR) for the
frequency band 310 to 350 MHz that is
pin compatible with the ASK Receiver
TDA5201. The IC offers a high level of
integration and needs only a few exter-
nal components. The device contains
a low noise amplifier (LNA), a double
balanced mixer, a fully integrated
VCO, a PLL synthesiser, a crystal
oscillator, a limiter with RSSI genera-
tor, a PLL FSK demodulator, a data fil-
ter, a data comparator (slicer) and a
peak detector. Additionally there is a
power down feature to save battery
life.
Features ꢀ Low supply current (Is = 5.7 mA
typ. in FSK mode, Is = 5 mA typ. in
ASK mode)
ꢀ Selectable frequency ranges 310-
330 MHz and 330-350 MHz
ꢀ Limiter with RSSI generation,
ꢀ Supply voltage range 5V ±10%
operating at 10.7MHz
ꢀ Power down mode with very low
ꢀ Selectable reference frequency
supply current (50nA typ.)
ꢀ 2nd order low pass data filter with
ꢀ FSK and ASK demodulation capa-
external capacitors
bility
ꢀ Data slicer with self-adjusting
ꢀ Fully integrated VCO and PLL
threshold
Synthesiser
ꢀ FSK sensitivity better than
-102 dBm over specified tempera-
ture range (- 40 to +105°C)
ꢀ ASK sensitivity better than
-110 dBm over specified tempera-
ture range (- 40 to +105°C)
Applications ꢀ Keyless Entry Systems
ꢀ Remote Control Systems
ꢀ Alarm Systems
ꢀ Low Bitrate Communication
Systems
Ordering Information
Type
Ordering Code
Q67037-A1147
Package
TDA 5211
samples available
P-TSSOP-28-1
Wireless Components
Product Info
Specification, May 2001
1
Table of Contents
1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
i
2 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
2
2.1
2.2
2.3
2.4
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2
3
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
2
3.1
3.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3.3
3.4
Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
9
3.4.1 Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2 Mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.3 PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.4 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.5 Limiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.6 FSK Demodulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.7 Data Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.8 Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.9 Peak Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.10 Bandgap Reference Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
10
10
10
11
11
12
12
12
12
4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
2
4.1
4.2
4.3
4.4
Choice of LNA Threshold Voltage and Time Constant. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quartz Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quartz Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
5
6
4.5
4.6
Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ASK/FSK Switch Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
8
4.6.1 FSK Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.2 ASK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
10
4.7
Principle of the Precharge Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
5 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
2
3
4
9
5.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.3 AC/DC Characteristics at TAMB = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.4 AC/DC Characteristics at TAMB = -40 to 105°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2
5.3
5.4
5.5
Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Board Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix - Noise Figure and Gain Circles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
13
15
17
2
Product Description
Contents of this Chapter
2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
TDA 5211
Product Description
2.1 Overview
The IC is a very low power consumption single chip FSK/ASK Superheterodyne
Receiver (SHR) for receive frequencies between 310 and 350 MHz that is pin
compatible to the ASK Receiver TDA5201. The IC offers a high level of integra-
tion and needs only a few external components. The device contains a low
noise amplifier (LNA), a double balanced mixer, a fully integrated VCO, a PLL
synthesiser, a crystal oscillator, a limiter with RSSI generator, a PLL FSK
demodulator, a data filter, a data comparator (slicer) and a peak detector. Addi-
tionally there is a power down feature to save battery life.
2.2 Application
ꢀ Keyless Entry Systems
ꢀ Remote Control Systems
ꢀ Alarm Systems
ꢀ Low Bitrate Communication Systems
2.3 Features
ꢀ Low supply current (Is = 5.7 mA typ.FSK mode, 5mA typ. ASK mode)
ꢀ Supply voltage range 5V ±10%
ꢀ Power down mode with very low supply current (50nA typ.)
ꢀ FSK and ASK demodulation capability
ꢀ Fully integrated VCO and PLL Synthesiser
ꢀ RF input sensitivity ASK -113dBm typ. at 25°C, better than -110dBm over
complete specified operating temperature range (-40 to +105°C)
ꢀ RF input sensitivity FSK -105dBm typ. at 25°C, better than -102dBm over
complete specified operating temperature range (-40 to +105°C)
ꢀ Receive frequency range between 310 and 350 MHz
ꢀ Selectable reference frequency
ꢀ Limiter with RSSI generation, operating at 10.7MHz
ꢀ 2nd order low pass data filter with external capacitors
ꢀ Data slicer with self-adjusting threshold
Wireless Components
2 - 2
Specification, May 2001
TDA 5211
Product Description
2.4 Package Outlines
P_TSSOP_28.EPS
Figure 2-1
P-TSSOP-28-1 package outlines
Wireless Components
2 - 3
Specification, May 2001
3
Functional Description
Contents of this Chapter
3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.4 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
TDA 5211
Functional Description
3.1 Pin Configuration
CRST1
VCC
LNI
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CRST2
PDW N
PDO
2
3
TAG C
AG ND
LNO
4
DATA
3VO UT
THRES
FFB
5
6
VCC
M I
7
TDA 5211
8
O PP
M IX
9
SLN
AG ND
FSEL
IFO
10
11
12
13
14
SLP
LIM X
LIM
DG ND
VDD
CSEL
M SEL
Pin_Configuration_5211.wmf
Figure 3-1
IC Pin Configuration
Wireless Components
3 - 2
Specification, May 2001
TDA 5211
Functional Description
3.2 Pin Definition and Function
In the subsequent table the internal circuits connected to the pins of the device
are shown. ESD-protection circuits are omitted to ease reading.
.
Table 3-1 Pin Definition and Function
Pin No. Symbol
Equivalent I/O-Schematic
Function
1
CRST1
External Crystal Connector 1
4.15V
1
50uA
2
3
VCC
LNI
5V Supply
LNA Input
57uA
3
500uA
4k
1k
Wireless Components
3 - 3
Specification, May 2001
TDA 5211
Functional Description
4
TAGC
AGC Time Constant Control
4.3V
3uA
4
1k
1.4uA
1.7V
5
6
AGND
LNO
Analogue Ground Return
LNA Output
5V
1k
6
7
8
VCC
MI
5V Supply
Mixer Input
1.7V
2k
2k
9
MIX
Complementary Mixer Input
8
9
400uA
10
11
AGND
FSEL
Analogue Ground Return
not applicable - has to be left
open
Wireless Components
3 - 4
Specification, May 2001
TDA 5211
Functional Description
12
IFO
10.7 MHz IF Mixer Output
300uA
2.2V
60
12
4.5k
13
14
DGND
VDD
Digital Ground Return
5V Supply (PLL Counter Cir-
cuitry)
15
MSEL
ASK/FSK Modulation Format
Selector
1.2V
3.6k
15
16
CSEL
6.xx or 13.xx MHz Quartz
Selector
1.2V
80k
16
Wireless Components
3 - 5
Specification, May 2001
TDA 5211
Functional Description
17
18
LIM
Limiter Input
2.4V
15k
17
Complementary Limiter Input
LIMX
75uA
330
18
15k
19
SLP
Data Slicer Positive Input
15uA
100
3k
19
80µA
20
SLN
Data Slicer Negative Input
5uA
10k
20
21
OPP
OpAmp Noninverting Input
5uA
200
21
Wireless Components
3 - 6
Specification, May 2001
TDA 5211
Functional Description
22
23
24
FFB
Data Filter Feedback Pin
AGC Threshold Input
3V Reference Output
5uA
100k
22
THRES
5uA
10k
23
3VOUT
24
20k
3.1V
25
DATA
Data Output
500
25
40k
Wireless Components
3 - 7
Specification, May 2001
TDA 5211
Functional Description
26
PDO
Peak Detector Output
200
26
27
PDWN
Power Down Input
27
220k
220k
28
CRST2
External Crystal Connector 2
4.15V
28
50uA
Wireless Components
3 - 8
Specification, May 2001
TDA 5211
Functional Description
3.3 Functional Block Diagram
VCC
IF
Filter
MSEL
LNO
MI
MIX IFO
12
LIM
LIMX
FFB
OPP
SLP
SLN
20
6
8
9
17
18
15
21
19
22
LNI
3
4
LNA
RF
-
FSK
PLL Demod
-
DATA
FSK
ASK
25
+
+
LIMITER
SLICER
+
-
+
OP
-
TAGC
PEAK
DETECTOR
26 PDO
TDA 5211
OTA
THRES
23
24
UREF
3VOUT
AGC
Reference
Φ
DET
CRYSTAL
OSC
: 1 / 2
VCO
: 128 / 64
VCC
14
13
Bandgap
Reference
Loop
Filter
DGND
16
1
28
27
11
2,7
5,10
PDWN
VCC AGND
(FSEL)
CSEL
Crystal
Functional_diagram_5211.wmf
Figure 3-2
Main Block Diagram
3.4 Functional Blocks
3.4.1 Low Noise Amplifier (LNA)
The LNA is an on-chip cascode amplifier with a voltage gain of 15 to 20dB. The
gain figure is determined by the external matching networks situated ahead of
LNA and between the LNA output LNO (Pin 6) and the Mixer Inputs MI and MIX
(Pins 8 and 9). The noise figure of the LNA is approximately 3dB, the current
consumption is 500µA. The gain can be reduced by approximately 18dB. The
switching point of this AGC action can be determined externally by applying a
threshold voltage at the THRES pin (Pin 23). This voltage is compared internally
with the received signal (RSSI) level generated by the limiter circuitry. In case
that the RSSI level is higher than the threshold voltage the LNA gain is reduced
and vice versa. The threshold voltage can be generated by attaching a voltage
divider between the 3VOUT pin (Pin 24) which provides a temperature stable
3V output generated from the internal bandgap voltage and the THRES pin as
described in Section 4.1. The time constant of the AGC action can be deter-
Wireless Components
3 - 9
Specification, May 2001
TDA 5211
Functional Description
mined by connecting a capacitor to the TAGC pin (Pin 4) and should be chosen
along with the appropriate threshold voltage according to the intended operat-
ing case and interference scenario to be expected during operation. The opti-
mum choice of AGC time constant and the threshold voltage is described in
Section 4.1.
3.4.2 Mixer
The Double Balanced Mixer downconverts the input frequency (RF) in the
range of 310-350MHz to the intermediate frequency (IF) at 10.7MHz with a vol-
tage gain of approximately 21dB by utilising either high- or low-side injection of
the local oscillator signal. In case the mixer is interfaced only single-ended, the
unused mixer input has to be tied to ground via a capacitor. The mixer is fol-
lowed by a low pass filter with a corner frequency of 20MHz in order to suppress
RF signals to appear at the IF output (IFO pin). The IF output is internally con-
sisting of an emitter follower that has a source impedance of approximately
330Ω to facilitate interfacing the pin directly to a standard 10.7MHz ceramic filter
without additional matching circuitry.
3.4.3 PLL Synthesizer
The Phase Locked Loop synthesizer consists of a VCO, an asynchronous
divider chain, a phase detector with charge pump and a loop filter and is fully
implemented on-chip. The VCO is including spiral inductors and varactor
diodes. The FSEL pin (Pin11) has to be left open. The tuning range of the VCO
was designed to guarantee over production spread and the specified tempera-
ture range a receive frequency range between 310 and 350MHz depending on
whether high- or low-side injection of the local oscillator is used. The oscillator
signal is fed both to the synthesiser divider chain and to a divider that is dividing
the signal by 2 before it is applied to the downconverting mixer. Local oscillator
high side injection has to be used for receive frequencies between approxi-
mately 310 and 330 MHz, low side injection for receive frequencies between
330 and 350MHz - see also Section 4.4..
3.4.4 Crystal Oscillator
The on-chip crystal oscillator circuitry allows for utilisation of quartzes both in
the 5 and 10MHz range as the overall division ratio of the PLL can be switched
between 32 and 64 via the CSEL (Pin 16 ) pin according to the following table.
Table 3-2 CSEL Pin Operating States
CSEL
Crystal Frequency
5.xx MHz
Open
Shorted to ground
10.xx MHz
Wireless Components
3 - 10
Specification, May 2001
TDA 5211
Functional Description
The calculation of the value of the necessary quartz load capacitance is shown
in Section 4.3, the quartz frequency calculation is explained in Section 4.4.
3.4.5 Limiter
The Limiter is an AC coupled multistage amplifier with a cumulative gain of
approximately 80 dB that has a bandpass-characteristic centred around
10.7 MHz. It has a typical input impedance of 330 Ω to allow for easy interfacing
to a 10.7 MHz ceramic IF filter. The limiter circuit also acts as a Receive Signal
Strength Indicator (RSSI) generator which produces a DC voltage that is
directly proportional to the input signal level as can be seen in Figure 4-2. This
signal is used to demodulate ASK-modulated receive signals in the subsequent
baseband circuitry. The RSSI output is applied to the modulation format switch,
to the Peak Detector input and to the AGC circuitry.
In order to demodulate ASK signals the MSEL pin has to be left open as
described in the next chapter.
3.4.6 FSK Demodulator
To demodulate frequency shift keyed (FSK) signals a PLL circuit is used that is
contained fully on chip. The Limiter output differential signal is fed to the linear
phase detector as is the output of the 10.7 MHz center frequency VCO. The
demodulator gain is typically 140µV/kHz. The passive loop filter output that is
comprised fully on chip is fed to both the VCO and the modulation format switch
described in more detail below. This signal is representing the demodulated sig-
nal with low frequencies applied to the demodulator demodulated to logic ones
and high frequencies demodulated to logic zeroes. However this is only valid in
case the local oscillator is low-side injected to the mixer which is applicable to
receive frequencies above 330MHz (e.g. 345MHz). In case of receive frequen-
cies below 330MHz (e.g.315MHz) high frequencies are demodulated as logical
ones due to a sign inversion in the downconversion mixing process. See also
Section 4.4.
The modulation format switch is actually a switchable amplifier with an AC gain
of 11 that is controlled by the MSEL pin (Pin 15) as shown in the following table.
This gain was chosen to facilitate detection in the subsequent circuits. The DC
gain is 1 in order not to saturate the subsequent Data Filter wih the DC offset
produced by the demodulator in case of large frequency offsets of the IF signal.
The resulting frequency characteristic and details on the principle of operation
of the switch are described in Section 4.6.
Table 3-3 MSEL Pin Operating States
MSEL
Modulation Format
Open
ASK
FSK
Shorted to ground
Wireless Components
3 - 11
Specification, May 2001
TDA 5211
Functional Description
The demodulator circuit is switched off in case of reception of ASK signals.
3.4.7 Data Filter
The data filter comprises an OP-Amp with a bandwidth of 100kHz used as a
voltage follower and two 100kΩ on-chip resistors. Along with two external
capacitors a 2nd order Sallen-Key low pass filter is formed. The selection of the
capacitor values is described in Section 4.2.
3.4.8 Data Slicer
The data slicer is a fast comparator with a bandwidth of 100 kHz. This allows
for a maximum receive data rate of up to 100kBaud. The maximum achievable
data rate also depends on the IF Filter bandwidth and the local oscillator toler-
ance values. Both inputs are accessible. The output delivers a digital data sig-
nal (CMOS-like levels) for sbsequent circuits. The self-adjusting threshold on
pin 20 its generated by RC-term or peak detector depending on the baseband
coding scheme. The data slicer threshold generation alternatives are described
in more detail in Section 4.5.
3.4.9 Peak Detector
The peak detector generates a DC voltage which is proportional to the peak
value of the receive data signal. An external RC network is necessary. The input
is connected to the output of the RSSI-output of the Limiter, the output is con-
nected to the PDO pin (Pin 26 ). This output can be used as an indicator for the
received signal strength to use in wake-up circuits and as a reference for the
data slicer in ASK mode. The output current is typically 950µA, the discharge
current is lower than 2µA. Note that the RSSI level is also output in case of FSK
mode.
3.4.10 Bandgap Reference Circuitry
A Bandgap Reference Circuit provides a temperature stable reference voltage
for the device. A power down mode is available to switch off all subcircuits which
is controlled by the PWDN pin (Pin 27) as shown in the following table. The sup-
ply current drawn in this case is typically 50nA.
Table 3-4 PDWN Pin Operating States
PDWN
Operating State
Powerdown Mode
Receiver On
Open or tied to ground
Tied to Vs
Wireless Components
3 - 12
Specification, May 2001
4
Applications
Contents of this Chapter
4.1 Choice of LNA Threshold Voltage and Time Constant. . . . . . . . . . . . 4-2
4.2 Data Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.3 Quartz Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.4 Quartz Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.5 Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4.6 ASK/FSK Switch Functional Description . . . . . . . . . . . . . . . . . . . . . . 4-8
4.7 Principle of the Precharge Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
TDA 5211
Applications
4.1 Choice of LNA Threshold Voltage and Time Constant
In the following figure the internal circuitry of the LNA automatic gain control is
shown.
R1
R2
U
th re s h old
23
Pins:
24
RSSI (0.8 - 2.8V)
20kΩ
OTA
VCC
+3.1V
I
LNA
load
Gain control
voltage
RSSI > Uthres hold: Iload=4.2µA
RSSI < Uthres hold: Iload= -1.5µA
4
Uc :< 2.6V : Gain high
Uc :> 2.6V : Gain low
UC
C
Uc max = VCC - 0.7V
Uc min = 1.67V
LNA_autom.wmf
Figure 4-1
LNA Automatic Gain Control Circuitry
The LNA automatic gain control circuitry consists of an operational transimped-
ance amplifier that is used to compare the received signal strength signal
(RSSI) generated by the Limiter with an externally provided threshold voltage
Uthres. As shown in the following figure the threshold voltage can have any
value between approximately 0.8 and 2.8V to provide a switching point within
the receive signal dynamic range.
This voltage Uthres is applied to the THRES pin (Pin 23) The threshold voltage
can be generated by attaching a voltage divider between the 3VOUT pin
(Pin 24) which provides a temperature stable 3V output generated from the
internal bandgap voltage and the THRES pin. If the RSSI level generated by the
Limiter is higher than Uthres, the OTA generates a positive current Iload. This
yields a voltage rise on the TAGC pin (Pin 4). Otherwise, the OTA generates a
negative current. These currents do not have the same values in order to
achieve a fast-attack and slow-release action of the AGC and are used to
charge an external capacitor which finally generates the LNA gain control volt-
age.
Wireless Components
4 - 2
Specification, May 2001
TDA 5211
Applications
3
2.5
2
RSSI Level
1.5
1
0.5
0
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
Input Level at LNA Input [dBm]
RSSI-AGC.wmf
Figure 4-2
RSSI Level and Permissive AGC Threshold Levels
The switching point should be chosen according to the intended operating sce-
nario. The determination of the optimum point is described in the accompanying
Application Note, a threshold voltage level of 1.8V is apparently a viable choice.
It should be noted that the output of the 3VOUT pin is capable of driving up to
50µA, but that the THRES pin input current is only in the region of 40nA. As the
current drawn out of the 3VOUT pin is directly related to the receiver power con-
sumption, the power divider resistors should have high impedance values. The
sum of R1 and R2 has to be 600kΩ in order to yield 3V at the 3VOUT pin. R1
can thus be chosen as 240kΩ, R2 as 360kΩ to yield an overall 3VOUT output
current of 5µA1 and a threshold voltage of 1.8V
Note: If the LNA gain shall be kept in either high or low gain mode this has to
be accomplished by tying the THRES pin to a fixed voltage. In order to achieve
high gain mode operation, a voltage higher than 2.8V shall be applied to the
THRES pin, such as a short to the 3VOLT pin. In order to achieve low gain
mode operation a voltage lower than 0.7V shall be applied to the THRES, such
as a short to ground.
As stated above the capacitor connected to the TAGC pin is generating the gain
control voltage of the LNA due to the charging and discharging currents of the
OTA and thus is also responsible for the AGC time constant. As the charging
and discharging currents are not equal two different time constants will result.
The time constant corresponding to the charging process of the capacitor shall
be chosen according to the data rate. According to measurements performed
at Infineon the capacitor value should be greater than 47nF.
1. note the 20kΩ resistor in series with the 3.1V internal voltage source
Wireless Components
4 - 3
Specification, May 2001
TDA 5211
Applications
4.2 Data Filter Design
Utilising the on-board voltage follower and the two 100kΩ on-chip resistors a
2nd order Sallen-Key low pass data filter can be constructed by adding 2 exter-
nal capacitors between pins 19 (SLP) and 22 (FFB) and to pin 21 (OPP) as
depicted in the following figure and described in the following formulas1.
C1
22
C2
21
Pins:
19
R
R
100k
100k
Filter_Design.wmf
Figure 4-3
(1)(2)
Data Filter Design
b
2Q b
R2Πf3dB
C2 = ---------------------------
4QRΠf3dB
C1 = ----------------------
with
b
a
(3)the quality factor of the poles
Q = ------
where
in case of a Bessel filter a = 1.3617, b = 0.618
and thus Q = 0.577
and in case of a Butterworth filtera = 1.414, b = 1
and thus Q = 0.71
Example: Butterworth filter with f3dB = 5kHz and R = 100kΩ:
C1 = 450pF, C2 = 225pF
1. taken from Tietze/Schenk: Halbleiterschaltungstechnik, Springer Berlin, 1999
Wireless Components
4 - 4
Specification, May 2001
TDA 5211
Applications
4.3 Quartz Load Capacitance Calculation
The value of the capacitor necessary to achieve that the quartz oscillator is
operating at the intended frequency is determined by the reactive part of the
negative resistance of the oscillator circuit as shown in Section 5.1.3 and by the
quartz specifications given by the quartz manufacturer.
CS
Pin 28
Input
impedance
Crystal
Z1-28
TDA5211
Pin 1
Quartz_load_5211.wmf
Figure 4-4
Determination of Series Capacitance Value for the Quartz Oscillator
Crystal specified with load capacitance
1
CS =
1
+ 2π f X L
Cl
with Cl the load capacitance (refer to the quartz crystal specification).
Example:
10.18 MHz: CL = 12 pF
XL=870 Ω
CS = 7.2 pF
This value may be obtained by putting two capacitors in series to the quartz,
such as 18pF and 22pF in the 5.1MHz case and 18pF and 12pF in the 10.2MHz
case.
Wireless Components
4 - 5
Specification, May 2001
TDA 5211
Applications
4.4 Quartz Frequency Calculation
As described in Section 3.4.3 the operating range of the on-chip VCO is wide
enough to guarantee a receive frequency range between 310 and 350MHz. The
VCO signal is divided by 2 before applied to the mixer . This local oscillator sig-
nal can be used to downconvert the RF signals both with high- or low-side injec-
tion at the mixer. High-side injection of the local oscillator has to be used for
receive frequencies between 310 and 330 MHz. In this case the local oscillator
frequency is calculated by adding the IF frequency (10.7 MHz) to the RF fre-
quency. In this case the higher frequency of a FSK-modulated signal is
demodulated as a logical one (high).
Low-side injection has to be used for receive frequencies between 330 and
350 MHz. The local oscillator frequency is calculated by subtracting the IF fre-
quency (10.7 MHz) from the RF frequency then. Please note that in this case
sign-inversion occurs and the higher frequency of a FSK-modulated signal is
demodulated as a logical zero (low). The overall division ratios in the PLL are
64 or 32 depending on whether the CSEL-pin is left open or tied to ground.
Therefore the quartz frequency may be calculated by using the following for-
mula:
ƒQU = (ƒRF ± 10.7) / r
with ƒRF receive frequency
ƒLO local oscillator (PLL) frequency (ƒRF ± 10.7)
ƒQU quartz oscillator frequency
r
ratio of local oscillator (PLL) frequency and quartz frequency as
shown in the subsequent table
Table 4-1 PLL Division Ratio Dependence on States of CSEL
CSEL
open
GND
Ratio r = (fLO/fQU)
64
32
This yields the following examples:
CSEL tied to GND:
fQU
fQU
=
=
(
315MHz +10.7MHz
)
)
/ 32 = 10.1781 MHz
/ 32 = 10.4469 MHz
(
345MHz −10.7MHz
CSEL open:
fQU
fQU
=
=
(
315MHz + 10.7MHz
)
/ 64 = 5.0891 MHz
/ 64 = 5.2234 MHz
(
345MHz −10.7MHz
)
Wireless Components
4 - 6
Specification, May 2001
TDA 5211
Applications
4.5 Data Slicer Threshold Generation
The threshold of the data slicer can be generated using an external R-C inte-
grator as shown in Figure 4-5. The cut-off frequency of the R-C integrator has
to be lower than the lowest frequency appearing in the data signal. In order to
keep distortion low, the minimum value for R is 20kΩ.
R
C
data out
Pins:
19
20
25
Uthreshold
data
filter
data slicer
Data_slice1.wmf
Figure 4-5
Data Slicer Threshold Generation with External R-C Integrator
In case of ASK operation another possibility for threshold generation is to use
the peak detector in connection with two resistors and one capacitor as shown
in the following figure. The component values are depending on the coding
scheme and the protocol used.
R
C
R
data out
Pins:
20
19
26
25
Uthreshold
peak detector
data slicer
data
filter
Data_slice2.wmf
Figure 4-6
Data Slicer Threshold Generation Utilising the Peak Detector
Wireless Components
4 - 7
Specification, May 2001
TDA 5211
Applications
4.6 ASK/FSK Switch Functional Description
The TDA5211 is containing an ASK/FSK switch which can be controlled via
Pin 15 (MSEL). This switch is actually consisting of 2 operational amplifiers that
are having a gain of 1 in case of the ASK amplifier and a gain of 11 in case of
the FSK amplifier in order to achieve an appropriate demodulation gain charac-
teristic. In order to compensate for the DC-offset generated especially in case
of the FSK PLL demodulator there is a feedback connection between the
threshold voltage of the bit slicer comparator (Pin 20) to the negative input of
the FSK switch amplifier. This is shown in the following figure.
MSEL
15
RSSI (ASK signal)
ASK/FSK Switch
Data Filter
R2=100k
DATA Out
25
R1=100k
-
FSK PLL Demodulator
ASK
FSK
+
+
-
v = 1
Comp
+
-
0.18 mV/kHz
R3=300k
typ. 2 V
1.5 V......2.5 V
R4=30k
FFB
OPP SLP
SLN
22
21
19
20
ASK mode : v=1
FSK mode : v=11
R
C1
C2
C
ask_fsk_datapath.WMF
Figure 4-7
ASK/FSK mode datapath
4.6.1 FSK Mode
The FSK datapath has a bandpass characterisitc due to the feedback shown
above (highpass) and the data filter (lowpass). The lower cutoff frequency f2 is
determined by the external RC-combination. The upper cutoff frequency f3 is
determined by the data filter bandwidth.
The demodulation gain of the FSK PLL demodulator is 140µV/kHz. This gain is
increased by the gain v of the FSK switch, which is 11. Therefore the resulting
dynamic gain of this circuit is 1.5mV/kHz within the bandpass. The gain for the
DC content of FSK signal remains at 140µV/kHz. The cutoff frequencies of the
bandpass have to be chosen such that the spectrum of the data signal is influ-
enced in an acceptable amount.
In case that the user data is containing long sequences of logical zeroes the
effect of the drift-off of the bit slicer threshold voltage can be lowered if the offset
voltage inherent at the negative input of the slicer comparator (Pin20) is used.
The comparator has no hysteresis built in.
Wireless Components
4 - 8
Specification, May 2001
TDA 5211
Applications
This offset voltage is generated by the bias current of the negative input of the
comparator (i.e. 20nA) running over the external resistor R. This voltage raises
the voltage appearing at pin 20 (e.g. 1mV with R = 100kΩ). In order to obtain
benefit of this asymmetrical offset for the demodulation of long zeros the lower
of the two FSK frequencies should be chosen in the transmitter as the zero-
symbol frequency.
In the following figure the shape of the above mentioned bandpass is shown.
gain (pin19)
v
v-3dB
20dB/dec
-40dB/dec
3dB
0dB
f
DC
f1
f2
f3
0.18mV/kHz
2mV/kHz
frequenzgang.WMF
Figure 4-8
Frequency characterstic in case of FSK mode
The cutoff frequencies are calculated with the following formulas:
1
f1 =
R 330kΩ
2π
C
R + 330kΩ
f2 = v f1 =11 f1
f3 = f3dB
f3 is the 3dB cutoff frequency of the data filter - see Section 4.2.
Example:
R = 100kΩ, C = 47nF
This leads tof1 = 44Hz and f2 = 485Hz
Wireless Components
4 - 9
Specification, May 2001
TDA 5211
Applications
4.6.2 ASK Mode
In case the receiver is operated in ASK mode the datapath frequency charac-
tersitic is dominated by the data filter alone, thus it is lowpass shaped.The cutoff
frequency is determined by the external capacitors C12 and C14 and the inter-
nal 100k resistors as described in Section 4.2
0dB
-3dB
-40dB/dec
f
f3dB
freq_ask.WMF
Figure 4-9
Frequency charcteristic in case of ASK mode
Wireless Components
4 - 10
Specification, May 2001
TDA 5211
Applications
4.7 Principle of the Precharge Circuit
In case the data slicer threshold shall be generated with an external RC network
as described in Section 4.5 it is necessary to use large values for the capacitor
C attached to the SLN pin (pin 20) in order to achieve long time constants. This
results also from the fact that the choice of the value for R connected between
the SLP and SLN pins (pins 19 and 20) is limited by the 330kΩ resistor appear-
ing in parallel to R as can be seen in Figure 4-7. Apart from this a resistor value
of 100kΩ leads to a voltage offset of 1mv at the comparator input as described
in Section 4.6.1. The resulting startup time constant τ1 can be calculated with:
τ1 = (R // 330kΩ) · C
In case R is chosen to be 100kΩ and C is chosen as 47nF this leads to
τ1 = (100kΩ // 330kΩ) · 47nF = 77kΩ · 47nF = 3.6ms
When the device is turned on this time constant dominates the time necessary
for the device to be able to demodulate data properly. In the powerdown mode
the capacitor is only discharged by leakage currents.
In order to reduce the turn-on time in the presence of large values of C a pre-
charge circuit was included in the TDA5211 as shown in the following figure.
C2
R1+R2=600k
R2
R1
C
R
U
thres hold
20
19
24
23
Iload
Uc
ASK/FSK Switch
Uc>Us Uc<Us
DataFilter
-
U2
+
0 / 240uA
OTA
Us
U2<2.4V : I=240uA
U2>2.4V: I=0
-
20k
+2.4V
+3.1V
precharge.WMF
Figure 4-10 Principle of the precharge circuit
Wireless Components
4 - 11
Specification, May 2001
TDA 5211
Applications
This circuit charges the capacitor C with an inrush current Iload of typically
220µA for a duration of T2 until the voltage Uc appearing on the capacitor is
equal to the voltage Us at the input of the data filter. This voltage is limited to
2.5V. As soon as these voltages are equal or the duration T2 is exceeded the
precharge circuit is disabled.
τ2 is the time constant of the charging process of C which can be calculated as
τ2 ≈ 20kΩ · C2
as the sum of R1 and R2 is sufficiently large and thus can be neglected. T2 can
then be calculated according to the following formula:
§
¨
¨
¨
¨
©
·
¸
¸
¸
¸
¹
1
T2 = τ 2 ln
≈ τ 2 1.6
2.4V
3V
1 −
The voltage transient during the charging of C2 is shown in the following figure:
U2
3V
2.4V
T2
2
e-fkt1.WMF
Figure 4-11 Voltage appearing on C2 during precharging process
The voltage appearing on the capacitor C connected to pin 20 is shown in the
following figure. It can be seen that due to the fact that it is charged by a con-
stant current source it exhibits is a linear increase in voltage which is limited to
USmax = 2.5V which is also the approximate operating point of the data filter
input. The time constant appearing in this case can be denoted as T3, which
can be calculated with
USmax
C
2.5V
220µA
----------------
T3 = ----------------------- =
C
220µA
Wireless Components
4 - 12
Specification, May 2001
TDA 5211
Applications
Uc
Us
T3
e-Fkt2.WMF
Figure 4-12 Voltage transient on capacitor C attached to pin 20
As an example the choice of C2 = 22nF and C = 47nF yields
τ2 = 0.44ms
T2 = 0.71ms
T3 = 0.53ms
This means that in this case the inrush current could flow for a duration of
0.64ms but stops already after 0.49ms when the USmax limit has been reached.
T3 should always be chosen to be shorter than T2.
It has to be noted finally that during the turn-on duration T2 the overall device
power consumption is increased by the 220µA needed to charge C.
The precharge circuit may be disabled if C2 is not equipped. This yields a T2
close to zero. Note that the sum of R4 and R5 has to be 600kΩ in order to pro-
duce 3V at the THRES pin as this voltage is internally used also as the refer-
ence for the FSK demodulator.
Wireless Components
4 - 13
Specification, May 2001
5
Reference
Contents of this Chapter
5.1 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.2 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.3 Test Board Layouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5.4 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
TDA 5211
preliminary
Reference
5.1 Electrical Data
5.1.1 Absolute Maximum Ratings
WARNING
The maximum ratings may not be exceeded under any circumstances, not even
momentarily and individually, as permanent damage to the IC will result.
Table 5-1 Absolute Maximum Ratings, Ambient temperature T
=-40°C ... + 105°C
AMB
#
Parameter
Symbol
Limit Values
Unit
Remarks
min
-0.3
max
5.5
1
2
3
4
5
Supply Voltage
Vs
Tj
V
°C
Junction Temperature
Storage Temperature
Thermal Resistance
-40
-40
+150
+125
114
Ts
°C
RthJA
VESD
K/W
ESD integrity, all pins excl. Pins 1,3, 6, 28
ESD integrity Pins 1,3,6,28
+2
+1.5
kV
kV
HBM
according to
MIL STD
883D,
method
3015.7
Wireless Components
5 - 2
Specification, May 2001
TDA 5211
preliminary
Reference
5.1.2 Operating Range
Within the operational range the IC operates as explained in the circuit descrip-
tion. The AC/DC characteristic limits are not guaranteed. Currents flowing into
the device are denoted as positive currents and v.v.
Supply voltage: VCC = 4.5V .. 5.5V
Table 5-2 Operating Range, Ambient temperature T
= -40°C ... + 105°C
AMB
#
1
2
Parameter
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
max
Supply Current
I
3.9
3.2
7.5
6.8
mA
mA
f
f
= 315MHz, FSK Mode
= 315MHz, ASK Mode
SF
RF
RF
I
SA
Receiver Input Level
ASK
FSK, frequ. dev. ± 50kHz
@ source impedance 50Ω,
BER 2E-3, average power
level, Manchester encoded
datarate 4kBit, 280kHz IF
Bandwidth
ꢀ
RFin
-110
-102
-13
-13
dBm
dBm
3
4
LNI Input Frequency
MI/X Input Frequency
fRF
fMI
310
310
350
350
MHz
MHz
5
3dB IF Frequency Range
ASK
FSK
fIF -3dB
5
10.4
23
11
MHz
ꢀ
6
7
8
Powerdown Mode On
Powerdown Mode Off
PWDNON
PWDNOFF
VTHRES
0
2
0.8
V
V
V
V
S
S
Gain Control Voltage,
LNA high gain state
2.8
V
9
Gain Control Voltage,
LNA low gain state
VTHRES
0
0.7
V
ꢀꢀ This value is guaranteed by design.
Wireless Components
5 - 3
Specification, May 2001
TDA 5211
preliminary
Reference
5.1.3 AC/DC Characteristics at TAMB = 25°C
AC/DC characteristics involve the spread of values guaranteed within the spe-
cified voltage and ambient temperature range. Typical characteristics are the
median of the production. Currents flowing into the device are denoted as po-
sitive currents and vice versa.
The device performance parameters marked with ꢀ were measured on an
Infineon evaluation board as described in Section 5.2.
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V
Parameter
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
typ
max
Supply
Supply Current
1
Supply current,
standby mode
IS PDWN
50
100
6.5
nA
Pin 27 (PDWN)
open or tied to 0 V
2
Supply current, device
operating in FSK mode
I
4.9
4.2
5.7
mA
Pin 11 (FSEL)
open, Pin 15
(MSEL) tied to GND
SF
3
Supply current, device
operating in ASK mode
I
5
5.8
mA
Pin 11 (FSEL)
open, Pin 15
(MSEL) open
SA
LNA
Signal Input LNI (PIN 3), V
> 2.8V, high gain mode
THRES
1
Average Power Level
at BER = 2E-3
(Sensitivity)
RFin
-113
dBm Manchester
encoded datarate
ꢀ
ꢀ
4kBit, 280kHz IF
Bandwidth
2
Average Power Level
at BER = 2E-3
RFin
-105
dBm Manchester enc.
datarate 4kBit,
(Sensitivity) FSK
280kHz IF Bandw.,
± 50kHz pk. dev.
ꢀ
ꢀ
ꢀ
3
4
5
Input impedance,
S
0.895 / -25.5 deg
11 LNA
f
= 315 MHz
RF
Input level @ 1dB C.P.
fRF=315 MHz
P1dB
IIP3
-14
-10
dBm
LNA
Input 3rd order intercept
LNA
LNI
dBm
dBm
fin = 315 & 317MHz
point f = 315 MHz
RF
ꢀ
6
LO signal feedthrough
at antenna port
LO
-119
Signal Output LNO (PIN 6), V
> 2.8V, high gain mode
THRES
ꢀ
ꢀ
1
2
Gain f = 315 MHz
RF
S
1.577 / 150.3 deg
0.897 / -10.3 deg
21 LNA
Output impedance,
S
22 LNA
f
= 315 MHz
RF
Wireless Components
5 - 4
Specification, May 2001
TDA 5211
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)
Parameter
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
typ
21
max
ꢀ
ꢀ
3
4
Voltage Gain Antenna
G
dB
dB
AntMI
to MI f = 315 MHz
RF
Noise Figure
NF
2
excluding matching
network loss - see
Appendix
LNA
Signal Input LNI, V
= GND, low gain mode
THRES
ꢀ
ꢀ
ꢀ
1
2
3
Input impedance,
= 315 MHz
S
0.918 / -25.2 deg
11 LNA
f
RF
Input level @ 1dB C. P.
= 315 MHz
P1dB
-7
dBm matched input
LNA
LNA
f
RF
Input 3rd order intercept
point f = 315 MHz
IIP3
-13
dBm fin = 315 & 317MHz
RF
Signal Output LNO, V
= GND, low gain mode
THRES
ꢀ
ꢀ
1
2
Gain f = 315 MHz
S
0.193 / 153.7 deg
RF
21 LNA
22 LNA
Output impedance,
S
0.907 / -10.5 deg
f
= 315 MHz
RF
3
Voltage Gain Antenna
G
2
dB
ꢀ
AntMI
to MI f = 315 MHz
RF
Signal 3VOUT (PIN 24)
1
2
Output voltage
Current out
V
2.9
-3
3.1
-5
3.3
V
3VOUT Pin open
see Section 4.1
3VOUT
I
-10
µA
3VOUT
Signal THRES (PIN 23)
1
2
3
4
Input Voltage range
LNA low gain mode
LNA high gain mode
Current in
V
V
V
0
0
V
S
V
V
see Section 4.1
THRES
THRES
THRES
0.3
3.3
V
S
V
or shorted to VCC
ITHRES_in
5
nA
Signal TAGC (PIN 4)
1
Current out,
LNA low gain state
ITAGC_out
-3.6
1
-4.2
1.6
-5
µA
µA
RSSI > V
RSSI < V
THRES
2
Current in,
I
2.2
TAGC_in
THRES
LNA high gain state
MIXER
Signal Input MI/MIX (PINS 8/9)
ꢀ
ꢀ
1
Input impedance,
= 315 MHz
S
0.954 / -10.9 deg
-25
11 MIX
f
RF
Input 3rd order intercept
point
MIX
2
IIP3
dBm
Wireless Components
5 - 5
Specification, May 2001
TDA 5211
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)
Parameter
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
typ
max
Signal Output IFO (PIN 12)
ꢀ
ꢀ
1
2
Output impedance
Z
330
21
Ω
IFO
Conversion Voltage
G
dB
MIX
Gain f = 315 MHz
RF
ꢀ
ꢀ
3
4
Noise Figure, SSB
(~DSB NF+3dB)
NF
13
46
dB
dB
MIX
RF to IF isolation
A
RF-IF
LIMITER
Signal Input LIM/X (PINS 17/18)
ꢀ
1
2
3
4
Input Impedance
RSSI dynamic range
RSSI linearity
Z
264
60
330
396
80
Ω
dB
LIM
DR
LIN
f
RSSI
RSSI
ꢀ
ꢀ
dB
±1
Operating frequency
(3dB points)
5
10.7
23
MHz
LIM
DATA FILTER
ꢀ
1
2
Useable bandwidth
BW
100
1
kHz
V
BB FILT
RSSI Level at Data Fil-
ter Output SLP,
RSSI
0.3
1.8
LNA in high gain
mode
low
RF =-103dBm
IN
3
RSSI Level at Data Fil-
ter Output SLP,
RSSI
3
V
LNA in high gain
mode
high
RF =-30dBm
IN
SLICER
Signal Output DATA (PIN 25)
ꢀ
1
Maximum Datarate
DR
100
0.1
kBps NRZ, 20pF capaci-
tive loading
max
2
3
LOW output voltage
HIGH output voltage
V
V
0
V
V
SLIC_L
V -
S
V -1V
S
V -
S
SLIC_H
1.3V
-100
0.7V
-300
Slicer, Signal Output DATA (PIN 20)
Precharge Current Out
1
I
-220
µA
see Section 4.7
PCH_SLN
Wireless Components
5 - 6
Specification, May 2001
TDA 5211
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)
Parameter
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
typ
max
PEAK DETECTOR
Signal Output PDO (PIN 26)
1
2
Load current
I
-600
0
-950
200
-1300
1000
µA
nA
load
Leakage current
I
leakage
CRYSTAL OSCILLATOR
Signals CRSTL1, CRISTL 2, (PINS 1/28)
1
Operating frequency
f
5
11
MHz fundamental mode,
series resonance
CRSTL
ꢀ
ꢀ
2
Input Impedance
@ ~5MHz
Z
-850 +
j 625
Ω
1-28
1-28
3
4
5
Input Impedance
@ ~10MHz
Z
-700 +
j 865
Ω
Serial Capacity
@ ~5MHz
C
=C1
9.7
pF
pF
S 5
Serial Capacity
@ ~10MHz
C
=C1
7.2
S10
ASK/FSK Signal Switch
Signal MSEL (PIN 15)
1
2
ASK Mode
FSK Mode
V
1.4
0
4
V
V
or open
MSEL
V
0.2
or tied to ground
MSEL
FSK DEMODULATOR
1
Demodulation Gain
G
85
140
225
µV/
FMDEM
kHz
2
Useable IF Bandwidth
BW
10.2
10.7
11.2
MHz
IFPLL
POWER DOWN MODE
Signal PDWN (PIN 27)
1
2
3
Powerdown Mode On
Powerdown Mode Off
PWDN
0
0.8
V
V
ON
PWDN
I
2.8
V
S
Off
Input bias current
PDWN
19
µA
Power On Mode
PDWN
4
Start-up Time until valid
IF signal is detected
T
1
ms
SU
Wireless Components
5 - 7
Specification, May 2001
TDA 5211
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)
Parameter
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
typ
max
PLL DIVIDER
Signal CSEL (PIN 16)
1
2
f
range 5.xxMHz
V
1.4
0
4
V
V
or open
CRSTL
CSEL
f
range
V
0.2
CRSTL
CSEL
10.xxMHz
3
Input bias current
CSEL
I
-3
-5
-7
µA
CSEL tied to GND
CSEL
ꢀꢀ Measured only in lab.
Wireless Components
5 - 8
Specification, May 2001
TDA 5211
preliminary
Reference
5.1.4 AC/DC Characteristics at TAMB = -40 to 105°C
Currents flowing into the device are denoted as positive currents and vice
versa.
Table 5-4 AC/DC Characteristics with T
= -40°C ... + 105°C, VVCC = 4.5 ... 5.5 V
AMB
Parameter
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
typ
max
Supply
Supply Current
1
Supply current,
standby mode
IS PDWN
50
400
7.5
nA
Pin 27 (PDWN)
open or tied to 0 V
2
Supply current, device
operating in FSK mode
I
3.9
3.2
5.7
mA
Pin 11 (FSEL) tied
to GND, Pin 15
(MSEL) tied to GND
SF
3
Supply current, device
operating in ASK mode
I
5
6.8
mA
Pin 11 (FSEL)
open, Pin 15
(MSEL) open
SA
Signal 3VOUT (PIN 24)
1
2
Output voltage
Current out
V
I
2.9
-3
3.1
-5
3.3
-10
V
3VOUT Pin open
see Section 4.1
3VOUT
µA
3VOUT
Signal THRES (PIN 23)
1
2
3
4
Input Voltage range
LNA low gain mode
LNA high gain mode
Current in
V
0
0
3
V -1V
S
V
V
see Section 4.1
THRES
THRES
THRES
V
V
0.3
V
V
or shorted to Pin 24
S
ITHRES_in
5
nA
Signal TAGC (PIN 4)
1
Current out,
LNA low gain state
ITAGC_out
-1
-4.2
1.5
-8
µA
µA
RSSI > V
RSSI < V
THRES
2
Current in, LNA high
gain state
V
0.5
5
TAGC_in
THRES
MIXER
Conversion Voltage
Gain f = 315 MHz
1
G
+19
dB
MIX
RF
LIMITER
Signal Input LIM/X (PINS 17/18)
1
2
RSSI dynamic range
DR
60
80
1
dB
V
RSSI
RSSI Level at Data Fil-
ter Output SLP,
RSSI
0.3
LNA in high gain
mode
low
RF = -103dBm
IN
3
RSSI Level at Data Fil-
ter Output SLP,
RSSI
1.8
3
V
LNA in high gain
mode
high
RF = -30dBm
IN
Wireless Components
5 - 9
Specification, May 2001
TDA 5211
preliminary
Reference
Table 5-4 AC/DC Characteristics with T
= -40°C ... + 105°C, VVCC = 4.5 ... 5.5 V
AMB
Parameter
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
typ
max
DATA FILTER
Slicer, Signal Output DATA (PIN 25)
ꢀ
1
Maximum Datarate
DR
100
0.1
kBps NRZ, 20pF capaci-
tive loading
max
2
3
LOW output voltage
HIGH output voltage
V
V
0
V
V
SLIC_L
V -
S
V -1V
S
V -
S
SLIC_H
1.5V
-100
0.5V
-300
Slicer, Signal Output DATA (PIN 20)
1
Precharge Current Out
I
-220
µA
see Section 4.7
PCH_SLN
PEAK DETECTOR
Signal Output PDO (PIN 26)
1
2
Load current
I
-400
0
-850
700
-1400
2000
µA
nA
load
Leakage current
I
leakage
CRYSTAL OSCILLATOR
Signals CRSTL1, CRSTL 2, (PINS 1/28)
Operating frequency
1
f
5
11
MHz
fundamental mode,
series resonance
CRSTL
ASK/FSK Signal Switch
Signal MSEL (PIN 15)
1
2
ASK Mode
FSK Mode
V
V
1.4
0
4
V
V
or open
MSEL
0.2
MSEL
FSK DEMODULATOR
1
Demodulation Gain
G
105
140
245
11
µV/
kHz
FMDEM
2
Useable IF Bandwidth
BW
10.4
10.7
MHz
IFPLL
POWER DOWN MODE
Signal PDWN (PIN 27)
1
2
3
Powerdown Mode On
Powerdown Mode Off
PWDN
0
0.8
V
V
ON
PWDN
2.8
V
S
Off
Start-up Time until valid
signal is detected at IF
T
1
ms
SU
PLL DIVIDER
Signal CSEL (PIN 16)
1
2
f
range 5.xxMHz
V
1.4
0
4
V
V
or open
CRSTL
CSEL
f
range
V
0.2
CRSTL
CSEL
10.xxMHz
3
Input bias current
CSEL
I
-3
-5
-7
µA
CSEL tied to GND
CSEL
Wireless Components
5 - 10
Specification, May 2001
TDA 5211
preliminary
Reference
5.2 Test Circuit
The device performance parameters marked with ꢀ in Section 5.1.3 were mea-
sured on an Infineon evaluation board. This evaluation board can be obtained
together with evaluation boards of the accompanying transmitter device
TDA5101 in an evaluation kit that may be ordered on the INFINEON RKE
Webpage www.infineon.com/rke. In case a matching codeword is received,
decoded and accepted by the decoder the on-board LED will turn on. This sig-
nal is also accessible on a 2-pole pin connector and can be used for simple
remote-control applications. More information on the kit is available on request.
TDA521x_testboard_20_schematic.WMF
Figure 5-1
Schematic of the Evaluation Board
Wireless Components
5 - 11
Specification, May 2001
TDA 5211
preliminary
Reference
5.3 Test Board Layouts
tda521x_testboard_20_top.WMF
Figure 5-2
Top Side of the Evaluation Board
tda521x_testboard_20_bot.WMF
Figure 5-3
Bottom Side of the Evaluation Board
Wireless Components
5 - 12
Specification, May 2001
TDA 5211
preliminary
Reference
tda521x_testboard_20_plc.EMF
Figure 5-4
Component Placement on the Evaluation Board
Wireless Components
5 - 13
Specification, May 2001
TDA 5211
preliminary
Reference
5.4 Bill of Materials
The following components are necessary for evaluation of the TDA5211 at
315 MHz without use of a Microchip HCS512 decoder.
Table 5-5 Bill of Materials
Ref
Value
100kΩ
100kΩ
820kΩ
240kΩ
360kΩ
10kΩ
15nH
12pF
Specification
0805, ± 5%
R1
R2
0805, ± 5%
R3
0805, ± 5%
R4
0805, ± 5%
R5
0805, ± 5%
R6
0805, ± 5%
L1
Toko, PTL2012-F15N0G
0805,COG, ± 2%
0805, COG, ± 0.1pF
0805, COG, ± 0.1pF
0805, COG, ± 0.1pF
0805, COG, ± 5%
1206, X7R, ± 10%
Toko, PTL2012-F15N0G
0805, COG, ± 5%
0805, COG, ± 5%
0805, COG, ± 5%
0805, X7R, ± 10%
0805, X7R, ± 10%
0805, COG, ± 5%
0805, X7R, ± 10%
0805, COG, ± 5%
0805, COG, ± 5%
0805, COG, ± 1%
0805, COG, ± 1%
0805, X7R, ± 5%
L2
C1
3.3 pF
10pF
C2
C3
6.8pF
100pF
47nF
C4
C5
C6
15nH
100pF
33pF
C7
C8
C9
100pF
10nF
C10
C11
C12
C13
C14
C15
C16
C17
C18
10nF
220pF
47nF
470pF
47nF
12pF
18pF
22nF
Q1
(315 + 10.7MHz)/32
HC49/U, fundamental mode, C = 12pF,
L
e.g. 315 MHz: Jauch Q 10,178130-S11-1017-12-10/20
Q2
SFE10.7MA5-A
142-0701-801
Murata
X2, X3
Johnson
Wireless Components
5 - 14
Specification, May 2001
TDA 5211
preliminary
Reference
S1-S3, S6
X1
2-pole pin connector
S4
3-pole pin connector, or not equipped
Infineon
IC1
TDA 5211
Please note that a capacitor has to be soldered in place L2 and an inductor in
place C6.
The following components are necessary in addition to the above mentioned
ones for evaluation of the TDA5211 in conjunction with a Microchip HCS512
decoder.
Table 5-6 Bill of Materials Addendum
Ref
Value
100kΩ
10kΩ
Specification
0805, ± 5%
R7
R8
0805, ± 5%
R9
100kΩ
22kΩ
0805, ± 5%
R10
R11
R12
R13
R14
R21
R22
R23
R24
R25
C19
C21
C22
IC2
0805, ± 5%
100Ω
100Ω
100Ω
100Ω
22kΩ
0805, ± 5%
0805, ± 5%
0805, ± 5%
0805, ± 5%
0805, ± 5%
10kΩ
0805, ± 5%
22kΩ
0805, ± 5%
820kΩ
560Ω
10pF
0805, ± 5%
0805, ± 5%
0805, COG, ± 5%
1206, X7R, ± 10%
1206, X7R, ± 10%
Microchip
100nF
100nF
HCS512
S5, X4-X9
T1, T2
D1
2-pole pin connector
Infineon
BC 847B
LS T670-JL
Infineon
Wireless Components
5 - 15
Specification, May 2001
TDA 5211
preliminary
Reference
5.5 Appendix - Noise Figure and Gain Circles
The following gain and noise figure circles were measured utilizing Microlab
Stub Stretchers and a HP8514 network analyser. Maximum gain is shown at
point 1 at 18.5 dB, minimum noise figure ist 1.9dB at point 2, step size of circles
is 0.5dB.
Figure 5-5
Gain and Noise Circles of the TDA5211 at 315 MHz.
Wireless Components
5 - 16
Specification, May 2001
TDA 5211
preliminary
Reference
Wireless Components
5 - 17
Specification, May 2001
TDA 5211
List of Figures
List of Figures
Figure 2-1 P-TSSOP-28-1 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3-1 IC Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3-2 Main Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-1 LNA Automatic Gain Control Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-2 RSSI Level and Permissive AGC Threshold Levels . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-3 Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-4 Determination of Series Capacitance Value for the Quartz Oscillator . . . . . . . . . . . . . .
Figure 4-5 Data Slicer Threshold Generation with External R-C Integrator . . . . . . . . . . . . . . . . . .
Figure 4-6 Data Slicer Threshold Generation Utilising the Peak Detector . . . . . . . . . . . . . . . . . . .
Figure 4-7 ASK/FSK mode datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-8 Frequency characterstic in case of FSK mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-3
3-2
3-9
4-2
4-3
4-4
4-5
4-7
4-7
4-8
4-9
Figure 4-9 Frequency charcteristic in case of ASK mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
Figure 4-10 Principle of the precharge circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Figure 4-11 Voltage appearing on C2 during precharging process . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Figure 4-12 Voltage transient on capacitor C attached to pin 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Figure 5-1 Schematic of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Figure 5-2 Top Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Figure 5-3 Bottom Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Figure 5-4 Component Placement on the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Figure 5-5 Gain and Noise Circles of the TDA5211 at 315 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
Wireless Components
List of Figures - 1
Specification, May 2001
TDA 5211
List of Tables
List of Tables
Table 3-1 Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-3
Table 3-2 CSEL Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Table 3-3 MSEL Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Table 3-4 PDWN Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Table 4-1 PLL Division Ratio Dependence on States of CSEL . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-1 Absolute Maximum Ratings, Ambient temperature TAMB=-40°C ... + 105°C . . . . . . . .
Table 5-2 Operating Range, Ambient temperature TAMB= -40°C ... + 105°C . . . . . . . . . . . . . . . .
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V . . . . . . . . . . . . . . . . . . . . .
Table 5-4 AC/DC Characteristics with TAMB= -40°C ... + 105°C, VVCC = 4.5 ... 5.5 V . . . . . . . . .
4-6
5-2
5-3
5-4
5-9
Table 5-5 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Table 5-6 Bill of Materials Addendum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Wireless Components
List of Tables - 1
Specification, May 2001
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