TDA5204E1 [INFINEON]
ASK Single Conversion Receiver 390MHz; ASK单转换接收器390MHz
| 型号： | TDA5204E1 |
| 厂家： | 
Infineon |
| 描述： | ASK Single Conversion Receiver 390MHz |
| 文件： | 总40页 (文件大小：1218K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Wireless Components
ASK Single Conversion Receiver 390MHz
TDA 5204 E1
Version 1.0
Specification December 2000
preliminary
Revision History
Current Version: 1.0 as of 12.01.01
Previous Version: none
Page
Page
Subjects (major changes since last revision)
(in previous
Version)
(in current
Version)
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Edition 12.00
Published by Infineon Technologies AG,
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© Infineon Technologies AG December 2000.
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TDA 5204 E1
preliminary
Product Info
Product Info
Package
General Description The IC is a very low power consump-
tion single chip ASK Single Conver-
sion Receiver for receive frequencies
between 385 and 406MHz. The
Receiver offers a high level of integra-
tion and needs only a few external
components. The device contains a
low noise amplifier (LNA), a double
balanced mixer, a fully integrated
VCO, a PLL synthesiser, a crystal
oscillator, a limiter with RSSI genera-
tor, a data filter, a data comparator
(slicer) and a peak detector. Addition-
ally there is a power down feature to
save battery life.
Features
Low supply current
(Is = 4.8mA typ.)
390MHz band
Selectable reference frequency
Supply voltage range 5V 10%
Limiter with RSSI generation,
operating at 10.7MHz
Temperature range -40°C...+85°C
Power down mode with very low
supply current (50nA typ)
2nd order low pass data filter with
external capacitors
Fully integrated VCO and PLL
Synthesiser
Data slicer with self-adjusting
threshold
RF input sensitivity < –110dBm
Application
Keyless Entry Systems
Remote Control Systems
Fire Alarm Systems
Low Bitrate Communication
Systems
Ordering Information
Type
Ordering Code
Q67037-A1169
Package
TDA 5204
P-TSSOP-28-1
available on tape and reel
Wireless Components
Product Info
Specification, December 2000
1
Table of Contents
1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-i
2 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1
2-2
2.1
2.2
2.3
2.4
2.5
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Possible Receive Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-2
2-2
2-3
2-3
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1
3-2
3.1
3.2
3.3
3.4
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-3
3-8
3-8
3-8
3-9
3-9
3-9
3.4.1 Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2 Mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.3 PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.4 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.5 Limiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.4.6 Data Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.4.7 Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.4.8 Peak Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.4.9 Bandgap Reference Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-1
4-2
4.1
4.2
4.3
4.4
4.5
LNA and Automatic Gain Control (AGC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quartz Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quartz Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4
4-5
4-6
4-7
5
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-1
5-2
5-2
5-3
5-4
5.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2
5.3
5.4
Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Board Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-8
5-9
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
2
Product Description
Contents of this Chapter
2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.4 Possible Receive Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
TDA 5204 E1
preliminary
Product Description
2.1 Overview
The IC is a very low power consumption single chip ASK Superheterodyne
Receiver (SHR) for the frequency band 390MHz. The SHR offers a high level
of integration and needs only a few external components. The device contains
a low noise amplifier (LNA), a double balanced mixer, a fully integrated VCO, a
PLL synthesiser, a crystal oscillator, a limiter with RSSI generator, a data filter,
a data comparator (slicer) and a peak detector. Additionally there is a power
down feature to save battery life.
2.2 Application
Keyless Entry Systems
Remote Control Systems
Fire Alarm Systems
Low Bitrate Communication Systems
2.3 Features
Low supply current (Is = 4.8mA typ.)
Supply voltage range 5V 10%
Power down mode with very low supply current (50nA typ.)
Fully integrated VCO and PLL Synthesiser
RF input sensitivity < –110dBm
frequency band 390MHz
Selectable reference frequency
Limiter with RSSI generation, operating at 10.7MHz
2nd order low pass data filter with external capacitors
Data slicer with self-adjusting threshold
Temperature range -40°C...+85°C
Wireless Components
2 - 2
Specification, December 2000
TDA 5204 E1
preliminary
Product Description
2.4 Possible Receive Ranges
385...406MHz (high-side injected)
406...428MHz (low-side injected)
781...823MHz (high-side injected)
803...844MHz (low-side injected)
2.5 Package Outlines
P_TSSOP_28.EPS
Figure 2-1
P-TSSOP-28-1 package outlines
Wireless Components
2 - 3
Specification, December 2000
3
Functional Description
Contents of this Chapter
3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.4 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
TDA 5204 E1
preliminary
Functional Description
3.1 Pin Configuration
CRST1
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CRST2
PWDN
PDO
VCC
2
LNI
3
TAGC
4
DATA
3VOUT
THRES
FFB
TDA5204
AGND
5
LNO
6
VCC
7
MI
8
OPP
MIX
9
SLN
AGND
10
SLP
FSEL
11
LIMX
LIM
IFO
12
DGND
13
CSEL
LF
VDD
14
Pin_Configuration.wmf
Figure 3-1
IC Pin Configuration
Wireless Components
3 - 2
Specification, December 2000
TDA 5204 E1
preliminary
Functional Description
3.2 Pin Definition and Function
Table 3-1 Pin Definition and Function
Pin No. Symbol
Equivalent I/O-Schematic
Function
1
CRST1
External Crystal Connector 1
4.15V
1
2
3
VCC
LNI
5V Supply
LNA Input
3
1k
4
TAGC
AGC Time Constant Control
4.3V
4uA
1k
4
1.5uA
1.7V
5
6
AGND
LNO
Analogue Ground Return
LNA Output
1k
6
7
VCC
5V Supply
Wireless Components
3 - 3
Specification, December 2000
TDA 5204 E1
preliminary
Functional Description
8
9
MI
Mixer Input
1.7V
2k
2k
8
9
MIX
Complementary Mixer Input
Analogue Ground Return
10
11
AGND
FSEL
390MHz:
not applicable - has to be left
open
1.2V
40k
11
12
IFO
10.7 MHz IF Mixer Output
300uA
2.2V
60
12
4.5k
13
14
DGND
VDD
Digital Ground Return
5V Supply (PLL Counter Cir-
cuitry)
15
LF
PLL Filter Access Point
(Loop Filter)
4.8V
30uA
30uA
200
100
15
2.4V
Wireless Components
3 - 4
Specification, December 2000
TDA 5204 E1
preliminary
Functional Description
16
CSEL
6.xx or 12.xx MHz Quartz
Selector
1.2V
80k
16
17
LIM
Limiter Input
2.4V
17
18
18
19
LIMX
SLP
Complementary Limiter Input
Data Filter Output
Data Slicer Positive Input
Peak Detector Input
10k
100
19
10k
40u
20
SLN
Data Slicer Negative Input
10k
20
21
OPP
OpAmp Noninverting Input
200
21
Wireless Components
3 - 5
Specification, December 2000
TDA 5204 E1
preliminary
Functional Description
22
23
24
25
FFB
Data Filter Feedback Pin
AGC Threshold Input
3V Reference Output
Data Output
100k
22
THRES
3VOUT
DATA
10k
23
24
3V
200
25
80k
Wireless Components
3 - 6
Specification, December 2000
TDA 5204 E1
preliminary
Functional Description
26
27
28
PDO
Peak Detector Output
200
26
PDWN
Power Down Input
Vs --> Power ON
GND---> Power Down
27
220k
220k
CRST2
External Crystal Connector 2
4.15V
28
Wireless Components
3 - 7
Specification, December 2000
TDA 5204 E1
preliminary
Functional Description
3.3 Functional Block Diagram
VCC
IF
Filter
LNO
6
MI MIX IFO
LIM
17
LIMX
18
FFB
22
OPP
21
SLP
19
SLN
20
9
8
12
25
DATA
3
RF
LNA
RSSI
SLICER
PDO
26
23
4
TAGC
VDD
THRES
3VOUT
AGC
Reference
24
TDA 5204
14
UREF
Φ
Crystal
: 1/2
VCO
: 128/64
DET
OSC
DGND 13
Bandgap
Loop
Filter
Reference
2/7
VCC
5/10
AGND
28
11
FSEL
15
LF
16
CSEL
1
27
PDWN
Crystal
Function_5204.wmf
Figure 3-2
Main Block Diagram
3.4 Functional Blocks
3.4.1 Low Noise Amplifier (LNA)
The LNA is an on-chip cascode amplifier with a voltage gain of 15 to 20dB. The
gain figure is determined by the external matching networks situated ahead of
LNA and between the LNA output LNO (Pin 6) and the Mixer Inputs MI and MIX
(Pins 8 and 9). The noise figure of the LNA is approximately 2dB, the current
consumption is 500µA. The gain can be reduced by approximately 18dB. The
switching point of this AGC action can be determined externally by applying a
threshold voltage at the THRES pin (Pin 23). This voltage is compared internally
with the received signal (RSSI) level generated by the limiter circuitry. In case
that the RSSI level is higher than the threshold voltage the LNA gain is reduced
and vice versa. The threshold voltage can be generated by attaching a voltage
divider between the 3VOUT pin (Pin 24) which provides a temperature stable
3V output generated from the internal bandgap voltage and the THRES pin as
described in Section 4.1. The time constant of the AGC action can be deter-
mined by connecting a capacitor to the TAGC pin (Pin 4) and should be chosen
along with the appropriate threshold voltage according to the intended operat-
Wireless Components
3 - 8
Specification, December 2000
TDA 5204 E1
preliminary
Functional Description
ing case and interference scenario to be expected during operation. The opti-
mum choice of AGC time constant and the threshold voltage is described in
Section 4.1.
3.4.2 Mixer
The Double Balanced Mixer downconverts the input frequency (RF) 390MHz to
the intermediate frequency (IF) at 10.7MHz with a voltage gain of approximately
21dB. A low pass filter with a corner frequency of 20MHz is built on chip in order
to suppress RF signals to appear at the IF output ( IFO pin). The IF output is
internally consisting of an emitter follower that has a source impedance of
approximately 330Ω= to facilitate interfacing the pin directly to a standard
10.7MHz ceramic filter without additional matching circuitry.
3.4.3 PLL Synthesizer
The Phase Locked Loop synthesiser consists of a VCO, an asynchronous
divider chain, a phase detector with charge pump and a loop filter and is fully
implemented on-chip. The VCO is including spiral inductors and varactor
diodes. It’s nominal centre frequency is 800MHz. The FSEL pin (Pin 11) has to
be left open. No additional components are necessary. The oscillator signal is
fed both to the synthesiser divider chain and to the downconverting mixer. The
VCO signal is divided by two before it is fed to the mixer. The loop filter is also
realised fully on-chip.
3.4.4 Crystal Oscillator
The on-chip crystal oscillator circuitry allows for utilisation of quartzes both in
the 6 and 12MHz range as the overall division ratio of the PLL can be switched
between 64 and 128 via the CSEL (Pin 16 ) pin according to the following table.
Table 3-2 CSEL Pin Operating States
CSEL
Crystal Frequency
6.xx MHz
Open
Shorted to ground
12.xx MHz
The calculation of the value of the necessary quartz load capacitance is shown
in Section 4.3, the quartz frequency calculation is expained in Section 4.4.
Wireless Components
3 - 9
Specification, December 2000
TDA 5204 E1
preliminary
Functional Description
3.4.5 Limiter
The Limiter is an AC coupled multistage amplifier with a cumulative gain of
approximately 80dB that has a bandpass-characteristic centred around
10.7MHz. It has an input impedance of 330 Ω=to allow for easy interfacing to a
10.7MHz ceramic IF filter. The limiter circuit acts as a Receive Signal Strength
Indicator (RSSI) generator which produces a DC voltage that is directly propor-
tional to the input signal level as can be seen in Figure 4.1. This signal is used
to demodulate the ASK receive signal in the subsequent baseband circuitry and
to turn down the LNA gain by approximately 18dB in case the input signal
strength is too strong as described in Section 3.4.1 and Section 4.1.
3.4.6 Data Filter
The data filter comprises an OP-Amp with a bandwidth of 100kHz used as a
voltage follower and two 100kΩ= on-chip resistors. Along with two external
capacitors a 2nd order Sallen-Key low pass filter is formed. The selection of the
capacitor values is described in Section 4.2.
3.4.7 Data Slicer
The data slicer is a fast comparator with a bandwidth of 100 kHz. This allows
for a maximum receive data rate of approximately 120kBaud. The maximum
achievable data rate also depends on the IF Filter bandwidth and the local oscil-
lator tolerance values. Both inputs are accessible. The output delivers a digital
data signal (CMOS-like levels) for the detector. The self-adjusting threshold on
pin SLN (pin 20) its generated by RC-term or peak detector depending on the
baseband coding scheme. The data slicer threshold generation alternatives are
described in more detail in Section 4.5.
3.4.8 Peak Detector
The peak detector generates a DC voltage which is proportional to the peak
value of the receive data signal. An external RC network is necessary. The out-
put can be used as an indicator for the signal strength and also as a reference
for the data slicer. The maximum output current is approx. 900µA.
Wireless Components
3 - 10
Specification, December 2000
TDA 5204 E1
preliminary
Functional Description
3.4.9 Bandgap Reference Circuitry
A Bandgap Reference Circuit provides a temperature stable reference voltage
for the device. A power down mode is available to switch off all subcircuits which
is controlled by the PWDN pin (Pin 27) as shown in the following table. The sup-
ply current drawn in this case is typically 50nA.
Table 3-3 PDWN Pin Operating States
PDWN
Operating State
Powerdown Mode
Receiver On
Open or tied to ground
Tied to Vs
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3 - 11
Specification, December 2000
4
Applications
Contents of this Chapter
4.1 LNA and Automatic Gain Control (AGC) . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2 Data Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.3 Quartz Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.4 Quartz Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.5 Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
TDA 5204 E1
preliminary
Applications
4.1 LNA and Automatic Gain Control (AGC)
The AGC extends the dynamic range of the receiver.
The automatic gain control in the TDA5204 is a narrow-band control loop which
compares the receive signal strength signal (RSSI, 0.8V to 2.8V) from the lim-
iter with a fixed threshold voltage applied to pin 23 (THRES).
In the following figure the internal circuitry of the LNA automatic gain control is
shown.
R4
R5
Uthreshold
Pins:
24
23
RSSI (0.8 - 2.8V)
+3V
OTA
VCC
Iload
LNA
Gain control
voltage
RSSI > Uthreshold: Iload=4.2µA
RSSI < Uthreshold: Iload= -1.5µA
4
Uc:< 2.6V : Gain high
Uc:> 2.6V : Gain low
UC
C
U
U
cmax= VCC - 0.7V
cmin = 1.67V
LNA_autom.wmf
Figure 4-1
LNA Automatic Gain Control Circuitry
The fixed voltage on pin 23 is generated on the external voltage divider. The
comparator is a transimpedance amplifier (OTA), which creates a positive cur-
rent (+4.2uA) in the case the RSSI level is larger than the threshold voltage.
Otherwise the current is -1.5uA. This leads to an asymmetric fast-attack and
slow-release behaviour and thus to fast reaction to the low gain mode and slow
reaction to the high gain mode.
This current is converted into a control voltage over an external capacitor C
attached to pin 4 (TAGC) which defines the gain of the LNA. The limits of the
control voltages for the LNA on pin4 are 1.67V for high gain mode and Vcc-0.7V
for low gain mode.
Wireless Components
4 - 2
Specification, January 2001
TDA 5204 E1
preliminary
Applications
3
2.5
2
RSSI Level
1.5
1
0.5
0
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
Input Level at LNA Input [dBm]
RSSI-AGC.wmf
Figure 4-2
RSSI Level an Permissive AGC Threhold Level
The value of the capacitor defines the response time of the AGC. For a stable
control loop the capacitor value should be at least 47nF.
The AGC can be disabled by tying the THRES-pin either to GND or to VCC as
show here:
LNA high gain:
LNA low gain:
- pin 23 (THRES) shorted to VCC
- pin 23 (THRES) shorted to GND
In these cases capacitor and voltage divider are not necessary.
Wireless Components
4 - 3
Specification, January 2001
TDA 5204 E1
preliminary
Applications
4.2 Data Filter Design
Utilising the on-board voltage follower and the two 100kΩ on-chip resistors a
2nd order Sallen-Key low pass data filter can be constructed by adding 2 exter-
nal capacitors between pins 19 (SLP) and 22 (FFB) and to pin 21 (OPP) as
depicted in the following figure and described in the following formulas1.
C1
22
C2
21
Pins:
19
R
R
100k
100k
Filter_Design.wmf
Figure 4-3
(1)
Data Filter Design
(2)
b
2 ⋅ Q b
C2 = ---------------------------------
C1 = -------------------------
R ⋅ 2πf3dB
4Q ⋅ R ⋅ πf3dB
with
b
a
(3)
the quality factor of the poles
Q = ------
where
in case of a Bessel filter
and thus
a = 1.3617, b = 0.618
Q = 0.577
and in case of a Butterworth filter
and thus
a = 1.41, b = 1
Q = 0.71
Example: Butterworth filter with f3dB = 5kHz and R = 100kΩ:
C1 = 450pF, C2 = 225pF
1. taken from Tietze/Schenk: Halbleiterschaltungstechnik, Springer Berlin, 1999
Wireless Components
4 - 4
Specification, January 2001
TDA 5204 E1
preliminary
Applications
4.3 Quartz Load Capacitance Calculation
The value of the capacitor necessary to achieve that the quartz oscillator is
operating at the intended frequency is determined by the reactive part of the
negative resistance of the oscillator circuit as shown in Section 5.1.3 and by the
quartz specifications given by the quartz manufacturer.
CS
Pin 28
Input
Crystal
impedance
Z1-28
TDA5204
Pin 1
Quartz_load.wmf
Figure 4-4
Determination of Series Capacitance Value for the Quartz Oscillator
The quartz oscillator input impedance consists of a negative resistance and an
inductance L.
Crystal specified with load capacitance
1
C S =
1
C L
2
+
(
2π f
)
L
with CL the load capacitance (refer to the quartz crystal specification).
Examples with typ. values:
6.26 MHz:
CL = 12 pF
L=21uH
L=19uH
CS = 8.6 pF
CS = 5 pF
12.52 MHz: CL = 12 pF
These values may be obtained by putting two capacitors in series to the quartz.
Wireless Components
4 - 5
Specification, January 2001
TDA 5204 E1
preliminary
Applications
4.4 Quartz Frequency Calculation
The quartz frequency is calculated by using the following formula:
ƒQU = (ƒRF 10.7MHz) / r
(1),
with
ƒRF ....
+/- ...
receive frequency
high-side / low-side injected
ƒLO ....
ƒQU ....
local oscillator (PLL) frequency (ƒRF 10.7)
quartz oscillator frequency
r
....
ratio of local oscillator (PLL) frequency and quartz
frequency as shown in the subsequent table.
Table 4-1
frequency range
fRF
high-side
injected
low-side
injected
FSEL
Pin11
385...406MHz
406...428MHz
781...823MHz
803...844MHz
X
open
open
GND
GND
X
X
X
Table 4-2
Table 4-3
quartz crystal
range
CSEL
FSEL
CSEL
Ratio r
(fLO/fQU
Pin16
open
GND
)
6.xx MHz
open
open
GND
GND
open
GND
open
GND
64
32
12.xx MHz
128
64
Example:
fRF=390MHz
f
QU=(390MHz+10.7MHz) / 64 = 6.2609375MHz
QU=(390MHz+10.7MHz) / 32 = 12.521875MHz
f
Wireless Components
4 - 6
Specification, January 2001
TDA 5204 E1
preliminary
Applications
4.5 Data Slicer Threshold Generation
The threshold of the data slicer can be generated in two ways, depending on
the signal coding scheme used. In case of a signal coding scheme without DC
content such as Manchester coding the threshold can be generated using an
external R-C integrator as shown in the following . The cut-off frequency of the
R-C integrator has to be lower than the lowest frequency appearing in the data
signal. In order to keep distortion low, the minimum value for R is 20kΩ.
R
C
data out
25
Pins:
19
20
Uthreshold
data
filter
data slicer
Data_slice1.wmf
Figure 4-5
Data Slicer Threshold Generation with External R-C Integrator
Another possibility for threshold generation is to use the peak detector in con-
nection with two resistors and one capacitor as shown in the following figure.
The component values are depending on the coding scheme and the protocol
used.
R
C
R
data out
25
Pins:
20
19
26
Uthreshold
peak detector
data slicer
data
filter
Data_slice2.wmf
Figure 4-6
Data Slicer Threshold Generation Utilising the Peak Detector
Wireless Components
4 - 7
Specification, January 2001
5
Reference
Contents of this Chapter
5.1 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.2 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.3 Test Board Layouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.4 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
TDA 5204 E1
preliminary
Reference
5.1 Electrical Data
5.1.1 Absolute Maximum Ratings
WARNING
The maximum ratings may not be exceeded under any circumstances, not even
momentarily and individually, as permanent damage to the IC will result.
Table 5-1 Absolute Maximum Ratings, Ambient temperature T
=-40°C ... + 85°C
AMB
#
Parameter
Symbol
Limit Values
Unit
Remarks
min
-0.3
max
5.5
1
2
3
4
5
Supply Voltage
Vs
Tj
V
°C
Junction Temperature
Storage Temperature
Thermal Resistance
ESD integrity, all pins
-40
-60
+125
+150
114
+1
Ts
°C
RthJA
VESD
K/W
kV
-1
HBM
according to
MIL STD
883D,
method
3015.7
Wireless Components
5 - 2
Specification, January 2001
TDA 5204 E1
preliminary
Reference
5.1.2 Operating Range
Within the operating range the IC operates as explained in the circuit descrip-
tion. The AC/DC characteristic limits are not guaranteed.
Supply voltage: VCC = 4.5V .. 5.5V
Table 5-2 Operating Range, Ambient temperature T
= -40°C ... + 85°C
AMB
#
Parameter
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
max
6.4
1
2
3
Supply Current
I
mA
nA
f
= 390MHz
S
RF
Power Down Current
Receiver Input Level
IPWDN
RFin
250
-13
-110
dBm
@ source impedance 50Ω,
BER 2E-3, average power
level, Manchester encoded
datarate 4kBit, 280kHz IF
Bandwidth, with AGC
4
Receive Frequency
fRF
385
406
MHz
This value is guaranteed by design.
Wireless Components
5 - 3
Specification, January 2001
TDA 5204 E1
preliminary
Reference
5.1.3 AC/DC Characteristics
AC/DC characteristics involve the spread of values guaranteed within the spec-
ified voltage and ambient temp. range. Typical characteristics are the median
of the production. The device performance parameters marked with
were
measured on an Infineon evaluation board as desdribed in Section 5.2. Cur-
rents flowing into the device are denoted as positive currents and vice versa.
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V
#
Parameter
Symbol
Limit Values
Unit Test Conditions
L
Item
min
typ
max
Supply
Supply Current
1
Supply current,
standby mode
IS PDWN
50
150
5.5
nA
Pin 27 (PDWN)
open or tied to 0 V
2
Supply current
I
4.8
mA
S
LNA
Signal Input LNI (PIN 3), high gain mode
1
Average Power Level
at BER = 2E-3
(Sensitivity)
RFin
-112
dBm Manchester
encoded datarate
4kBit, 280kHz IF
Bandwidth
2
3
4
Input impedance,
S
0.879 / -31 deg
11 LNA
f
= 390 MHz
RF
Input level @ 1dB C.P.
fRF=390 MHz
P1dB
-14
-10
dBm
LNA
Input 3rd order intercept
LNA
IIP3
LO
dBm fin = 390MHz
dBm
point f = 390 MHz
RF
5
LO signal feedthrough at
antenna port
-119
LNI
Signal Output LNO (PIN 6), high gain mode
1
2
Gain f = 390 MHz
RF
S
1.578 / 141.8deg
21 LNA
22 LNA
Output impedance,
S
0.8822 / -12.13deg
f
= 390 MHz
RF
3
4
Voltage Gain Antenna to
G
21
2
dB
AntMI
MI f = 390 MHz
RF
Noise Figure
NF
dB
excluding matching
LNA
network loss - see
Appendix
Signal Input LNI, low gain mode
1
Input impedance,
= 390 MHz
S
0.903 / -31.8deg
-7
11 LNA
f
RF
2
Input level @ 1dB C. P.
= 390 MHz
P1dB
dBm matched input
LNA
f
RF
Wireless Components
5 - 4
Specification, January 2001
TDA 5204 E1
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)
Parameter
Symbol
Limit Values
Unit Test Conditions
L
Item
min
= GND, low gain mode
typ
max
Signal Input LNI, V
THRES
Input 3rd order intercept
LNA
3
IIP3
-13
dBm fin = 390MHz
point f = 390 MHz
RF
Signal Output LNO, V
= GND, low gain mode
THRES
1
2
Gain f = 390 MHz
S
0.1834 / 144deg
RF
21 LNA
22 LNA
Output impedance,
S
0.897 / -12.4deg
f
= 390 MHz
RF
3
Voltage Gain Antenna to
MI f = 390 MHz
G
2
dB
AntMI
RF
Signal 3VOUT (PIN 24)
1
2
Output voltage
V
2.9
3
3.1
-50
V
3VOUT
Load current out
I
µA
3VOUT
Signal THRES (PIN 23)
1
2
3
4
Input Voltage range
LNA low gain mode
LNA high gain mode
Current in
V
V
V
0
0
V
V
V
see chapter 4.1
THRES
THRES
THRES
S
0.5
3.3
V
V
S
ITHRES_in
-5
nA
Signal TAGC (PIN 4)
1
Current out,
LNA low gain state
ITAGC_out
-2.5
0.5
-4.2
1.5
-5.5
4
µA
µA
RSSI > V
RSSI < V
THRES
2
Current in,
LNA high gain state
I
TAGC_in
THRES
MIXER
Signal Input MI/MIX (PINS 8/9)
1
Input impedance,
= 390 MHz
S
0.9413 / -13.1deg
-25
11 MIX
f
RF
Input 3rd order intercept
point
MIX
2
IIP3
dBm
Signal Output IFO (PIN 12)
1
2
Output impedance
Z
330
+21
Ω
IFO
Conversion Voltage Gain
G
dB
MIX
f
=390 MHz
RF
3
4
Noise Figure, SSB
(~DSB NF+3dB)
NF
13
46
dB
dB
MIX
RF to IF isolation
A
RF-IF
Wireless Components
5 - 5
Specification, January 2001
TDA 5204 E1
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)
Parameter
Symbol
Limit Values
Unit Test Conditions
L
Item
min
typ
max
LIMITER
Signal Input LIM/X (PINS 17/18)
1
2
3
4
Input Impedance
RSSI dynamic range
RSSI linearity
Z
264
60
330
70
396
80
Ω
dB
LIM
DR
RSSI
RSSI
LIM
LIN
dB
1
Operating frequency (3dB
points)
f
5
10.7
23
1.2
3.2
MHz
5
6
RSSI Level at Data Filter
Output SLP
RSSI
0.4
2.3
0.8
2.8
V
V
Limiter_in: 10uV
low
RSSI Level at Data Filter
Output SLP
RSSI
Limiter_in: 100mV
high
DATA FILTER
1
Max. useable bandwidth
BW
FILT
100
100
kHz
kHz
BB
SLICER
Signal Output DATA (PIN 25)
1
Max. useable bandwith
BW
BB
SLIC
2
3
4
5
LOW output voltage
HIGH output voltage
Output current
V
0
100
Vs-0.7
-1100
100
mV
V
SLIC_L
SLIC_H
V
Vs-1.2
-400
60
V -1
S
I
-800
80
µA
kΩ
high level drive
low level drive
SLIC_out
Output impedance
Rout
PEAK DETECTOR
Signal Output PDO (PIN 26)
1
2
Load current
I
-500
0
-950
700
-1200
2000
µA
nA
load
Leakage current
I
leakage
Wireless Components
5 - 6
Specification, January 2001
TDA 5204 E1
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)
Parameter
Symbol
Limit Values
Unit Test Conditions
L
Item
min
typ
max
CRYSTAL OSCILLATOR
Signals CRSTL1, CRISTL 2, (PINS 1/28)
1
Operating frequency
f
1
14
MHz fundamental mode,
series resonance
CRSTL
2
Negative Resistance
@ ~6MHz
-750
-450
21
Ω
Re{Z
Re{Z
}
}
1-28
3
4
5
Negatve Resitance
@ ~12MHz
Ω
1-28
Input Indutance
@ ~6MHz
uH
uH
Im{Z1-28}/
2π f
Input Inductance
@ ~12MHz
19
Im{Z1-28}/
2π f
PLL
Signal LF (PIN 15)
1
Tuning voltage relative to
V
0.5
1.05
2
V
TUNE
V
s
POWER DOWN Pin
Signal PDWN (PIN 27)
1
2
3
4
Powerdown Mode On
Powerdown Mode Off
Input bias current
PWDN
PWDN
0
0.8
V
V
ON
2.8
V
S
Off
IPWD
19
uA
ms
Power On Mode
Start-up Time until valid IF
signal is detected
T
1
SU
PLL DIVIDER
Signal CSEL (PIN 16)
1
2
f
range 6.xxMHz
range 12.xxMHz
V
1.4
0
4
V
V
or open
CRSTL
CRSTL
CSEL
CSEL
f
V
0.2
3
Bias current CSEL
I
-5
µA
CSEL tied to GND
CSEL
Measured only in lab.
Wireless Components
5 - 7
Specification, January 2001
TDA 5204 E1
preliminary
Reference
5.2 Test Circuit
The device performance parameters marked with in Section 5.1.3 were mea-
sured on an Infineon evaluation board. This evaluation board can be obtained
together with evaluation boards of the accompanying transmitter device
TDA51xx in an evaluation kit that may be ordered on the INFINEON RKE
Webpage www.infineon.com/rke
Test_circuit.wmf
Figure 5-1
Schematic of the Evaluation Board
Wireless Components
5 - 8
Specification, January 2001
TDA 5204 E1
preliminary
Reference
5.3 Test Board Layouts
Figure 5-2
Top Side of the Evaluation Board (TDA5210 Testboard is the same)
Figure 5-3
Bottom Side of the Evaluation Board
Wireless Components
5 - 9
Specification, January 2001
TDA 5204 E1
preliminary
Reference
Figure 5-4
Component Placement on the Evaluation Board
Wireless Components
5 - 10
Specification, January 2001
TDA 5204 E1
preliminary
Reference
5.4 Bill of Materials
The following components are necessary for evaluation of the TDA5204 at
390MHz without use of a Microchip HCS515 decoder.
Table 5-4 Bill of Materials
Ref
Value
100kΩ
100kΩ
820kΩ
120kΩ
180kΩ
10kΩ
Specification
0805, 5%
R1
R2
R3
R4
R5
R6
L1
0805, 5%
0805, 5%
0805, 5%
0805, 5%
0805, 5%
15nH
Toko, PTL2012-F15N0G
0805,COG, 2%
10pF a
L2
C1
C2
C3
C4
C5
C6
1.8pF
6.8pF
6.8pF
100pF
47nF
0805, COG, 0.1pF
0805, COG, 0.1pF
0805, COG, 0.1pF
0805, COG, 5%
1206, X7R, 10%
12nH b
100pF
33pF
Toko, PTL2012-F15N0G
C7
C8
0805, COG, 5%
0805, COG, 5%
0805, COG, 5%
0805, X7R, 10%
0805, X7R, 10%
0805, COG, 5%
0805, X7R, 10%
0805, COG, 5%
0805, X7R, 10%
0805, COG, 0.1pF
0805, COG, 2%
C9
100pF
10nF
C10
C11
C12
C13
C14
C15
C16
C17
10nF
220pF
47nF
470pF
47nF
12pF
12pF
Q2
(390MHz + 10.7MHz)/32
HC49/U, fundamental mode, C = 12pF,
L
12.521875 MHz: Jauch Q12.521875-S11-1252-12-10/20
F1
X2, X3
X1, X4, S1, S5
S4
SFE10.7MA5-A
142-0701-801
Murata
Johnson
2-pole pin connector
3-pole pin connector, or not equipped
Infineon
IC1
TDA 5204
a. / b. The coil is at the place of the capacity and vice versa.
Wireless Components
5 - 11
Specification, January 2001
TDA 5204 E1
preliminary
Reference
The following components are necessary in addition to the above mentioned
ones for evaluation of the TDA5204 in conjunction with a Microchip HCS515
decoder.
Table 5-5 Bill of Materials Addendum
Ref
Value
22kΩ
Specification
0805, 5%
0805, 5%
0805, 5%
0805, 5%
0805, 5%
1206, X7R, 10%
1206, X7R, 10%
Microchip
R21
R22
R23
R24
R25
C21
C22
IC2
T1
100kΩ
22kΩ
820kΩ
560kΩ
100nF
100nF
HCS515
BC 847B
LS T670-JL
Infineon
D1
Infineon
Wireless Components
5 - 12
Specification, January 2001
TDA 5204 E1
preliminary
List of Figures
List of Figures
Figure 2-1 P-TSSOP-28-1 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3-1 IC Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3-2 Main Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-1 LNA Automatic Gain Control Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-2 RSSI Level an Permissive AGC Threhold Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-3 Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-4 Determination of Series Capacitance Value for the Quartz Oscillator . . . . . . . . . . . . . .
Figure 4-5 Data Slicer Threshold Generation with External R-C Integrator . . . . . . . . . . . . . . . . . .
Figure 4-6 Data Slicer Threshold Generation Utilising the Peak Detector . . . . . . . . . . . . . . . . . . .
Figure 5-1 Schematic of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5-2 Top Side of the Evaluation Board (TDA5210 Testboard is the same) . . . . . . . . . . . . . .
Figure 5-3 Bottom Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-3
3-2
3-8
4-2
4-3
4-4
4-5
4-7
4-7
5-8
5-9
5-9
Figure 5-4 Component Placement on the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Wireless Components
List of Figures - 1
Specification, December 2000
TDA 5204 E1
preliminary
List of Tables
List of Tables
Table 3-1 Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-3
Table 3-3 PDWN Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Table 5-1 Absolute Maximum Ratings, Ambient temperature TAMB=-40°C ... + 85°C . . . . . . . . .
Table 5-2 Operating Range, Ambient temperature TAMB= -40°C ... + 85°C . . . . . . . . . . . . . . . . .
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V . . . . . . . . . . . . . . . . . . . . .
5-2
5-3
5-4
Table 5-4 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Table 5-5 Bill of Materials Addendum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Wireless Components
List of Tables - 1
Specification, December 2000
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