TLE6285_技术文档

LIN-Transceiver LDO

TLE 6285

Target Data Sheet

1

Overview

1.1

Features

• Single-wire transceiver, suitable for LIN protocol

• Transmission rate up to 20 kBaud

• Compatible to LIN specification

• Compatible to ISO 9141 functions

• Very low current consumption in sleep mode

• Control output for voltage regulator

• Short circuit proof to ground and battery

• Overtemperature protection

P-DSO-16-4

• Output voltage 5V, tolerance £ ± 2 %

• 150 mA output current capability

• Low-drop voltage

• Overtemperature protection

• Reverse polarity protection

• Short-circuit proof

• Adjustable reset threshold

• Wide temperature range

• Suitable for use in automotive electronics

Type

TLE 6285 G

Ordering Code

on request

Package

P-DSO-16-4

1.2

Description

The TLE 6285 is a single-wire transceiver with a LDO. It is chip by chip integrated circuit

in a P-DSO-16-4 package. It works as an interface between the protocol controller and

the physical bus. The TLE 6285 is especially suitable to drive the bus line in LIN systems

in automotive and industrial applications. Further it can be used in standard ISO9141

systems.

In order to reduce the current consumption the TLE 6285 offers a sleep operation mode.

In this mode a voltage regulator can be controlled in order to minimize the current

consumption of the whole application (VR in sleep mode <1µA!). The on-chip voltage

regulator (VR) is designed for this application but it is also possible to use an external

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voltage regulator. A wake-up caused by a message on the bus enables the voltage

regulator and sets the RxD output low until the device is switched to normal operation

mode. To achieve proper operation of the µC, the device supplies a reset signal. The

reset delay time is selected application specific by an external capacitor. The reset

threshold is adjustable.

®

The IC is based on the Smart Power Technology SPT which allows bipolar and CMOS

control circuitry in accordance with DMOS power devices existing on the same

monolithic circuit.

The TLE 6285 is designed to withstand the severe conditions of automotive applications.

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1.3

Pin Configuration (top view)

GND

INHI

1

2

3

4

5

16

15

14

13

GND

RD

RO

R_Th

V_CCO

INHO

RxD

V_BAT

BUS

TxD

12

6

7

11

10

ENLIN

GND

V_CCI

8

9

GND

P-DSO-16-4

Leadframe

1

16

15

14

13

12

11

10

9

GND

RD

2

INHI

RO

Chip:

3

4

5

6

7

R_Th

Voltage

Regulator

V_CCO

INHO

RxD

V_BAT

BUS

Chip:

TxD

V_CCI

Transceiver

ENLIN

GND

8

GND

P-DSO-16-4

Figure 1 Pinout

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1.4

Pin Definitions and Functions:

Pin No. Symbol Function

1,8,9,16 GND

Ground; place to cooling tabs to improve thermal behavior

2

INHI

Inhibit Voltage Regulator Input; TTL compatible, HIGH active

(HIGH switches the VR on); connect to V_BATif not needed

3

RO

Reset Output; open collector output connected to the output via

a resistor of 20kW

4

5

6

V_CCO

INHO

RxD

5V Output; connected to GND with 22µF capacitor, ESC<3W

Inhibit LIN Output; to control a voltage regulator

Receive Data Output; internal 30kW pull up to Vs, LOW in

dominat state

7

ENLIN

Enable LIN Input; integrated 30kW pull down, transceiver in

normal operation mode when HIGH

10

11

V_CCI

TxD

5V Supply Input; V_CCinput to supply the LIN transceiver

Transmit Data Input; internal 30kW pull up to Vs, LOW in

dominant state

12

13

BUS

V_BAT

LIN BUS Output/Input; internal 30kW pull up to Vs, LOW in

dominant state

Battery Supply Input; a reverse current protection diode is

required, block GND with 100nF ceramic capacitor and 22µF

capacitor

14

15

R_Th

RD

Reset Threshold; internal defined typical 4.6V, adjustable down

to 3.5V according to the voltage level on this pin; connect to GND

if not needed

Reset delay; connected to ground via external delay capacitor

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1.5

Functional Block Diagram

13

5

V_BAT

INHO

10

V_CCI

Mode

7

ENLIN

Output

Stage

30 k

9

Control

Driver

30 k

9

12

Bus

Temp.-

Protection

11

TxD

Receiver

6

RxD

TLE 6259 G

5

GND

TLE 4299

13

I

V_Bat

4

Q

V

CCO

Band-

Gap-

Reference

Current

and

Saturation

Control

R_SO

Inhibit

Control

R_RO

INHI

INH

2

SO

SI

Reference

3

RORO

Reset

Control

R

14

RADJ

Th

1,8,9,16

GND

15

D

AEB03104

RD

Figure 2 Block Diagram

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2

Circuit Description

The TLE 6285 is a single-wire transceiver combined with a LDO. It is a chip by chip

integrated circuit in a P-DSO-16-4 package. It works as an interface between the

protocol controller and the physical bus. The TLE 6285 is especially suitable to drive the

bus line in LIN systems in automotive and industrial applications. Further it can be used

in standard ISO9141 systems. The on-chip voltage regulator with watchdog is designed

for sleep mode applications but it is also possible to use an external voltage regulator.

Start Up

Power Up

Normal Mode

ENLIN INHO V_CC

high high

ON

ENLIN high

low

ENLIN

Stand-By

INHO

ENLIN

low high

RxD V_CC

low¹⁾

ON

3)

ENLIN

(V_CC

high

ON)

high

Wake Up

t > t_WAKE

Sleep Mode

ENLIN INHO V_CC

low floating OFF²⁾

1)

after wake-up via bus

2)

3)

ON when INHO not connected to INHI

after start up

Figure 3 Operation Mode State Diagram

2.1 Operation Modes

In order to reduce the current consumption the TLE 6285 offers a sleep operation mode.

This mode is selected by switching the enable input EN low (see figure 3, state

diagram). In the sleep mode a voltage regulator can be controlled via the INHO output

in order to minimize the current consumption of the whole application. A wake-up caused

by a message on the communication bus automatically enables the voltage regulator by

switching the INHO output high. In parallel the wake-up is indicated by setting the RxD

output low. When entering the normal mode this wake-up flag is reset and the RxD

output is released to transmit the bus data.

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In case the voltage regulator control input is not connected to INH output or the

microcontroller is active respectively, the TLE6285 can be set in normal operation mode

without a wake-up via the communication bus.

2.2

LIN Transceiver

The LIN Transceiver has already a pull up resistor of 30kW as termination implemented.

There is also a diode in this path, to protect the circuit from feedback of voltages from

the bus line to the power supply. To configure the TLE 6285 as a master node, an

additional external termination resistor of 1kW is required. To avoid reverse currents from

the bus line into the battery supply line in case of an unpowered node, it is also

recommended to place a diode in series to the external pull up. For small systems (low

bus capacitance) the EMC performance of the system is supported by an additional

capacitor of at least 1nF in the master node (see figure 6, application circuit).

An capacitor of 10µF at the supply voltage input V_Sbuffers the input voltage. In

combination with the required reverse polarity diode this prevents the device from

detecting power down conditions in case of negative transients on the supply line.

2.3

Input Capacitor

The input capacitor C_Iis necessary for compensation of line influences. Using a resistor

of approx. 1 W in series with C_I, the oscillating circuit consisting of input inductivity and

input capacitance can be damped. The output capacitor is necessary for the stability of

the regulating circuit. Stability is guaranteed at values ³ 22 mF and an ESR of £ 5 W

within the operating temperature range. For small tolerances of the reset delay the

spread of the capacitance of the delay capacitor and its temperature coefficient should

be noted.

2.4

Voltage regulator

The 6285 incorporates a PNP based very low drop linear voltage regular. It regulates the

output voltage to V_CC= 5 V for an input voltage range of 5.5 V £ V_I£ 45 V. The control

circuit protects the device against potential caused by damages overcurrent and

overtemperature.

The internal control circuit achieves a 5 V output voltage with a tolerance of ± 2% in the

temperature range of T_j= – 40 to 150 °C.

The device includes a power on reset and an under voltage reset function with adjustable

reset delay time and adjustable reset switching threshold as well as a sense control/early

warning function. The device includes an inhibit function to disable it when the ECU is

not used for example while the motor is off.

The reset logic compares the output voltage V_CCto an internal threshold. If the output

voltage drops below this level, the external reset delay capacitor C_Dis discharged. When

V_Dis lower than V_LD, the reset output RO is switched Low. If the output voltage drop is

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very short, the V_LDlevel is not reached and no reset-signal is asserted. This feature

avoids resets at short negative spikes at the output voltage e.g. caused by load changes.

As soon as the output voltage is more positive than the reset threshold, the delay

capacitor is charged with constant current. When the voltage reaches V_UDthe reset

output RO is set High again.

The reset threshold is either the internal defined V_RTvoltage (typical 4.6 V) or can be

lowered by a voltage level at the R_Thinput down to 3.5 V. The reset delay time and the

reset reaction time are defined by the external capacitor C_D. The reset function is active

down to V_I= 1 V.

The device is capable to supply 150 mA. For protection at high input voltage above 25 V,

the output current is reduced (SOA protection).

2.5

Reset

The power on reset feature is necessary for a defined start of the microprocessor when

switching on the application. For the reset delay time after the output voltage of the

regulator is above the reset threshold, the reset signal is set High again. The reset delay

time is defined by the reset delay capacitor C_Dat pin RD (refer to figure 4 and 5).

The under-voltage reset circuitry supervises the output voltage. In case V_Qdecreases

below the reset threshold the reset output is set LOW after the reset reaction time. The

reset LOW signal is generated down to an output voltage V_CCto 1 V. Both the reset

reaction time and the reset delay time is defined by the capacitor value.

The power on reset delay time is defined by the charging time of an external delay

capacitor C_D.

C_D= (t_d´ I_D) / DV

[1]

With

C_Dreset delay capacitor

t_d

reset delay time

DV = V_UD,

typical 1.8 V for power up reset

DV = V_UD– V_LDtypical 1.35 V for undervoltage reset

charge current typical 6.5 mA

For a delay capacitor C_D=100 nF the typical power on reset delay time is 28 ms.

I_D

The reset reaction time t_RRis the time it takes the voltage regulator to set reset output

LOW after the output voltage has dropped below the reset threshold. It is typically 1 ms

for delay capacitor of 100 nF. For other values for C_Dthe reaction time can be estimated

using the following equation:

t

_RR= 10 ns / nF ´ C_D

[2]

The reset output is an open collector output with a pull-up resistor of typical 20 kW to Q.

An external pull-up can be added with a resistor value of at least 5.6 kW.

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In addition the reset switching threshold can be adjusted by an external voltage divider.

The feature is useful for microprocessors which guarantee safe operation down to

voltages below the internally set reset threshold of 4.65 V typical.

If the internal used reset threshold of typical 4.65 V is used, the pin RADJ has to be

connected to GND.

If a lower reset threshold is required by the system, a voltage divider defines the reset

threshold V_Rthbetween 3.5 V and 4.60 V:

V

_Rth= V_{RADJ TH}´ (R₁+ R₂) / R₂

[3]

V_{RADJ TH}is typical 1.36 V.

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3

Electrical Characteristics

Absolute Maximum Ratings

3.1

Parameter

Symbol Limit Values Unit

Remarks

min.

max.

Voltages

Supply voltage

V_CC

V_S

V_bus

V_I

-0.3

-20

-0.3

6

V

Battery supply voltage

Bus input voltage

Logic voltages at

EN, TxD, RxD

40

32

40

t < 1 s

0 V < V_CC< 5.5 V

V_CC

+ 0.3

Input voltages at INH

V_INH

-0.3

V_S

V

+ 0.3

Output current at INH

Reset output voltage

Reset delay voltage

Output voltage Vcc

INHIBIT voltage

Reset Threshold voltage

Reset Threshold current

Electrostatic discharge

voltage at Vs, Bus

I_INH

V_R

1

7

45

7

10

4

mA

V

mA

kV

– 0.3

– 40

– 0.3

– 10

-4

V_D

V_Q

V_INH

V_Th

I_Th

V_ESD

human body model

(100 pF via 1.5 kW)

Electrostatic discharge

voltage

V_ESD

-2

2

kV

human body model

(100 pF via 1.5 kW)

Temperatures

Junction temperature

T_j

-40

150

°C

Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause

irreversible damage to the integrated circuit.

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3.2

Operating Range

Parameter

Symbol Limit Values Unit

Remarks

min.

4.5

6

max.

5.5

20

Supply voltage

Battery Supply Voltage

Junction temperature

V_CC

V_S

T_j

V

°C

–

– 40

150

Thermal Shutdown (junction temperature)

Thermal shutdown temp.

Thermal shutdown hyst.

T_jSD

DT

150

–

170

10

190

–

°C

K

Thermal Resistances

–

Junction ambient LIN

Junction ambient Vreg

R_thj-a

–

185

70

K/W

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3.3

Electrical Characteristics

4.5 V < V_CC< 5.5 V; 6.0 V < V_S< 20 V; R_L= 1 kW; V_EN> V_EN,ON; -40 °C < T_j< 125 °C; all voltages with

respect to ground; positive current flowing into pin; unless otherwise specified.

Parameter

Symbol

Limit Values

Unit Remarks

min. typ. max.

Current Consumption LIN

recessive state;

Current consumption

I_CC

I_S

0.5

0.7

20

1.5

1.0

2.0

1.5

30

mA

V

_TxD= V_CC

recessive state;

_TxD= V_CC

Current consumption

mA

µA

V

dominant state;

_TxD= 0 V

I_CC

I_S

V

dominant state;

_TxD= 0 V

V

sleep mode;

I_S

T_j= 25 °C

sleep mode

I_S

20

40

µA

Current Consumption Vreg

Inhibit ON;

Current consumption;

I_q

–

65

170

0.7

–

105

100

500

2

mA

I_Q£ 1 mA, T_j< 85 °C

I_q= I_I– I_Q

Inhibit ON;

Current consumption;

I_Q£ 1 mA, T_j= 25 °C

I_q= I_I– I_Q

Inhibit ON;

Current consumption;

I_Q= 10 mA

I_q= I_I– I_Q

Inhibit ON;

Current consumption;

I_q= I_I– I_Q

I_Q= 50 mA

V_INHI= 0 V;

T_j= 25 °C

Current consumption;

1

I_q= I_I– I_Q

Receiver Output R´D

V_RD= 0.8 x V_CC

V_RD= 0.2 x V_CC

,

HIGH level output current

LOW level output current

I_RD,H

I_RD,L

-0.7 -0.4 mA

0.7 mA

0.4

12

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3.3

Electrical Characteristics (cont’d)

4.5 V < V_CC< 5.5 V; 6.0 V < V_S< 20 V; R_L= 1 kW; V_EN> V_EN,ON; -40 °C < T_j< 125 °C; all voltages with

respect to ground; positive current flowing into pin; unless otherwise specified.

Parameter

Symbol

Limit Values

Unit Remarks

min. typ. max.

Bus receiver

-8 V < V_bus< V_bus,dom

Receiver threshold voltage, V_bus,rd0.44 0.48

V

recessive to dominant edge

x V_Sx V_S

0.52 0.56

x V_Sx V_S

V_bus,rec< V_bus< 20 V

Receiver threshold voltage, V_bus,dr

dominant to recessive edge

V_bus,hys

=

Receiver hysteresis

V_bus,hys0.02 0.04 0.06 mV

x V_Sx V_Sx V_S

V

_bus,rec- V_bus,dom

wake-up threshold voltage

V_wake

0.40 0.55 0.70

V

x V_Sx V_Sx V_S

Transmission Input T´D

recessive state

HIGH level input voltage

threshold

V_TD,H

2.9

0.7 x V

V_CC

TxD input hysteresis

LOW level input voltage

threshold

V_TD,hys300 600

mV

V

dominant state

V_TxD< 0.3 Vcc

V_TD,L

0.3 x 2.1

V_CC

TxD pull up current

I_TD

-150 -110 -80

µA

Bus transmitter

V_TxD= V_CC

Bus recessive output voltage V_bus,rec0.9 x

V_S

V

V_S

V_TxD= 0 V;

Bus dominant output voltage V_bus,dom

0

1.5

V

V_bus,short= 13.5 V

Bus short circuit current

Leakage current

I_bus,sc

I_bus,lk

40

85

125

mA

V_CC= 0 V, V_S= 0 V,

V_bus= -8 V, T_j< 85 °C

-350 -100

V_CC= 0 V, V_S= 0 V,

V_bus= 20 V, T_j< 85 °C

5

20

47

mA

kW

Bus pull up resistance

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R_bus

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30

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3.3

Electrical Characteristics (cont’d)

4.5 V < V_CC< 5.5 V; 6.0 V < V_S< 20 V; R_L= 1 kW; V_EN> V_EN,ON; -40 °C < T_j< 125 °C; all voltages with

respect to ground; positive current flowing into pin; unless otherwise specified.

Parameter

Symbol

Limit Values

Unit Remarks

min. typ. max.

Enable input (pin ENLIN)

normal mode

HIGH level input voltage

threshold

V_EN,on

2.8

0.7 x V

V_CC

low power mode

LOW level input voltage

threshold

V_EN,off0.3 x 2.2

V

V_CC

EN input hysteresis

V_EN,hys300 600

mV

EN pull down resistance

R_EN

15

30

60

kW

Inhibit output (pin INHO)

I_INHO= - 0.15 mA

HIGH level drop voltage

DV_INH

0.5

1.0

5.0

V

DV_INH= V_S- V_INH

sleep mode;

Leakage current

I_INH,lk

- 5.0

µA

V_INHO= 0 V

Vcc Output (pin Vcco)

1 mA £ I_Q£ 100 mA;

Output voltage

V_Q

4.90 5.00 5.10

4.85 5.00 5.15

V

6 V £ V_I£ 16 V

I_Q£ 150 mA;

Output voltage

V

6 V £ V_I£ 16 V

–

Current limit

I_Q

250 400

500

mA

I_Q= 100 mA¹⁾

Drop voltage

Load regulation

Line regulation

V_dr

DV_Q

–

0.22 0.5

V

mV

I_Q= 1 mA to 100 mA

5

30

25

V_I= 6 V to 28 V;

10

I_Q= 1 mA

f_r= 100 Hz; V_r= 1 V_SS

;

Power Supply Ripple

rejection

PSRR

–

66

–

dB

I_Q= 100 mA

5 mA £ I_Q£ 150 mA;

Output voltage

V_Q

4.90 5.00 5.10

V

6 V £ V_I£ 28 V

6 V £ V_I£ 32 V;

Output voltage

V

I_Q= 100 mA;

T_j= 100 °C

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3.3

Electrical Characteristics (cont’d)

4.5 V < V_CC< 5.5 V; 6.0 V < V_S< 20 V; R_L= 1 kW; V_EN> V_EN,ON; -40 °C < T_j< 125 °C; all voltages with

respect to ground; positive current flowing into pin; unless otherwise specified.

Parameter

Symbol

Limit Values

Unit Remarks

min. typ. max.

Reset Generator (pins RO,RD)

–

Switching threshold

Reset pull up

Reset low voltage

V_rt

R_RO

V_R

4.50 4.60 4.80

V

kW

V

–

10

–

20

40

V_Q< 4.5 V; internal

R_RO; I_R= 1 mA

0.17 0.40

Pull up resistor to Q

–

External reset pull up

Delay switching threshold

Switching threshold

Reset delay low voltage

Charge current

Reset delay time

Reset reaction time

Reset adjust switching

threshold

V_{R ext}

V_DT

V_ST

V_D

I_ch

t_d

5.6

1.5

–

kW

V

1.85 2.2

–

0.40 0.50 0.60

–

4.0

17

0.5

V_Q< V_RT

V_D= 1 V

C_D= 100 nF

V_Q> 3.5 V

–

0.1

12.0 mA

35

3.0

V

8.0

28

1.2

ms

V

t_rr

V_{RADJ TH}1.26 1.36 1.44

Inhibit Input (pin INHI)

V_Qoff

Inhibit OFF voltage range

V_INH

–

0.8

V

OFF

V_Qon

Inhibit ON voltage range

High input current

Low input current

V_{INH ON}3.5

–

3

0.5

–

5

2

V

mA

V_INHI= 5 V

V_INHI= 0 V

I_{INH ON}

–

I_{INH OFF}

Note: The reset output is low within

the range V_Q= 1 V to V_Q,rt

¹⁾Drop voltage = V_i– V_Q(measured

when the output voltage has

dropped 100 mV

from the nominal value obtained at

6 V input)

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3.3

Electrical Characteristics (cont’d)

4.5 V < V_CC< 5.5 V; 6.0 V < V_S< 20 V; R_L= 1 kW; V_EN> V_EN,ON; -40 °C < T_j< 125 °C; all voltages with

respect to ground; positive current flowing into pin; unless otherwise specified.

Parameter

Symbol

Limit Values

Unit Remarks

min. typ. max.

Dynamic Transceiver Characteristics

80% > V_bus> 20%

falling edge slew rate

S_bus(L)

-3

-2.0 -1

V/µs

C_bus= 3.3 nF;

T_ambient< 85 °C;

V

_CC= 5 V; V_S= 13.5 V

20% < V_bus< 80%

rising edge slew rate

S_bus(H)

t_d(L),TR

1

2

1.5

5

3

V/µs

µs

C_bus= 3.3 nF;

V

_CC= 5 V; V_S= 13.5 V

C_bus= 3.3nF;

Propagation delay

TxD-to-RxD LOW (recessive

to dominant)

10

V

_CC= 5 V; V_S= 13.5 V

C_RxD= 20 pF

C_bus= 3.3 nF;

Propagation delay

TxD-to-RxD HIGH (dominant

to recessive)

t_d(H),TR

2

5

10

µs

V

_CC= 5 V; V_S= 13.5 V

C_RxD= 20 nF

V_CC= 5 V

Propagation delay

TxD LOW to bus

Propagation delay

TxD HIGH to bus

t_d(L),T

t_d(H),T

t_d(L),R

t_d(H),R

t_sym,R

1

4

µs

V_CC= 5 V

V_CC= 5V;

Propagation delay

C_RxD= 20pF

bus dominant to RxD LOW

V_CC= 5 V;

Propagation delay

C_RxD= 20 pF

bus recessive to RxD HIGH

t_sym,R= t_d(L),R- t_d(H),R

t_sym,T= t_d(L),T- t_d(H),T

Receiver delay symmetry

Transmitter delay symmetry t_sym,T

Wake-up delay time

-2

30

2

200

µs

t_wake

100

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4

Diagrams

V

I

<

t_rr

t

V_Q

V_{Q, rt}

I_{D, ch}

d

V

t

=

V_D

C_D

V_DU

V_DRL

t_rd

t_rr

V_RO

Power-ON

Reset

Over-

temperature

Voltage Drop Under-

at Input voltage

Secondary

Spike

Load

Bounce

AET03066

Figure 4

Time Response, Watchdog with High-Frequency Clock

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Target Data TLE 6285

Typical Performance Characteristics

Output Voltage V_Qversus

Temperature T_j

Output Voltage V_Qversus

Input Voltage V_I

AED01671

AED01808

5.2

12

V_Q

V

5.1

10

V_Ι= 13.5 V

5.0

8

4.9

4.8

4.7

4.6

6

R_L= 50

Ω

4

2

0

-40

0

40

80

120 C 160

0

2

4

6

8

V 10

T_j

V_Ι

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Target Data TLE 6285

Charge Current I_chversus

Temperature T_j

Drop Voltage V_drversus

Output Current I_Q

AED03108

AED02929

12

400

mV

µA

10

I_D

V_DR

125 ˚C

300

250

200

150

100

50

8

6

4

2

0

25 ˚C

V

= 13.5 V

I

V_D= 1 V

0

-40

0

40

80

120 ˚C 160

0

50

100

150 mA 200

T_j

I_Q

Switching Voltage V_dtand V_stversus

Temperature T_j

Reset Adjust Switching Threshold

V_RADJTHversus Temperature T_j

AED03109

AED01804

1.5

3.2

V

V_D

V

V_RADJTH

2.8

1.4

1.3

1.2

1.1

1.0

0.9

V_Ι= 13.5 V

2.4

2.0

1.6

1.2

0.8

0.4

0

V_UD

V

LD

-40

0

40

80

120 ˚C 160

-40

0

40

80

120 C 160

T_j

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Target Data TLE 6285

Sense Threshold V_si

Output Current Limit I_Qversus

versus Temperature T_j

Input Voltage V_I

AED02933

AED03110

350

1.6

Ι _Q

mA

V

V_Si

300

1.5

Sense Output High

Sense Output Low

250

200

150

100

50

1.4

1.3

1.2

1.1

1.0

T_j= 25 C

T_j= 125 C

0

-40

0

40

80

120 ˚C 160

0

10

20

30

40

V 50

T_j

V_Ι

Current Consumption I_qversus

Output Current I_Q

Current Consumption I_qversus

Output Current I_Q

AED02931

AED02932

1.0

mA

5

mA

I_q

0.8

0.6

0.4

0.2

0

4

3

2

1

0

10

20

30

40

mA 60

0

50

100

150 mA 200

I_Q

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Target Data TLE 6285

5

Application

V_batLIN bus

master node

3

7

RO

V_BAT

13

ENLIN

22 µF

6

11

10

RxD

TxD

V_CCI

µP

100 nF

1 k

12 Bus

5

INHO

GND

TLE 6285 G

100 nF

5V

4

V_CCO

2

INHI

RD

R₁

R₂

22 µF

R_Th

1,8,9,16

15

14

GND

C_D

100 nF

ECU 1

slave node

3

7

RO

V_BAT

13

ENLIN

22 µF

6

RxD

TxD

V_CCI

µP

100 nF

12

5

11

10

Bus

INHO

GND

TLE 6285 G

100 nF

5V

4

V_CCO

2

INHI

RD

R₁

R₂

22 µF

R_Th

1,8,9,16

15

14

GND

C_D

100 nF

ECU X

Figure 5

Application Circuit

Version 1.02

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2002-05-15

Target Data TLE 6285

6

Package Outlines

P-DSO-16-4

(Plastic Dual Small Outline Package)

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our

Data Book “Package Information”.

SMD = Surface Mounted Device

Dimensions in mm

Version 1.02

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Target Data TLE 6285

Edition 1999-10-12

Published by Infineon Technologies AG

St.-Martin-Strasse 53

D-81541 München

Attention please!

The information herein is given to describe certain components and

shall not be considered as warranted characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited

to warranties of non-infringement, regarding circuits, descriptions

and charts stated herein.

Infineon Technologies is an approved CECC manufacturer.

Information

For further information on technology, delivery terms and condi-

tions and prices please contact your nearest Infineon Technologies

Office in Germany or our Infineon Technologies Representatives

worldwide (see address list).

Warnings

Due to technical requirements components may contain dangerous

substances. For information on the types in question please contact

your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-sup-

port devices or systems with the express written approval of Infine-

on Technologies, if a failure of such components can reasonably be

expected to cause the failure of that life-support device or system,

or to affect the safety or effectiveness of that device or system. Life

support devices or systems are intended to be implanted in the hu-

man body, or to support and/or maintain and sustain and/or protect

human life. If they fail, it is reasonable to assume that the health of

the user or other persons may be endangered.

Version 1.02

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2002-05-15


型号：	TLE6285
厂家：	Infineon
描述：	LIN-Transceiver LDO LIN收发器LDO
文件：	总23页 (文件大小：649K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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