FAGD1651132BA [INTEL]

Support Circuit, 1-Func, PQFP32, 5 X 5 MM, 1.40 MM HEIGHT, HEAT SINK, PLASTIC, TQFP-32;
FAGD1651132BA
型号: FAGD1651132BA
厂家: INTEL    INTEL
描述:

Support Circuit, 1-Func, PQFP32, 5 X 5 MM, 1.40 MM HEIGHT, HEAT SINK, PLASTIC, TQFP-32

ATM 异步传输模式 电信 电信集成电路
文件: 总5页 (文件大小:97K)
中文:  中文翻译
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2.5 Gbit/s  
Limiting  
Amplifier  
GD16511  
an Intel company  
Preliminary  
General Information  
Features  
l
GD16511 is a wide bandwidth, limiting  
amplifier designed for:  
The amplifier allows for input signals  
from 1 mVPP to above 1 VPP  
30 dB gain (typ.).  
.
u
l
SDH STM-16  
SONET OC-48  
optical communication systems.  
Large dynamic range.  
u
GD16511 is manufactured in a Silicon  
Process and uses a single positive or  
negative 5 V supply with a typical power  
dissipation of 0.13 W.  
l
3 dB bandwidth above 3 GHz.  
l
It features a linear gain of at least 28 dB  
and a 3 dB bandwidth larger than 3 GHz,  
measured in a 50 W system.  
Differential loop through inputs.  
l
GD16511 is delivered in a TQFP 32 Lead  
5 × 5 mm plastic package with exposed  
heat slug for enhanced VEE connection.  
Differential CML outputs.  
l
GD16511 has been measured together  
with a 2.5 Gbit/s Clock and Data Re-  
covery (CDR) circuit, and error free  
operation has been measured down to  
below 3 mVPP input signal (10–9 BER).  
Operates up to 3.5 Gbit/s.  
l
Low power consumption: 0.13 W typ.  
l
Small 5 × 5 mm plastic package.  
Applications  
l
Limiting amplifier for optical communi-  
cation systems:  
SDH STM-16  
SONET OC-48  
DIREFN  
Limiter  
DIN  
DI  
OUT  
l
l
Pulse shaper.  
OUTN  
Datacom up to 3.125 Gbit/s.  
DIREF  
VDD  
VEE  
Data Sheet Rev.: 5  
Application Information  
Inputs  
Outputs  
The inputs of GD16511 may be either AC  
or DC coupled. In either case input termi-  
nation is made through the pins DIREF /  
DIREFN which must be terminated  
through the external resistors (R1 and  
R2) and de-coupled to ground with ca-  
pacitors (C1 and C2), as shown in the  
Figure 1 below.  
The outputs of GD16511 are open collec-  
tors (CML) and must be terminated to  
VDD via an external resistor matching  
the external transmission line imped-  
ance. Best performance is typically  
achieved using a 50 W termination resis-  
tor (please refer to Figure 3 below), how-  
ever the voltage gain may be adjusted by  
using a different termination resistor (and  
characteristic transmission line imped-  
ance).  
If the inputs are AC coupled GD16511  
features an internal offset cancelling DC  
feedback. Because of the voltage divi-  
sion between the capacitors C3 and C1,  
(which must have the same value) on DI  
/ DIREF and C4 and C2 (which also must  
have the same value) on DIN / DIREFN,  
the lower cut-off frequency is in the kHz  
range. Notice that the offset cancellation  
will only work if DIREF and DIREFN are  
not shorted together, and if the inputs are  
AC coupled, as shown in the Figure 1  
below.  
50W  
50W  
OUT  
VOUT  
OUTN  
VOUTN  
VOUT  
VOUTN  
R1  
R2  
C1 DIREFN  
Vdiff = VOUT - VOUTN  
C3  
C4  
C2  
DIN  
DI  
Data  
from  
Line  
V
OUT +VOUTN  
VCM  
=
2
DIREF  
Figure 3. DC Coupled Output with 50 W  
Termination  
VDI  
VDIN  
AC coupling of the outputs are possible  
by using a resistor of 300 W to VDD for  
the DC return path and AC couple e.g.  
a transmission line terminated with its  
characteristic impedance, see Figure 4  
below.  
Vdiff = VDI - VDIN  
V
DI +VDIN  
VCM  
=
2
Figure 1. AC Coupled Input  
VDD VDD  
300  
300  
OUT  
50  
50  
50  
50  
OUTN  
VTT  
R1  
R2  
DIREFN  
DIN  
Data  
from  
Line  
DI  
Figure 4. AC Coupled Output  
DIREF  
Figure 2. DC Coupling for Large Input  
Ampltude  
Data Sheet Rev.: 5  
GD16511  
Page 2 of 5  
 
Pin List  
Mnemonic:  
DI, DIN  
Pin No.:  
6, 4  
Pin Type:  
Anl. Input  
Anl. Input  
CML  
Description:  
Data inputs. If AC coupled the inputs are self biased.  
Loop through termination pins for data inputs.  
CML output pins. The outputs require an external path to VDD.  
Ground pins.  
DIREF, DIREFN  
OUT, OUTN  
VDD  
7, 3  
21, 20  
2, 5, 8, 9, 19, 22,  
27, 30, 32  
PWR  
VEE  
1, 10, 11, 12, 13,  
14, 15, 16, 17, 18,  
23, 24, 25, 26, 28,  
29, 31  
PWR  
Supply pins.  
Heat sink  
Package backside  
Connected to VEE.  
Package Pinout  
1
2
3
4
5
6
7
8
24  
VEE  
VDD  
VEE  
23  
VEE  
22  
DIREFN  
DIN  
VDD  
21  
OUT  
20  
VDD  
DI  
OUTN  
19  
VDD  
18  
DIREF  
VDD  
VEE  
17  
VEE  
Figure 5. Package Pinout, 32 pin - Top View  
Data Sheet Rev.: 5  
GD16511  
Page 3 of 5  
Maximum Ratings  
These are the limits beyond which the component may be damaged.  
All voltages in table is referred to VDD.  
All currents are defined positive out of the pin.  
Symbol:  
VEE  
Characteristic:  
Conditions:  
MIN.:  
-6  
TYP.:  
MAX.:  
0
UNIT:  
V
Negative Supply  
VCMLT  
CML Resistor Termination Voltage  
CML Output Voltage  
CML Output Current  
Junction Temperature  
Storage Temperature  
VEE  
VEE  
-10  
-55  
-65  
0
V
V
O CML  
0
V
I
O CML  
Note 1  
+1  
mA  
oC  
TJ  
+125  
+150  
TS  
oC  
Note 1: Nominal supply voltages.  
Electrical Characteristics  
TCASE = -40 °C to 85 °C.  
Specifications are tested at 85 °C. Performance at lower temperatures has been shown to be better in engineering samples.  
All voltages in table are referred to VDD  
All currents are defined positive out of pin.  
Symbol:  
VEE  
Characteristic:  
Condiions:  
MIN.:  
TYP.:  
-5.0  
25  
MAX.: UNIT:  
Negative supply voltage  
Supply current  
-5.5  
-4.5  
V
mA  
V
IEE  
V
diff DI,DIN  
CM DI,DIN  
Input voltage for DI, DIN  
Note 4, 5  
1.0  
V
Common mode range for DC coupled data  
input  
DC coupled inputs  
Note 6  
-2.0  
-1.3  
0.4  
-0.2  
V
V DI,DIN  
V OUT,OUTN  
VLO OUT,OUTN  
tr tf,  
Input offset voltage  
1
mV  
V
Output voltage swing  
Note 1, 2, 5  
Note 1, 2  
0.3  
Minimum voltage on outputs  
Output rise and fall times (10 - 90%)  
Output duty cycle variation  
Small signal gain  
-1.2  
V
100  
55  
ps  
D OUT,OUTN  
G
45  
28  
50  
32  
%
Note 1, 3  
Note 1, 3  
35  
dB  
GHz  
f 3dB  
3 dB bandwidth  
3.0  
3.5  
Note 1: Output externally terminated with 50 W to VDD.  
Note 2: Limiting operation.  
Note 3: Linear operation.  
Note 4: Single ended or differential voltage. Defined as VDI - VDIN , see Figure 1.  
Note 5: Defined as VOUT - VOUTN , see Figure 2.  
V
DI +V  
Note 6: Defined as  
DIN, see Figure 1.  
2
Data Sheet Rev.: 5  
GD16511  
Page 4 of 5  
Package Outline  
Figure 6. Package 32 pin  
Ordering Information  
Please order as specified below:  
Product Name:  
Intel Order Number:  
Package Type:  
Case Temperature Range:  
GD16511-32BA  
FAGD1651132BA  
MM#: 836058  
32pin L TQFP  
-40...85 °C  
GD16511, Data Sheet Rev.: 5 - Date: 24 July 2001  
an Intel company  
Mileparken 22, DK-2740 Skovlunde  
Denmark  
Phone : +45 7010 1062  
Distributor:  
The information herein is assumed to be  
reliable. GIGA assumes no responsibility  
for the use of this information, and all such  
information shall be at the users own risk.  
Prices and specifications are subject to  
change without notice. No patent rights or  
licenses to any of the circuits described  
herein are implied or granted to any third  
party. GIGA does not authorise or warrant  
any GIGA Product for use in life support  
devices and/or systems.  
Fax : +45 7010 1063  
E-mail : sales@giga.dk  
Web site : http://www.intel.com/ixa  
Copyright © 2001 GIGA ApS  
An Intel company  
All rights reserved  
Please check our Internet web site  
for latest version of this data sheet.  

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