HA-2540_03 [INTERSIL]
400MHz, Fast Settling Operational Amplifier; 400MHz的，快速建立运算放大器
| 型号： | HA-2540_03 |
| 厂家： | 
Intersil |
| 描述： | 400MHz, Fast Settling Operational Amplifier |
| 文件： | 总8页 (文件大小：549K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HA-2540
®
Data Sheet
J uly 2003
FN2897.5
400MHz, Fas t Settling Operational
Amplifier
Features
• Very High Slew Rate . . . . . . . . . . . . . . . . . . . . . . 400V/µs
The Intersil HA-2540 is a wideband, very high slew rate,
monolithic operational amplifier featuring superior speed and
bandwidth characteristics. Bipolar construction coupled with
dielectric isolation allows this truly differential device to
deliver outstanding performance in circuits where closed
loop gain is 10 or greater. Additionally, the HA-2540 has a
drive capability of ±10V into a 1kΩ load. Other desirable
characteristics include low input voltage noise, low offset
voltage, and fast settling time.
• Fast Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . . 140ns
• Wide Gain Bandwidth (A ≥ 10). . . . . . . . . . . . . . 400MHz
V
• Power Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . 6MHz
• Low Offset Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 8mV
• Input Voltage Noise . . . . . . . . . . . . . . . . . . . . . . . 6nV/√Hz
• Output Voltage Swing . . . . . . . . . . . . . . . . . . . . . . . ±10V
• Monolithic Bipolar Construction
A 400V/µs slew rate ensures high performance in video and
pulse amplification circuits, while the 400MHz gain-
bandwidth product is ideally suited for wideband signal
amplification. A settling time of 140ns also makes the
HA-2540 an excellent selection for high speed Data
Acquisition Systems.
Applications
• Pulse and Video Amplifiers
• Wideband Amplifiers
• High Speed Sample-Hold Circuits
• Fast, Precise D/A Converters
Refer to Application Note AN541 and Application Note
AN556 for more information on High Speed Op Amp
applications.
Ordering Information
For a lower power version of this product, please see
the HA-2850 datasheet.
PART
NUMBER
TEMP.
RANGE ( C)
o
PACKAGE
PKG. DWG. #
HA1-2540-5
0 to 75
14 Ld CERDIP F14.3
Pinout
HA-2540 (CERDIP)
TOP VIEW
NC
NC
NC
-IN
+IN
V-
1
2
3
4
5
6
7
14 NC
13 NC
12 NC
11 V+
-
+
10 OUTPUT
9
8
NC
NC
NC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
HA-2540
Absolute Maximum Ratings
Thermal Information
o
o
Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . 35V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V
Thermal Resistance (Typical, Note 2)
CERDIP Package. . . . . . . . . . . . . . . . .
θ
( C/W)
θ
( C/W)
JA
JC
75
20
Output Current . . . . . . . . . . . . . . 33mA
Continuous, 50mA
Maximum Internal Power Dissipation (Note 1)
Maximum Junction Temperature (Ceramic Package) . . . . . . 175 C
Maximum Storage Temperature Range . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C
RMS
PEAK
o
o
o
Operating Conditions
o
Temperature Range
HA-2540-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 75 C
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
o
1. Maximum power dissipation with load conditions must be designed to maintain the maximum junction temperature below 175 C for the ceramic
o
package, and below 150 C for the plastic package. By using Application Note AN556 on Safe Operating Area Equations, along with the thermal
o
resistances, proper load conditions can be determined. Heat sinking is recommended above 75 C.
2. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Electrical Specifications
V
= ±15V, R = 1kΩ, C < 10pF, Unless Otherwise Specified
SUPPLY L L
o
PARAMETER
TEMP ( C)
MIN
TYP
MAX
UNITS
INPUT CHARACTERISTICS
Offset Voltage
25
Full
Full
25
-
8
13
20
5
15
20
-
mV
mV
-
o
Average Offset Voltage Drift
Bias Current
-
µV/ C
-
20
25
6
µA
µA
Full
25
-
-
Offset Current
-
1
µA
Full
25
-
-
8
µA
Input Resistance
-
10
1
-
kΩ
Input Capacitance
25
-
-
pF
Common Mode Range
Input Noise Current (f = 1kHz, R
Input Noise Voltage (f = 1kHz, R
Full
25
±10
-
-
V
= 0Ω)
= 0Ω)
-
-
6
-
pA/√Hz
nV/√Hz
SOURCE
SOURCE
25
6
-
TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 3)
25
Full
Full
25
10
5
15
-
-
-
-
-
-
kV/V
kV/V
dB
Common-Mode Rejection Ratio (Note 4)
Minimum Stable Gain
60
10
-
72
-
V/V
Gain Bandwidth Product (Notes 5, 6)
OUTPUT CHARACTERISTICS
Output Voltage Swing (Notes 3, 10)
Output Current (Note 3)
Output Resistance
25
400
MHz
Full
25
±10
±10
-
-
±20
30
6
-
-
-
-
V
mA
Ω
25
Full Power Bandwidth (Notes 3, 7)
TRANSIENT RESPONSE (Note 8)
Rise Time
25
5.5
MHz
25
25
25
25
-
14
5
-
-
-
-
ns
%
Overshoot
-
320
-
Slew Rate
400
140
V/µs
ns
Settling Time: 10V Step to 0.1%
2
HA-2540
Electrical Specifications
V
= ±15V, R = 1kΩ, C < 10pF, Unless Otherwise Specified (Continued)
SUPPLY
L
L
o
PARAMETER
TEMP ( C)
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
Supply Current
Full
Full
-
20
70
25
-
mA
dB
Power Supply Rejection Ratio (Note 9)
NOTES:
60
3. R = 1kΩ, V = ±10V.
L
O
4. V
= ±10V.
CM
5. V = 90mV.
O
6. A = 10.
V
Slew Rate
7. Full power bandwidth guaranteed based on slew rate measurement using: FPBW = --------------------------- .
8. Refer to Test Circuits section of the data sheet.
2πV
PEAK
9. V
= +5V, -15V and +15V, -5V.
SUPPLY
10. Guaranteed range for output voltage is ±10V. Functional operation outside of this range is not guaranteed.
Tes t Circuits and Waveforms
V
IN
+
V
OUT
-
900
100
NOTES:
11. A = +10.
V
12. C ≤ 10pF.
L
FIGURE 1. LARGE AND SMALL SIGNAL RESPONSE TEST CIRCUIT
A
B
Vertical Scale: A = 0.5V/Div., B = 5.0V/Div.
Horizontal Scale: 50ns/Div.
Vertical Scale: Input = 10mV/Div.; Output = 50mV/Div.
Horizontal Scale: 20ns/Div.
LARGE SIGNAL RESPONSE
SMALL SIGNAL RESPONSE
0.001µF
1µF
V+
NOTES:
13. A = -10.
V
14. Load Capacitance should be less than 10pF. Turn on time delay
typically 4ns.
200Ω
INPUT
OUTPUT
-
15. It is recommended that resistors be carbon composition and the
feedback and summing network ratios be matched to 0.1%.
+
0.001µF
1µF
PROBE
MONITOR
16. SETTLE POINT (Summing Node) capacitance should be less
than 10pF. For optimum settling time results, it is recommended
that the test circuit be constructed directly onto the device pins. A
Tektronix 568 Sampling Oscilloscope with S-3A sampling heads
is recommended as a settle point monitor.
500Ω
V-
2kΩ
5kΩ
SETTLE
POINT
FIGURE 2. SETTLING TIME TEST CIRCUIT
3
HA-2540
Schematic Diagram
V+
R
4
R
R
3
R
R
2
1
23
Q
P28
Q
P18
Q
Q
P22
P6
Q
P17
R5
Q
P19
R
13
R
24
V-
Q
P5
Q
P25
C
2
C
1
R
V-
22
R
C2
Q
N2
Q
Q
N1
N7
Q
N9
R
R
R
7
6
8
Q
P8
+ INPUT
R
18
OUTPUT
Q
R
P23
Q
9
N21
R
19
Q
N10
Q
P4
Q
P3
Q
P11
- INPUT
V+
R
21
25
Z
Q
1
N25
Q
N12
V+
R
R
10
Q
N20
R
Q
16
Q
N13
N15
Q
R
Q
N14
D
N16
Z1
D
Z2
Q
R
R
14
11
N29
R
R
12
15
17
V-
Typical Applications
V+
R
1
2K
4K
C
(NOTE 18)
1
10K
200
-
1K
R
2
4K
+
HA-2540
V+
C
(NOTE 17)
F
SIGNAL
OUT
OFFSET
ADJUST
HA-2540
0.1µF
1K
-
+
V-
R
5
R
4K
3
(NOTE 19)
2K
R
4
4K
V-
NOTES:
17. Used for experimental purposes. C ≅ 3pF.
F
NOTE: With one HA-2540 and two low capacitance
switching diodes, signals exceeding 10MHz can be
separated. This circuit is most useful for full wave
rectification, AM detectors or sync generation.
18. C is optional (0.001µF → 0.01µF ceramic).
1
19. R is optional and can be utilized to reduce input signal
5
amplitude and/or balance input conditions. R = 500Ω to 1kΩ.
5
FIGURE 3. WIDEBAND SIGNAL SPLITTER
FIGURE 4. BOOTSTRAPPING FOR MORE OUTPUT
CURRENT AND VOLTAGE SWING
Refer to Application Note AN541 For Further Application Information.
4
HA-2540
Typical Performance Curves
28
24
20
16
12
8
100
90
V
V
= ±15V
S
80
70
60
= ±10V
= ±5V
S
50
40
30
20
10
0
V
S
4
0
-10
100
1K
10K
100K
1M
10M
100M
1K
10K
100K
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 5. CLOSED LOOP FREQUENCY RESPONSE
FIGURE 6. OUTPUT VOLTAGE SWING vs FREQUENCY
1.4
1.3
28
24
20
16
12
8
1.2
1.1
BANDWIDTH
1.0
SLEW RATE
0.9
0.8
0.7
4
0.6
0
0
200
400
600
800
1K
1.2K
-80
-40
0
40
80
120
160
o
RESISTANCE (Ω)
TEMPERATURE ( C)
FIGURE 7. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE
FIGURE 8. NORMALIZED AC PARAMETERS vs
TEMPERATURE
28
10
8
10mV
V
= ±15V
= ±5V
24
20
16
12
8
S
1mV
6
4
2
V
0
S
-2
-4
-6
-8
-10
1mV
10mV
4
0
-80
-40
0
40
80
120
160
0
40
80
120
160
200
240
o
SETTLING TIME (ns)
TEMPERATURE ( C)
FIGURE 9. SETTLING TIME FOR VARIOUS OUTPUT STEP
VOLTAGES
FIGURE 10. POWER SUPPLY CURRENT vs TEMPERATURE
5
HA-2540
Typical Performance Curves (Continued)
14
7
6
5
4
3
2
1
0
R
= 0Ω, V = ±15
S
SOURCE
12
25
20
15
10
5
50
40
30
20
10
0
10
OFFSET VOLTAGE
8
6
CURRENT NOISE
4
BIAS CURRENT
VOLTAGE
NOISE
2
0
-80
0
-40
0
40
80
120
160
10
100
1K
10K
100K
o
TEMPERATURE ( C)
FREQUENCY (Hz)
FIGURE 11. INPUT OFFSET VOLTAGE AND BIAS CURRENT vs
TEMPERATURE
FIGURE 12. INPUT NOISE VOLTAGE AND NOISE CURRENT vs
FREQUENCY
+40µV
+30µV
+20µV
+10µV
0µV
V
= ±15, R = 1K
S
L
120
100
80
60
40
20
0
-10µV
-20µV
-30µV
-40µV
Vertical Scale: 10mV/Div.
Horizontal Scale: 50ms/Div.
1K
10K
100K
1M
10M
FREQUENCY (Hz)
FIGURE 13. BROADBAND NOISE (0.1Hz TO 1MHz)
FIGURE 14. COMMON MODE REJECTION RATIO vs
FREQUENCY
100
100
80
0
80
45
90
GAIN
60
60
PHASE
POSITIVE SUPPLY
40
20
40
20
0
NEGATIVE SUPPLY
135
180
225
0
-10
100
1K
10K
100K
1M
10M
100M
1K
10K
100K
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 15. POWER SUPPLY REJECTION RATIO vs FREQUENCY
FIGURE 16. OPEN LOOP GAIN/PHASE vs FREQUENCY
6
HA-2540
Die Characteris tics
DIE DIMENSIONS:
SUBSTRATE POTENTIAL (Powered Up):
62 mils x 76 mils x 19 mils
V-
1575 µmx 1930µm x 483µm
TRANSISTOR COUNT:
30
METALLIZATION:
Type: Al, 1% Cu
Thickness: 16kÅ ±2kÅ
PROCESS:
Bipolar Dielectric Isolation
PASSIVATION:
Type: Nitride (Si N ) over Silox (SiO , 5% Phos.)
3
4
2
Silox Thickness: 12kÅ ±2kÅ
Nitride Thickness: 3.5kÅ ±1.5kÅ
Metallization Mas k Layout
HA-2540
V+
OUTPUT
V-
+IN
-IN
- IN
+ IN
7
HA-2540
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 LEAD FINISH
F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A)
14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
E
-A-
INCHES
MIN
MILLIMETERS
BASE
(c)
METAL
SYMBOL
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.785
0.310
MIN
-
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
19.94
7.87
NOTES
b1
A
b
-
-
M
M
(b)
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
2
-B-
b1
b2
b3
c
3
SECTION A-A
bbb
C A - B
D
D
S
S
S
-
4
BASE
PLANE
Q
2
A
-C-
SEATING
PLANE
c1
D
3
L
α
5
S1
b2
eA
A A
e
E
0.220
5.59
5
b
C A - B
eA/2
aaa M C A - B S D S
c
e
0.100 BSC
2.54 BSC
-
eA
eA/2
L
0.300 BSC
0.150 BSC
7.62 BSC
3.81 BSC
-
ccc
D
S
M
S
-
NOTES:
0.125
0.200
0.060
-
3.18
5.08
1.52
-
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
Q
0.015
0.005
0.38
0.13
6
S1
7
o
o
o
o
90
105
90
105
-
α
aaa
bbb
ccc
M
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
-
2, 3
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
14
14
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
8
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