HI5805BIBZ [INTERSIL]
12-Bit, 5MSPS A/D Converter; 12位， 5MSPS A / D转换器
| 型号： | HI5805BIBZ |
| 厂家： | 
Intersil |
| 描述： | 12-Bit, 5MSPS A/D Converter |
| 文件： | 总12页 (文件大小：617K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI5805
®
Data Sheet
March 31, 2005
FN3984.7
12-Bit, 5MSPS A/D Converter
Features
The HI5805 is a monolithic, 12-bit, Analog-to-Digital
Converter fabricated in Intersil’s HBC10 BiCMOS process. It
is designed for high speed, high resolution applications
where wide bandwidth and low power consumption are
essential.
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . .5MSPS
• Low Power
• Internal Sample and Hold
• Fully Differential Architecture
The HI5805 is designed in a fully differential pipelined
architecture with a front end differential-in-differential-out
sample-and-hold (S/H). The HI5805 has excellent dynamic
performance while consuming 300mW power at 5MSPS.
• Full Power Input Bandwidth . . . . . . . . . . . . . . . . . 100MHz
• Low Distortion
• Internal Voltage Reference
The 100MHz full power input bandwidth is ideal for
communication systems and document scanner
applications. Data output latches are provided which present
valid data to the output bus with a latency of 3 clock cycles.
The digital outputs have a separate supply pin which can be
powered from a 3.0V to 5.0V supply.
• TTL/CMOS Compatible Digital I/O
• Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . 5V to 3.0V
• Pb-Free Available (RoHS Compliant)
Applications
• Digital Communication Systems
• Undersampling Digital IF
• Document Scanners
Ordering Information
PART
SAMPLE
RATE
TEMP.
PKG.
DWG. #
o
NUMBER
RANGE ( C)
PACKAGE
HI5805BIB
5MSPS
-40 to 85
28 Ld SOIC (W) M28.3
• Additional Reference Documents
- AN9214 Using Intersil High Speed A/D Converters
- AN9707 Using the HI5805EVAL1 Evaluation Board
HI5805BIBZ 5MSPS
(See Note)
-40 to 85
28 Ld SOIC (W) M28.3
(Pb-free)
HI5805EVAL1
25
Evaluation Board
Pinout
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
HI5805
(SOIC)
TOP VIEW
1
2
28 D0
27 D1
CLK
DV
CC1
3
26
25
24
23
22
21
D
D2
D3
D4
D5
DV
GND1
4
DV
D
CC1
5
GND1
6
AV
CC
7
A
GND
CC2
8
V
D
GND2
IN+
9
20 D6
V
IN-
10
11
12
13
14
19
V
D7
DC
V
18
17
D8
D9
ROUT
V
RIN
16 D10
15
A
GND
D11
AV
CC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2000, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HI5805
Functional Block Diagram
V
V
BIAS
DC
CLOCK
REF
CLK
-
IN
V
+
IN
V
V
ROUT
RIN
S/H
STAGE 1
DV
CC2
4-BIT
FLASH
4-BIT
DAC
+
-
∑
D11 (MSB)
D10
D9
X8
D8
D7
STAGE 3
D6
D5
D4
4-BIT
FLASH
4-BIT
DAC
D3
+
D2
-
∑
D1
X8
D0 (LSB)
STAGE 4
4-BIT
FLASH
D
GND2
AV
CC
A
DV
D
GND1
GND
CC1
Typical Application Schematic
(LSB) (28) D0
(27) D1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
(26) D2
(11)
V
V
ROUT
(25) D3
(12)
RIN
(24) D4
A
(7)
GND
A
D
BNC
(23) D5
(20) D6
(19) D7
(18) D8
(17) D9
(16) D10
GND
GND
A
D
D
D
(13)
GND
(3)
GND1
GND1
GND2
(5)
(21)
(MSB) (15) D11
V
+
-
V
+ (8)
(10)
(4) DV
(2) DV
CC1
IN
IN
V
V
DC
CC1
CC2
- (9) (22) DV
V
+5V
+5V
IN
IN
+
0.1µF
10µF
10µF AND 0.1µF CAPS ARE PLACED
AS CLOSE TO PART AS POSSIBLE
CLK (1)
(6) AV
CLOCK
CC
CC
(14) AV
HI5805
+
0.1µF
10µF
2
HI5805
Absolute Maximum Ratings
Thermal Information
o
Supply Voltage, AV
or DV
to A
or D . . . . . . . . . +6.0V
GND
Thermal Resistance (Typical, Note 1)
θJA ( C/W)
CC
CC
GND
D
to A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V
GND
GND
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150 C
Maximum Storage Temperature Range . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . .300 C
70
o
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D
Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A
to DV
to AV
GND
GND
CC
o
o
CC
o
(SOIC - Lead Tips Only)
Operating Conditions
o
o
Temperature Range, HI5805BIB . . . . . . . . . . . . . . . . -40 C to 85 C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Electrical Specifications AV = DV
= DV
= DV
= +5.0V, f = 5MSPS at 50% Duty Cycle, V
= 3.5V, C = 10pF,
RIN L
CC
CC1
CC2
CC3
S
o
o
o
T
= -40 C to 85 C, Differential Analog Input, Typical Values are Test Results at 25 C,
A
Unless Otherwise Specified
o
o
HI5805BIB (-40 C TO 85 C)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
ACCURACY
Resolution
12
-
-
-
Bits
LSB
LSB
Integral Linearity Error, INL
f
f
= DC
±1
±2
±1
IN
IN
Differential Linearity Error, DNL
(Guaranteed No Missing Codes)
= DC
-
±0.5
Offset Error, V
f
f
= DC
= DC
-
-
19
32
-
-
LSB
LSB
OS
IN
IN
Full Scale Error, FSE
DYNAMIC CHARACTERISTICS
Minimum Conversion Rate
Maximum Conversion Rate
Effective Number of Bits, ENOB
No Missing Codes
No Missing Codes
-
5
0.5
-
-
-
-
-
MSPS
MSPS
Bits
f
f
= 1MHz
= 1MHz
10.0
-
11
68
IN
IN
Signal to Noise and Distortion Ratio, SINAD
dB
RMS Signal
= -------------------------------------------------------------
RMS Noise + Distortion
Signal to Noise Ratio, SNR
f
= 1MHz
-
68
-
-
dB
IN
RMS Signal
= -------------------------------
RMS Noise
Total Harmonic Distortion, THD
2nd Harmonic Distortion
f
f
f
f
f
= 1MHz
= 1MHz
= 1MHz
= 1MHz
-
-
-
-
-
-
-
-80
-86
-83
83
-68
1
dBc
dBc
IN
IN
IN
IN
3rd Harmonic Distortion
-
-
-
-
-
dBc
Spurious Free Dynamic Range, SFDR
Intermodulation Distortion, IMD
Transient Response
dBc
= 1MHz, f = 1.02MHz
dBc
1
2
Cycle
Cycle
Over-Voltage Recovery
0.2V Overdrive
2
ANALOG INPUT
Maximum Peak-to-Peak Differential Analog Input Range
-
±2.0
-
V
(V + - V -)
IN IN
Maximum Peak-to-Peak Single-Ended Analog Input Range
Analog Input Resistance, R
-
1
4.0
-
-
V
MΩ
pF
(Notes 2, 3)
(Note 3)
-
IN
Analog Input Capacitance, C
-
10
-
-
IN
Analog Input Bias Current, I + or I -
-10
-
+10
µA
B
B
Differential Analog Input Bias Current I
= (I + - I -)
±0.5
100
-
-
µA
B DIFF
B
B
Full Power Input Bandwidth, FPBW
-
MHz
3
HI5805
Electrical Specifications AV = DV
= DV
= DV
= +5.0V, f = 5MSPS at 50% Duty Cycle, V
= 3.5V, C = 10pF,
RIN L
CC
CC1
CC2
CC3
S
o
o
o
T
= -40 C to 85 C, Differential Analog Input, Typical Values are Test Results at 25 C,
A
Unless Otherwise Specified (Continued)
o
o
HI5805BIB (-40 C TO 85 C)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
Analog Input Common Mode Voltage Range (V + + V -)/2
Differential Mode (Note 2)
1
2.3
4
V
IN IN
INTERNAL VOLTAGE REFERENCE
Reference Output Voltage, V
Reference Output Current
(Loaded)
-
-
-
3.5
-
-
1
-
V
ROUT
mA
o
Reference Temperature Coefficient
200
ppm/ C
REFERENCE VOLTAGE INPUT
Reference Voltage Input, V
-
-
-
3.5
7.8
450
-
-
-
V
RIN
Total Reference Resistance, R
Reference Current
kΩ
µA
L
DC BIAS VOLTAGE
DC Bias Voltage Output, V
-
-
2.3
-
-
V
DC
Max Output Current (Not To Exceed)
1
mA
DIGITAL INPUTS (CLK)
Input Logic High Voltage, V
2.0
-
-
-
V
IH
Input Logic Low Voltage, V
-
-
-
-
0.8
10.0
10.0
-
V
IL
Input Logic High Current, I
V
V
= 5V
= 0V
-
µA
µA
pF
IH
CLK
CLK
Input Logic Low Current, I
-
IL
Input Capacitance, C
7
IN
DIGITAL OUTPUTS (D0-D11)
Output Logic Sink Current, I
V
= 0.4V (Note 2)
O
1.6
-
1.6
-
-
-
-
-
-
mA
mA
mA
mA
pF
OL
DV
= 3.0V, V = 0.4V
-
CC3
= 2.4V (Note 2)
O
O
Output Logic Source Current, I
V
-0.2
OH
DV
= 3.0V, V = 2.4V
-
-
-0.2
5
CC3
O
Output Capacitance, C
OUT
TIMING CHARACTERISTICS
Aperture Delay, t
-
-
5
5
-
ns
ps (RMS)
ns
AP
Aperture Jitter, t
-
-
AJ
Data Output Delay, t
-
8
OD
Data Output Hold, t
-
8
-
ns
H
Data Latency, t
For a Valid Sample (Note 2)
5MSPS Clock
-
-
3
Cycles
ns
LAT
Clock Pulse Width (Low)
Clock Pulse Width (High)
90
90
100
100
110
110
5MSPS Clock
ns
POWER SUPPLY CHARACTERISTICS
Total Supply Current, I
V
V
V
V
V
+ - V - = 2V
IN
-
-
-
-
-
-
-
60
46
13
1
70
mA
mA
CC
Analog Supply Current, AI
IN
IN
IN
IN
IN
+ - V - = 2V
IN
-
CC
Digital Supply Current, DI
+ - V - = 2V
IN
-
mA
CC1
Output Supply Current, DI
Power Dissipation
+ - V - = 2V
IN
-
mA
CC2
+ - V - = 2V
IN
300
2
350
mW
LSB
LSB
Offset Error PSRR, ∆V
AV
AV
or DV
= 5V ±5%
= 5V ±5%
-
-
OS
CC
CC
CC
CC
Gain Error PSRR, ∆FSE
or DV
30
NOTES:
2. Parameter guaranteed by design or characterization and not production tested.
3. With the clock off (clock low, hold mode).
4
HI5805
Timing Waveforms
ANALOG
INPUT
CLOCK
INPUT
S
H
S
H
S
H
S
H
S
H
S
H
S
H
S
H
N + 6
N-1
N - 1
N
N
N + 1
N + 1
N + 2
N + 2
N + 3
N + 3
N+4
N + 4
N + 5
N + 5
N + 6
INPUT
S/H
1ST
STAGE
B
B
B
B
B
B
B
B
B
1, N - 1
1, N
1, N + 1
1, N + 2
1, N + 3
1, N + 4
1, N + 5
2ND
STAGE
B
B
B
B
B
B
B
2, N - 2
2, N - 1
2, N
2, N + 1
2, N + 2
2, N + 3
2, N + 4
3RD
STAGE
B
B
B
B
B
3, N + 2
3, N - 2
3, N - 1
3, N
3, N + 1
3, N + 3
3, N + 4
4TH
STAGE
B
B
B
B
B
B
B
4, N + 3
4, N - 3
4, N - 2
4, N - 1
4, N
4, N + 1
4, N + 2
DATA
OUTPUT
D
D
D
D
D
D
D
N + 3
N - 3
N - 2
N - 1
N
N + 1
N + 2
t
LAT
NOTES:
4. S : N-th sampling period.
N
5. H : N-th holding period.
N
6. B
: M-th stage digital output corresponding to N-th sampled input.
7. D : Final data output corresponding to N-th sampled input.
M, N
N
FIGURE 1. INTERNAL CIRCUIT TIMING
ANALOG
INPUT
t
AP
t
AJ
CLOCK
INPUT
1.5V
1.5V
t
OD
t
H
2.0V
0.8V
DATA
DATA N - 1
DATA N
OUTPUT
FIGURE 2. INPUT-TO-OUTPUT TIMING
5
HI5805
Typical Performance Curves
11
70
f
= 5MSPS
S
f
= 5MSPS
S
o
10
o
TEMPERATURE = 25 C
TEMPERATURE = 25 C
60
50
40
30
9
8
7
6
5
10
INPUT FREQUENCY (MHz)
1
100
10
INPUT FREQUENCY (MHz)
1
100
FIGURE 3. EFFECTIVE NUMBER OF BITS (ENOB) vs INPUT
FREQUENCY
FIGURE 4. SIGNAL TO NOISE AND DISTORTION (SINAD) vs
INPUT FREQUENCY
70
-40
f
= 5MSPS
f
= 5MSPS
S
S
o
o
TEMPERATURE = 25 C
TEMPERATURE = 25 C
60
50
40
30
-50
-60
-70
-80
10
INPUT FREQUENCY (MHz)
10
INPUT FREQUENCY (MHz)
1
1
100
100
FIGURE 5. SIGNAL TO NOISE RATIO (SNR) vs INPUT
FREQUENCY
FIGURE 6. TOTAL HARMONIC DISTORTION (THD) vs INPUT
FREQUENCY
80
11
f
= 5MSPS
2MHz
5MHz
1MHz
S
o
TEMPERATURE = 25 C
10
9
70
60
50
40
10MHz
20MHz
8
f
= 5MSPS
S
o
TEMPERATURE = 25 C
7
50MHz
6
5
100MHz
10
INPUT FREQUENCY (MHz)
1
100
0.5
DUTY CYCLE (t
0.4
0.6
/t
)
CLK-LOW CLK
FIGURE 7. SPURIOUS FREE DYNAMIC RANGE (SFDR) vs
INPUT FREQUENCY
FIGURE 8. EFFECTIVE NUMBER OF BITS (ENOB) vs CLOCK
DUTY CYCLE AND INPUT FREQUENCY
6
HI5805
Typical Performance Curves (Continued)
3.525
11
2MHz
5MHz
1MHz
10
9
3.515
3.505
3.495
3.485
3.475
V
10MHz
20MHz
REFNOM
8
f
= 5MSPS
S
V
REFLD
7
50MHz
6
5
100MHz
-40
-20
0
20
40
o
60
80
-40
-20
0
20
40
o
60
80
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 9. EFFECTIVE NUMBER OF BITS (ENOB) vs
TEMPERATURE AND INPUT FREQUENCY
FIGURE 10. INTERNAL VOLTAGE REFERENCE OUTPUT
(VROUT) vs TEMPERATURE AND LOAD
306
304
70
I
TOT
60
50
40
30
20
10
0
f
V
= 5MSPS
S
302
300
298
296
+ = V - = V
A
IN
IN
DC
ICC
f
= 5MSPS
S
V
+ = V - = V
IN
IN
DC
D
ICC1
D
ICC2
-40
-20
0
20
40
o
60
80
-40
-20
0
20
40
o
60
80
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 11. POWER DISSIPATION vs TEMPERATURE
FIGURE 12. POWER SUPPLY CURRENT vs TEMPERATURE
0
-20
f
= 1MHz, f = 5MSPS
S
IN
-40
-60
-80
-100
-120
200
400
600
800
1000
FREQUENCY BIN
FIGURE 13. 2048 POINT FFT SPECTRAL PLOT
7
HI5805
see only the on-resistance of a switch and C . The relatively
S
small values of these components result in a typical full power
input bandwidth of 100MHz for the converter.
Pin Des criptions
PIN NO.
NAME
DESCRIPTION
1
CLK
Input Clock.
2
DV
Digital Supply (5.0V).
Digital Ground.
CC1
φ1
φ1
C
H
3
D
GND1
φ1
φ2
φ1
C
C
S
S
4
DV
Digital Supply (5.0V).
Digital Ground
V
+
CC1
IN
V
+
OUT
5
D
- +
+ -
GND1
V
-
6
AV
Analog Supply (5.0V).
Analog Ground.
OUT
CC
V
-
IN
7
A
GND
C
H
8
V
+
Positive Analog Input.
Negative Analog Input.
DC Bias Voltage Output.
Reference Voltage Output.
Reference Voltage Input.
Analog Ground.
IN
φ1
φ1
9
V
V
-
IN
DC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
FIGURE 14. ANALOG INPUT SAMPLE-AND-HOLD
V
ROUT
V
RIN
As illustrated in the functional block diagram and the timing
diagram in Figure 1, three identical pipeline subconverter
stages, each containing a four-bit flash converter, a four-bit
digital-to-analog converter and an amplifier with a voltage
gain of 8, follow the S/H circuit with the fourth stage being
only a 4-bit flash converter. Each converter stage in the
pipeline will be sampling in one phase and amplifying in the
other clock phase. Each individual sub-converter clock
signal is offset by 180 degrees from the previous stage
clock signal, with the result that alternate stages in the
pipeline will perform the same operation.
A
GND
AV
Analog Supply (5.0V).
Data Bit 11 Output (MSB).
Data Bit 10 Output.
Data Bit 9 Output.
CC
D11
D10
D9
D8
D7
D6
Data Bit 8 Output.
Data Bit 7 Output.
Data Bit 6 Output.
D
Digital Output Ground.
Digital Output Supply (3.0V to 5.0V).
Data Bit 5 Output.
GND2
DV
CC2
The 4-bit digital output of each stage is fed to a digital delay
line controlled by the internal clock. The purpose of the delay
line is to align the digital output data to the corresponding
sampled analog input signal. This delayed data is fed to the
digital error correction circuit which corrects the error in the
output data with the information contained in the redundant
bits to form the final 12-bit output for the converter.
D5
D4
D3
D2
D1
D0
Data Bit 4 Output.
Data Bit 3 Output.
Data Bit 2 Output.
Data Bit 1 Output.
Data Bit 0 Output (LSB).
Because of the pipeline nature of this converter, the data on
the bus is output at the 3rd cycle of the clock after the analog
sample is taken. This delay is specified as the data latency.
After the data latency time, the data representing each
succeeding sample is output at the following clock pulse. The
output data is synchronized to the external clock by a latch.
The digital outputs are in offset binary format (See Table 1).
Detailed Des cription
Theory of Operation
The HI5805 is a 12-bit, fully-differential, sampling pipeline A/D
converter with digital error correction. Figure 14 depicts the
circuit for the front end differential-in-differential-out sample-
and-hold (S/H). The switches are controlled by an internal
clock which is a non-overlapping two phase signal, f and f ,
1
2
Internal Reference Generator, V
ROUT
and V
RIN
derived from the master clock. During the sampling phase, f ,
1
The HI5805 has an internal reference generator, therefore, no
external reference voltage is required. V must be
the input signal is applied to the sampling capacitors, C . At
S
ROUT
when using the internal reference voltage.
the same time the holding capacitors, C , are discharged to
H
connected to V
RIN
analog ground. At the falling edge of f the input signal is
1
sampled on the bottom plates of the sampling capacitors. In
The HI5805 can be used with an external reference. The
converter requires only one external reference voltage
the next clock phase, f , the two bottom plates of the
2
sampling capacitors are connected together and the holding
capacitors are switched to the op-amp output nodes. The
connected to the V
pin with V
left open.
RIN
ROUT
The HI5805 is tested with V
converter, two reference voltages of 1.3V and 3.3V are
generated for a fully differential input signal range of ±2V.
equal to 3.5V. Internal to the
RIN
charge then redistributes between C and C completing one
S
H
sample-and-hold cycle. The output is a fully-differential,
sampled-data representation of the analog input. The circuit
not only performs the sample-and-hold function but will also
convert a single-ended input to a fully-differential output for
In order to minimize overall converter noise, it is
recommended that adequate high frequency decoupling be
the converter core. During the sampling phase, the V pins
IN
provided at the reference voltage input pin, V
.
RIN
8
HI5805
TABLE 1.
OFFSET BINARY OUTPUT CODE
DIFFERENTIAL
INPUT VOLTAGE†
(USING INTERNAL
REFERENCE)
MSB
LSB
D0
1
CODE CENTER
DESCRIPTION
D11
1
D10
D9
1
D8
1
D7
1
D6
1
D5
1
D4
1
D3
1
D2
1
D1
1
1
+Full Scale (+FS) - / LSB
4
+1.99976V
1.99878V
732.4µV
1
1
0
1
0
0
1
+FS - 1 / LSB
4
1
1
1
1
1
1
1
1
1
1
0
3
+
-
/
LSB
1
0
0
0
0
0
0
0
0
0
0
4
1
/
LSB
3
-244.1µV
-1.99829V
-1.99927V
0
1
1
1
1
1
1
1
1
1
1
4
-FS + 1 / LSB
0
0
0
0
0
0
0
0
0
0
1
4
3
-Full Scale (-FS) + / LSB
0
0
0
0
0
0
0
0
0
0
0
4
† The voltages listed above represent the ideal center of each offset binary output code shown.
scale, all 1s digital data output code, when the V + input is
IN
Analog Input, Differential Connection
at V
+1V and the V - input is at V
-1V (V +-V - =
DC
IN
DC IN IN
The analog input to the HI5805 can be configured in various
ways depending on the signal source and the required level
of performance. A fully differential connection (Figure 15) will
give the best performance for the converter.
2V). Conversely, the ADC will be at negative full scale, all
0s digital data output code, when the V + input is equal to
IN
V
- 1V and V - is at V +1V (V +-V - = -2V). From
DC
IN DC IN IN
this, the converter is seen to have a peak-to-peak
differential analog input voltage range of ±2V.
V
V
+
V
The analog input can be DC coupled (Figure 16) as long as
the inputs are within the analog input common mode voltage
range (1.0V ≤ VDC ≤ 4.0V).
IN
IN
HI5805
DC
V
IN
-V
V
+
IN
IN
V -
VDC
VDC
IN
R
R
HI5805
C
FIGURE 15. AC COUPLED DIFFERENTIAL INPUT
V
V
DC
-V
IN
Since the HI5805 is powered off a single +5V supply, the
analog input must be biased so it lies within the analog input
common mode voltage range of 1.0V to 4.0V. The
-
IN
performance of the ADC does not change significantly with
the value of the analog input common mode voltage.
FIGURE 16. DC COUPLED DIFFERENTIAL INPUT
The resistors, R, in Figure 16 are not absolutely necessary
but may be used as load setting resistors. A capacitor, C,
A 2.3V DC bias voltage source, V , half way between the
DC
top and bottom internal reference voltages, is made
available to the user to help simplify circuit design when
using a differential input. This low output impedance voltage
source is not designed to be a reference but makes an
excellent bias source and stays within the analog input
common mode voltage range over temperature.
connected from V + to V - will help filter any high
IN IN
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
The difference between the converter’s two internal voltage
references is 2V. For the AC coupled differential input,
Analog Input, Single-Ended Connection
The configuration shown in Figure 17 may be used with a
single ended AC coupled input. Sufficient headroom must be
provided such that the input voltage never goes above +5V
(Figure 15), if V is a 2V
degrees out of phase with V , then V + is a 2V
sinewave with -V being 180
IN
P-P
IN
IN IN
P-P
and
sinewave riding on a DC bias voltage equal to V
DC
sinewave riding on a DC bias voltage equal
or below A
GND
.
V
- is a 2V
IN
P-P
to V . Consequently, the converter will be at positive full
DC
9
HI5805
The digital CMOS outputs have a separate digital supply.
This allows the digital outputs to operate from a 3.0V to 5.0V
supply. When driving CMOS logic, the digital outputs will
swing to the rails. When driving standard TTL loads, the
digital outputs will meet standard TTL level requirements
even with a 3.0V supply.
V
+
V
IN
IN
HI5805
VDC
In order to ensure rated performance of the HI5805, the duty
cycle of the clock should be held at 50% ±5%. It must also
have low jitter and operate at standard TTL levels.
V
-
IN
FIGURE 17. AC COUPLED SINGLE ENDED INPUT
Performance of the HI5805 will only be guaranteed at
conversion rates above 0.5MSPS. This ensures proper
performance of the internal dynamic circuits.
Again, the difference between the two internal voltage
references is 2V. If V is a 4V
sinewave, then V + is a
IN P-P
IN
4V
P-P
sinewave riding on a positive voltage equal to VDC.
Supply and Ground Cons iderations
The converter will be at positive full scale when V + is at
IN
The HI5805 has separate analog and digital supply and
ground pins to keep digital noise out of the analog signal
path. The part should be mounted on a board that provides
separate low impedance connections for the analog and
digital supplies and grounds. For best performance, the
supplies to the HI5805 should be driven by clean, linear
regulated supplies. The board should also have good high
frequency decoupling capacitors mounted as close as
possible to the converter. If the part is powered off a single
supply then the analog supply and ground pins should be
isolated by ferrite beads from the digital supply and ground
pins.
VDC + 2V (V + - V - = 2V) and will be at negative full scale
IN IN
when V + is equal to VDC - 2V (V + - V - = -2V). In this
IN
IN
IN
case, V
could range between 2V and 3V without a
DC
significant change in ADC performance. The simplest way to
produce VDC is to use the V
HI5805.
bias voltage output of the
DC
The single ended analog input can be DC coupled (Figure
18) as long as the input is within the analog input common
mode voltage range.
V
IN
V
+
V
IN
DC
Refer to the Application Note AN9214, “Using Intersil High
Speed A/D Converters” for additional considerations when
using high speed converters.
R
HI5805
C
Static Performance Definitions
V
V
-
DC
IN
Offs et Error (V
OS
The midscale code transition should occur at a level / LSB
)
1
4
above half scale. Offset is defined as the deviation of the
actual code transition from this point.
FIGURE 18. DC COUPLED SINGLE ENDED INPUT
The resistor, R, in Figure 18 is not absolutely necessary but
may be used as a load setting resistor. A capacitor, C,
Full-Scale Error (FSE)
The last code transition should occur for an analog input that
3
connected from V + to V - will help filter any high
IN IN
is / LSB below positive full scale with the offset error
4
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
removed. Full-scale error is defined as the deviation of the
actual code transition from this point.
Differential Linearity Error (DNL)
DNL is the worst case deviation of a code width from the
ideal value of 1 LSB.
A single ended source will give better overall system
performance if it is first converted to differential before
driving the HI5805.
Integral Linearity Error (INL)
INL is the worst case deviation of a code center from a best
fit straight line calculated from the measured data.
Digital I/O and Clock Requirements
The HI5805 provides a standard high-speed interface to
external TTL/CMOS logic families. The digital CMOS clock
input has TTL level thresholds. The low input bias current
allows the HI5805 to be driven by CMOS logic.
Power Supply Rejection Ratio (PSRR)
Each of the power supplies are moved plus and minus 5%
and the shift in the offset and gain error (in LSBs) is noted.
10
HI5805
Total Harmonic Dis tortion (THD)
Dynamic Performance Definitions
THD is the ratio of the RMS sum of the first 5 harmonic
components to the RMS value of the fundamental input
signal.
Fast Fourier Transform (FFT) techniques are used to
evaluate the dynamic performance of the HI5805. A low
distortion sine wave is applied to the input, it is coherently
sampled, and the output is stored in RAM. The data is then
transformed into the frequency domain with an FFT and
analyzed to evaluate the dynamic performance of the A/D.
The sine wave input to the part is -0.5dB down from full scale
for all these tests. SNR and SINAD are quoted in dB. The
distortion numbers are quoted in dBc (decibels with respect
to carrier) and DO NOT include any correction factors for
normalizing to full scale.
2nd and 3rd Harmonic Dis tortion
This is the ratio of the RMS value of the applicable
harmonic component to the RMS value of the fundamental
input signal.
Spurious Free Dynamic Range (SFDR)
SFDR is the ratio of the fundamental RMS amplitude to the
RMS amplitude of the next largest spur or spectral
component in the spectrum below f /2.
S
Signal-to-Nois e Ratio (SNR)
SNR is the measured RMS signal to RMS noise at a
specified input and sampling frequency. The noise is the
RMS sum of all of the spectral components except the
fundamental and the first five harmonics.
Intermodulation Dis tortion (IMD)
Nonlinearities in the signal path will tend to generate
intermodulation products when two tones, f and f , are
present at the inputs. The ratio of the measured signal to
the distortion terms is calculated. The terms included in the
1
2
Signal-to-Nois e + Dis tortion Ratio (SINAD)
calculation are (f + f ), (f - f ), (2f ), (2f ), (2f + f ),
1
2
1
2
1
2
1
2
SINAD is the measured RMS signal to RMS sum of all
other spectral components below the Nyquist frequency,
f /2, excluding DC.
S
(2f - f ), (f + 2f ), (f - 2f ). The ADC is tested with each
1
2
1
2
1
2
tone 6dB below full scale.
Effective Number Of Bits (ENOB)
The effective number of bits (ENOB) is calculated from the
SINAD data by:
ENOB = (SINAD + V
-1.76)/6.02,
CORR
where: V
= 0.5dB.
adjusts the ENOB for the amount the input is below
CORR
V
CORR
fullscale.
11
HI5805
Trans ient Res pons e
Aperture Delay (t
)
AP
Transient response is measured by providing a full-scale
transition to the analog input of the ADC and measuring the
number of cycles it takes for the output code to settle within
12-bit accuracy.
Aperture delay is the time delay between the external
sample command (the falling edge of the clock) and the time
at which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
Over-Voltage Recovery
Aperture J itter (t
)
AJ
Over-voltage Recovery is measured by providing a full-scale
transition to the analog input of the ADC which overdrives
the input by 200mV, and measuring the number of cycles it
takes for the output code to settle within 12-bit accuracy.
Aperture Jitter is the RMS variation in the aperture delay due
to variation of internal clock path delays.
Data Hold Time (t )
H
Data hold time is the time to where the previous data (N - 1)
is no longer valid.
Full Power Input Bandwidth (FPBW)
Full power input bandwidth is the analog input frequency at
which the amplitude of the digitally reconstructed output has
decreased 3dB below the amplitude of the input sinewave.
Data Output Delay Time (t
)
OD
Data output delay time is the time to where the new data (N)
is valid.
The input sinewave has an amplitude which swings from -f
S
to +f . The bandwidth given is measured at the specified
sampling frequency.
S
Data Latency (t
)
LAT
After the analog sample is taken, the digital data is output on
the bus at the third cycle of the clock. This is due to the
pipeline nature of the converter where the data has to ripple
through the stages. This delay is specified as the data
latency. After the data latency time, the data representing
each succeeding sample is output at the following clock
pulse. The digital data lags the analog input sample by 3
clock cycles.
Timing Definitions
Refer to Figure 1, Internal Circuit Timing, and Figure 2,
Input-To-Output Timing, for these definitions.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
12
相关型号：
HI5810JIB-T
CMOS 10 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold
INTERSIL
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