HI5808_01 [INTERSIL]
12-Bit, 9MSPS A/D Converter; 12位， 9MSPS A / D转换器
| 型号： | HI5808_01 |
| 厂家： | 
Intersil |
| 描述： | 12-Bit, 9MSPS A/D Converter |
| 文件： | 总12页 (文件大小：180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI5808
TM
Data Sheet
April 2001
File Number 4233.5
12-Bit, 9MSPS A/D Converter
Features
The HI5808 is a monolithic, 12-bit, Analog-to-Digital
Converter fabricated in Intersil’s HBC10 BiCMOS process. It
is designed for high speed, high resolution applications
where wide bandwidth and low power consumption are
essential.
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9MSPS
• Low Power
• Internal Sample and Hold
• Fully Differential Architecture
The HI5808 is designed in a fully differential pipelined
architecture with a front end differential-in-differential-out
sample-and-hold (S/H). The HI5808 has excellent dynamic
performance while consuming 325mW power at 9MSPS.
• Full Power Input Bandwidth . . . . . . . . . . . . . . . . . 100MHz
• Low Distortion
• Internal Voltage Reference
The 100MHz full power input bandwidth is ideal for
communication systems and document scanner
applications. Data output latches are provided which present
valid data to the output bus with a latency of 3 clock cycles.
The digital outputs have a separate supply pin which can be
powered from a 3V to 5V supply.
• TTL/CMOS Compatible Digital I/O
• Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . 5V to 3.0V
Applications
• Digital Communication Systems
• Undersampling Digital IF
• Document Scanners
Ordering Information
PART
NUMBER
SAMPLE
RATE
TEMP.
PKG.
NO.
o
• Additional Reference Documents
RANGE ( C)
-40 to 85
25
PACKAGE
28 Ld SOIC
- AN9214 Using Intersil High Speed A/D Converters
- AN9724 Using the HI5808EVAL1 Evaluation Board
HI5808BIB
9MSPS
M28.3
HI5808EVAL1
Evaluation Board
Pinout
HI5808
(SOIC)
TOP VIEW
CLK
D0
D1
D2
D3
D4
1
2
28
27
26
25
24
DV
CC1
D
3
GND1
DV
D
4
CC1
5
GND1
AV
CC
6
23 D5
22 DV
A
7
GND
CC2
V
+
-
8
21
20
D
GND2
IN
V
D6
9
IN
V
19 D7
D8
10
11
12
13
14
DC
V
18
17 D9
ROUT
V
RIN
D10
A
16
15
GND
D11
AV
CC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001, All Rights Reserved
1
HI5808
Functional Block Diagram
V
V
BIAS
DC
CLOCK
REF
CLK
-
IN
V
+
IN
V
V
ROUT
RIN
S/H
STAGE 1
DV
CC2
4-BIT
FLASH
4-BIT
DAC
+
-
D11 (MSB)
D10
D9
X8
D8
D7
STAGE 3
D6
D5
D4
4-BIT
FLASH
4-BIT
DAC
D3
+
D2
-
D1
X8
D0 (LSB)
STAGE 4
4-BIT
FLASH
D
GND2
AV
CC
A
DV
CC1
D
GND1
GND
Typical Applications Schematic
(LSB) (28) D0
(27) D1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
(26) D2
V
V
(11)
ROUT
(25) D3
(24) D4
(12)
RIN
A
(7)
GND
A
D
BNC
(23) D5
(20) D6
(19) D7
(18) D8
(17) D9
(16) D10
GND
GND
A
D
D
D
(13)
GND
(3)
GND1
GND1
GND2
(5)
(21)
(MSB) (15) D11
(4) DV
(2) DV
V
+
-
V
V
V
+ (8)
(10)
IN
IN
CC1
DC
CC1
CC2
- (9) (22) DV
V
+5V
+5V
IN
IN
+
10µF
0.1µF
0.1µF
10µF AND 0.1µF CAPS ARE PLACED
AS CLOSE TO PART AS POSSIBLE
CLK (1)
(6) AV
CLOCK
CC
(14) AV
HI5808
CC
+
10µF
2
HI5808
Absolute Maximum Ratings
Thermal Information
o
Supply Voltage, AV
or DV
to A
or D
. . . . . . . . . +6.0V
Thermal Resistance (Typical, Note 1)
θ
( C/W)
CC
CC
GND
GND
JA
D
to A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V
GND
GND
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . .300 C
70
o
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D
Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A
to DV
to AV
GND
CC
o
o
GND
CC
o
(SOIC - Lead Tips Only)
Operating Conditions
o
o
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications AV = DV
= DV
= +5V, f = 9MSPS at 50% Duty Cycle, V
= 3.5V, C = 10pF,
RIN L
CC
CC1
CC2
S
o
o
o
T
= -40 C to 85 C, Differential Analog Input, Typical Values are Test Results at 25 C,
A
Unless Otherwise Specified
HI5808BIB
o
o
-40 C TO 85 C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ACCURACY
Resolution
12
-
-
-
Bits
LSB
LSB
Integral Linearity Error, INL
f
f
= DC
= DC
±1
±2
±1
IN
Differential Linearity Error, DNL
(Guaranteed No Missing Codes)
-
±0.5
IN
Offset Error, V
f
f
= DC
= DC
-
-
19
32
-
-
LSB
LSB
OS
IN
Full Scale Error, FSE
IN
DYNAMIC CHARACTERISTICS
Minimum Conversion Rate
Maximum Conversion Rate
Effective Number of Bits, ENOB
No Missing Codes
No Missing Codes
-
9
0.5
-
-
-
-
-
MSPS
MSPS
Bits
f
= 1MHz
= 1MHz
10.0
-
10.8
66.5
IN
IN
Signal to Noise and Distortion Ratio, SINAD
f
dB
RMS Signal
= -------------------------------------------------------------
RMS Noise + Distortion
Signal to Noise Ratio, SNR
f
= 1MHz
-
67.3
-
-
dB
IN
RMS Signal
= -------------------------------
RMS Noise
Total Harmonic Distortion, THD
2nd Harmonic Distortion
f
f
f
f
f
= 1MHz
= 1MHz
= 1MHz
= 1MHz
-
-
-
-
-
-
-
-75
-80
-77
77
-65
1
dBc
dBc
IN
IN
IN
IN
3rd Harmonic Distortion
-
-
-
-
-
dBc
Spurious Free Dynamic Range, SFDR
Intermodulation Distortion, IMD
Transient Response
dBc
= 1MHz, f = 1.02MHz
dBc
1
2
Cycle
Cycle
Overvoltage Recovery
0.2V Overdrive
2
ANALOG INPUT
Maximum Peak-to-Peak Differential Analog Input Range
-
±2.0
-
V
(V + - V -)
IN IN
Maximum Peak-to-Peak Single-Ended Analog Input Range
Analog Input Resistance, R
-
1
4.0
-
-
V
(Notes 2, 3)
(Note 3)
-
MΩ
pF
IN
Analog Input Capacitance, C
-
10
-
-
+10
-
IN
Analog Input Bias Current, I + or I -
-10
-
µA
µA
B
B
Differential Analog Input Bias Current
= (I + - I -)
±0.5
I
B DIFF
B
B
Full Power Input Bandwidth, FPBW
-
100
-
MHz
3
HI5808
Electrical Specifications AV = DV
= DV
= +5V, f = 9MSPS at 50% Duty Cycle, V
S
= 3.5V, C = 10pF,
RIN L
CC
CC1
CC2
o
o
o
T
= -40 C to 85 C, Differential Analog Input, Typical Values are Test Results at 25 C,
A
Unless Otherwise Specified (Continued)
HI5808BIB
o
o
-40 C TO 85 C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Analog Input Common Mode Voltage Range (V + + V -)/2
Differential Mode (Note 2)
1
2.3
4
V
IN IN
INTERNAL VOLTAGE REFERENCE
Reference Output Voltage, V
Reference Output Current
(Loaded)
-
-
-
3.5
-
-
1
-
V
ROUT
mA
o
Reference Temperature Coefficient
50
ppm/ C
REFERENCE VOLTAGE INPUT
Reference Voltage Input, V
RIN
-
-
-
3.5
7.8
450
-
-
-
V
Total Reference Resistance, R
kΩ
µA
L
Reference Current
DC BIAS VOLTAGE
DC Bias Voltage Output, V
-
-
2.3
-
-
V
DC
Max Output Current (Not To Exceed)
1
mA
DIGITAL INPUTS (CLK)
Input Logic High Voltage, V
2.0
-
-
-
V
IH
Input Logic Low Voltage, V
-
-
-
-
0.8
10.0
10.0
-
V
IL
Input Logic High Current, I
IH
V
V
= 5V
= 0V
-
µA
µA
pF
CLK
Input Logic Low Current, I
-
IL
CLK
Input Capacitance, C
7
IN
DIGITAL OUTPUTS (D0-D11)
Output Logic Sink Current, I
V
= 0.4V (Note 2)
1.6
-
1.6
-
-
-
-
-
-
mA
mA
mA
mA
pF
OL
O
DV
CC3
= 3.0V, V = 0.4V
-
O
Output Logic Source Current, I
V
= 2.4V (Note 2)
-0.2
OH
O
DV
CC3
= 3.0V, V = 2.4V
-
-
-0.2
5
O
Output Capacitance, C
OUT
TIMING CHARACTERISTICS
Aperture Delay, t
-
-
5
5
-
-
ns
ps (RMS)
ns
AP
Aperture Jitter, t
AJ
Data Output Delay, t
OD
-
8
-
Data Output Hold, t
-
8
-
ns
H
Data Latency, t
For a Valid Sample (Note 2)
9MSPS Clock
-
-
3
Cycles
ns
LAT
Clock Pulse Width (Low)
Clock Pulse Width (High)
45
45
50
50
55
55
9MSPS Clock
ns
POWER SUPPLY CHARACTERISTICS
Total Supply Current, I
V
V
V
V
V
+ - V - = 2V
IN
-
-
-
-
-
-
-
65
46
17
2
73
mA
mA
CC
Analog Supply Current, AI
IN
IN
IN
IN
IN
+ - V - = 2V
IN
-
CC
Digital Supply Current, DI
+ - V - = 2V
IN
-
mA
CC1
Output Supply Current, DI
Power Dissipation
+ - V - = 2V
IN
-
mA
CC2
+ - V - = 2V
IN
325
2
365
mW
LSB
LSB
Offset Error PSRR, ∆V
AV
AV
or DV
= 5V ±5%
= 5V ±5%
-
-
OS
CC
CC
CC
CC
Gain Error PSRR, ∆FSE
or DV
30
NOTES:
2. Parameter guaranteed by design or characterization and not production tested.
3. With the clock off (clock low, hold mode).
4
HI5808
Timing Waveforms
ANALOG
INPUT
CLOCK
INPUT
S
H
S
H
S
H
S
H
S
H
S
H
S
H
S
H
N + 6
N - 1
N - 1
N
N
N + 1
N + 1
N + 2
N + 2
N + 3
N + 3
N + 4
N + 4
N + 5
N + 5
N + 6
INPUT
S/H
1ST
STAGE
B
B
B
B
B
B
B
1, N + 5
1, N - 1
1, N
1, N + 1
1, N + 2
1, N + 3
1, N + 4
2ND
STAGE
B
B
B
B
B
B
B
B
2, N + 4
2, N - 2
2, N - 1
2, N
2, N + 1
2, N + 2
2, N + 3
3RD
STAGE
B
B
B
B
B
B
B
3, N + 4
3, N - 2
3, N - 1
3, N
3, N + 1
3, N + 2
3, N + 3
4TH
STAGE
B
B
B
B
B
B
4, N + 3
4, N - 3
4, N - 2
4, N - 1
4, N
4, N + 1
4, N + 2
DATA
OUTPUT
D
D
D
D
D
D
D
N + 3
N - 3
N - 2
N - 1
N
N + 1
N + 2
t
LAT
NOTES:
4. S : N-th sampling period.
N
5. H : N-th holding period.
N
6. B
: M-th stage digital output corresponding to N-th sampled input.
M, N
7. D : Final data output corresponding to N-th sampled input.
N
FIGURE 1. INTERNAL CIRCUIT TIMING
ANALOG
INPUT
t
AP
t
AJ
CLOCK
INPUT
1.5V
1.5V
t
OD
t
H
2.0V
0.8V
DATA
DATA N - 1
DATA N
OUTPUT
FIGURE 2. INPUT-TO-OUTPUT TIMING
5
HI5808
Typical Performance Curves
11
70
f
= 9MSPS
S
f
= 9MSPS
S
o
10
9
TEMPERATURE = 25 C
o
TEMPERATURE = 25 C
60
50
40
30
8
7
6
5
10
INPUT FREQUENCY (MHz)
1
100
10
INPUT FREQUENCY (MHz)
1
100
FIGURE 3. EFFECTIVE NUMBER OF BITS (ENOB) vs INPUT
FREQUENCY
FIGURE 4. SIGNAL TO NOISE AND DISTORTION (SINAD) vs
INPUT FREQUENCY
70
-40
f
= 9MSPS
f
= 9MSPS
S
S
o
o
TEMPERATURE = 25 C
TEMPERATURE = 25 C
60
50
40
30
-50
-60
-70
-80
10
INPUT FREQUENCY (MHz)
10
INPUT FREQUENCY (MHz)
1
1
100
100
FIGURE 5. SIGNAL TO NOISE RATIO (SNR) vs INPUT
FREQUENCY
FIGURE 6. TOTAL HARMONIC DISTORTION (THD) vs INPUT
FREQUENCY
80
11
2MHz
5MHz
1MHz
f
= 9MSPS
S
o
10
9
TEMPERATURE = 25 C
70
60
50
40
10MHz
20MHz
8
f
= 9MSPS
S
o
TEMPERATURE = 25 C
7
50MHz
6
5
100MHz
0.5
DUTY CYCLE (t
0.4
10
INPUT FREQUENCY (MHz)
0.6
1
100
/t
CLK-LOW CLK
)
FIGURE 7. SPURIOUS FREE DYNAMIC RANGE (SFDR) vs
INPUT FREQUENCY
FIGURE 8. EFFECTIVE NUMBER OF BITS (ENOB) vs CLOCK
DUTY CYCLE AND INPUT FREQUENCY
6
HI5808
Typical Performance Curves (Continued)
11
3.525
3.515
3.505
3.495
3.485
3.475
2MHz
5MHz
10MHz
1MHz
= 9MSPS
-20
10
9
V
REFNOM
20MHz
8
f
S
V
REFLD
7
50MHz
6
5
100MHz
-40
0
20
40
o
60
80
-40
-20
0
20
40
60
80
o
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 9. EFFECTIVE NUMBER OF BITS (ENOB) vs
TEMPERATURE AND INPUT FREQUENCY
FIGURE 10. INTERNAL VOLTAGE REFERENCE OUTPUT
(V ) vs TEMPERATURE AND LOAD
ROUT
326
324
70
I
TOT
60
50
40
30
20
10
0
f
= 9MSPS
S
A
D
ICC
322
320
318
316
V
+ = V - = V
IN
IN
DC
f
= 9MSPS
S
V
+ = V - = V
IN
IN
DC
ICC1
D
ICC2
-40
-20
0
20
40
o
60
80
-40
-20
0
20
40
60
80
o
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 11. POWER DISSIPATION vs TEMPERATURE
FIGURE 12. POWER SUPPLY CURRENT vs TEMPERATURE
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
f
= 1MHz, f = 9MSPS
S
IN
1024
2048
FREQUENCY BIN
FIGURE 13. 4096 POINT FFT SPECTRAL PLOT
7
HI5808
fully-differential output for the converter core. During the
sampling phase, the V pins see only the on-resistance of a
Pin Descriptions
IN
PIN NO.
NAME
DESCRIPTION
switch and C . The relatively small values of these
S
1
CLK
Sample Clock Input.
components result in a typical full power input bandwidth of
100MHz for the converter.
2
DV
Digital Supply (5.0V).
Digital Ground.
CC1
3
D
GND1
φ1
φ1
4
DV
Digital Supply (5.0V).
Digital Ground.
CC1
C
H
φ1
φ2
5
D
GND1
C
C
S
S
V
+
IN
6
AV
Analog Supply (5.0V).
Analog Ground.
V
+
CC
OUT
- +
+ -
7
A
GND
V
-
OUT
V
-
IN
8
V
Positive Analog Input.
Negative Analog Input.
DC Bias Voltage Output.
Reference Voltage Output.
Reference Voltage Input.
Analog Ground.
IN+
φ1
C
9
V
H
IN-
DC
φ1
φ1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
V
ROUT
FIGURE 14. ANALOG INPUT SAMPLE-AND-HOLD
V
RIN
A
As illustrated in the functional block diagram and the timing
diagram in Figure 1, three identical pipeline subconverter
stages, each containing a four-bit flash converter, a four-bit
digital-to-analog converter and an amplifier with a voltage gain
of 8, follow the S/H circuit with the fourth stage being only a 4-
bit flash converter. Each converter stage in the pipeline will be
sampling in one phase and amplifying in the other clock phase.
Each individual sub-converter clock signal is offset by 180
degrees from the previous stage clock signal, with the result
that alternate stages in the pipeline will perform the same
operation.
GND
AV
Analog Supply (5.0V).
Data Bit 11 Output (MSB).
Data Bit 10 Output.
Data Bit 9 Output.
CC
D11
D10
D9
D8
D7
D6
Data Bit 8 Output.
Data Bit 7 Output.
Data Bit 6 Output.
D
Digital Output Ground.
Digital Output Supply (3.0V to 5.0V).
Data Bit 5 Output.
GND2
DV
CC2
The digital output of each of the three identical 4-bit
subconverter stages is a four-bit digital word containing a
supplementary bit to be used by the digital error correction
logic. The output of each subconverter stage is input to a digital
delay line which is controlled by the internal sampling clock.
The function of the digital delay line is to time align the digital
outputs of the three identical four-bit subconverter stages with
the corresponding output of the fourth stage flash converter
before applying the sixteen bit result to the digital error
correction logic. The digital error correction logic uses the
supplementary bits to correct any error that may exist before
generating the final twelve bit digital data output of the
converter.
D5
D4
D3
D2
D1
D0
Data Bit 4 Output.
Data Bit 3 Output.
Data Bit 2 Output.
Data Bit 1 Output.
Data Bit 0 Output (LSB).
Detailed Description
Theory of Operation
The HI5808 is a 12-bit fully differential sampling pipeline A/D
converter with digital error correction. Figure 14 depicts the
circuit for the front end differential-in-differential-out sample-
and-hold (S/H). The switches are controlled by an internal
clock which is a non-overlapping two phase signal, φ and φ ,
derived from the master clock. During the sampling phase,
φ , the input signal is applied to the sampling capacitors,
C . At the same time the holding capacitors, C , are
discharged to analog ground. At the falling edge of φ the
input signal is sampled on the bottom plates of the sampling
Because of the pipeline nature of this converter, the digital
data representing an analog input sample is output to the
digital data bus on the 3rd cycle of the clock after the analog
sample is taken. This time delay is specified as the data
latency. After the data latency time, the digital data
representing each succeeding analog sample is output on
the following clock pulse. The digital output data is
synchronized to the external sampling clock with an output
latch. The output of the digital error correction circuit is
available in offset binary format (see Table 1, A/D Code
Table).
1
2
1
S
H
1
capacitors. In the next clock phase, φ , the two bottom
plates of the sampling capacitors are connected together
and the holding capacitors are switched to the op-amp
2
output nodes. The charge then redistributes between C
S
and C completing one sample-and-hold cycle. The output
H
is a fully-differential, sampled-data representation of the
analog input. The circuit not only performs the sample-and-
hold function but will also convert a single-ended input to a
8
HI5808
TABLE 1. A/D CODE TABLE
OFFSET BINARY OUTPUT CODE
DIFFERENTIAL
INPUT VOLTAGE †
(USING INTERNAL
REFERENCE)
MSB
LSB
D0
1
CODE CENTER
DESCRIPTION
D11
1
D10
1
D9
1
D8
1
D7
1
D6
1
D5
1
D4
1
D3
1
D2
1
D1
1
1
+Full Scale (+FS) -
1
/
LSB
+1.99976V
1.99878V
732.4µV
4
+FS - 1 / LSB
4
1
1
1
1
1
1
1
1
1
1
1
0
3
+
-
/
LSB
1
0
0
0
0
0
0
0
0
0
0
0
4
1
/
LSB
3
-244.1µV
-1.99829V
-1.99927V
0
1
1
1
1
1
1
1
1
1
1
1
4
-FS + 1 / LSB
4
0
0
0
0
0
0
0
0
0
0
0
1
3
-Full Scale (-FS) +
/
LSB
0
0
0
0
0
0
0
0
0
0
0
0
4
† The voltages listed above represent the ideal center of each offset binary output code shown.
using a differential input. This low output impedance voltage
source is not designed to be a reference but makes an
excellent bias source and stays within the analog input
common mode voltage range over temperature.
Internal Reference Generator, V
and V
RIN
ROUT
The HI5808 has an internal reference generator, therefore, no
external reference voltage is required. V must be
ROUT
when using the internal reference voltage.
connected to V
RIN
The difference between the converter’s two internal voltage
references is 2V. For the AC coupled differential input, (Figure
The HI5808 can be used with an external reference. The
converter requires only one external reference voltage
15), if V is a 2V
sinewave with -V being 180 degrees out
IN
P-P
IN
connected to the V
pin with V
left open.
RIN
ROUT
of phase with V , then V + is a 2V
sinewave riding on a
IN IN
P-P
The HI5808 is tested with V
equal to 3.5V. Internal to the
DC bias voltage equal to V
DC
and V - is a 2V
sinewave
RIN
IN P-P
converter, two reference voltages of 1.3V and 3.3V are
generated for a fully differential input signal range of ±2V.
riding on a DC bias voltage equal to V . Consequently, the
DC
converter will be at positive full scale, all 1’s digital data output
code, when the V + input is at V
+1V and the V - input is
IN DC
IN
In order to minimize overall converter noise, it is
recommended that adequate high frequency decoupling be
at V
-1V (V +-V - = 2V). Conversely, the ADC will be
IN IN
DC
at negative full scale, all 0’s digital data output code, when
the V + input is equal to V -1V and V - is at V +1V
provided at the reference voltage input pin, V
.
RIN
IN IN DC
DC
Analog Input, Differential Connection
(V +-V - = -2V). From this, the converter is seen to have
IN IN
a peak-to-peak differential analog input voltage range of ±2V.
The analog input to the HI5808 can be configured in various
ways depending on the signal source and the required level
of performance. A fully differential connection (Figure 15) will
give the best performance for the converter.
The analog input can be DC coupled (Figure 16) as long as
the inputs are within the analog input common mode voltage
range (1.0V ≤ VDC ≤ 4.0V).
V
IN
V
+
V
IN
IN
V
+
IN
VDC
VDC
HI5808
R
R
HI5808
C
V
V
DC
V
V
DC
-V
IN
-V
IN
-
IN
-
IN
FIGURE 16. DC COUPLED DIFFERENTIAL INPUT
FIGURE 15. AC COUPLED DIFFERENTIAL INPUT
Since the HI5808 is powered off a single +5V supply, the
analog input must be biased so it lies within the analog input
common mode voltage range of 1.0V to 4.0V. The
The resistors, R, in Figure 16 are not absolutely necessary
but may be used as load setting resistors. A capacitor, C,
connected from V + to V - will help filter any high
IN IN
performance of the ADC does not change significantly with
the value of the analog input common mode voltage.
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
A 2.3V DC bias voltage source, V , half way between the
DC
top and bottom internal reference voltages, is made
available to the user to help simplify circuit design when
9
HI5808
Analog Input, Single-Ended Connection
Digital I/O and Clock Requirements
The configuration shown in Figure 17 may be used with a
single ended AC coupled input. Sufficient headroom must be
provided such that the input voltage never goes above +5V
The HI5808 provides a standard high-speed interface to
external TTL/CMOS logic families. The digital CMOS clock
input has TTL level thresholds. The low input bias current
allows the HI5808 to be driven by CMOS logic.
or below A
.
GND
The digital CMOS outputs have a separate digital supply. This
allows the digital outputs to operate from a 3.0V to 5.0V supply.
When driving CMOS logic, the digital outputs will swing to the
rails. When driving standard TTL loads, the digital outputs will
meet standard TTL level requirements even with a 3.0V supply.
V
+
V
IN
IN
HI5808
VDC
In order to ensure rated performance of the HI5808, the duty
cycle of the clock should be held at 50% ±5%. It must also
have low jitter and operate at standard TTL levels.
V
-
IN
Performance of the HI5808 will only be guaranteed at
conversion rates above 0.5MSPS. This ensures proper
performance of the internal dynamic circuits.
FIGURE 17. AC COUPLED SINGLE ENDED INPUT
Again, the difference between the two internal voltage
references is 2V. If V is a 4V
IN
sinewave, then V + is a
IN
P-P
sinewave riding on a positive voltage equal to VDC.
4V
Supply and Ground Considerations
P-P
The converter will be at positive full scale when V + is at
IN
The HI5808 has separate analog and digital supply and
ground pins to keep digital noise out of the analog signal path.
The part should be mounted on a board that provides
separate low impedance connections for the analog and
digital supplies and grounds. For best performance, the
supplies to the HI5808 should be driven by clean, linear
regulated supplies. The board should also have good high
frequency decoupling capacitors mounted as close as
possible to the converter. If the part is powered off a single
supply then the analog supply and ground pins should be
isolated by ferrite beads from the digital supply and ground
pins.
VDC + 2V (V + - V - = 2V) and will be at negative full
IN IN
scale when V + is equal to VDC - 2V (V + - V - = -2V).
IN IN IN
In this case, VDC could range between 2V and 3V without
a significant change in ADC performance. The simplest
way to produce VDC is to use the V
of the HI5808.
bias voltage output
DC
The single ended analog input can be DC coupled (Figure
18) as long as the input is within the analog input common
mode voltage range.
V
IN
Refer to the Application Note AN9214, “Using Intersil High
Speed A/D Converters” for additional considerations when
using high speed converters.
V
+
VDC
IN
R
HI5808
C
Static Performance Definitions
Offset Error (V
)
OS
VDC
V
-
IN
1
The midscale code transition should occur at a level / LSB
4
above half-scale. Offset is defined as the deviation of the
actual code transition from this point.
FIGURE 18. DC COUPLED SINGLE ENDED INPUT
Full-Scale Error (FSE)
The resistor, R, in Figure 18 is not absolutely necessary but
may be used as a load setting resistor. A capacitor, C,
The last code transition should occur for an analog input that
3
is
/ LSB below positive full scale with the offset error
4
connected from V + to V - will help filter any high
IN IN
removed. Full-scale error is defined as the deviation of the
actual code transition from this point.
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
Differential Linearity Error (DNL)
DNL is the worst case deviation of a code width from the
ideal value of 1 LSB.
A single ended source will give better overall system
performance if it is first converted to differential before
driving the HI5808.
Integral Linearity Error (INL)
INL is the worst case deviation of a code center from a best
fit straight line calculated from the measured data.
10
HI5808
distortion terms is calculated. The terms included in the
calculation are (f + f ), (f - f ), (2f ), (2f ), (2f + f ), (2f - f ),
Power Supply Rejection Ratio (PSRR)
1
2
1
2
1
2
1
2
1
2
Each of the power supplies are moved plus and minus 5%
and the shift in the offset and gain error (in LSBs) is noted.
(f + 2f ), (f - 2f ). The ADC is tested with each tone 6dB
1
2
1
2
below full scale.
Dynamic Performance Definitions
Transient Response
Fast Fourier Transform (FFT) techniques are used to
evaluate the dynamic performance of the HI5808. A low
distortion sine wave is applied to the input, it is coherently
sampled, and the output is stored in RAM. The data is then
transformed into the frequency domain with an FFT and
analyzed to evaluate the dynamic performance of the A/D.
The sine wave input to the part is -0.5dB down from full scale
for all these tests. SNR and SINAD are quoted in dB. The
distortion numbers are quoted in dBc (decibels with respect
to carrier) and DO NOT include any correction factors for
normalizing to full scale.
Transient response is measured by providing a full-scale
transition to the analog input of the ADC and measuring the
number of cycles it takes for the output code to settle within
12-bit accuracy.
Overvoltage Recovery
Overvoltage Recovery is measured by providing a full-scale
transition to the analog input of the ADC which overdrives the
input by 200mV, and measuring the number of cycles it takes
for the output code to settle within 12-bit accuracy.
Full Power Input Bandwidth (FPBW)
Full power input bandwidth is the analog input frequency at
which the amplitude of the digitally reconstructed output has
decreased 3dB below the amplitude of the input sinewave.
Signal-to-Noise Ratio (SNR)
SNR is the measured RMS signal to RMS noise at a
specified input and sampling frequency. The noise is the
RMS sum of all of the spectral components except the
fundamental and the first five harmonics.
The input sinewave has an amplitude which swings from -f to
S
+f . The bandwidth given is measured at the specified
S
sampling frequency.
Signal-to-Noise + Distortion Ratio (SINAD)
Timing Definitions
Refer to Figure 1, Internal Circuit Timing, and Figure 2, Input-
To-Output Timing, for these definitions.
SINAD is the measured RMS signal to RMS sum of all
other spectral components below the Nyquist frequency,
f /2, excluding DC.
S
Aperture Delay (t
)
AP
Effective Number Of Bits (ENOB)
Aperture delay is the time delay between the external sample
command (the falling edge of the clock) and the time at which
the signal is actually sampled. This delay is due to internal
clock path propagation delays.
The effective number of bits (ENOB) is calculated from the
SINAD data by:
ENOB = (SINAD + V
-1.76)/6.02,
CORR
Aperture Jitter (t
)
AJ
where: V
= 0.5dB.
CORR
Aperture Jitter is the RMS variation in the aperture delay due
to variation of internal clock path delays.
V
adjusts the ENOB for the amount the input is below
CORR
full scale.
Data Hold Time (t )
H
Data hold time is the time to where the previous data (N - 1)
is no longer valid.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first 5 harmonic
components to the RMS value of the fundamental input
signal.
Data Output Delay Time (t
)
OD
Data output delay time is the time to where the new data (N)
is valid.
2nd and 3rd Harmonic Distortion
This is the ratio of the RMS value of the applicable
harmonic component to the RMS value of the fundamental
input signal.
Data Latency (t
)
LAT
After the analog sample is taken, the digital data is output on
the bus at the third cycle of the clock. This is due to the
pipeline nature of the converter where the data has to ripple
through the stages. This delay is specified as the data
latency. After the data latency time, the data representing
each succeeding sample is output at the following clock
pulse. The digital data lags the analog input sample by 3
clock cycles.
Spurious Free Dynamic Range (SFDR)
SFDR is the ratio of the fundamental RMS amplitude to the
RMS amplitude of the next largest spur or spectral
component in the spectrum below f /2.
S
Intermodulation Distortion (IMD)
Nonlinearities in the signal path will tend to generate
intermodulation products when two tones, f and f , are
1
2
present at the inputs. The ratio of the measured signal to the
11
HI5808
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
0.25(0.010)
M
B M
H
AREA
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
17.70
7.40
MAX
2.65
0.30
0.51
0.32
18.10
7.60
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
0.7125
0.2992
-
-
1
2
3
L
9
SEATING PLANE
A
0.0091
0.6969
0.2914
-
3
-A-
o
h x 45
D
4
0.05 BSC
1.27 BSC
-
-C-
α
µ
H
h
0.394
0.01
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
0.016
6
0.25(0.010) M
C A M B S
N
α
28
28
7
o
o
o
o
0
8
0
8
-
NOTES:
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. How-
ever, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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12
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