IS31FL3741-QFLS4-TR [ISSI]
Display Driver,;
| 型号： | IS31FL3741-QFLS4-TR |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Display Driver, 驱动 接口集成电路 |
| 文件： | 总22页 (文件大小：561K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS31FL3741
39×9 DOTS MATRIX LED DRIVER
Preliminary Information
September 2017
GENERAL DESCRIPTION
FEATURES
The IS31FL3741 is a general purpose 39×9 LED
Matrix programmed via an I2C compatible interface.
Each LED can be dimmed individually with 8-bit PWM
data and 8-bit scaling data which allowing 256 steps
of linear PWM dimming and 256 steps of DC current
adjustable level.
Supply voltage range: 2.7V ~ 5.5V
39 Current Sink × 9 SW matrix size: drive up to
351 LEDs or 117 RGBs
Individual 256 PWM control steps
Individual 256 DC current steps
Global 255 current setting
SDB rising edge reset I2C module
Programmable H/L logic: 1.4/0.4, 2.4/0.6
29kHz PWM frequency
1MHz I2C-compatible interface
interrupt and state lookup registers
Individual open and short error detect function
De-ghost
Additionally each LED open and short state can be
detected, IS31FL3741 store the open or short
information in Open-Short Registers. The Open-Short
Registers allowing MCU to read out via I2C
compatible interface. Inform MCU whether there are
LEDs open or short and the locations of open or short
LEDs.
The IS31FL3741 operates from 2.7V to 5.5V and
features a very low shutdown and operational current.
QFN-60 (7mm×7mm) package
APPLICATIONS
IS31FL3741 is available in QFN-60 (7mm×7mm)
package. It operates from 2.7V to 5.5V over the
temperature range of -40°C to +125°C.
Mobile phones and other hand-held devices for
LED display
Gaming device (Keyboard, Mouse etc.)
LED in write goods application
Music box
TYPICAL APPLICATION CIRCUIT
5V
15
PVCC
24
23
SW9
1 F 0.1
1 F 0.1
1 F 0.1
F
F
F
25
14
SW8
PVCC
AVCC
SW2
SW1
SW3 SW4 SW5 SW6 SW7 SW8 SW9
17
16
SW2
SW1
20
20
20
CS39
CS38
CS37
VIO/MC
100k
1k
1k
9
10
7
SDA
SCL
INTB
SDB
IS31FL3741
Micro
Controller
11
6
5
20
20
20
CS39
CS38
CS3
CS2
CS1
100k
10k
0.1
F
13
8
R_EXT
ADDR
GND
27
26
CS2
CS1
12
36,55
Figure 1 Typical Application Circuit (Single Color: 39×9)
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Rev. 0B, 09/06/2017
IS31FL3741
TYPICAL APPLICATION CIRCUIT (CONTINUED)
Figure 2 Typical Application Circuit (RGB Color: 13×9)
Note: For the mobile applications the IC should be placed far away from the mobile antenna in order to prevent the EMI.
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Rev. 0B, 09/06/2017
IS31FL3741
PIN CONFIGURATION
Package Pin Configuration (Top View)
QFN-60
PIN DESCRIPTION
No.
Pin
Descrpton
26~35,37~54,
56~60,1~6
CS1~CS39
Current sink pin for LED matrix.
Interrupt output pin. Register F0h sets the function of the
INTB pin and active low when the interrupt event
7
INTB
happens. Can be NC (float) if interrupt function no used.
8
ADDR
SDA
I2C address select pin.
9
I2C compatible serial data.
I2C compatible serial clock.
Shutdown pin.
10
SCL
11
SDB
12,36,55
13
GND
Power GND (36, 55) and analog GND pin (12).
IOUT setting register.
R_EXT
AVCC
PVCC
SW1~SW9
14
Power for analog and digital circuits.
Power for current source.
15,25
16~24
Source/switch pin for LED matrix.
Thermal Pad Need to connect to GND pins in PCB.
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IS31FL3741
ORDERING INFORMATION
Industrial Range: -40°C to +125°C
Order Part No.
Package
QTY/Reel
IS31FL3741-QFLS4-TR
QFN-60, Lead-free
2500
Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any
time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are
advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the
product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not
authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
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Rev. 0B, 09/06/2017
IS31FL3741
ABSOLUTE MAXIMUM RATINGS
Supply voltage, VCC
-0.3V ~+6.0V
-0.3V ~ VCC+0.3V
150°C
-65°C ~+150°C
-40°C ~ +125°C
33.08°C/W
±2kV
Voltage at any input pin
Maximum junction temperature, TJMAX
Storage temperature range, TSTG
Operating temperature range, TA=TJ
Thermal resistance, junction to ambient, θJA
ESD (HBM)
ESD (CDM)
±1kV
Note:
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
The following specifications apply for VCC= 3.6V, TA= 25°C, unless otherwise noted.
Symbol
Parameter
Supply voltage
Conditions
Min.
Typ.
Max. Unit
VCC
ICC
2.7
5.5
6
V
Quiescent power supply current
VSDB=VCC, all LEDs off
4.5
2
mA
VSDB=0V
5
ISD
Shutdown current
μA
VSDB= VCC, Configuration Register
written “0000 0000
2
5
Maximum constant current of
CS1~CS39
REXT=10kΩ, GCC=0xFF,
SL=0xFF
IOUT
ILED
38
mA
mA
Average current on each LED
REXT=10kΩ, GCC=0xFF,
SL=0xFF
3.75
400
ILED = IOUT/10.125
Current switch headroom voltage
SW1~SW9
ISWITCH=1A (Note 1, 2)
VHR
mV
Current sink headroom voltage
CS1~CS39
ISINK=38mA (Note 1)
300
32
tSCAN Period of scanning
Non-overlap blanking time during
tNOL1 scan, the SWx and CSy are all off
during this time
µs
µs
2
2
Delay total time for CS1 to CS39,
tNOL2 during this time, the SWx is on
but CSx is not all turned on
µs
Logic Electrical Characteristics (SDA, SCL, ADDR, SDB)
VCC=2.7V, LGC=0
0.4
0.6
VIL
VIH
Logic “0” input voltage
Logic “1” input voltage
V
V
V
VCC=2.7V, LGC=1
VCC=5.5V, LGC=0
VCC=5.5V, LGC=1
VCC=3.6V, LGC=0
VCC=3.6V, LGC=1
VINPUT= L (Note 4)
VINPUT= H (Note 4)
1.4
2.4
0.2
0.2
VHYS Input schmitt trigger hysteresis
IIL
Logic “0” input current
Logic “1” input current
nA
nA
IIH
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IS31FL3741
DIGITAL INPUT SWITCHING CHARACTERISTICS (NOTE 3)
Fast Mode
Fast Mode Plus
Symbol
Parameter
Units
Min. Typ. Max. Min. Typ. Max.
fSCL
tBUF
Serial-clock frequency
-
400
-
-
1000 kHz
Bus free time between a STOP and a START
condition
1.3
0.5
-
μs
tHD, STA Hold time (repeated) START condition
tSU, STA Repeated START condition setup time
tSU, STO STOP condition setup time
tHD, DAT Data hold time
0.6
0.6
0.6
-
-
0.26
0.26
0.26
-
-
μs
μs
μs
μs
ns
μs
μs
ns
ns
-
-
-
-
-
-
tSU, DAT Data setup time
100
1.3
0.7
-
-
-
50
-
-
tLOW
tHIGH
tR
SCL clock low period
0.5
0.26
-
SCL clock high period
-
-
Rise time of both SDA and SCL signals, receiving
Fall time of both SDA and SCL signals, receiving
300
300
120
120
tF
-
-
Note 1: Global Current Control Register (GCC, PG4, 01h) written “1111 1111”, SL written “1111 1111”, REXT=10kΩ.
Note 2: All LEDs PWM=“1111 1111”, GCC = “0xFF”.
Note 3: Guaranteed by design.
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IS31FL3741
DETAILED DESCRIPTION
I2C INTERFACE
Following acknowledge of IS31FL3741, the register
address byte is sent, most significant bit first.
IS31FL3741 must generate another acknowledge
indicating that the register address has been received.
The IS31FL3741 uses a serial bus, which conforms to
the I2C protocol, to control the chip’s functions with
two wires: SCL and SDA. The IS31FL3741 has a 7-bit
slave address (A7:A1), followed by the R/W bit, A0.
Set A0 to “0” for a write command and set A0 to “1” for
a read command. The value of bits A1 and A2 are
decided by the connection of the ADDR pin.
Then 8-bit of data byte are sent next, most significant
bit first. Each data bit should be valid while the SCL
level is stable high. After the data byte is sent, the
IS31FL3741 must generate another acknowledge to
indicate that the data was received.
Table 1 Slave Address
The “STOP” signal ends the transfer. To signal
“STOP”, the SDA signal goes high while the SCL
signal is high.
Bit
A7:A3
A2:A1
ADDR
A0
Value
01100
0/1
ADDRESS AUTO INCREMENT
ADDR connects to GND, ADDR= 00;
ADDR connects to VCC, ADDR= 11;
ADDR connects to SCL, ADDR= 01;
ADDR connects to SDA, ADDR= 10;
To write multiple bytes of data into IS31FL3741, load
the address of the data register that the first data byte
is intended for. During the IS31FL3741 acknowledge
of receiving the data byte, the internal address pointer
will increment by one. The next data byte sent to
IS31FL3741 will be placed in the new address, and so
on. The auto increment of the address will continue as
long as data continues to be written to IS31FL3741
(Figure 6).
The SCL line is uni-directional. The SDA line is bi-
directional (open-collector) with a pull-up resistor
(typically 400kHz IIC with 4.7kꢀ, 1MHz IIC with 1kꢀ).
The maximum clock frequency specified by the I2C
standard is 1MHz. In this discussion, the master is the
microcontroller and the slave is the IS31FL3741.
READING OPERATION
The timing diagram for the I2C is shown in Figure 3.
The SDA is latched in on the stable high level of the
SCL. When there is no interface activity, the SDA line
should be held high.
Most of the registers can be read.
To read the FCh, FEh, F0h and F1h, after I2C start
condition, the bus master must send the IS31FL3741
The “START” signal is generated by lowering the SDA
signal while the SCL signal is high. The start signal will
alert all devices attached to the I2C bus to check the
incoming address against their own chip address.
____
device address with the R/W bit set to “0”, followed by
the register address (FEh or F1h) which determines
which register is accessed. Then restart I2C, the bus
master should send the IS31FL3741 device address
____
The 8-bit chip address is sent next, most significant bit
first. Each address bit must be stable while the SCL
level is high.
with the R/W bit set to “1”. Data from the register
defined by the command byte is then sent from the
IS31FL3741 to the master (Figure 7).
After the last bit of the chip address is sent, the master
checks for the IS31FL3741’s acknowledge. The
master releases the SDA line high (through a pull-up
resistor). Then the master sends an SCL pulse. If the
IS31FL3741 has received the address correctly, then it
holds the SDA line low during the SCL pulse. If the
SDA line is not low, then the master should send a
“STOP” signal (discussed later) and abort the transfer.
To read the registers of Page 0 thru Page 5, the FDh
should write with 00h before follow the Figure 7
sequence to read the data. That means, when you
want to read register of Page 0, the FDh should point
to Page 0 first and you can read the Page 0 data.
SDA
t
SU,DAT
tHD,DAT
tSU,STA
tHD,STA
tSU,STO
tBUF
tLOW
S
tHIGH
R
P
SCL
tHD,STA
t
R
tF
Start Condition
Restart Condition
Figure 3 Interface Timing
Stop Condition Start Condition
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IS31FL3742
Figure 4 Bit Transfer
gure 5 Writing to IS31FL3741 (Typic
Figure 6 iinS31FL3741 omatic address increment)
Figure 7 Reading from IS31FL3741
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IS31FL3742
Table 2 Register Definition-1
Address
Name
Function
Table R/W
Default
FDh
FEh
F0h
F1h
Command Register
Available Page 0 to Page 4 registers
3
4
5
6
W
R/W
W
0000 0000
Command Register Write Lock To lock/unlock Command Register
Interrupt Mask Register
Interrupt Status Register
Configure the interrupt function
Show the interrupt status
0000 0000
R
Slave
Address
FCh
ID Register
For read the product ID only
-
R
REGISTER CONTROL
Table 3 FDh Command Register (Write Only)
Data
Function
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
Others
Point to Page 0 (PG0, PWM Register 1 is available)
Point to Page 1 (PG1, PWM Register 2 is available)
Point to Page 2 (PG2, Scaling Register 1 is available)
Point to Page 3 (PG3, Scaling Register 2 is available)
Point to Page 4 (PG4, Function Register is available)
Not allowed
Note: FDh is locked when power up, need to unlock this register before write command to it. See Table 4 for detail.
The Command Register should be configured first after writing in the slave address to choose the available register. Then write data in the
choosing register. Power up default state is “0000 0000”.
For example, when write “0000 0010” in the Command Register (FDh), the data which writing after will be stored in the page 2 Registers. Write
new data can configure other frame position.
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IS31FL3741
Table 4 FEh Command Register Write Lock
(Read/Write)
Table 6 F1h Interrupt Status Register (Read Only)
Bit
D7:D2
D1
D0
Bit
D7:D0
Name
-
SB
0
OB
0
Name
CRWL
Default
0000 00
Default
0000 0000
Show the interrupt status for IC.
To select the PG0~PG4, need to unlock this register
first, with the purpose to avoid mis-operation of this
register. When FEh is written with “1100 0101”, FDh
is allowed to modify once, after the FDh is modified
the FEh will reset to be “0000 0000” at once.
SB
0
1
Short Bit
No short
Short happens
OB
0
1
Open Bit
No open
Open happens
CRWL
0000 0000
1100 0101
Command Register Write Lock
FDh write disable
FDh write enable once
FCh ID Register
Table 5 F0h Interrupt Mask Register (Write Only)
ID register is read only and read result is the device
slave address. For example, if ADDR pin connects to
GND, read result is 0x60.
Bit
D7:D5
D4
D3:D2
D1
D0
Name
-
IAC
0
-
IS
0
IO
0
Default
000
00
Configure the interrupt function for IC.
IAC
0
Auto Clear Interrupt Bit
Interrupt could not auto clear
1
Interrupt auto clear when INTB stay low
exceeds 8ms
IS
0
1
Dot Short Interrupt Bit
Disable dot short interrupt
Enable dot short interrupt
IO
0
1
Dot Open Interrupt Bit
Disable dot open interrupt
Enable dot open interrupt
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IS31FL3741
Table 7 Register Definition-2
Address
Name
Function
Table R/W
Default
PG0 (0x00): PWM Register 1
00h~B3h PWM Register
PG1 (0x01): PWM Register 2
00h~AAh PWM Register
PG2 (0x02): LED Scaling 1
00h~B3h Scaling Register
PG3 (0x03): LED Scaling 2
00h~AAh Scaling Register
PG4 (0x04): Function Register
Set PWM for each LED
Set PWM for each LED
Set Scaling for each LED
Set Scaling for each LED
8
8
9
9
R/W 0000 0000
R/W 0000 0000
R/W 0000 0000
R/W 0000 0000
00h
01h
Configuration Register
Configure the operation mode
Set the global current
11
12
R/W 0000 0000
R/W 0000 0000
Global Current Control
Register
Pull Down/Up Resistor
Selection Register
Set the pull down resistor for SWx and
pull up resistor for CSy
02h
13
R/W 0101 0101
03h~2Fh Open/Short Register
3Fh Reset Register
Store the open or short information
Reset all register to POR state
14
-
R
0000 0000
0000 0000
W
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IS31FL3741
Page 0/1 (PG0/PG1, FDh= 0x00/0x01): PWM Register 1/2
Fgue 8 PWM Regier
Table 8
32s
32s2s2s
1
1
Duty
9 10.125
(2)
PG0: 00h ~ B3h PWM Register
PG1: 00h ~ AAh PWM Register
IOUT is the output current of CSy (y=1~39),
Bit
D7:D0
383 GCC SL
Name
PWM
IOUT(PEAK)
(3)
REXT 256 256
Default
0000 0000
GCC is the Global Current Control register (PG4,
Each dot has a byte to modulate the PWM duty in
256 steps.
01h) value, SL is the Scaling Register value as Table
9 and REXT is the external resistor of R_EXT pin. D[n]
stands for the individual bit value, 1 or 0, in location
n.
The value of the PWM Registers decides the
average current of each LED noted ILED
.
ILED computed by Formula (1):
For example: if D7:D0=1011 0101 (0xB5, 181),
GCC=1111 1111, REXT=10kꢀ, SL=1111 1111:
PWM
I LED
IOUT (PEAK ) Duty
(1)
383 255 255
1
181
256
I LED
2.54mA
7
10k 256 256 10.125 256
PWM
D[n] 2n
n0
Where Duty is the duty cycle of SWx,
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IS31FL3741
Page 2/3 (PG2/PG3, FDh= 0x02/0x03): Scaling Register 1/2
Fgure Scaling Regter
Table 9
IOUT is the output current of CSy (y=1~39), GCC is
the Global Current Control Register (PG4, 01h)
value and REXT is the external resistor of R_EXT pin.
D[n] stands for the individual bit value, 1 or 0, in
location n.
PG2: 00h ~ B3h Scaling Register
PG3: 00h ~ AAh Scaling Register
Bit
D7:D0
Name
SL
For example: if REXT=10kꢀ, GCC=1111 1111,
SL=0111 1111:
Default
0000 0000
7
Scaling register control the DC output current of
each dot. Each dot has a byte to modulate the
scaling in 256 steps.
SL
D[n] 2n 127
n0
383
255 127
The value of the Scaling Register decides the peak
IOUT
18.93mA
current of each LED noted IOUT
.
10k 256 256
I
OUT computed by Formula (3):
1
PWM
ILED 18.93mA
10.125
256
383 GCC SL
IOUT(PEAK)
(3)
REXT 256 256
7
SL
D[n] 2n
n0
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IS31FL3741
Table 10 Page 4 (PG4, FDh= 0x04): Function Register
Register
Name
Function
Table R/W
Default
00h
01h
Configuration Register
Configure the operation mode
11
12
R/W 0000 0000
R/W 0000 0000
Global Current Control Register Set the global current
Pull Down/Up Resistor Selection Set the pull down resistor for SWx
02h
13
R/W 0101 0101
Register
and pull up resistor for CSy
03h~2Fh Open/Short Register
3Fh Reset Register
Store the open or short information
Reset all register to POR state
14
-
R
0000 0000
0000 0000
W
Table 11 00h Configuration Register
SWS control the duty cycle of the SW, default mode is
1/9.
Bit
D7:D4
D3
D2:D1
D0
Name
SWS
0000
LGC
0
OSDE
00
SSD
0
Table 12 01h Global Current Control Register
Default
Bit
D7:D0
The Configuration Register sets operating mode of
IS31FL3741.
Name
GCC
Default
0000 0000
The Global Current Control Register modulates all
CSy (x=1~39) DC current which is noted as IOUT in
256 steps.
SSD
0
1
Software Shutdown Control
Software shutdown
Normal operation
IOUT is computed by the Formula (3):
OSDE Open Short Detection Enable
00 Disable open/short detection
01/11 Enable open detection
10 Enable short detection
383 GCC SL
IOUT(PEAK)
(3)
REXT 256 256
7
GCC
D[n] 2n
n0
LGC H/L Logic
Where D[n] stands for the individual bit value, 1 or 0,
in location n.
0
1
1.4V/0.4V
2.4V/0.6V
Table 13 02h Pull Down/Up Resistor Selection
Register
SWS SWx Setting
0000 SW1~SW9, 1/9
0001 SW1~SW8, 1/8, SW9 no-active
0010 SW1~SW7, 1/7, SW8~SW9 no-active
0011 SW1~SW6, 1/6, SW7~SW9 no-active
0100 SW1~SW5, 1/5, SW6~SW9 no-active
0101 SW1~SW4, 1/4, SW5~SW9 no-active
0110 SW1~SW3, 1/3, SW4~SW9 no-active
Bit
D7
D6:D4
D3
D2:D0
Name
-
PDR
101
-
PUR
101
Default
0
0
Set pull down resistor for SWx and pull up resistor for
CSy.
0111
SW1~SW2, 1/2, SW3~SW9 no-active
1000 All CSx work as current sinks only, no scan
Others 1/9
PUR SWx Pull Up Resistor Selection Bit
000
001
010
011
100
101
110
111
No pull down resistor
0.5kꢀ
1.0kꢀ
2.0kꢀ
4.0kꢀ
8.0kꢀ
16kꢀ
32kꢀ
When OSDE set to “01”, open detection will be trigger
once, the user could trigger open detection again by
set OSDE from “00” to “01”.
When OSDE set “10”, short detection will be trigger
once, the user could trigger short detection again by
set OSDE from “00” to “10”.
When SSD is “0”, IS31FL3741 works in software
shutdown mode and to normal operate the SSD bit
should set to “1”.
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IS31FL3741
PDR CSy Pull Down Resistor Selection Bit
When OSDE (PG4, 00h) is set to “01”, open detection
will be trigger once, and the open information will be
stored at 03h~2Fh.
000
001
010
011
100
101
110
111
No pull up resistor
0.5kꢀ
1.0kꢀ
2.0kꢀ
4.0kꢀ
8.0kꢀ
16kꢀ
32kꢀ
When OSDE (PG4, 00h) set to “10”, short detection
will be trigger once, and the short information will be
stored at 03h~2Fh.
Before set OSDE, the GCC should set to 0x01.
Table 14-1 Open/Short Register (Read Only)
03h~06h Open/Short Information
08h~0Bh Open/Short Information
0Dh~10h Open/Short Information
12h~15h Open/Short Information
17h~1Ah Open/Short Information
1Ch~1Fh Open/Short Information
21h~24h Open/Short Information
26h~29h Open/Short Information
2Bh~2Eh Open/Short Information
Bit
D7:D0
CS8:CS1;CS16:CS9;CS24:CS17;CS32:C
S25 (MSB:LSB)
Name
Default
0000 0000
07h Open/Short Information
0Ch Open/Short Information
11h Open/Short Information
16h Open/Short Information
1Bh Open/Short Information
20h Open/Short Information
25h Open/Short Information
2Ah Open/Short Information
2Fh Open/Short Information
Figure 10 Open/Short Register
Table 14-2 Open/Short Register (Read Only)
3Fh Reset Register
Bit
D7
D6:D0
Once user writes the Reset Register with 0xAE,
IS31FL3741 will reset all the IS31FL3741 registers to
their default value. On initial power-up, the
IS31FL3741 registers are reset to their default values
for a blank display.
Name
-
CS39:CS33
0000 000
Default
0
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IS31FL3741
APPLICATION INFORMATION
383 GCC SL
IOUT (PEAK
)
REXT
256 256
Figure 11 Scng ng
1
PWM
SCANING TIMING
ILED 38mA
10.125
256
As shown in Figure 11, the SW1~SW9 is turned on by
serial, LED is driven 9 by 9 within the SWx (x=1~9) on
time (SWx, x=1~9) is sink and pull low when LED on) ,
including the non-overlap blanking time during scan,
the duty cycle of SWx (active low, x=1~9) is:
Writing new data continuously to the registers can
modulate the brightness of the LEDs to achieve a
breathing effect.
GAMMA CORRECTION
32s
32s2s2s
1
1
In order to perform a better visual LED breathing
effect we recommend using a gamma corrected PWM
value to set the LED intensity. This results in a
reduced number of steps for the LED intensity setting,
but causes the change in intensity to appear more
linear to the human eye.
Duty
9 10.125
(2)
Where 32μs is tSCAN, the period of scanning and 2μs is
tNOL1 and tNOL2, the non-overlap time and CSx delay
time.
PWM CONTROL
Gamma correction, also known as gamma
compression or encoding, is used to encode linear
luminance to match the non-linear characteristics of
display. Since the IS31FL3741 can modulate the
brightness of the LEDs with 256 steps, a gamma
correction function can be applied when computing
each subsequent LED intensity setting such that the
changes in brightness matches the human eye's
brightness curve.
After setting the IOUT and GCC, the brightness of each
LEDs (LED average current (ILED)) can be modulated
with 256 steps by PWM Register, as described in
Formula (1).
PWM
ILED
IOUT (PEAK ) Duty
(1)
256
Where PWM is PWM Registers (PG0, 00h~B3h /PG1,
00h~AAh) data showing in Table 8.
For example, in Figure 1, if REXT= 10kꢀ, PWM= 255,
and GCC= 255, Scaling= 255, then
383 255 255
IOUT ( PEAK )
38mA
10k 256 256
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IS31FL3741
Table 21 32 Gamma Steps with 256 PWM Steps
256
224
192
160
128
96
C(0)
0
C(1)
1
C(2)
2
C(3)
4
C(4)
6
C(5)
10
C(6)
13
C(7)
18
C(8)
22
C(9)
28
C(10) C(11) C(12) C(13) C(14) C(15)
33 39 46 53 61 69
C(16) C(17) C(18) C(19) C(20) C(21) C(22) C(23)
78 86 96 106 116 126 138 149
C(24) C(25) C(26) C(27) C(28) C(29) C(30) C(31)
64
161
173
186
199
212
226
240
255
256
224
192
160
128
96
32
0
0
8
16
24
32
40
48
56
64
Intensity Steps
Figure 13 Gamma Correction (64 Steps)
Note: The data of 32 gamma steps is the standard value and the
data of 64 gamma steps is the recommended value.
OPERATING MODE
PWM Mode
64
32
IS31FL3741can only operate in PWM Mode. The
brightness of each LED can be modulated with 256
steps by PWM registers. For example, if the data in
PWM Register is “0000 0100”, then the PWM is the
fourth step.
0
0
4
8
12
16
20
24
28
32
Intensity Steps
Figure 12 Gamma Correction (32 Steps)
Writing new data continuously to the registers can
modulate the brightness of the LEDs to achieve a
breathing effect.
Choosing more gamma steps provides for a more
continuous looking breathing effect. This is useful for
very long breathing cycles. The recommended
configuration is defined by the breath cycle T. When
T=1s, choose 32 gamma steps, when T=2s, choose
64 gamma steps. The user must decide the final
number of gamma steps not only by the LED itself, but
also based on the visual performance of the finished
product.
De-Ghost Function
The “ghost” term is used to describe the behavior of
an LED that should be OFF but instead glows dimly
when another LED is turned ON. A ghosting effect
typically can occur when multiplexing LEDs. In matrix
architecture any parasitic capacitance found in the
constant-current outputs or the PCB traces to the
LEDs may provide sufficient current to dimly light an
LED to create a ghosting effect.
Table 22 64 Gamma Steps with 256 PWM Steps
C(0)
0
C(1)
1
C(2)
2
C(3)
3
C(4)
4
C(5)
5
C(6)
6
C(7)
7
To prevent this LED ghost effect, the IS31FL3741 has
integrated Pull down resistors for each SWx (x=1~9)
and Pull up resistors for each CSy (y=1~39). Select
the right SWx Pull down resistor (PG4, 02h) and CSy
Pull up resistor (PG4, 02h) which eliminates the ghost
LED for a particular matrix layout configuration.
C(8)
8
C(9)
10
C(10) C(11) C(12) C(13) C(14) C(15)
12 14 16 18 20 22
C(16) C(17) C(18) C(19) C(20) C(21) C(22) C(23)
24 26 29 32 35 38 41 44
C(24) C(25) C(26) C(27) C(28) C(29) C(30) C(31)
47 50 53 57 61 65 69 73
C(32) C(33) C(34) C(35) C(36) C(37) C(38) C(39)
77 81 85 89 94 99 104 109
C(40) C(41) C(42) C(43) C(44) C(45) C(46) C(47)
114 119 124 129 134 140 146 152
C(48) C(49) C(50) C(51) C(52) C(53) C(54) C(55)
158 164 170 176 182 188 195 202
C(56) C(57) C(58) C(59) C(60) C(61) C(62) C(63)
209 216 223 230 237 244 251 255
Typically, selecting the 32kꢀ will be sufficient to
eliminate the LED ghost phenomenon.
The SWx Pull down resistors and CSy Pull up
resistors are active only when the CSy/SWx output
working the OFF state and therefore no power is lost
through these resistors.
SHUTDOWN MODE
Shutdown mode can be used as a means of reducing
power consumption. During shutdown mode all
registers retain their data.
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IS31FL3741
Software Shutdown
LAYOUT
As described in external resistor (REXT), the chip
consumes lots of power. Please consider below
factors when layout the PCB.
By setting SSD bit of the Configuration Register (PG4,
00h) to “0”, the IS31FL3741 will operate in software
shutdown mode. When the IS31FL3741 is in software
shutdown, all current sources are switched off, so that
the matrix is blanked. All registers can be operated.
Typical current consume is 3μA.
1. The VCC (PVCC, AVCC) capacitors need to close to
the chip and the ground side should well connected to
the GND of the chip.
Hardware Shutdown
2. REXT should be close to the chip and the ground
side should well connect to the GND of the chip.
The chip enters hardware shutdown when the SDB pin
is pulled low. All analog circuits are disabled during
hardware shutdown, typical the current consume is
2μA.
3. The thermal pad should connect to ground pins and
the PCB should have the thermal pad too, usually this
pad should have 16 or 25 via thru the PCB to other
side’s ground area to help radiate the heat. About the
thermal pad size, please refer to the land pattern of
each package.
The chip releases hardware shutdown when the SDB
pin is pulled high. During hardware shutdown state
Function Register can be operated.
4. The CSy pins maximum current is 38mA
(REXT=10kꢀ), and the SWx pins maximum current is
larger, the width of the trace, SWx should have wider
trace then CSy.
If VCC has risk drop below 1.75V but above 0.1V
during SDB pulled low, please re-initialize all Function
Registers before SDB pulled high.
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Rev. 0B, 09/06/2017
IS31FL3741
CLASSIFICATION REFLOW PROFILES
Profile Feature
Pb-Free Assembly
Preheat & Soak
150°C
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
200°C
60-120 seconds
Average ramp-up rate (Tsmax to Tp)
3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL)
217°C
60-150 seconds
Peak package body temperature (Tp)*
Max 260°C
Time (tp)** within 5°C of the specified
classification temperature (Tc)
Max 30 seconds
Average ramp-down rate (Tp to Tsmax)
Time 25°C to peak temperature
6°C/second max.
8 minutes max.
Figure 14 Classification Profile
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Rev. 0B, 09/06/2017
IS31FL3741
PACKAGE INFORMATION
QFN-60
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Rev. 0B, 09/06/2017
IS31FL3741
RECOMMENDED LAND PATTERN
QFN-60
Note:
1. Land pattern complies to IPC-7351.
2. All dimensions in MM.
3. This document (including dimensions, notes & specs) is a recommendation based on typical circuit board manufacturing parameters. Since
land pattern design depends on many factors unknown (eg. user’s board manufacturing specs), user must determine suitability for use.
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Rev. 0B, 09/06/2017
IS31FL3741
REVISION HISTORY
Revision
Detail Information
Date
0A
0B
Initial release
2017.06.02
1. Update the ILED formula
2. Update Land Pattern and θJA
3. Update Logic Electrical Characteristics Table
4. Update Figure 1 and Figure 2
2017.09.06
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Rev. 0B, 09/06/2017
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