IS31IO7328-QFLS4-TR [ISSI]
Buffer/Inverter Based Peripheral Driver, LEAD FREE, QFN-16;
| 型号： | IS31IO7328-QFLS4-TR |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Buffer/Inverter Based Peripheral Driver, LEAD FREE, QFN-16 驱动 接口集成电路 |
| 文件： | 总13页 (文件大小：362K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS31IO7328
MULTI-FUNCTION I/O DRIVER
January 2014
GENERAL DESCRIPTION
FEATURES
The IS31IO7328 2-wire serial-interfaced peripheral
features 8 I/O ports. Ports are divided into four push
pull I/Os and four open-drain I/Os and transition
detection.
400kHz I2C serial interface
2.4V to 5.5V operation
4 push-pull I/O ports
4 open-drain I/O ports, rated to 20mA sink current
at 0.22V headroom
Selectable I/O port power-up default logic states
INTB output alerts change on inputs
Low 0.3μA (Typ.) standby current
Any of the 8 I/O ports can be configured as an input or
an output. All I/O ports configured as inputs are
continuously monitored for state changes (transition
detection). State changes are indicated by the INTB
output. The interrupt is latched, allowing detection of
transient changes. When the IS31IO7328 is
subsequently read through the serial interface, any
pending interrupt is cleared.
-40°C to +125°C temperature range
APPLICATIONS
Cell phones
Notebooks
SAN/NAS
Satellite radio
Servers
The open-drain outputs are rated to sink 20mA at
0.22V headroom, and are capable of driving LEDs.
The RSTB input clears the serial interface, terminating
any I2C communication to or from the IS31IO7328. The
IS31IO7328 uses two address inputs to allow 2 I2C
slave addresses. The slave address also determines
the power-up logic state for the I/O ports.
Automotive
TYPICAL APPLICATION CIRCUIT
Figure 1 Typical Application Circuit
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Rev. B, 01/03/2014
1
IS31IO7328
PIN CONFIGURATION
Package
Pin Configuration (Top View)
AD
RSTB
INTB
VCC
PP2
PP1
PP0
OD3
1
2
3
4
12
11
10
9
QFN-16
PIN DESCRIPTION
No.
Pin
Description
1
AD
Address Inputs. Select device slave address with AD.
Reset Input, active Low. Drive RSTB pin low to clear the
2-wire interface.
2
3
4
RSTB
INTB
VCC
Interrupt output, active Low. This is an open-drain output.
Positive supply voltage. Bypass VCC to GND with a ceramic
capacitor of at least 1μF.
5,14
6~9
10~13
15
GND
OD0~OD3
PP0~PP3
SCL
Ground.
Open-drain I/O ports.
CMOS push-pull I/O ports.
I2C-compatible serial-clock input.
I2C-compatible serial-data I/O.
16
SDA
Thermal Pad Connect to GND.
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Rev. B, 01/03/2014
IS31IO7328
ORDERING INFORMATION
Industrial Range: -40°C to +125°C
Order Part No.
Package
QTY/Reel
2500
IS31IO7328-QFLS4-TR
QFN-16, Lead-free
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any
time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are
advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the
product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not
authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
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Rev. B, 01/03/2014
IS31IO7328
ABSOLUTE MAXIMUM RATINGS
Supply voltage, VCC
Voltage at any input pin
SCL, SDA, AD, RSTB, INTB, OD0~OD3
PP0~PP3
PP source output current
PP/OD sink current
-0.3V ~ +6.0V
-0.3V ~ VCC+0.3V
-0.3V ~ +6.0V
-0.3V ~ VCC+0.3V
±100mA
120mA
SDA sink current
10mA
INTB sink current
10mA
Maximum junction temperature, TJMAX
Storage temperature range, TSTG
Operating temperature range, TA
ESD (HBM)
150°C
-65°C ~ +150°C
−40°C ~ +125°C
4kV
ESD (CDM)
1kV
Note:
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
TA = -40°C ~ +125°C, VCC = 2.4V ~ 5.5V, unless otherwise noted.
Typical values are at VCC = 3.3V, TA = 25°C. (Note 1)
Symbol
Parameter
Supply voltage
Condition
Min.
Typ. Max.
Unit
VCC
2.4
5.5
2.35
2.3
V
V
CC falling, TA = -40°C
VPOR
Power-on-reset voltage
V
VCC falling, TA = -20°C
SCL and SDA and other digital
inputs at VCC
ISTB
I+
Standby current (Interface idle)
Supply current (Interface running)
0.3
8
1.9
20
μA
μA
V
fSCL = 400kHz, other digital
inputs at VCC
Input high-voltage, SDA, SCL, AD,
RSTB, OD0~OD3, PP0~PP3
VIH
VIL
1.4
Input low-voltage, SDA, SCL, AD,
RSTB, OD0~OD3, PP0~PP3
0.4
V
SDA, SCL, AD, RSTB,
OD0~OD3, PP0~PP3 at VCC or -0.2
GND.
Input leakage current, SDA, SCL,
AD, RSTB, OD0~OD3, PP0~PP3
IIH, IIL
+0.2
μA
Input capacitance, SDA, SCL, AD,
RSTB, OD0~OD3, PP0~PP3
CIN
(Note 3)
10
pF
V
CC = 2.5V, ISINK = 10mA
200
240
250
Output low voltage, PP0~PP3,
OD0~OD3
VOL
VCC = 3.3V, ISINK = 15mA
VCC = 5.0V, ISINK = 20mA
mV
mV
V
CC = 2.5V, ISOURCE = 5mA
2.2
3.1
Output high voltage
PP0~PP3
VOH
VCC = 3.3V, ISOURCE = 5mA
VCC = 5.0V, ISOURCE = 10mA
ISINK = 6mA
4.72
VOLSDA
VOLINTB
Output low-voltage SDA
Output low-voltage INTB
180
180
mV
mV
ISINK = 5mA
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Rev. B, 01/03/2014
IS31IO7328
TIMING CHARACTERISTICS
VCC = 2.4V ~ 5.5V, unless otherwise noted. Typical values are at VCC = 3.3V, TA = 25°C. (Note 3)
Symbol
Parameter
Serial-clock frequency
Condition
Min.
Typ.
Max.
Unit
fSCL
400
kHz
Bus free time between a STOP and a
START Condition
tBUF
1.3
μs
tHD, STA
tSU, STA
tSU, STO
tHD, DAT
tSU, DAT
tLOW
Hold time (repeated) START condition
Repeated START condition setup time
STOP condition setup time
Data hold time
0.6
0.6
0.6
μs
μs
μs
μs
ns
μs
μs
(Note 2)
0.9
Data setup time
100
1.3
0.7
SCL clock low period
tHIGH
SCL clock high period
Rise time of both SDA and SCL signals,
receiving
tR
tF
(Note 4)
(Note 4)
20+0.1Cb
20+0.1Cb
300
ns
ns
Fall time of both SDA and SCL signals,
receiving
300
250
tF, TX
tSP
Cb
Fall time of SDA transmitting
Pulse width of spike suppressed
Capacitive load for each bus line
RSTB pulse width
(Note 4)
(Note 5)
20+0.1Cb
50
ns
ns
pF
ns
400
tW
500
1
RSTB rising to START condition setup
time
tRSTB
μs
PORT AND INTERRUPT INTB TIMING CHARACTERISTIC
CC = 2.4V ~ 5.5V, unless otherwise noted. Typical values are at VCC = 3.3V, TA = 25°C. (Note 3)
V
Parameter
Port Output Data Valid
Symbol
Condition
Min.
Typ.
Max.
Unit
tPV
tPSU
tPH
tIV
CL≤ 100pF
CL≤ 100pF
CL≤ 100pF
CL≤ 100pF
CL≤ 100pF
4
μs
μs
μs
μs
μs
Port Input Setup Time
0
4
Port Input Hold Time
INTB Input Data Valid Time
INTB Reset Delay Time from Acknowledge
4
4
tIR
Note 1: All parameters are tested at TA = 25°C. Specifications over temperature are guaranteed by design.
Note 2: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to bridge the
undefined region of SCL’s falling edge.
Note 3: Guaranteed by design.
Note 4: Cb = total capacitance of one bus line in pF. ISINK ≤ 6mA. tR and tF measured between 0.3 × VCC and 0.7 × VCC
Note 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
.
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Rev. B, 01/03/2014
IS31IO7328
Table 1 Power Up Default State For I/O Ports
Pin Connection
Port Power Up Default
AD
PP3
0
PP2
0
PP1
0
PP0
0
OD3
0
OD2
0
OD1
0
OD0
0
AD = GND
AD = VCC
1
1
1
1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Table 2 Command Byte Register
Command Byte Address
Function
Power-up Default
Protocol
00h (Note 6)
01h (Note 6)
02h (Note 6)
03h (Note 6)
04h (Note 6,7)
05h (Note 6,7)
06h (Note 6)
07h (Note 6)
Input port A (OD0~OD3)
Input port B (PP0~PP3)
Output port A
XXXX
XXXX
R
R
Refer to Table 1
Refer to Table 1
0000
R/W
R/W
R/W
R/W
R/W
R/W
Output port B
Port A configuration
Port B configuration
Port A interrupt control
Port B interrupt control
0000
0000
0000
Note 6: When reading or writing data from/to the port A/B, the 4 MSBs of the data are effective
Note 7: When configuring the command byte registers with address 04 or 05, the LSBs of data have to be set to 0.
Figure 2 2-Wire Serial Interface Timing Details
Figure 3 START and STOP Conditions
Figure 4 Bit Transfer
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Rev. B, 01/03/2014
IS31IO7328
FUNCTIONAL BLOCK DIAGRAM
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Rev. B, 01/03/2014
IS31IO7328
APPLICATION INFORMATION
FUNCTIONAL OVERVIEW
STANDBY MODE
The IS31IO7328 is a Multi-function I/O driver operating
from a 2.4V to 5.5V supply with four push-pull and four
open-drain I/O ports. Each open-drain and push-pull
port is rated to sink 20mA at 0.22V headroom, and the
entire device is rated to sink 160mA at 0.22V
When the serial interface is idle, the IS31IO7328
automatically enters standby mode, drawing minimal
supply current.
I/O PORT INPUT TRANSITION DETECTION
headroom into all ports combined. The outputs drive
loads connected to supplies up to +5.5V.
All I/O ports configured as inputs are monitored for
changes since the expander was last accessed
through the serial interface. The open-drain interrupt
output, INTB, activates when one of the port pins
changes states and only when the pin is configured as
an input. The interrupt deactivates when the
input/output register is read. A pin configured as an
output does not cause an interrupt. Each 8-bit port
register is read independently; therefore, an interrupt
caused by port A (OD0~OD3) is not cleared by a read
of port B (PP0~PP3)’s register.
The IS31IO7328 is set to two I2C slave addresses
using the address select inputs AD, and is accessed
over an I2C serial interface up to 400kHz. The RSTB
input clears the serial interface in case of a bus lockup,
terminating any serial transaction to or from the
IS31IO7328.
The IS31IO7328 consists of input, output port registers,
configuration registers and interrupt control register. All
I/O ports offer latching transition detection when
configured as inputs. All input ports are continuously
monitored for changes.
Changing an I/O from an output to an input may cause
a false interrupt to occur if the state of that I/O does not
match the content of output port register. The
IS31IO7328 has interrupt control register to avoid false
interrupt by setting the interrupt control register bit high
firstly, when the I/O state is stable, clear the interrupt
control register to enable the input transition detection
function.
A latching interrupt output, INTB, is programmed to
flag logic changes on ports used as inputs. Data
changes on any input port forces INTB to a logic-low.
Changing the I/O port level through the serial interface
does not cause an interrupt. The interrupt output INTB
is cleared successfully by reading the corresponding
input/output ports.
ACCESSING THE IS31IO7328
Serial Addressing
Ports default to logic-high or logic-low on power-up in
groups of two (see Table 1).
The IS31IO7328 operates as a slave that sends and
receives data through a 2-wire interface. The interface
uses a serial data line (SDA) and a serial clock line
(SCL) to achieve bidirectional communication between
master(s) and slave(s). A master, typically a
microcontroller, initiates all data transfers to and from
the IS31IO7328, and generates the SCL clock that
synchronizes the data transfer (see Figure 2).
INITIAL POWER-UP
On power-up, the transition detection logic is reset,
and INTB is reset. The power-up default states of the 8
I/O ports are set according to the I2C slave address
selection inputs, AD (see Table 1). For I/O ports used
as inputs, ensure that the default states are logic-high
so that the I/O ports power up in the high impedance
state.
SDA operates as both an input and an open-drain
output. A pull up resistor, typically 4.7kΩ, is required on
SDA. SCL operates only as an input. A pull up resistor,
typically 4.7kΩ, is required on SCL if there are multiple
masters on the 2-wire interface, or if the master in a
single-master system has an open-drain SCL output.
Each transmission consists of a START condition sent
by a master, followed by the IS31IO7328’s 7-bit slave
addresses plus R/W bits, 1 or more data bytes, and
finally a STOP condition (see Figure 3).
POWER-ON RESET
The IS31IO7328 contains an integral power-on-reset
(POR) circuit that ensures all registers are reset to a
known state on power-up. When VCC rises above VPOR
(2.3V max), the POR circuit releases the registers and
2-wire interface for normal operation. When VCC drops
to less than VPOR, the IS31IO7328 resets all register
contents to the POR defaults.
RSTB INPUT
The active-low RSTB input voids any I2C transaction
involving the IS31IO7328, forcing the IS31IO7328 into
the I2C STOP condition. A reset does not affect the
interrupt output.
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Rev. B, 01/03/2014
IS31IO7328
START and STOP Conditions
Bit Transfer
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a
transmission with a START (S) condition by
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 4).
transitioning SDA from high to low while SCL is high.
When the master has finished communicating with the
slave, the master issues a STOP (P) condition by
transitioning SDA from low to high while SCL is high.
The bus is then free for another transmission (see
Figure 3).
Figure 5 Acknowledge
Figure 6 Writing to the IS31IO7328
Figure 7 Reading I/O Ports of IS31IO7328
Note: Data from/to IS31IO7328, only the 4 MSBs of the data are effective.
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Rev. B, 01/03/2014
IS31IO7328
Slave Address
the command byte.
The IS31IO7328 uses a serial bus, which conforms to
the I2C protocol, to control the chip’s functions with two
A write to either output port groups of the IS31IO7328
starts with the master transmitting the group’s slave
____
wires: SCL and SDA. The IS31IO7328 has a 7-bit
address with the R/W bit set low. The master can now
transmit one or more bytes of data. The IS31IO7328
acknowledges these subsequent bytes of data and
updates the corresponding group’s ports with each
new byte until the master issues a STOP condition
(Figure 6).
____
slave address (A7:A1), followed by the R/W bit, A0.
Set A0 to “0” for a write command and set A0 to “1” for
a read command. The bit A2 is selected by the
connection of AD pin.
The complete slave address is:
Reading Port Registers
Table 3 Slave Address:
To read the device data, the bus master must first send
____
Bit
A7:A3
10110
A2
A1
0
A0
the IS31IO7328 address with the R/W bit set to zero,
followed by the command byte, which determines
which register is accessed. After a restart, the bus
Default
AD
0/1
AD connects to VCC, AD =1;
AD connects to GND, AD =0;
master must then send the IS31IO7328 address with
____
the R/W bit set to 1. Data from the register defined by
the command byte is then sent from the IS31IO7328 to
the master.
Data Bus Transaction
The command byte is the first byte to follow the 8-bit
device slave address during a write transmission (see
Table 2). The command byte is used to determine
which of the following registers are written or read.
The IS31IO7328 acknowledges the slave address, and
samples the ports during the acknowledge bit. INTB
desserts during the slave address acknowledge. When
the master reads one byte from the I/O ports of the
IS31IO7328 and subsequently issues a STOP
condition (Figure 7), the IS31IO7328 transmits the
current port data, clears the change flags, and resets
the transition detection. INTB desserts during the slave
acknowledge. The new snapshot data is the current
port data transmitted to the master, and therefore, port
changes occurring during the transmission are
detected.
Acknowledge
The acknowledge bit is a clocked 9th bit the recipient
uses to acknowledge receipt of each byte of data (see
Figure 5). Each byte transferred effectively requires
9bits. The master generates the 9th clock pulse, and
the recipient pulls down SDA during the acknowledge
clock pulse, such that the SDA line is stable low during
the high period of the clock pulse. When the master is
transmitting to the IS31IO7328, the device generates
the acknowledge bit because the IS31IO7328 is the
recipient. When the IS31IO7328 is transmitting to the
master, the master generates the acknowledge bit
because the master is the recipient.
Port Output Signal-Level Translation
The open-drain output architecture allows for level
translation to higher or lower voltages than the
IS31IO7328’s supply. Each of the push-pull output
ports has protection diodes to V+ and GND. When a
port output is driven to a voltage higher than V+ or
lower than GND, the appropriate protection diode
clamps the output to a diode drop above V+ or below
GND. When the IS31IO7328 is powered down (V+ =
0V), every output port’s protection diodes to V+ and
GND continue to appear as a diode clamp from each
output to GND (Figure 8). Each of the I/O ports
OD0~OD3 has a protection diode to GND (Figure 9).
When a port is driven to a voltage lower than GND, the
protection diode clamps the port to a diode drop below
GND. To obtain a high voltage, Open-Drain I/O Ports
should connect a resistance to VDD (Figure 9).
Configuration Registers
The configuration registers configure the directions of
the I/O pins. Set the bit in the respective configuration
register to enable the corresponding port as an input.
Clear the bit in the configuration register to enable the
corresponding port as an output. The 4 LSBs of the
commend data should be set to 0.
Interrupt Control Registers
The interrupt control registers control the interrupt
function of I/O ports when the I/O port used as input.
Set the bit in the respective interrupt control register to
disable the corresponding port’s interrupt function.
Clear the bit in the interrupt control register to enable
the corresponding port’s interrupt function.
Writing to Port Registers
Transmit data to the IS31IO7328 by sending the
device slave address and setting the LSB to a logic
zero. The command byte is sent after the address and
determines which registers receive the data following
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Rev. B, 01/03/2014
IS31IO7328
DRIVING LEDS
In the case that an OD output is used to drive an LED,
a 100kΩ pull-up resistor should be used to prevent the
output from floating while the LED is off. An OD port
which is left floating may experience a slight increase
in input leakage current due to the input structure of
the I/O port.
100k
VDD
VCC
OD0
OD1
OD2
OD3
Figure 8 IS31IO7328 Push-Pull I/O Ports Structure
IS31IO7328
Figure 10 Driving LEDs with OD Ports
Figure 9 IS31IO7328 Open-Drain I/O Ports Structure
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Rev. B, 01/03/2014
IS31IO7328
CLASSIFICATION REFLOW PROFILES
Profile Feature
Pb-Free Assembly
Preheat & Soak
150°C
200°C
60-120 seconds
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate (Tsmax to Tp)
3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL)
217°C
60-150 seconds
Peak package body temperature (Tp)*
Max 260°C
Time (tp)** within 5°C of the specified
classification temperature (Tc)
Max 30 seconds
Average ramp-down rate (Tp to Tsmax)
Time 25°C to peak temperature
6°C/second max.
8 minutes max.
Figure 11 Classification Profile
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Rev. B, 01/03/2014
IS31IO7328
PACKAGE INFORMATION
QFN-16
Note: All dimensions in millimeters unless otherwise stated.
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Rev. B, 01/03/2014
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