LT3013B_技术文档

LT3013B

250mA, 4V to 80V

Low Dropout Micropower

Linear Regulator with PWRGD

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FEATURES

DESCRIPTIO

The LT^®3013B is a high voltage, micropower low dropout

linearregulator.Thedeviceiscapableofsupplying250mA

of output current with a dropout voltage of 400mV. De-

signed for use in battery-powered or high voltage sys-

tems, the low quiescent current (65µA operating) makes

theLT3013Banidealchoice.Quiescentcurrentisalsowell

controlled in dropout.

■

Wide Input Voltage Range: 4V to 80V

■

Low Quiescent Current: 65µA

■

Low Dropout Voltage: 400mV

■

Output Current: 250mA

■

No Protection Diodes Needed

■

Adjustable Output from 1.24V to 60V

■

Stable with 3.3µF Output Capacitor

■

Stable with Aluminum, Tantalum or Ceramic

Other features of the LT3013B include a PWRGD flag to

indicate output regulation. The delay between regulated

output level and flag indication is programmable with a

single capacitor. The LT3013B also has the ability to

operate with very small output capacitors. The regulator is

stable with only 3.3µF on the output while most older

devices require between 10µF and 100µF for stability.

Smallceramiccapacitorscanbeusedwithoutanyneedfor

series resistance (ESR) as is common with other regula-

tors. Internal protection circuitry includes reverse-battery

protection, current limiting, thermal limiting and reverse

current protection.

Capacitors

Reverse-Battery Protection

■

No Reverse Current Flow from Output to Input

■

Thermal Limiting

■

Thermally Enhanced 16-Lead TSSOP and 12 Pin

(4mm × 3mm) DFN Package

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APPLICATIO S

■

Low Current High Voltage Regulators

■

Regulator for Battery-Powered Systems

■

Telecom Applications

Automotive Applications

The device is available with an adjustable output with a

1.24V reference voltage. The LT3013B regulator is avail-

ableinthethermallyenhanced16-leadTSSOPandthelow

profile (0.75mm), 12 pin (4mm × 3mm) DFN package,

both providing excellent thermal characteristics.

■

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

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Dropout Voltage

TYPICAL APPLICATIO

400

350

300

250

200

150

100

50

5V Supply

V

OUT

IN

OUT

LT3013B

5V

250mA

V

IN

750k

249k

5.4V TO

80V

1.6M

3.3µF

1µF

ADJ

PWRGD

GND

C

T

3013 TA01

1000pF

0

50

100

150

200

250

OUTPUT CURRENT (mA)

3013 TA02

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LT3013B

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ABSOLUTE AXI U RATI GS

(Note 1)

IN Pin Voltage................................................... ±80V

OUT Pin Voltage ............................................... ±60V

IN to OUT Differential Voltage........................... ±80V

ADJ Pin Voltage .................................................. ±7V

Storage Temperature Range

TSSOP Package ........................... –65°C to 150°C

DFN Package ............................... –65°C to 125°C

Operating Junction Temperature Range

C Pin Voltage ........................................... 7V, –0.5V

(Notes 3, 9, 10) ........................... –40°C to 125°C

Lead Temperature (FE16 Soldering, 10 sec)... 300°C

T

PWRGD Pin Voltage ................................ 80V, –0.5V

Output Short-Circuit Duration..................... Indefinite

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PACKAGE/ORDER I FOR ATIO

TOP VIEW

GND

NC

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

GND

NC

IN

NC

OUT

1

2

3

4

5

6

12 NC

11 IN

10 IN

OUT

IN

13

17

ADJ

9

8

7

NC

ADJ

NC

GND

PWRGD

GND

C

T

PWRGD

C

T

GND

DE PACKAGE

12-LEAD (4mm × 3mm) PLASTIC DFN

FE PACKAGE

16-LEAD PLASTIC TSSOP

T_JMAX= 125°C, θ_JA= 40°C/ W, θ_JC= 16°C/ W

EXPOSED PAD (PIN13) IS GND

MUST BE SOLDERED TO PCB

EXPOSED PAD (PIN17) IS GND

MUST BE SOLDERED TO PCB

ORDER PART NUMBER

DE PART MARKING

3013B

ORDER PART NUMBER

LT3013BEFE

FE PART MARKING

3013BEFE

LT3013BEDE

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The

●

denotes specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C.

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PARAMETER

CONDITIONS

= 250mA

MIN

TYP

MAX

UNITS

Minimum Input Voltage

ADJ Pin Voltage (Notes 2,3)

I

●

4

4.5

V

LOAD

V

IN

= 4V, I

= 1mA

1.225

1.2

1.24

1.255

1.28

V

LOAD

4.5V < V < 80V, 1mA < I

< 250mA

LOAD

●

IN

Line Regulation

∆V = 4V to 80V, I

= 1mA (Note 2)

0.1

7

5

mV

IN

LOAD

Load Regulation (Note 2)

V

= 4.5V, ∆I

= 1mA to 250mA

12

25

mV

IN

LOAD

●

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LT3013B

ELECTRICAL CHARACTERISTICS

The

●

denotes specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C.

J

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Dropout Voltage

I

= 10mA

160

230

300

mV

LOAD

V

= V

●

IN

OUT(NOMINAL)

(Notes 4, 5)

I

= 50mA

250

400

340

420

mV

LOAD

I

= 250mA

490

620

mV

LOAD

●

GND Pin Current

I

= 0mA

= 100mA

= 250mA

65

3

10

120

µA

mA

LOAD

V

= 4.5V

IN

(Notes 4, 6)

●

18

Output Voltage Noise

ADJ Pin Bias Current

PWRGD Trip Point

C

= 10µF, I

= 250mA, BW = 10Hz to 100kHz

100

30

µV

RMS

OUT

LOAD

(Note 7)

100

94

nA

% of Nominal Output Voltage, Output Rising

% of Nominal Output Voltage

●

85

90

%

PWRGD Trip Point Hysteresis

PWRGD Output Low Voltage

1.1

140

3.6

1.6

75

I

= 50µA

250

6

mV

µA

V

PWRGD

C Pin Charging Current

T

C Pin Voltage Differential

T

V

– V

CT(PWRGD High) CT(PWRGD Low)

Ripple Rejection

Current Limit

= 7V(Avg), V

= 0.5V , f

= 120Hz, I = 250mA

LOAD

65

dB

IN

RIPPLE

P-P RIPPLE

V

= 7V, V

= 0V

400

mA

IN

OUT

= 4.5V, ∆V

= –0.1V (Note 2)

●

270

OUT

Reverse Output Current (Note 8)

V

= 1.24V, V < 1.24V (Note 2)

12

25

µA

OUT

IN

Note 6: GND pin current is tested with V = 4.5V and a current source

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

IN

load. This means the device is tested while operating close to its dropout

region. This is the worst-case GND pin current. The GND pin current will

decrease slightly at higher input voltages.

Note 7: ADJ pin bias current flows into the ADJ pin.

Note 2: The LT3013B is tested and specified for these conditions with the

ADJ pin connected to the OUT pin.

Note 8: Reverse output current is tested with the IN pin grounded and the

OUT pin forced to the rated output voltage. This current flows into the OUT

pin and out the GND pin.

Note 9: The LT3013BE is guaranteed to meet performance specifications

from 0°C to 125°C operating junction temperature. Specifications over

the –40°C to 125°C operating junction temperature range are assured by

design, characterization and correlation with statistical process controls.

Note 3: Operating conditions are limited by maximum junction

temperature. The regulated output voltage specification will not apply for

all possible combinations of input voltage and output current. When

operating at maximum input voltage, the output current range must be

limited. When operating at maximum output current, the input voltage

range must be limited.

Note 4: To satisfy requirements for minimum input voltage, the LT3013B

is tested and specified for these conditions with an external resistor divider

(249k bottom, 549k top) for an output voltage of 4V. The external resistor

divider will add a 5µA DC load on the output.

Note 10: This IC includes overtemperature protection that is intended to

protect the device during momentary overload conditions. Junction

temperature will exceed 125°C when overtemperature protection is

active. Continuous operation above the specified maximum operating

junction temperature may impair device reliability.

Note 5: Dropout voltage is the minimum input to output voltage differential

needed to maintain regulation at a specified output current. In dropout, the

output voltage will be equal to (V – V

).

IN

DROPOUT

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LT3013B

TYPICAL PERFOR A CE CHARACTERISTICS

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Typical Dropout Voltage

Guaranteed Dropout Voltage

Dropout Voltage

600

500

400

300

200

100

0

600

500

400

300

200

100

0

600

500

= TEST POINTS

T

≤ 125°C

J

T

= 125°C

J

I

L

= 250mA

I

L

= 100mA

400

300

T

≤ 25°C

J

T

= 25°C

J

I

L

= 50mA

200

100

0

I

= 10mA

= 1mA

L

0

50

100

150

200

250

0

50

100

150

200

250

–50

0

25

50

75 100 125

–25

OUTPUT CURRENT (mA)

TEMPERATURE (°C)

OUTPUT CURRENT (mA)

3013 G01

3013 G02

3013 G03

Quiescent Current

ADJ Pin Voltage

Quiescent Current

600

1.260

80

70

60

50

40

30

20

10

0

T

= 25°C

I

= 1mA

J

L

R

=

∞

500

400

300

200

100

0

1.255

1.250

I = 250mA

L

I = 100mA

L

1.245

1.240

1.235

1.230

1.225

I = 50mA

L

I = 10mA

L

I = 1mA

L

1.220

–50

0

25

50

75 100 125

–25

0

50

75 100 125

1

2

6

7

9

–50

25

0

3

4

5

8

10

TEMPERATURE (°C)

INPUT VOLTAGE (V)

3013 G03

3013 G05

3013 G06

GND Pin Current

GND Pin Current vs I

LOAD

GND Pin Current

1.2

10

9

8

7

6

5

4

3

2

1

0

10

9

8

7

6

5

4

3

2

1

0

T

= 25°C, *FOR V

= 1.24V

OUT

V

T

= 4.5V

T

= 25°C

J

IN

J

= 25°C

*FOR V

= 1.24V

OUT

1.0

0.8

0.6

0.4

0.2

0

R

I

= 49.6Ω

= 25mA*

L

R = 4.96Ω

L

I = 250mA*

L

R

I

= 124Ω

= 10mA*

L

R

L

= 12.4Ω

L

I

= 100mA*

R

L

I

L

= 1.24k

= 1mA*

R

= 24.8Ω, I = 50mA*

L

0

1

2

3

4

5

6

7

8

9

10

0

1

2

3

4

5

6

7

8

9

10

0

50

100

150

200

250

INPUT VOLTAGE (V)

LOAD CURRENT (mA)

3013 G07

3013 G08

3013 G09

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LT3013B

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TYPICAL PERFOR A CE CHARACTERISTICS

PWRGD Trip Point

PWRGD Output Low Voltage

ADJ Pin Bias Current

95

94

93

92

91

90

89

88

87

86

85

200

180

160

140

120

100

80

50

45

40

35

30

25

20

15

10

5

I

= 50µA

PWRGD

OUTPUT RISING

OUTPUT FALLING

60

40

20

0

–25

0

50

75 100 125

–25

0

50

75 100 125

–50

25

–50

25

–25

0

50

75 100 125

–50

25

TEMPERATURE (°C)

3013 G25

3013 G26

3013 G13

Current Limit

CT Charging Current

CT Comparator Thresholds

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

PWRGD TRIPPED HIGH

V

= 0V

OUT

V

(HIGH)

CT

T

= 25°C

J

T

= 125°C

J

V

(LOW)

50

CT

–25

0

50

75 100 125

–25

0

75 100 125

10 20 30 40 50 60 70 80

–50

25

–50

25

0

TEMPERATURE (°C)

INPUT VOLTAGE (V)

3013 G27

3013 G28

3013 G14

Current Limit

Reverse Output Current

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

200

180

160

140

120

100

80

35

30

25

20

15

10

5

T

V

= 25°C

V

= 0V

= V

J

IN

OUT

= 0V

= 1.24V

ADJ

IN

OUT

= V

ADJ

CURRENT FLOWS

INTO OUTPUT PIN

ADJ

PIN CLAMP

(SEE APPLICATIONS

INFORMATION)

60

40

V

= 7V

IN

OUT

20

= 0V

0

–50

0

25

50

75 100 125

0

1

2

3

4

5

6

7

8

9

10

–50 –25

0

25

50

75 100 125

–25

TEMPERATURE (°C)

OUTPUT VOLTAGE (V)

TEMPERATURE (°C)

3013 G15

3013 G16

3013 G17

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LT3013B

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TYPICAL PERFOR A CE CHARACTERISTICS

Input Ripple Rejection

Minimum Input Voltage

100

4.0

92

V

LOAD

= 4.5V + 50mV RIPPLE

IN

RMS

I

= 250mA

LOAD

90

80

70

I

= 250mA

3.5

3.0

88

84

80

76

72

68

64

60

2.5

2.0

1.5

1.0

0.5

60

50

C

OUT

= 10µF

40

30

20

10

0

V

L

V

= 4.5V + 0.5V RIPPLE AT f = 120Hz

P-P

IN

C

= 3.3µF

OUT

I

= 250mA

= 1.24V

OUT

0

10

100

1k

10k

100k

1M

–25

0

50

75 100 125

–50

25

–50

0

25

50

75 100 125

–25

FREQUENCY (Hz)

TEMPERATURE (°C)

3013 G19

3013 G20

3013 G18

Output Noise Spectral Density

Load Regulation

10

1

0

–2

C

= 3.3µF

= 250mA

∆I = 1mA TO 250mA

L

OUT

I

LOAD

–4

–6

–8

–10

–12

–14

–16

–18

–20

0.1

0.01

–25

0

50

75 100 125

–50

25

10

100

1k

FREQUENCY (Hz)

10k

100k

TEMPERATURE (°C)

3013 G22

3013 G21

10Hz to 100kHz Output Noise

Transient Response

0.15

0.10

0.05

0

V_OUT

100µV/DIV

–0.05

–0.10

–0.15

300

V

C

= 6V

= 5V

= 3.3µF CERAMIC

IN

OUT

IN

= 3.3µF CERAMIC

LOAD

OUT

∆I

= 100mA TO 200mA

200

C

_OUT= 10µF

1ms/DIV

3013B G23

100

I_L= 250mA

V_OUT= V_ADJ

0

100

200

300

400

500

TIME (µs)

3013 G24

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LT3013B

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PI FU CTIO S

(DFN Package)/(TSSOP Package)

OUT (Pins 2, 3)/(Pins 3, 4): Output. The output supplies

power to the load. A minimum output capacitor of 3.3µF is

required to prevent oscillations. Larger output capacitors

will be required for applications with large transient loads

to limit peak voltage transients. See the Applications

Information section for more information on output ca-

pacitance and reverse output characteristics.

C_T(Pin 7)/(Pin 10): Timing Capacitor. The C_Tpin allows

theuseofasmallcapacitortodelaythetimingbetweenthe

point where the output crosses the PWRGD threshold and

the PWRGD flag changes to a high impedance state.

Current out of this pin during the charging phase is 3µA.

The voltage difference between the PWRGD low and

PWRGDhighstatesis1.6V(seetheApplicationsInforma-

tion Section).

ADJ (Pin 4)/(Pin 5): Adjust. This is the input to the error

amplifier. This pin is internally clamped to ±7V. It has a

bias current of 30nA which flows into the pin (see curve of

ADJPinBiasCurrentvsTemperatureintheTypicalPerfor-

mance Characteristics). The ADJ pin voltage is 1.24V

referenced to ground, and the output voltage range is

1.24V to 60V.

IN (Pins 10, 11)/(Pins 13,14): Input. Power is supplied to

the device through the IN pin. A bypass capacitor is

required on this pin if the device is more than six inches

away from the main input filter capacitor. In general, the

output impedance of a battery rises with frequency, so it

is advisable to include a bypass capacitor in battery-

poweredcircuits. Abypasscapacitorintherangeof1µFto

10µF is sufficient. The LT3013B is designed to withstand

reverse voltages on the IN pin with respect to ground and

the OUT pin. In the case of a reversed input, which can

happen if a battery is plugged in backwards, the LT3013B

will act as if there is a diode in series with its input. There

will be no reverse current flow into the LT3013B and no

reverse voltage will appear at the load. The device will

protect both itself and the load.

GND (Pins 5, 13)/(Pins 1, 6, 8, 9, 16, 17): Ground. The

exposed backside of the package is an electrical connec-

tion for GND. As such, to ensure optimum device opera-

tion and thermal performance, the exposed pad must be

connected directly to pin 5/pin 6 on the PC board.

PWRGD (Pin 6)/(Pin 7): Power Good. The PWRGD flag is

an open collector flag to indicate that the output voltage

has come up to above 90% of the nominal output voltage.

There is no internal pull-up on this pin; a pull-up resistor

must be used. The PWRGD pin will change state from an

open-collector to high impedance after both the output is

above90%ofthenominalvoltageandthecapacitoronthe

C_Tpin has charged through a 1V differential. The maxi-

mum pull-down current of the PWRGD pin in the low state

is 50µA.

NC (Pins 1, 8, 9, 12)/(Pins 2, 11, 12, 15):No Connect. No

Connect pins may be floated, tied to IN or tied to GND.

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LT3013B

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APPLICATIO S I FOR ATIO

The LT3013B is a 250mA high voltage low dropout regu-

lator with micropower quiescent current. The device is

capable of supplying 250mA at a dropout voltage of

400mV. Operating quiescent current is only 65µA. In

addition to the low quiescent current, the LT3013B incor-

porates several protection features which make it ideal for

use in battery-powered systems. The device is protected

against both reverse input and reverse output voltages. In

battery backup applications where the output can be held

up by a backup battery when the input is pulled to ground,

theLT3013Bactslikeithasadiodeinserieswithitsoutput

and prevents reverse current flow.

for output voltages greater than 1.24V will be proportional

to the ratio of the desired output voltage to 1.24V; (V_OUT

/

1.24V). For example, load regulation for an

output current change of 1mA to 250mA is –7mV typical

at V_OUT= 1.24V. At V_OUT= 12V, load regulation is:

(12V/1.24V) • (–7mV) = –68mV

Output Capacitance and Transient Response

The LT3013B is designed to be stable with a wide range of

output capacitors. The ESR of the output capacitor affects

stability, most notably with small capacitors. A minimum

output capacitor of 3.3µF with an ESR of 3Ω or less is

recommended to prevent oscillations. The LT3013B is a

micropower device and output transient response will be

a function of output capacitance. Larger values of output

capacitance decrease the peak deviations and provide

improved transient response for larger load current

changes. Bypass capacitors, used to decouple individual

components powered by the LT3013B, will increase the

effective output capacitor value.

Adjustable Operation

The LT3013B has an output voltage range of 1.24V to

60V. The output voltage is set by the ratio of two external

resistors as shown in Figure 1. The device servos the

output to maintain the voltage at the adjust pin at 1.24V

referenced to ground. The current in R1 is then equal to

1.24V/R1 and the current in R2 is the current in R1 plus

the ADJ pin bias current. The ADJ pin bias current, 30nA

at 25°C, flows through R2 into the ADJ pin. The output

voltage can be calculated using the formula in Figure 1.

The value of R1 should be less than 250k to minimize

errors in the output voltage caused by the ADJ pin bias

current.

Extra consideration must be given to the use of ceramic

capacitors. Ceramic capacitors are manufactured with a

variety of dielectrics, each with different behavior across

temperature and applied voltage. The most common di-

electrics used are specified with EIA temperature charac-

teristiccodesofZ5U,Y5V,X5RandX7R.TheZ5UandY5V

dielectrics are good for providing high capacitances in a

small package, but they tend to have strong voltage and

The adjustable device is tested and specified with the ADJ

pintiedtotheOUTpinanda5µADCload(unlessotherwise

specified) for an output voltage of 1.24V. Specifications

V

OUT

IN

LT3013B

ADJ

OUT

+

R2

V

IN

GND

R1

3013 F01

R2

R1

V

= 1.24V 1 +

+ (I )(R2)

ADJ

OUT

(

)

= 1.24V

ADJ

I

= 30nA AT 25°C

OUTPUT RANGE = 1.24V TO 60V

ADJ

Figure 1. Adjustable Operation

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LT3013B

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APPLICATIO S I FOR ATIO

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temperature coefficients as shown in Figures 2 and 3.

When used with a 5V regulator, a 16V 10µF Y5V capacitor

can exhibit an effective value as low as 1µF to 2µF for the

DC bias voltage applied and over the operating tempera-

ture range. The X5R and X7R dielectrics result in more

stable characteristics and are more suitable for use as the

output capacitor. The X7R type has better stability across

temperature, while the X5R is less expensive and is

available in higher values. Care still must be exercised

when using X5R and X7R capacitors; the X5R and X7R

codesonlyspecifyoperatingtemperaturerangeandmaxi-

mum capacitance change over temperature. Capacitance

change due to DC bias with X5R and X7R capacitors is

better than Y5V and Z5U capacitors, but can still be

significant enough to drop capacitor values below appro-

priate levels. Capacitor DC bias characteristics tend to

improve as component case size increases, but expected

capacitance at operating voltage should be verified.

Voltage and temperature coefficients are not the only

sources of problems. Some ceramic capacitors have a

piezoelectric response. A piezoelectric device generates

voltage across its terminals due to mechanical stress,

similar to the way a piezoelectric accelerometer or micro-

phone works. For a ceramic capacitor the stress can be

induced by vibrations in the system or thermal transients.

20

BOTH CAPACITORS ARE 16V,

1210 CASE SIZE, 10µF

0

X5R

–20

–40

PWRGD Flag and Timing Capacitor Delay

–60

The PWRGD flag is used to indicate that the ADJ pin

voltageiswithin10%oftheregulatedvoltage.ThePWRGD

pin is an open-collector output, capable of sinking 50µA of

current when the ADJ pin voltage is low. There is no

internal pull-up on the PWRGD pin; an external pull-up

resistor must be used. When the ADJ pin rises to within

10% of its final reference value, a delay timer is started. At

the end of this delay, programmed by the value of the

capacitor on the CT pin, the PWRGD pin switches to a high

impedance and is pulled up to a logic level by an external

pull-up resistor.

Y5V

–80

–100

0

8

12 14

2

4

6

10

16

DC BIAS VOLTAGE (V)

3013 F02

Figure 2. Ceramic Capacitor DC Bias Characterics

40

20

0

To calculate the capacitor value on the CT pin, use the

following formula:

X5R

–20

–40

Y5V

I_CT•t_DELAY

V_CT(HIGH)– V_CT(LOW)

C_TIME

=

–60

–80

BOTH CAPACITORS ARE 16V,

Figure 4 shows a block diagram of the PWRGD circuit. At

startup,thetimingcapacitorisdischargedandthePWRGD

pin will be held low. As the output voltage increases and

the ADJ pin crosses the 90% threshold, the JK flip-flop is

reset, and the 3µA current source begins to charge the

1210 CASE SIZE, 10µF

–100

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

75

3013 F03

Figure 3. Ceramic Capacitor Temperature Characterics

3013bfa

9

LT3013B

W U U

U

APPLICATIO S I FOR ATIO

I

CT

3µA

CT

PWRGD

+

ADJ

V

– V

BE

CT(HIGH)

J

Q

(~1.1V)

K

V

• 90%

–

REF

–

+

V

CT(LOW)

~0.1V

3013 F04

Figure 4. PWRGD Circuit Block Diagram

maximum junction temperature rating may impair the life

of the device.

timing capacitor. Once the voltage on the CT pin reaches

the V_CT(HIGH)threshold (approximately 1.7V at 25°C), the

capacitor voltage is clamped and the PWRGD pin is set to

a high impedance state.

Thermal Considerations

The power handling capability of the device will be limited

by the maximum rated junction temperature (125°C). The

power dissipated by the device will be made up of two

components:

Duringnormaloperation,aninternalglitchfilterwillignore

short transients (<15µs). Longer transients below the

90% threshold will reset the JK flip-flop. This flip-flop

ensures that the capacitor on the CT pin is quickly dis-

charged all the way to the V_CT(LOW)threshold before re-

starting the time delay. This provides a consistent time

delay after the ADJ pin is within 10% of the regulated

voltage before the PWRGD pin switches to high

impedance.

1. Output current multiplied by the input/output voltage

differential: I_OUT• (V_IN– V_OUT) and,

2. GND pin current multiplied by the input voltage:

I_GND• V_IN.

The GND pin current can be found by examining the GND

Pin Current curves in the Typical Performance Character-

istics. Powerdissipationwillbeequaltothesumofthetwo

components listed above.

Current Limit and Safe Operating Area Protection

Like many IC power regulators, the LT3013B has safe

operating area protection. The safe operating area protec-

tion decreases the current limit as the input voltage

increases and keeps the power transistor in a safe operat-

ing region. The protection is designed to provide some

outputcurrentatallvaluesofinputvoltageuptothedevice

breakdown (see curve of Current Limit vs Input Voltage in

the Typical Performance Characteristics).

The LT3013B series regulators have internal thermal lim-

iting designed to protect the device during overload con-

ditions. For continuous normal conditions the maximum

junction temperature rating of 125°C must not be ex-

ceeded. It is important to give careful consideration to all

sources of thermal resistance from junction to ambient.

Additional heat sources mounted nearby must also be

considered.

The LT3013B is limited for operating conditions by maxi-

mum junction temperature. While operating at maximum

input voltage, the output current range must be limited;

when operating at maximum output current, the input

voltage range must be limited. Device specifications will

not apply for all possible combinations of input voltage

and output current. Operating the LT3013B beyond the

For surface mount devices, heat sinking is accomplished

by using the heat spreading capabilities of the PC board

and its copper traces. Copper board stiffeners and plated

through-holes can also be used to spread the heat gener-

ated by power devices.

3013bfa

10

LT3013B

W U U

APPLICATIO S I FOR ATIO

U

The following tables list thermal resistance for several

different board sizes and copper areas. All measurements

were taken in still air on 3/32" FR-4 board with one ounce

copper.

250mA, and a maximum ambient temperature of 30°C,

what will the maximum junction temperature be?

The power dissipated by the device will be equal to:

I_OUT(MAX)• (V_IN(MAX)– V_OUT) + (I_GND• V_IN(MAX)

where:

I_OUT(MAX)= 250mA

_IN(MAX)= 12V

I_GNDat (I_OUT= 250mA, V_IN= 12V) = 8mA

So:

)

Table 1. Measured Thermal Resistance (TSSOP)

COPPER AREA

THERMAL RESISTANCE

TOPSIDE

2500 sq mm

1000 sq mm

225 sq mm

100 sq mm

BACKSIDE

2500 sq mm

BOARD AREA

2500 sq mm

(JUNCTION-TO-AMBIENT)

40°C/W

V

45°C/W

50°C/W

62°C/W

Table 2. Measured Thermal Resistance (DFN)

P = 250mA • (12V – 5V) + (8mA • 12V) = 1.85W

COPPER AREA

THERMAL RESISTANCE

The thermal resistance will be in the range of 40°C/W to

62°C/W depending on the copper area. So the junction

temperature rise above ambient will be approximately

equal to:

TOPSIDE

2500 sq mm

1000 sq mm

225 sq mm

100 sq mm

BACKSIDE

2500 sq mm

BOARD AREA

2500 sq mm

(JUNCTION-TO-AMBIENT)

40°C/W

45°C/W

50°C/W

1.85W • 50°C/W = 92.3°C

62°C/W

The maximum junction temperature will then be equal to

the maximum junction temperature rise above ambient

plus the maximum ambient temperature or:

The thermal resistance junction-to-case (θ_JC), measured

at the exposed pad on the back of the die, is 16°C/W.

Continuous operation at large input/output voltage differ-

entials and maximum load current is not practical due to

thermal limitations. Transient operation at high input/

output differentials is possible. The approximate thermal

time constant for a 2500sq mm 3/32" FR-4 board with

maximumtopsideandbacksideareaforoneouncecopper

is 3 seconds. This time constant will increase as more

thermal mass is added (i.e. vias, larger board, and other

components).

T_JMAX= 30°C + 92.3°C = 122.3°C

Example 2: Given an output voltage of 5V, an input voltage

of 48V that rises to 72V for 5ms(max) out of every 100ms,

and a 5mA load that steps to 200mA for 50ms out of every

250ms, what is the junction temperature rise above ambi-

ent? Using a 500ms period (well under the time constant

of the board), power dissipation is as follows:

P1(48V in, 5mA load) = 5mA • (48V – 5V)

+ (200µA • 48V) = 0.23W

For an application with transient high power peaks, aver-

age power dissipation can be used for junction tempera-

turecalculationsaslongasthepulseperiodissignificantly

less than the thermal time constant of the device and

board.

P2(48V in, 50mA load) = 200mA • (48V – 5V)

+ (8mA • 48V) = 8.98W

P3(72V in, 5mA load) = 5mA • (72V – 5V)

+ (200µA • 72V) = 0.35W

P4(72V in, 50mA load) = 200mA • (72V – 5V)

+ (8mA • 72V) = 13.98W

Calculating Junction Temperature

Example 1: Given an output voltage of 5V, an input voltage

range of 8V to 12V, an output current range of 0mA to

3013bfa

11

LT3013B

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U

APPLICATIO S I FOR ATIO

Operation at the different power levels is as follows:

voltage if the output is pulled high, the ADJ pin input

current must be limited to less than 5mA. For example, a

resistor divider is used to provide a regulated 1.5V output

fromthe1.24Vreferencewhentheoutputisforcedto60V.

The top resistor of the resistor divider must be chosen to

limitthecurrentintotheADJpintolessthan5mAwhenthe

ADJ pin is at 7V. The 53V difference between the OUT and

ADJ pins divided by the 5mA maximum current into the

ADJ pin yields a minimum top resistor value of 10.6k.

76% operation at P1, 19% for P2, 4% for P3, and

1% for P4.

P

_EFF= 76%(0.23W) + 19%(8.98W) + 4%(0.35W)

+ 1%(13.98W) = 2.03W

With a thermal resistance in the range of 40°C/W to

62°C/W, this translates to a junction temperature rise

above ambient of 81°C to 125°C.

In circuits where a backup battery is required, several

different input/output conditions can occur. The output

voltage may be held up while the input is either pulled to

ground, pulled to some intermediate voltage, or is left

open circuit. Current flow back into the output will follow

the curve shown in Figure 5. The rise in reverse output

current above 7V occurs from the breakdown of the 7V

clamp on the ADJ pin. With a resistor divider on the

regulator output, this current will be reduced depending

on the size of the resistor divider.

Protection Features

The LT3013B incorporates several protection features

which make it ideal for use in battery-powered circuits. In

addition to the normal protection features associated with

monolithic regulators, such as current limiting and ther-

mal limiting, the device is protected against reverse-input

voltages, and reverse voltages from output to input.

Current limit protection and thermal overload protection

areintendedtoprotectthedeviceagainstcurrentoverload

conditions at the output of the device. For normal opera-

tion, the junction temperature should not exceed 125°C.

When the IN pin of the LT3013B is forced below the OUT

pin or the OUT pin is pulled above the IN pin, input current

will typically drop to less than 2µA. This can happen if the

input of the LT3013B is connected to a discharged (low

voltage) battery and the output is held up by either a

backup battery or a second regulator circuit.

The input of the device will withstand reverse voltages of

80V. No negative voltage will appear at the output. The

device will protect both itself and the load. This provides

protection against batteries which can be plugged in

backward.

200

The ADJ pin of the device can be pulled above or below

ground by as much as 7V without damaging the device. If

the input is left open circuit or grounded, the ADJ pin will

act like an open circuit when pulled below ground, and like

alargeresistor(typically100k)inserieswithadiodewhen

pulled above ground. If the input is powered by a voltage

source, pulling the ADJ pin below the reference voltage

will cause the device to try and force the current limit

current out of the output. This will cause the output to go

to a unregulated high voltage. Pulling the ADJ pin above

the reference voltage will turn off all output current.

T

V

= 25°C

J

= 0V

180

160

140

120

100

80

IN

OUT

= V

ADJ

CURRENT FLOWS

INTO OUTPUT PIN

ADJ

PIN CLAMP

(SEE ABOVE)

60

40

20

0

1

2

3

4

5

6

7

8

9

10

OUTPUT VOLTAGE (V)

3013 F05

In situations where the ADJ pin is connected to a resistor

divider that would pull the ADJ pin above its 7V clamp

Figure 5. Reverse Output Current

3013bfa

12

LT3013B

U

TYPICAL APPLICATIO S

LT3013B Automotive Application

IN

OUT

ADJ

NO PROTECTION

DIODE NEEDED!

+

V

IN

LT3013B

GND

750k

249k

3.3µF

12V

1µF

LOAD: CLOCK,

SECURITY SYSTEM

ETC

(LATER 42V)

LT3013B Telecom Application

V

IN

OUT

48V

(72V TRANSIENT)

+

–

LT3013B

750k

249k

BACKUP

BATTERY

NO PROTECTION

DIODE NEEDED!

3.3µF

1µF

LOAD:

SYSTEM MONITOR

ETC

ADJ

GND

3013 TA05

Constant Brightness for Indicator LED over Wide Input Voltage Range

RETURN

IN

LT3013B

ADJ

OUT

1µF

3.3µF

GND

R

SET

–48V

3013 TA06

I

= 1.24V/R

SET

LED

–48V CAN VARY FROM –4V TO –80V

3013bfa

13

LT3013B

U

PACKAGE DESCRIPTIO

DE Package

12-Lead Plastic DFN (4mm × 3mm)

(Reference LTC DWG # 05-08-1695 Rev C)

0.70 ±0.05

3.60 ±0.05

2.20 ±0.05 (2 SIDES)

1.70 ±0.05

PACKAGE OUTLINE

0.25 ± 0.05

0.50

BSC

3.30 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

0.40 ± 0.10

4.00 ±0.10

(2 SIDES)

R = 0.115

TYP

7

12

R = 0.05

TYP

3.00 ±0.10 1.70 ± 0.05

(2 SIDES)

PIN 1

TOP MARK

(NOTE 6)

PIN 1 NOTCH

R = 0.20 OR

0.35 × 45°

CHAMFER

(UE12/DE12) DFN 0905 REV C

6

0.25 ± 0.05

1

0.75 ±0.05

0.200 REF

0.50

BSC

3.30 ±0.05

(2 SIDES)

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING PROPOSED TO BE A VARIATION OF VERSION

(WGED) IN JEDEC PACKAGE OUTLINE M0-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3013bfa

14

LT3013B

U

PACKAGE DESCRIPTIO

FE Package

16-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663)

Exposed Pad Variation BB

4.90 – 5.10*

(.193 – .201)

3.58

(.141)

3.58

(.141)

16 1514 13 12 1110

9

6.60 ±0.10

4.50 ±0.10

2.94

(.116)

6.40

(.252)

BSC

SEE NOTE 4

2.94

(.116)

0.45 ±0.05

1.05 ±0.10

0.65 BSC

5

7

8

1

2

3

4

6

RECOMMENDED SOLDER PAD LAYOUT

1.10

(.0433)

MAX

4.30 – 4.50*

(.169 – .177)

0.25

REF

0° – 8°

0.65

(.0256)

BSC

0.09 – 0.20

(.0035 – .0079)

0.50 – 0.75

(.020 – .030)

0.05 – 0.15

(.002 – .006)

0.195 – 0.30

FE16 (BB) TSSOP 0204

(.0077 – .0118)

TYP

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE

FOR EXPOSED PAD ATTACHMENT

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

MILLIMETERS

(INCHES)

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

3013bfa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

15

LT3013B

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

V : 4.5V to 36V, V

LT1020

125mA, Micropower Regulator and Comparator

= 2.5V, V = 0.4V, I = 40µA, I = 40µA,

OUT DO Q SD

IN

Comparator and Reference, Class B Outputs, S16, PDIP14 Packages

LT1120/LT1120A 125mA, Micropower Regulator and Comparator

V : 4.5V to 36V, V = 2.5V, V = 0.4V, I = 40µA, I = 10µA,

Comparator and Reference,Logic Shutdown, Ref Sources and Sinks 2/4mA,

S8, N8 Packages

IN

OUT

DO

Q

SD

LT1121/

LT1121HV

150mA, Micropower, LDO

700mA, Micropower, LDO

V : 4.2V to 30/36V, V

Reverse Battery Protection, SOT-223, S8, Z Packages

= 3.75V, V = 0.42V, I = 30µA, I = 16µA,

OUT DO Q SD

IN

LT1129

LT1616

LT1676

LT1761

LT1762

LT1763

V : 4.2V to 30V, V = 3.75V, V = 0.4V, I = 50µA, I = 16µA,

IN

OUT

DO

Q

SD

DD, S0T-223, S8,TO220-5, TSSOP20 Packages

25V, 500mA (I ), 1.4MHz, High Efficiency

V : 3.6V to 25V, V

= 1.25V, I = 1.9mA, I = <1µA, ThinSOT Package

Q SD

OUT

IN

OUT

Step-Down DC/DC Converter

60V, 440mA (I ), 100kHz, High Efficiency

V : 7.4V to 60V, V

IN

= 1.24V, I = 3.2mA, I = 2.5µA, S8 Package

Q SD

OUT

Step-Down DC/DC Converter

100mA, Low Noise Micropower, LDO

V : 1.8V to 20V, V

= 1.22V, V = 0.3V, I = 20µA, I = <1µA,

OUT DO Q SD

IN

Low Noise < 20µV

, Stable with 1µF Ceramic Capacitors, ThinSOT Package

RMS P-P

150mA, Low Noise Micropower, LDO

500mA, Low Noise Micropower, LDO

V : 1.8V to 20V, V

IN

= 1.22V, V = 0.3V, I = 25µA, I = <1µA,

OUT

DO

Q

SD

Low Noise < 20µV

, MS8 Package

RMS P-P

V : 1.8V to 20V, V

IN

= 1.22V, V = 0.3V, I = 30µA, I = <1µA,

OUT

DO

Q

SD

Low Noise < 20µV

, S8 Package

RMS P-P

LT1764/LT1764A 3A, Low Noise, Fast Transient Response, LDO

V : 2.7V to 20V, V

= 1.21V, V = 0.34V, I = 1mA, I = <1µA,

OUT DO Q SD

IN

Low Noise < 40µV

, “A” Version Stable with Ceramic Capacitors,

RMS P-P

DD, TO220-5 Packages

LT1766

LT1776

60V, 1.2A (I ), 200kHz, High Efficiency

Step-Down DC/DC Converter

V : 5.5V to 60V, V

= 1.20V, I = 2.5mA, I = 25µA, TSSOP16/E Package

Q SD

OUT

IN

OUT

40V, 550mA (I ), 200kHz, High Efficiency

V : 7.4V to 40V, V

IN

= 1.24V, I = 3.2mA, I = 30µA, N8, S8 Packages

Q SD

OUT

Step-Down DC/DC Converter

LT1934/

LT1934-1

300mA/60mA, (I ), Constant Off-Time, High

Efficiency Step-Down DC/DC Converter

90% Efficiency, V : 3.2V to 34V, V

ThinSOT Package

= 1.25V, I = 14µA, I = <1µA,

OUT Q SD

OUT

IN

LT1956

60V, 1.2A (I ), 500kHz, High Efficiency

Step-Down DC/DC Converter

V : 5.5V to 60V, V

IN

= 1.20V, I = 2.5mA, I = 25µA, TSSOP16/E Package

OUT Q SD

OUT

LT1962

300mA, Low Noise Micropower, LDO

V : 1.8V to 20V, V

= 1.22V, V = 0.27V, I = 30µA, I = <1µA,

IN

OUT

DO

Q

SD

Low Noise < 20µV

, MS8 Package

RMS P-P

LT1963/LT1963A 1.5A, Low Noise, Fast Transient Response, LDO

V : 2.1V to 20V, V

= 1.21V, V = 0.34V, I = 1mA, I = <1µA,

OUT DO Q SD

IN

Low Noise < 40µV

, “A” Version Stable with Ceramic Capacitors,

RMS P-P

DD, TO220-5, S0T-223, S8 Packages

LT1964

LT3010

200mA, Low Noise Micropower, Negative LDO

50mA, High Voltage, Micropower LDO

V : –1.9V to –20V, V

= –1.21V, V = 0.34V, I = 30µA, I = 3µA,

OUT DO Q SD

IN

Low Noise < 30µV

, Stable with Ceramic Capacitors, ThinSOT Package

RMS P-P

V : 3V to 80V, V

IN

= 1.2V, V = 0.3V, I = 30µA, I < 1µA,

DO Q SD

, Stable with 1µF Output Capacitor, Exposed

OUT(MIN)

Low Noise: <100µV

MS8E Package

RMS

3013bfa

LT 0306 REV A • PRINTED IN USA

16 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LT3013B
厂家：	Linear
描述：	250mA, 4V to 80V Low Dropout Micropower Linear Regulator with PWRGD 250毫安， 4V至80V低压差微功耗线性稳压器，具有PWRGD 稳压器
文件：	总16页 (文件大小：217K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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