LT5546EUF_技术文档

LT5546

40MHz to 500MHz VGA

and I/Q Demodulator with

17MHz Baseband Bandwidth

U

FEATURES

DESCRIPTIO

TheLT^®5546isa40MHzto500MHzmonolithicintegrated

quadraturedemodulatorwithvariablegainamplifier(VGA)

and17MHzI/Qbasebandbandwidthdesignedforlowvolt-

ageoperation.Itsupportsstandardsthatusealinearmodu-

lationformat.ThechipconsistsofaVGA,quadraturedown-

converting mixers and 17MHz lowpass noise filters (LPF).

The LO port consists of a divide-by-two stage and LO

buffers. The IC provides all building blocks for IF down-

conversion to I and Q baseband signals with a single

supplyvoltageof1.8Vto5.25V. TheVGAgainhasalinear-

in-dB relationship to the control input voltage. Hard-clip-

ping amplifiers at the mixer outputs reduce the recovery

time from a signal overload condition. The lowpass filters

reduce the out-of-band noise and spurious frequency

components. The –3dB corner frequency of the noise

filters is approximately 17MHz and has a first order roll-

off. The standby mode provides reduced supply current

andfasttransientresponseintothenormaloperatingmode

when the I/Q outputs are AC-coupled to a baseband chip.

, LTC and LT are registered trademarks of Linear Technology Corporation.

■

17MHz I/Q Lowpass Output Noise Filters

■

Wide Range 1.8V to 5.25V Supply Voltage

■

Frequency Range: 40MHz to 500MHz

■

THD < 0.14% (–57dBc)

at 800mV_P-PDifferential Output Level

■

IF Overload Detector

■

Log Linear Gain Control Range: –7dB to 56dB

■

Baseband I/Q Amplitude Imbalance: 0.2dB

■

Baseband I/Q Phase Imbalance: 0.6°

■

7.8dB Noise Figure at Max Gain

■

Input IP3 at Low Gain: –1dBm

■

Low Supply Current: 24mA

■

Low Delay Shift Over Gain Control Range: 2ps/dB

■

Outputs Biased Up While in Standby

■

16-Lead QFN 4mm × 4mm Package with Exposed Pad

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APPLICATIO S

■

GPS IF Receivers

■

Satellite IF Receivers

■

VHF/UHF Receivers

Wireless Local Loop

■

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TYPICAL APPLICATIO

Total Harmonic Distortion vs

IF Input Level at 1.8V Supply

1.8V

280MHz

IF INPUT

C2

C1

+

–25

1µF

1nF

IF

L1

15nH

C3

10pF

L2

15nH

f

= 280MHz

= 280.1MHz

= 570MHz

IF, 1

IF, 2

2xLO

V

–30

–35

–40

–45

–50

–55

–60

CC

+

–

I

OUT

800mV DIFFERENTIAL OUT

P-P

–

IF

OUT

IF DET

+

V

CTRL

C3

1.8pF

GAIN CONTROL

+

2xLO

Q

OUT

2xLO

C4

L3

39nH

560MHz

3.3pF

–

÷2

Q

OUT

INPUT

–

2xLO

LT5546

EN

ENABLE

STBY

STANDBY

GND

C5

3.3pF

5546 TA01

–60

–40

–30

–20

–10

–50

IF INPUT POWER EACH TONE (dBm)

5546 TA01b

5546f

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LT5546

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ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

(Note 1)

TOP VIEW

ORDER PART

NUMBER

Supply Voltage ....................................................... 5.5V

Differential Voltage Between 2xLO⁺and 2xLO^–.......... 4V

IF⁺, IF^–............................................. –500mV to 500mV

I_OUT⁺, I_OUT^–, Q_OUT⁺, Q_OUT^–..................V_CC– 1.8V to V_CC

Operating Ambient Temperature

16 15 14 13

LT5546EUF

GND

1

2

3

4

12 STBY

+

IF

11 2xLO

17

–

IF

2xLO

EN

10

9

GND

(Note 2) ...................................................–40°C to 85°C

Storage Temperature Range ..................–65°C to 125°C

Voltage on Any Pin

5

6

7

8

UF PART MARKING

5546

Not to Exceed ........................ –500mV to V_CC+ 500mV

UF PACKAGE

16-LEAD (4mm × 4mm) PLASTIC QFN

T_JMAX= 125°C, θ_JA= 37°C/W

EXPOSED PAD IS GND (PIN 17)

(MUST BE SOLDERED TO PCB)

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

V_CC= 3V, f_2xLO= 570MHz, P_2xLO= –5dBm (Note 5), f_IF= 284MHz,

P_IF= –30dBm, I and Q outputs 800mV_P-Pinto 4kΩ differential load, T_A= 25°C, EN = V_CC, STBY = V_CC, unless otherwise noted. (Note 3)

SYMBOL

IF Input

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

f

Frequency Range

Nominal Input Level

Input Impedance

40 to 500

MHz

dBm

IF

R

= 200Ω Differential

–76 to –19

SOURCE

+

–

IF , IF to GND, EN = V

IF , IF to GND, EN = GND

100Ω//1.2pF

CC

+

–

1pF

NF

Noise Figure at Max Gain

Min Gain (Note 4)

V

= 1.7V

= 0.2V

= 1.7V

7.8

1.6

56

dB

CTRL

G

6

L

Max Gain (Note 4)

49

H

IIP3

Input IP3, Min Gain

Input IP3, Max Gain

P

= –22.5dBm (Note 7)

= –75dBm (Note 7)

–1

–49

dBm

IF

IIP2

Input IP2, Min Gain

Input IP2, Max Gain

V

= 0.2V (Note 9)

= 1.7V (Note 9)

36

–25

dBm

CTRL

Demodulator I/Q Output

Nominal Voltage Swing

(Note 6)

0.8

V

P-P

Clipping Level

1.47

P-P

DC Common Mode Voltage

I/Q Amplitude Imbalance

I/Q Phase Imbalance

DC Offset

V

– 1.19

V

CC

(Note 8)

0.14

0.6

3

dB

(Note 8)

0.6

21

Deg

mV

kΩ

(Notes 6, 8)

Single Ended, C

(Note 6)

Output Driving Capability

Small-Signal Output Impedance

STBY to Turn-On Delay

I/Q Output 1dB Compression

I/Q Output IM3

≤ 10pF

2

1.5

LOAD

r

180

0.3

Ω

o

µs

–10

–49

dBm

dBc

P

= –25.5dBm, 280MHz

= –25.5dBm, 280.1MHz (Note 7)

IF, 1

IF, 2

5546f

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LT5546

ELECTRICAL CHARACTERISTICS

V_CC= 3V, f_2×LO= 570MHz, P_2×LO= –5dBm (Note 5), f_IF= 284MHz,

P_IF= –30dBm, I and Q outputs 800mV_P-Pinto 4kΩ differential load, T_A= 25°C, EN = V_CC, STBY = V_CC, unless otherwise noted. (Note 3)

SYMBOL

Variable Gain Amplifier (VGA)

Gain Slope Linearity Error

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

= 0V to 1.4V

±0.5

±0.4

90

dB

CTRL

Temperature Gain Shift

T = –40°C to 85°C, V

= 0V to 1.4V

CTRL

Gain Control Response Time

Gain Control Voltage Range

Gain Control Slope

Settled within 10% of Final Value

ns

0 to 1.7

41

V

dB/V

kΩ

Gain Control Input Impedance

Delay Shift Over Gain Control

To Internal 0.2V Reference

Measured Over 10dB Step

25

2

ps/dB

Baseband Lowpass Filter (LPF)

–3dB Cutoff Frequency

Amplitude Roll-Off at 50MHz

Group Delay Ripple

13

17

–9

1

MHz

dB

ns

2xLO Input

f

Frequency Range

Input Power

80 to 1000

–5

MHz

dBm

2xLO

P

1:2 Transformer with 240Ω Shunt Resistor (Note 5)

–20

2xLO

Input Power

LC Balun (Note 5)

–10

+

–

Input Impedance

DC Common Mode Voltage

Differential Between 2xLO and 2xLO

800Ω//0.4pF

V

– 0.4

V

CC

IF Detector

IF Detector Range

Referred to IF Input

–30 to 8

0.27 to 1.2

80

dBm

V

Output Voltage Range

Detector Response Time

For P = –30dBm to 8dBm

IF

With External 1.8pF Load,

ns

Settling within 10% of Final Value

Power Supply

V

Supply Voltage

Supply Current

Shutdown Current

Standby Current

1.8

5.25

34

30

6

V

mA

µA

CC

I

EN = High, STBY = Low or High

EN, STBY < 350mV

24

0.2

3.6

CC

OFF

EN = Low; STBY = High

mA

STBY

Mode

Enable

Enable Pin Voltage

Standby Pin Voltage

EN = High

1

V

Disable

Standby

No Standby

EN = Low

0.5

STBY = High

STBY = Low

Note 1: Absolute Maximum Ratings are those values beyond which the life

Note 5: If a narrow-band match is used in the 2xLO path instead of a 1:2

transformer with 240Ω shunt resistor, 2xLO input power can be reduced

to –10dBm, without degrading the phase imbalance. See Figure 11 and

Figure 6.

of a device may be impaired.

Note 2: Specifications over the –40°C to 85°C temperature range are

assured by design, characterization and correlation with statistical process

controls.

Note 3: Tests are performed as shown in the configuration of Figure 6. The

IF input transformer loss is substracted from the measured values.

Note 4: Power gain is defined here as the I (or Q) output power into a 4kΩ

differential load, divided by the IF input power in dB. To calculate the

voltage gain between the differential I output (or Q output) and the IF

input, including ideal matching network, 10 • log(4kΩ/50) = 19dB has to

be added to this power gain.

+

–

Note 6: Differential between I

and I

(or differential between

OUT

+

–

Q

and Q

).

OUT

Note 7: The gain control voltage V

is set in such a way that the

CTRL

+

–

differential output voltage between I

and I

(or differential between

OUT

+

–

Q

OUT

and Q

) is 800mV , with the given input power P . IF

OUT

P-P

IF

frequencies are 280MHz and 280.1MHz, with f

= 570MHz.

2xLO

Note 8: The typical parameter is defined as the mean of the absolute

values of the data distribution.

Note 9: IF frequency is 125MHz, with f

= 502MHz.

2xLO

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LT5546

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TYPICAL PERFOR A CE CHARACTERISTICS

V_CC= 3V, f_2×LO= 570MHz, P_2×LO= –5dBm

(Note 5), f_IF= 284MHz, P_IF= –30dBm, I and Q outputs 800mV_P-Pinto 4kΩ differential load, T_A= 25°C, EN = V_CC, STBY = V_CC

,

unless otherwise noted. (Note 3)

Gain and Noise Figure

Supply Current vs Supply Voltage

vs Control Voltage at 3V Supply

28

26

24

22

20

60

50

40

30

20

10

0

85°C

25°C

NF

GAIN AT 25°C

NF AT 25°C

GAIN AT –40°C

NF AT –40°C

GAIN AT 85°C

NF AT 85°C

–40°C

GAIN

f

= 284MHz

IF

2xLO

= 570MHz

–10

1.75

2.75 3.25 3.75 4.25 4.75 5.25

SUPPLY VOLTAGE (V)

2.25

0.3

0.6

0.9

1.2

1.8

0

1.5

V

(V)

CTRL

5546 G01

5546 G02

Gain and Noise Figure

vs Control Voltage at 1.8V Supply

Gain Flatness

vs Control Voltage at 3V Supply

0.5

0.4

60

50

40

30

20

10

0

–40°C

0.3

0.2

85°C

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

25°C

NF

GAIN AT –40°C

NF AT 25°C

GAIN AT 25°C

NF AT –40°C

GAIN AT 85°C

NF AT 85°C

GAIN

f

= 284MHz

IF

2xLO

= 570MHz

–10

0

0.3

0.9

(V)

1.2

1.5

0.6

0.3

0.6

0.9

1.2

1.8

0

1.5

V

(V)

CTRL

5546 G04

5546 G03

Gain and Noise Figure

vs IF Frequency at 3V Supply

Gain and Noise Figure

vs Control Voltage and V_CC

60

50

40

30

20

10

0

60

50

40

30

20

10

0

GAIN, V

= 1.6V

CTRL

NF, V

= 0.2V

CTRL

GAIN, V

= 0.9V

CTRL

NF, V

= 0.9V

CTRL

NF

GAIN AT 1.8V

NF AT 1.8V

GAIN AT 3V

NF AT 3V

GAIN AT 5.25V

NF AT 5.25V

NF, V

= 1.6V

CTRL

GAIN

f

= 284MHz

GAIN, V

= 0.2V

IF

2xLO

CTRL

100

= 570MHz

–10

0.3

0.6

0.9

1.2

1.8

0

1.5

10

1000

IF FREQUENCY (MHz)

V

CTRL

(V)

5546 G06

5546 G05

5546f

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LT5546

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V_CC= 3V, f_2×LO= 570MHz, P_2×LO= –5dBm

TYPICAL PERFOR A CE CHARACTERISTICS

(Note 5), f_IF= 284MHz, P_IF= –30dBm, I and Q outputs 800mV_P-Pinto 4kΩ differential load, T_A= 25°C, EN = V_CC, STBY = V_CC

unless otherwise noted. (Note 3)

,

Total Harmonic Distortion

vs IF Input Power and IF

Frequency

Total Harmonic Distortion

vs IF Input Power at 3V Supply

and 800mV_P-PDifferential Out

vs IF Input Power at 1.8V Supply

and 800mV_P-PDifferential Out

–25

–30

–35

–40

–45

–50

–55

–60

–25

–30

–35

–40

–45

–50

–55

–60

–25

–30

–35

–40

–45

–50

–55

–60

f

= 280MHz

= 280.1MHz

= 570MHz

800mV DIFFERENTIAL OUT

P-P

3V SUPPLY

f

= 280MHz

= 280.1MHz

= 570MHz

IF,1

IF,2

2xLO

IF,1

IF,2

2xLO

25°C

–40°C

85°C

25°C

–40°C

85°C

f

= 280MHz

IF

f

= 40MHz

IF

f

IF

= 500MHz

–50

–40

–20

–10

–50

–40

–20

–10

–50

–40

–20

–10

–60

–30

IF INPUT POWER EACH TONE (dBm)

5546 G07

5546 G08

5546 G09

LPF Frequency Response

vs Baseband Frequency

and Temperature

Total Harmonic Distortion

vs IF Input Power at 500mV_P-P

Differential Out

Total Harmonic Distortion vs IF

Input Power and Supply Voltage

–25

–30

–35

–40

–45

–50

–55

–60

–20

–25

–30

0

800mV DIFFERENTIAL OUT

P-P

V

= 3V

CC

f

= 280MHz

= 280.1MHz

= 570MHz

IF,1

IF,2

f

= 280MHz

= 280.1MHz

= 570MHz

–1

–2

–3

IF,1

IF,2

2xLO

V

CC

= 3V

–40°C

–35

–40

–45

–50

–4

–5

3V

25°C

85°C

–6

–7

25°C

85°C

1.8V

–55

–60

–65

5.25V

–8

–9

–10

–50

–40

–20

–10

–60

–30

0

10 15 20 25 30 35 40 45 50 55

BASEBAND FREQUENCY (MHz)

5

–40

–35

–30

–25

–20

IF INPUT POWER EACH TONE (dBm)

5546 G10

5546 G12

5546 G11

LPF Frequency Response

vs Baseband Frequency and

Supply Voltage

IF Detector Output Voltage vs

IF Input CW Power at 3V Supply

IF Detector Output Voltage vs

IF Input CW Power at 1.8V Supply

1.4

1.2

1.4

1.2

0

f

IF

= 280MHz

f

IF

= 280MHz

T

= 25°C

A

–1

–2

–3

1.8V

1.0

0.8

1.0

0.8

85°C

–4

–5

85°C

3V

25°C

–6

–7

25°C

0.6

0.4

0.2

0.6

0.4

0.2

–8

–9

5.25V

–40°C

–40 –30

–10

–20

–10

0

10

–40

–30

–20

–10

0

10

0

10 15 20 25 30 35 40 45 50 55

BASEBAND FREQUENCY (MHz)

5

IF INPUT CW POWER (dBm)

5546 G15

5546 G14

5546 G13

5546f

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LT5546

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V_CC= 3V, f_2×LO= 570MHz, P_2×LO= –5dBm

TYPICAL PERFOR A CE CHARACTERISTICS

unless otherwise noted. (Note 3)

(Note 5), f_IF= 284MHz, P_IF= –30dBm, I and Q outputs 800mV_P-Pinto 4kΩ differential load, T_A= 25°C, EN = V_CC, STBY = V_CC

,

IF Detector Output Voltage

vs IF Input CW Power and

Supply Voltage

IF Detector Output Voltage vs IF

Input CW Power and IF Frequency

Phase Relation Between I and Q

Outputs vs LO Input Power

1.4

1.2

1.0

95

94

93

92

91

90

89

88

1.4

f

IF

f

IF

f

IF

f

IF

f

IF

= 284MHz, 25°C

= 284MHz, –40°C

= 284MHz, 85°C

= 40MHz, 25°C

= 500MHz, 25°C

V

CC

= 3V

f

IF

= 280MHz

f

IF

= 500MHz

1.2

f

IF

= 280MHz

5.25V

1.8V

1.0

0.8

3V

f

IF

= 40MHz

0.8

0.6

0.4

0.2

0.6

0.4

0.2

V

CC

= 3V

–30

–20

–10

10

–40

0

10

–20 –15

–10

–5

5

–40

–30

–20

–10

0

10

IF INPUT CW POWER (dBm)

LO INPUT POWER (dBm)

5546 G17

5546 G18

5546 G16

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PI FU CTIO S

GND (Pins 1, 4 and 17): Ground. Pins 1 and 4 are

connected to each other internally. The exposed pad (Pin

17) is not connected internally to Pins 1 and 4. For chip

functionality, the exposed pad and either Pin 1 or Pin 4

must be connected to ground. For best RF performance,

Pin 1, Pin 4 and the exposed pad should be connected to

RF ground.

IF⁺, IF^–(Pins 2, 3): Differential Inputs for the IF Signal.

Each pin must be DC grounded through an external

inductor or RF transformer with central ground tap. This

pathshouldhaveaDCresistancelowerthan2Ωtoground.

EN (Pin 9): Enable Input. When the enable pin voltage is

higher than 1V, the IC is completely turned on. When the

input voltage is less than 0.5V, the IC is turned off, except

the part of the circuit associated with standby mode.

2xLO^–, 2xLO⁺(Pins 10, 11): Differential Inputs for the

2xLO Input. The 2xLO input frequency must be twice that

of the IF frequency. The internal bias voltage is V_CC– 0.4V.

STBY (Pin 12): Standby Input. When the STBY pin is

higher than 1V, the standby mode circuit is turned on to

prebias the I/Q buffers. When the STBY pin is less than

0.5V, the standby mode circuit is turned off.

V_CC(Pins 5 and 8): Power Supply. These pins should be

decoupled to ground using 1000pF and 0.1µF capacitors.

+

Q_OUT^–, Q_OUT(Pins 13, 14): Differential Baseband Out-

puts of the Q Channel. Internally biased at V_CC– 1.19V.

V_CTRL(Pin 6): VGA Gain Control Input. This pin controls

the IF gain and its typical input voltage range is 0.2V to

1.7V. It is internally biased via a 25k resistor to 0.2V,

setting a low gain if the V_CTRLpin is left floating.

I_OUT^–, I_OUT⁺(Pins 15, 16): Differential Baseband Outputs

of the I Channel. Internally biased at V_CC– 1.19V.

IF DET (Pin 7): IF Detector Output. For strong IF input

signals, the DC level at this pin is a function of the IF input

signal level.

5546f

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LT5546

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BLOCK DIAGRA

V

CC

5

CC

8

+

CLIPPER

VGA

16

15

I

2

3

IF

OUT

I-MIXER LPF

–

IF

OUT

90°

7

IF DET

V

CTRL

6

DETECTOR

+

2×LO

LPF

Q-MIXER

11

+

Q

14

13

OUT

÷2

–

Q

0°

OUT

CLIPPER

–

2×LO 10

9

1

4

17

12

5546 BD

STBY

EN

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APPLICATIO S I FOR ATIO

The LT5546 consists of a variable gain amplifier (VGA),

I/Q demodulator, quadrature LO generator, lowpass fil-

ters (LPFs), clipping amplifiers (clippers) and bias cir-

cuitry.

schematic is shown using a 1:4 transformer. The mea-

suredinputsensitivityofthisboardisabout–80.5dBmfor

a 10dB signal-to-noise ratio. In the case of an L-C match-

ing circuit, the circuit of Figure 1 can be used. In Table 1

the matching network component values are given for a

range of IF frequencies. The matching circuit of Figure 1

approaches 180° phase shift between IF⁺and IF^–in a

broad range around its center frequency. However, some

amplitudemismatchoccursifthecircuitisnottunedtothe

center frequency. This leads to reduced circuit linearity

performance, because one of the inputs carries a higher

signal compared to the perfectly balanced case. A 10%

frequency shift from the center frequency results in about

a 2dB gain difference between the IF⁺and IF^–inputs. This

results in a 1.5dB higher IM3 contribution from the input

stage which leads to a 0.75dB drop in IIP3. Moreover, the

IIP2ofthecircuitisalsoreducedwhichcanleadtoahigher

second order harmonic contribution. The circuit can be

drivensingleended, butthisisnotrecommendedbecause

it leads to a 3dB drop in gain and a considerable increase

in IM5 and IM7 components. The single-ended noise

figure increases by 4dB if one IF input is directly grounded

and increases by 1.5dB if one IF input is grounded via a

1µH inductor. An IF input cannot be left open or connected

via a resistor to ground because this will disturb the

internal biasing, reducing the gain, noise and linearity

performance. For optimal performance, it is important to

keep the DC impedance to ground of both IF inputs lower

than 2Ω. In the matching network of Figure 1, inductor L3

is used for supplying the DC bias current to the IF⁺input.

The IF signal is fed to the inputs of the VGA. The VGA gain

is typically set by an external signal in such a way that the

amplified IF signal delivered to the I/Q mixers is constant.

The IF signal is then converted into I/Q baseband signals

using the I/Q down-converting mixers. The quadrature LO

signals that drive the mixers are internally generated from

the on-chip divide-by-two circuit. The I/Q signals are

passed through first-order low-pass filters and subse-

quently a pair of hard-clipping amplifiers (clippers). After

externallysettingtherequiredgain,theseamplifiersshould

notclip. However, intheeventofoverload, theyreducethe

settlingtimeofany(optional)externalACcouplingcapaci-

tors by preventing asymmetrical charging and discharg-

ing effects. The I/Q baseband outputs are buffered by

output drivers.

VGA and Input Matching

The VGA has a nominal 60dB gain control range with a

frequency range of 40MHz to 500MHz. The inputs of the

VGA must have a DC return to ground. This can be done

using a transformer with a central tap (on the secondary)

oranLCmatchingcircuitwithamatchedimpedanceatthe

frequency of interest and near zero impedance at DC. The

differential AC input impedance of the LT5546 is about

200Ω, thus a 1:4 (impedance ratio) RF transformer with

center tap can be used. In Figure 6, the evaluation board

5546f

7

LT5546

U

W

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APPLICATIO S I FOR ATIO

C3

L1

IF

INPUT

56pF

+

–

V

TO IF

C1

10pF

TO IF

BIAS

56nH

IF

INPUT

+

–

TO IF

75Ω

1mA

75Ω

L1

15nH

L2

15nH

C1

5.6pF

L3

120nH

L2

56nH

C2

5.6pF

+

–

IF

5546 F02

5546 F01

(2a)

(2b)

Figure 2a. Simplified IF Input Matching Network at 280MHz

and Figure 2b. Simplified Circuit Schematic of the IF Inputs

Figure 1. Example L-C IF Input Matching Network at 280MHz

Table 1. The Component Values of Matching Network L1, L2, L3,

C1, C2 and C3.

degrees, depending on the quality factor of the network.

This will result in a reduction in the gain. The higher the

chosen quality factor, the closer the phase difference will

approach 180 degrees. However, a higher quality factor

will reduce bandwidth and create more loss in the match-

ing network. For minimum board space, 0402 compo-

nents are used. The measured noise figure for maximum

gain with this matching network is about 9.4dB, and the

maximum gain is about 55dB. Assuming 0402 inductors

with Q = 35, the insertion loss of this network is about

2.5dB. The tolerance for the components in Figure 2a can

be 10% for a return loss higher than 10dB and a gain

reductionduetomismatchlessthan0.5dB. Themeasured

input sensitivity for this matching network (see also Fig-

ure 11) is about –78.3dBm for a 10dB signal-to-noise

ratio.

f (MHz)

L1, L2(nH)

C1, C2(pF)

34

L3(nH)

1800

470

C3(pF)

820

220

56

IF

50

340

159

106

80

100

150

200

250

300

350

400

450

500

15.9

10.6

8.0

470

64

6.4

120

53

5.3

120

56

45

4.5

120

56

40

4.0

120

56

35

3.5

120

56

32

3.2

120

56

To keep the DC resistance of L3 below 2Ω, 120nH is used.

Thisdisturbsthematchingnetworkslightlybycausingthe

frequency where the S11 is minimal to be lower than the

frequency where the amplitudes of IF⁺and IF^–are equal.

To compensate for this, the value of coupling capacitor C3

is lowered and will contribute some correcting reactance.

For low frequencies, it might not be possible to find any

practical inductor value for L3 with DC resistance smaller

than 2Ω. In that case it is recommended to use a trans-

formerwithacentertap.Thetoleranceforthecomponents

in Figure 1 can be 10% for a return loss higher than 16dB

and a gain reduction due to mismatch less than 0.3dB.

The gain of the VGA is set by the voltage at the V_CTRLpin.

For high gain settings, both the noise figure and the input

IP3 will be low. From a noise figure point of view, it is

advantageous to work as closely as possible to the maxi-

mum gain point. However, if the voltage at the V_CTRLpin

is increased beyond the maximum gain point (where

additional increase in control voltage does not give an

increase in gain), the response time of the gain control

circuit is increased. If control speed is crucial, a few dB of

gain margin should be allowed from the highest gain point

to be sure that at all temperatures, the maximum gain

settingisnotcrossed.Atlowgainsettings,thenoisefigure

and the input IP3 will be high. Optionally, the control

voltage V_CTRLcan be set lower than 0.2V. The normal

range is from V_CTRL= 0.2V to 1.7V, which results in a

nominal gain range from 1.6dB to 56.8dB. The linear-in-

dB gain relation with the V_CTRLvoltage still holds for

control voltages as low as –0.35V. This results in an

5546f

It is possible to simplify the input matching circuit and

compromise the performance. In Figure 2a, the simplified

matching network is given.

Thismatchingnetworkcandeliverequalamplitudestothe

IF⁺and IF^–inputs for a narrow frequency region, but the

phasedifferencebetweentheinputswillnotbeexactly180

degrees. In practice, the phase shift will be around 145

8

LT5546

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APPLICATIO S I FOR ATIO

U

V

CC

extended gain control range of –23dB to 57dB. The V_CTRL

pin is a very sensitive input because of its high input

impedance and therefore should be well shielded. Signal

pickup on the V_CTRLpin can lead to spurs and increased

noise floor in the I/Q baseband outputs. It can degrade the

linearity performance and it can cause asymmetry in the

two-tone test. If control speed is not important, 1µF

bypass capacitors are recommended between V_CTRLand

ground.

+

400mV

–

+

–

8k

2xLO

IF DET

1k

3.8k

5546 F03

(3b)

(3a)

A fast responding peak detector is connected to the VGA

input, sensitive to signal levels above the signal levels

where the VGA is operating in the linear range. It is active

from –22dBm up to 5dBm IF input signal levels. The DC

output voltage of this detector (IF DET) can be used by the

baseband controller to quickly determine the presence of

a strong input level at the desired channel, and adjust gain

accordingly. Figure 3a shows the simplified circuit sche-

matic of the IF DET output.

Figure 3a. Simplified Circuit Schematic of the

IF DET Output and Figure 3b. The 2xLO Inputs

3.3pF

100pF

2xLO

INPUT

2xLO

INPUT

+

–

TO 2xLO

56Ω

39nH

1:4

2xLO

INPUT

+

TO 2xLO

100pF

–

TO 2xLO

240Ω

3.3pF

–

TO 2xLO

5546 F04

I/Q Demodulators

(4b)

(4c)

(4a)

The quadrature demodulators are double balanced mix-

ers, down-converting the amplified IF signal from the VGA

into I/Q baseband signals. The quadrature LO signals are

generated internally from a double frequency external CW

signal. The nominal output voltage of the differential I/Q

baseband signals should be set to 0.8V_P-Por lower,

depending on the linearity requirements. The magnitudes

of I and Q are well matched and their phases are 90° apart.

Figure 4. 2xLO Input Matching Networks for 4a) Narrow Band

Tuned to 570MHz, 4b) Wide Band, 4c) Single-Ended Wide Band

dal waveforms of the 2xLO input signal. The phase rela-

tion between I and Q is always 90°, i.e. I always leads Q by

90°. Figure 3b shows the simplified circuit schematic of

the 2xLO inputs. Depending on the application, different

2xLO input matching networks can be chosen. In Figure

4,threeexamplesaregiven.Thefirstnetworkprovidesthe

best 2xLO input sensitivity because it can boost the 2xLO

differentialinputsignalusinganarrow-bandresonantap-

proach.Thesecondnetworkgivesawide-bandmatch,but

the 2xLO input sensitivity is about 2dB lower. The third

network gives a simple and less expensive wide-band

match,but2xLOinputsensitivitydropsbyabout9dB.The

IF input sensitivity doesn’t change significantly using any

of the three 2xLO matching networks.

Quadrature LO Generator

The quadrature LO generator consists of a divide-by-two

circuit and LO buffers. An input signal (2xLO) with twice

the desired IF signal frequency is used as the clock for the

divide-by-twocircuit,producingthequadratureLOsignals

for the demodulators. The outputs are buffered and then

drivethedown-convertingmixers. Withafullydifferential

approach, the quadrature LO signals are well matched.

Second harmonic content (or higher order even harmon-

ics)intheexternal2xLOsignalcandegradethe90° phase

shift between I and Q. Therefore, such content should be

minimized. Indisableorstandbymode, thedivide-by-two

stageispowereddown.Afterenablingthecircuit,thephase

relation between the IF signal and the baseband (I or Q)

signals can be either 0° or 180°, since the circuit cannot

distinguishbetweenthetwosubsequentidenticalsinusoi-

Baseband Circuit

The baseband circuit consists of I/Q low-pass filters, I/Q

hard limiters (clippers) and I/Q output buffers. The hard

limiters operate as linear amplifiers normally. However, if

a high level input temporarily overloads a linear amplifier,

then the circuit will limit symmetrically, which will help to

prevent the output buffer from overloading. This speeds

5546f

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APPLICATIO S I FOR ATIO

up recovery from an overload event, which can occur

during the gain settling. The clipping level is approxi-

mately constant over temperature. The first order inte-

grated lowpass filters are used for noise filtering of the

down-converted baseband signals for both the I channel

and the Q channel. These filters are well matched in gain

response. The –3dB corner frequency is typically 17MHz.

The I/Q outputs can drive 2kΩ in parallel with a maximum

capacitive loading of 10pF at 5MHz, from all four pins to

ground. The outputs are internally biased at V_CC– 1.19V.

Figure 5 shows the simplified output circuit schematic of

the I channel or Q channel.

and standby mode, the maximum discharging current is

about 300µA, and the maximum charging current is more

than 4mA. In Figure 5 the simplified circuit schematic of

the STBY (or EN) input is shown.

Table 2. The Logic of Different Operating Modes

EN

STBY

Comments

Low

High

Low

Shutdown Mode

Standby Mode

High

Low or High

Normal Operation Mode

V

CC

V

CC

TheI/QbasebandoutputscanbeDC-coupledtotheinputs

ofabasebandchip.ForAC-coupledapplicationswithlarge

capacitors, the STBY pin can be used to pre-bias the

outputs to nominal V_CC– 1.19V at much reduced current.

Thismodedrawsonly3.6mAsupplycurrent. WhentheEN

pin is then driven high (>1V), the chip is quickly switched

to normal operating mode, avoiding the introduction of

large charging time constants. Table 2 shows the logic of

the EN pin and STBY pin. In both normal operating mode

+

I CHANNEL (OR

Q CHANNEL):

DIFFERENTIAL

SIGNALS

I

OUT

+

–

(OR Q

)

OUT

–

I

OUT

(OR Q

)

OUT

22k

FROM LPF

STBY

(OR EN)

300µA

5546 F05

Figure 5. Simplified Circuit Schematic of I Channel

(or Q Channel) Outputs and STBY (or EN) Input

OPTIONAL

+

–

+

–

I

Q

OUT OUT

OUT

V

5V

CC3

C37

0.1µF

C35

4.7µF

C36

4.7µF

C38

0.1µF

R43

2k

R50

2k

C34

0.1µF

C27

0.1µF

R45

1k

R41

1k

C31

1µF

C30

1µF

3

2

3

2

7

R47

49.9Ω

R44

49.9Ω

+

J1

J2

U3

U2

6

C1

5.6pF

C2

5.6pF

R46

R39

Q

I

OUT

LT1818CS

3.09k

–

4

R49

2k

R42

2k

C33

0.1µF

C28

0.1µF

C32

1pF

C29

1pF

R48

R40

3.09k

16 15 14

13

–

+

–

+

I

Q

OUT OUT

OUT

V

CC2

T1, 1:4,TR-R

JTX-4-10T

MINI-CIRCUITS

C43

22nF

T2, 1:4, TR-R C45

JTX-4-10T

22nF J4

MINI-CIRCUITS

R35

20k

1

12

J3

GND

STBY

IF

IN

2XLO

2

3

4

11

10

9

+

1

6

IF

2XLO

U1

LT5546

R52

240Ω

–

6

1

GND

EN

R36

20k

IF

DET

7

V

CC

CC CTRL

1 = EN

2 = STBY

5

6

8

17

GND

V

CC1

C15

1nF

C22

1µF

C16

1nF

C39

1µF

5546 F04

SW1

V

CTRL

OVERLOAD

R51

100Ω

C25

1.5pF

C26

1.8pF

NOTE: OUTPUT BUFFERS U2 AND U3 WITH ASSOCIATED

COMPONENTS ARE INCLUDED FOR EVALUATION ONLY.

DEMO BOARD: DC696A

C43, C45, C22, R51, C25, C26 AND C39 ARE OPTIONAL

Figure 6. Evaluation Circuit Schematic with I/Q Output Buffers

5546f

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LT5546

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APPLICATIO S I FOR ATIO

U

Evaluation Board

There is a unity voltage gain relationship for AC signals

between the evaluation board outputs (I and Q) and the

I_OUT⁺, I_OUT^–or Q_OUT⁺and Q_OUT^–outputs of the LT5546

when the evaluation board outputs are terminated in 50Ω.

The evaluation circuit schematic is drawn in Figure 6. The

components associated with buffers U2 and U3 are in-

cluded to drive a 50Ω load for evaluation purposes only.

Figure 8. Component Side Layout of Evaluation Board

Figure 7. Component Side Silkscreen of Evaluation Board

Figure 10. Bottom Side Layout of Evaluation Board

Figure 9. Bottom Side Silkscreen of Evaluation Board

15nH

1.8V

1nF

RX INPUT:

1µF

2.4GHz TO 2.5GHz

10pF

280MHz

V

2

5, 8

CC

IF SAW BP FILTER

BASEBAND

HARD

VGA

RX

PROCESSOR

CLIPPER

I-MIXER LPF

FRONT END

16

15

15nH

3

A/D

I-OUTPUTS

IF DET

1ST LO,

2.12GHz

0°

TO 2.22GHz

7

A/D

D/A

MAIN

SYNTHESIZER

V

CTRL

6

Q-MIXER

14

2ND LO,

560MHz

–10dBm

A/D

13 Q-OUTPUTS

90°

11

AUX

SYNTHESIZER

LPF

HARD

CLIPPER

3.3pF

39nH

10

f/2

12

9

STBY

LT5546

EN

5546 F11

1,4,17

Figure 11. 2.4GHz to 2.5GHz Receiver Application (RX IF = 280MHz)

5546f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

11

LT5546

U

PACKAGE DESCRIPTIO

UF Package

16-Lead Plastic QFN (4mm × 4mm)

(Reference LTC DWG # 05-08-1692)

BOTTOM VIEW—EXPOSED PAD

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

0.75 ± 0.05

R = 0.115

TYP

0.55 ± 0.20

4.00 ± 0.10

(4 SIDES)

15

16

0.72 ±0.05

PIN 1

TOP MARK

1

2

4.35 ± 0.05

2.90 ± 0.05

2.15 ± 0.05

(4 SIDES)

2.15 ± 0.10

(4-SIDES)

PACKAGE

OUTLINE

(UF) QFN 0802

0.30 ± 0.05

0.65 BSC

0.200 REF

0.30 ±0.05

0.65 BCS

0.00 – 0.05

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGC)

2. ALL DIMENSIONS ARE IN MILLIMETERS

3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

4. EXPOSED PAD SHALL BE SOLDER PLATED

RELATED PARTS

PART NUMBER DESCRIPTION

Infrastructure

COMMENTS

LT5511

LT5512

LT5515

High Signal Level Upconverting Mixer

RF Output to 3GHz, 17dBm IIP3, Integrated LO Buffer

DC-3GHz, 20dBm IIP3, Integrated LO Buffer

High Signal Level Downconverting Mixer

1.5GHz to 2.5GHz Direct-Conversion

Quadrature Demodulator

20dBm IIP3, NF =16.8dB, Integrated LO Quadrature Generator

LT5516

LT5522

800MHz to 1.5GHz Direct-Conversion

Quadrature Demodulator

4V to 5.25V Supply, 21.5dBm IIP3, NF = 12.8dB,

Integrated LO Quadrature Generator

600MHz to 2.7GHz High Signal Level

Downconverting Mixer

4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB, 50Ω Single-Ended

RF and LO Ports

RF Power Detectors

LT5504

800MHz to 2.7GHz RF Measuring Receiver

2.7V to 5.25V Supply, 80dB Dynamic Range, Temperature Compensated

LTC5505

LTC5507

LTC5508

LTC5509

LTC5532

RF Power Detectors with >40dB Dynamic Range 2.7V to 6V Supply, 300MHz to 3.5GHz, Temperature Compensated

100kHz to 1000MHz RF Power Detector

0.3GHz to 7GHz RF Power Detector

2.7V to 6V Supply, 48dB Dynamic Range, Temperature Compensated

2.7V to 6V Supply, 44dB Dynamic Range, Temperature Compensated

–30dBm to 6dBm, 600µA Supply Current, Temperature Compensated

300MHz to 3GHz RF Power Detector

300MHz to 7GHz Precision RF Power Detector

Precision V

Offset Control, Adjustable Gain and Offset

OUT

RF Receiver Building Blocks

LT5500

LT5502

LT5503

LT5506

1.8GHz to 2.7GHz Receiver Front End

400MHz Quadrature IF Demodulator with RSSI

1.8V to 5.25V Supply, Dual-Gain LNA, Mixer

1.8V to 5.25V Supply, 70MHz to 400MHz IF, 84dB Limiting Gain, 90dB RSSI Range

1.2GHz to 2.7GHz Direct IQ Modulator and Mixer 1.8V to 5.25V Supply, Four Step RF Power Control, 120MHz Modulation Bandwidth

40MHz to 500MHz Quadrature IF Demodulator

with VGA

1.8V to 5.25V, I/Q Baseband Bandwidth 8.8MHz, –40dB to 57dB Linear Power Gain

5546f

LT/TP 1003 1K • PRINTED IN USA

12 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com

LINEAR TECHNOLOGY CORPORATION 2003


型号：	LT5546EUF
厂家：	Linear
描述：	40MHz to 500MHz VGA and I/Q Demodulator with 17MHz Baseband Bandwidth 40MHz至500MHz的VGA及I / Q解调器， 17MHz基带带宽
文件：	总12页 (文件大小：314K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT5546EUF [Linear]

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