LTC1657LCGN#TRPBF_技术文档

LTC1657/LTC1657L

Parallel 16-Bit Rail-to-Rail

Micropower DAC

FEATURES

DESCRIPTION

TheLTC^®1657/LTC1657Larecompletesinglesupply, rail-

to-rail voltage output, 16-bit digital-to-analog converters

(DAC)ina28-pinSSOPpackage.Theyincludearail-to-rail

output buffer amplifier, an internal reference and a double

buffered parallel digital interface.

n

16-Bit Monotonic Over Temperature

Deglitched Rail-to-Rail Voltage Output: 8nV•s

n

I : 650µA Typ

CC

n

Maximum DNL Error: 1LSꢀ

Settling Time: 20µs to 1LSꢀ

ꢀuilt-In Reference: 2.048V (LTC1657)

1.25V (LTC1657L)

TheLTC1657/LTC1657Lhaveseparatereferenceinputpins

that can be driven by an external reference. The full-scale

outputcanbe1or2timesthereferencevoltagedepending

onhowtheX1/X2pinisconnected. TheLTC1657operates

from a 4.5V to 5.5V supply and has an onboard 2.048V

reference. The LTC1657L operates from a 2.7V to 5.5V

supply and has an onboard 1.25V reference.

n

Internal Power-On Reset to Zero Volts

Asynchronous CLR Pin

Output ꢀuffer Conﬁgurable for Gain of 1 or 2

Parallel 16-ꢀit or 2-ꢀyte Double ꢀuffered Interface

Multiplying Capability

Narrow 28-Lead SSOP Package

The LTC1657/LTC1657L are similar to Linear Technology

Corporation’sLTC1450/LTC1450L12-bitV DACfamily,

OUT

APPLICATIONS

allowinganupgradepath.Theyaretheonlybuffered16-bit

parallel DACs in a 28-lead SSOP package and include an

onboard reference for stand alone performance.

n

Instrumentation

Digital Calibration

Industrial Process Control

Automatic Test Equipment

n

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

n

Communication Test Equipment

BLOCK DIAGRAM

LTC1657: 4.5V TO 5.5V

LTC1657L: 2.7V TO 5.5V

Differential Nonlinearity

vs Input Code

23

22

24

V

REFOUT

REFHI

CC

19 D15 (MSB)

REFERENCE

LTC1657: 2.048V

LTC1657L: 1.25V

18

17

1.0

0.8

MSB

8-BIT

16

15

14

13

12

INPUT

REGISTER

0.6

0.4

16-BIT

DAC

REGISTER

DATA IN FROM

MICROPROCESSOR

DATA BUS

16-BIT

DAC

D8

D7

+

LTC1657:

0.2

V

OUT

25

11

10

9

0V TO 4.096V

LTC1657L:

0V TO 2.5V

0

–

LSB

8-BIT

–0.2

–0.4

–0.6

–0.8

–1.0

8

R

7

INPUT

6

REGISTER

R

5

D0 (LSB)

4

3

1

2

CSMSB

WR

FROM

MICROPROCESSOR

DECODE LOGIC

0

16384

32768

49152

65535

CSLSB

DIGITAL INPUT CODE

28 LDAC

27 CLR

POWER-ON

RESET

1657 TA02

FROM

SYSTEM RESET

GND

20

REFLO

21

X1/X2

26

1657 TA01

1657lfa

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For more information www.linear.com/LTC1657

LTC1657/LTC1657L

ABSOLUTE MAXIMUM RATINGS

PACKAGE/ORDER INFORMATION

(Note 1)

TOP VIEW

V

to GND ............................................... –0.5V to 7.5V

CC

1

2

LDAC

CLR

28

27

26

25

24

23

22

21

20

19

18

17

16

15

WR

CSLSB

CSMSB

(LSB) D0

D1

TTL Input Voltage, REFHI, REFLO,

X1/X2 ....................................................... –0.5V to 7.5V

3

X1/X2

V

OUT

, REFOUT ............................. –0.5V to (V + 0.5V)

CC

4

V

OUT

Operating Temperature Range

5

V

CC

LTC1657C/LTC1657LC ........................... 0°C to 70°C

LTC1657I/LTC1657LI ......................... –40°C to 85°C

Maximum Junction Temperature .......................... 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

6

REFOUT

REFHI

REFLO

GND

D2

7

D3

8

D4

9

D5

10

11

12

13

14

D15 (MSB)

D14

D6

D7

D13

D8

D12

D9

D11

D10

OBSOLETE PACKAGE

N PACKAGE

28-LEAD PDIP

GN PACKAGE

28-LEAD PLASTIC SSOP

T

= 125°C, θ = 95°C/W (GN)

JA

JMAX

= 125°C, θ = 58°C/W (N)

JA

ORDER INFORMATION

LEAD FREE FINISH

LTC1657CGN#PꢀF

LTC1657IGN#PꢀF

LTC1657LCGN#PꢀF

LTC1657LIGN#PꢀF

TAPE AND REEL

PART MARKING

1657CGN

PACKAGE DESCRIPTION

28-Lead Plastic SSOP

TEMPERATURE RANGE

0°C to 70°C

LTC1657CGN#TRPꢀF

LTC1657IGN#TRPꢀF

LTC1657LCGN#TRPꢀF

LTC1657LIGN#TRPꢀF

1657IGN

–40°C to 85°C

0°C to 70°C

1657LCGN

1657LIGN

–40°C to 85°C

OBSOLETE PACKAGE

LTC1657CN#PꢀF

LTC1657IN#PꢀF

LTC1657LCN#PꢀF

LTC1657LIN#PꢀF

LTC1657CN#TRPꢀF

LTC1657IN#TRPꢀF

LTC1657LCN#TRPꢀF

LTC1657LIN#TRPꢀF

1657CN

1657IN

28-Lead PDIP

0°C to 70°C

–40°C to 85°C

0°C to 70°C

1657LCN

1657LIN

–40°C to 85°C

Consult LTC Marketing for parts specified with wider operating temperature ranges.

Consult LTC Marketing for information on nonstandard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

1657lfa

2

For more information www.linear.com/LTC1657

LTC1657/LTC1657L

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_CC= 4.5V to 5.5V (LTC1657), V_CC= 2.7V to 5.5V (LTC1657L),

V_OUTunloaded, REFOUT tied to REFHI, REFLO tied to GND, X1/X2 tied to GND, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

DAC (Note 2)

l

Resolution

16

ꢀits

Monotonicity

DNL

INL

Differential Nonlinearity

Integral Nonlinearity

Zero Scale Error

Offset Error

Guaranteed Monotonic (Note 3)

(Note 3)

0.5

4

1

12

2

LSꢀ

ZSE

0

mV

V

OS

Measured at Code 200 (LTC1657)

Measured at Code 200 (LTC1657L)

0.3

0.4

5

3

mV

4

mV

V

TC

OS

Offset Error Tempco

Gain Error

µV/°C

LSꢀ

l

2

16

Gain Error Drift

LTC1657

0.5

1.0

ppm/°C

LTC1657L

Power Supply

l

V

Positive Supply Voltage

For Specified Performance (LTC1657)

For Specified Performance (LTC1657L)

(Note 4)

4.5

2.7

5.5

V

CC

I

CC

Supply Current

650

1200

µA

Op Amp DC Performance

Short-Circuit Current Low

l

V

Shorted to GND

70

80

120

140

120

275

4

mA

OUT

Short-Circuit Current High

Output Impedance to GND

Shorted to V

CC

Input Code = 0 (LTC1657)

Input Code = 0 (LTC1657L)

40

Ω

120

Ω

Output Line Regulation

Input Code = 65535, LTC1657: V = 4.5V to 5.5V

mV/V

CC

Input Code = 65535, LTC1657L: V = 2.7V to 5.5V

3

CC

AC Performance

l

Voltage Output Slew Rate

(Note 5)

0.3

0.7

20

10

0.3

8

V/µs

µs

Voltage Output Settling Time

(Note 5) to 0.0015% (16-ꢀit Settling Time)

(Note 5) to 0.012% (13-ꢀit Settling Time)

(Note 6)

µs

Digital Feedthrough

nV•s

Midscale Glitch Impulse

DAC Switch ꢀetween 8000H and 7FFFH

Output Voltage Noise Using

Internal Reference at 1kHz

X1/X2 Tied to V

LTC1657

(Notes 8, 9)

OUT

165

105

nV/√Hz

LTC1657L

Output Voltage Noise Using

External Reference at 1kHz

X1/X2 Tied to V

(Notes 8, 9, 10)

(Notes 8, 9)

50

nV/√Hz

OUT

Output Voltage Noise Density Using

Internal Reference from 0.1Hz to 10Hz

8

µV

P-P

Reference Input Multiplying ꢀW

700

kHz

1657lfa

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For more information www.linear.com/LTC1657

LTC1657/LTC1657L

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_CC= 4.5V to 5.5V (LTC1657), V_CC= 2.7V to 5.5V (LTC1657L),

V_OUTunloaded, REFOUT tied to REFHI, REFLO tied to GND, X1/X2 tied to GND, unless otherwise noted.

SYMBOL

Reference Output (REFOUT)

Reference Output Voltage

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

LTC1657

2.036

1.240

2.048

1.250

15

2.060

1.260

V

LTC1657L

Reference Output

Temperature Coefficient

ppm/°C

l

Reference Line Regulation

Reference Load Regulation

Short-Circuit Current

LTC1657: V = 4.5V to 5.5V

1.5

1.0

5

mV/V

mV/A

mA

CC

LTC1657L: V = 2.7V to 5.5V

CC

Measured at I

= 100µA (LTC1657)

= 100µA (LTC1657L)

OUT

3

REFOUT Shorted to GND

50

150

90

6

100

Reference Output Voltage Noise at 1kHz LTC1657

LTC1657L

nV/√Hz

Reference Output Voltage Noise

Density from 0.1Hz to 10Hz

µV

P-P

Reference Input

REFHI, REFLO Input Range

(Note 7) See Applications Information

X1/X2 Tied to V

l

0

V

CC

– 1.5

V

OUT

X1/X2 Tied to GND

V /2

CC

l

REFHI Input Resistance

LTC1657

16

25

23

kΩ

LTC1657L (Relative to REFLO)

1657lfa

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For more information www.linear.com/LTC1657

LTC1657/LTC1657L

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range T_A= T_MINto T_MAX, V_CC= 5V (LTC1657), V_CC= 3V (LTC1657L), unless otherwise noted.

LTC1657

TYP

LTC1657L

TYP

SYMBOL

PARAMETER

CONDITIONS

MIN

MAX

MIN

MAX

UNITS

Digital I/O

l

V

Digital Input High Voltage

Digital Input Low Voltage

Digital Input Leakage

2.4

2.0

V

IH

0.8

10

0.6

10

IL

I

V

= GND to V

CC

µA

pF

LEAK

IN

C

Digital Input Capacitance

(Note 7)

IN

Switching Characteristics

l

t

CS (MSꢀ or LSꢀ) Pulse Width

WR Pulse Width

40

0

60

0

ns

CS

WR

CS to WR Setup

CWS

CWH

DWS

DWH

LDAC

CLR

CS to WR Hold

0

Data Valid to WR Setup

Data Valid to WR Hold

LDAC Pulse Width

CLR Pulse Width

40

0

60

0

40

60

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 5: DAC switched between all 1s and all 0s. V = 4.096V.

Note 6: D0 to D15 toggle between all 0s and all 1s with REFHI = 0V,

CSMSB = CSLSB = WR = LDAC = High

Note 7: Guaranteed by design. Not subject to test.

Note 8: DAC inputs all 1s.

Note 9: X1/X2 tied to GND, the voltage noise will be a factor of 2 greater.

FS

Note 2: External reference REFHI = 2.2V. V = 5V (LTC1657).

CC

External reference REFHI = 1.3V. V = 3V (LTC1657L).

CC

Note 3: Nonlinearity is defined from code 128 to code 65535 (full scale).

See Applications Information.

Note 10: Using 2.048V (1.25V) external reference with 3nV/√Hz noise at

1kHz for LTC1657/(LTC1657L).

Note 4: Digital inputs at 0V or V

.

CC

1657lfa

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For more information www.linear.com/LTC1657

LTC1657/LTC1657L

TYPICAL PERFORMANCE CHARACTERISTICS

LTC1657 Differential Nonlinearity

LTC1657L Differential Nonlinearity

LTC1657 Integral Nonlinearity

2.0

1.6

5

4

2.0

1.6

1.2

3

1.2

0.8

2

0.8

0.4

1

0.4

0

–1

–2

–3

–4

–5

–0.4

–0.8

–1.2

–1.6

–2.0

–0.4

–0.8

–1.2

–1.6

–2.0

0

16384

32768

49152

65535

0

16384

32768

49152

65535

0

16384

32768

49152

65535

DIGITAL INPUT CODE

1657 G02

1657 G03

1657 G01

LTC1657 Minimum Supply

Headroom for Full Output Swing

vs Load Current

LTC1657L Minimum Supply

Headroom for Full Output Swing

vs Load Current

LTC1657L Integral Nonlinearity

5

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

CODE ALL 1s

4

3

∆V

≤ 1LSB

∆V

OUT

≤ 1LSB

OUT

V

= 4.096V

V

= 2.5V

OUT

2

125°C

1

0

25°C

–1

–2

–3

–4

–5

25°C

–55°C

0

16384

32768

49152

65535

0

5

10

0

5

10

DIGITAL INPUT CODE

LOAD CURRENT (mA)

1657 G04

1657 G05

1657 G06

LTC1657 Minimum Output

Voltage vs Output Sink Current

LTC1657L Minimum Output

Voltage vs Output Sink Current

LTC1657 Full-Scale Voltage

vs Temperature

4.110

4.105

4.100

4.095

4.090

4.085

4.080

0.6

0.4

0.2

0

1.2

1.0

0.8

0.6

0.4

0.2

0

CODE ALL 0s

OUT

∆V

≤ 1LSB

125°C

25°C

–55°C

125°C

25°C

–55°C

CODE ALL 0s

∆V

≤ 1LSB

OUT

–55

–25

5

35

65

95

125

0

5

10

15

0

5

10

15

TEMPERATURE (°C)

OUTPUT SINK CURRENT (mA)

1657 G09

1657 G08

1657 G07

1657lfa

6

For more information www.linear.com/LTC1657

LTC1657/LTC1657L

TYPICAL PERFORMANCE CHARACTERISTICS

LTC1657L Full-Scale Voltage

vs Temperature

LTC1657 Offset Error

vs Temperature

LTC1657L Offset Error

vs Temperature

1.0

2.510

2.505

2.500

2.495

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

– 0.8

–1.0

2.490

–55 –25

5

35

65

95

125

–55

–10

35

80

125

–55

–10

35

80

125

TEMPERATURE (°C)

1657 G10

1657 G12

1657 G11

LTC1657 Supply Current

vs Logic Input Voltage

LTC1657L Supply Current

vs Logic Input Voltage

LTC1657 Supply Current

vs Temperature

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

700

680

660

640

620

600

580

560

540

520

500

8

7

6

5

4

3

2

1

0

V

= 3V

CC

V

= 5V

CC

V

= 5.5V

CC

V

= 5V

CC

= 4.5V

0

1

3

2

–55 –35 –15

5

25 45 65 85 105 125

0

1

2

3

4

5

LOGIC INPUT VOLTAGE (V)

TEMPERATURE (°C)

LOGIC INPUT VOLTAGE (V)

1657 G14

1657 G15

1657 G13

LTC1657L Supply Current

vs Temperature

LTC1657

Large-Signal Transient Response

LTC1657L

Large-Signal Transient Response

5

4

3

2

1

0

5

4

3

2

1

0

560

550

540

530

520

510

500

490

480

470

460

V

UNLOADED

V

T

UNLOADED

OUT

T

= 25°C

A

V

= 3.3V

CC

V

= 3V

CC

V

= 2.7V

CC

–55 –35 –15

5

25 45 65 85 105 125

TIME (20µs/DIV)

TEMPERATURE (°C)

1657 G18

1657 G17

1657 G16

1657lfa

7

For more information www.linear.com/LTC1657

LTC1657/LTC1657L

TYPICAL PERFORMANCE CHARACTERISTICS

LTC1657 0.1Hz to 10Hz

Voltage Noise

LTC1657L 0.1Hz to 10Hz

Voltage Noise

0

1

2

3

4

5

6

7

8

9

10

0

1

2

3

4

5

6

7

8

9

10

TIME (SEC)

1659 G19

1659 G20

PIN FUNCTIONS

REFLO(Pin21):LowerinputterminaloftheDAC’sinternal

WR (Pin 1): Write Input (Active Low). Used with CSMSB

and/or CSLSB to control the input registers. While WR

and CSMSB and/or CSLSB are held low, data writes into

the input register.

resistor ladder. Typically connected to Analog Ground. An

input code of (0000) will connect the positive input of

H

the output buffer to this end of the ladder. Can be used

to offset the zero scale above ground.

CSLSB (Pin 2): Chip Select Least Significant ꢀyte (Active

Low).UsedwithWRtocontroltheLSꢀ8-bitinputregisters.

While WR and CSLSB are held low, the LSꢀ byte writes

into the LSꢀ input register. Can be connected to CSMSB

for simultaneous loading of both sets of input latches on

a 16-bit bus.

REFHI (Pin 22): Upper input terminal of the DAC’s internal

resistor ladder. Typically connected to REFOUT. An input

codeof(FFFF) willconnectthepositiveinputoftheoutput

H

buffer to 1LSꢀ below this voltage.

REFOUT(Pin23):Outputoftheinternalreferenceis2.048V

(LTC1657), 1.25V (LTC1657L). Typically connected to

REFHI to drive internal DAC resistor ladder.

CSMSB (Pin 3): Chip Select Most Significant ꢀyte (Ac-

tive Low). Used with WR to control the MSꢀ 8-bit input

registers. While WR and CSMSB are held low, the MSꢀ

byte writes into the MSꢀ input register. Can be connected

to CSLSB for simultaneous loading of both sets of input

latches on a 16-bit bus.

V

(Pin 24): Positive Power Supply Input. 4.5V ≤ V

≤

CC

5.5V (LTC1657), 2.7V ≤ V ≤ 5.5V (LTC1657L). Requires

CC

a 0.1µF bypass capacitor to ground.

V

(Pin 25): ꢀuffered DAC Output.

OUT

D0 to D7 (Pins 4 to 11): Input data for the Least Significant

ꢀyte. Written into LSꢀ input register when WR = 0 and

CSLSB = 0.

X1/X2(Pin26):GainSettingResistorPin. ConnecttoGND

for G = 2 or to V for G = 1. This pin should always be

OUT

tied to a low impedance source, such as ground or V

,

OUT

D8 to D15 (Pins 12 to 19): Input data for the Most Signifi-

cant ꢀyte. Written into MSꢀ input register when WR = 0

and CSMSB = 0.

to ensure stability of the output buffer when driving ca-

pacitive loads.

GND (Pin 20): Ground.

1657lfa

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For more information www.linear.com/LTC1657

LTC1657/LTC1657L

PIN FUNCTIONS

CLR (Pin 27): Clear Input (Asynchronous Active Low). A

low on this pin asynchronously resets all input and DAC

registers to 0s.

LDAC (Pin 28): Load DAC (Asynchronous Active Low).

Used to asynchronously transfer the contents of the input

registers to the DAC register which updates the output

voltage. If held low, the DAC register loads data from the

input registers which will immediately update V

.

OUT

DIGITAL INTERFACE TRUTH TABLE

CLR

CSMSB

CSLSB

WR

LDAC

FUNCTION

L

X

L

X

H

L

X

L

Clears input and DAC registers to zero

Loads DAC register with contents of input registers

Freezes contents of DAC register

Writes MSꢀ byte into MSꢀ input register

Writes LSꢀ byte into LSꢀ input register

H

X

H

X

H

X

L

H

L

H

L

H

L

Writes MSꢀ and LSꢀ bytes into MSꢀ and LSꢀ input registers

Inhibits write to MSꢀ and LSꢀ input registers

Inhibits write to MSꢀ input register

H

X

H

X

L

X

H

L

H

X

H

X

Inhibits write to LSꢀ input register

H

L

Data bus flows directly through input and DAC registers

TIMING DIAGRAM

t

CS

CSLSB

t

CS

CSMSB

t

WR

CWH

CWS

t

WR

t

LDAC

t

DWH

t

DWS

DAC UPDATE

DATA VALID

DATA

1657 TD

1657lfa

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For more information www.linear.com/LTC1657

LTC1657/LTC1657L

DEFINITIONS

Resolution (n): Resolution is defined as the number of

DAC Transfer Characteristic:

digital input bits (n). It defines the number of DAC output













REFHI–REFLO

65536

n

states(2 )thatdividethefull-scalerange.Resolutiondoes

V

= G•

CODE +REFLO

(

)

OUT

not imply linearity.

Full-Scale Voltage (V ): This is the output of the DAC

G = 1 for X1/X2 connected to V

FS

OUT

when all bits are set to 1.

G = 2 for X1/X2 connected to GND

Voltage Offset Error (V ): Normally, the DAC offset is

OS

CODE = Decimal equivalent of digital input

(0 ≤ CODE ≤ 65535)

the voltage at the output when the DAC is loaded with

all zeros. The DAC can have a true negative offset, but

because the part is operated from a single supply, the

output cannot go below zero. If the offset is negative, the

output will remain near 0V resulting in the transfer curve

shown in Figure 1.

Zero-Scale Error (ZSE): The output voltage when the DAC

is loaded with all zeros. Since this is a single supply part,

this value cannot be less than 0V.

IntegralNonlinearity(INL):End-pointINListhemaximum

deviation from a straight line passing through the end

pointsoftheDACtransfercurve.ꢀecausethepartoperates

from a single supply and the output cannot go below zero,

the linearity is measured between full scale and the code

corresponding to the maximum offset specification. The

INL error at a given input code is calculated as follows:

OUTPUT

VOLTAGE

0V

NEGATIVE

OFFSET

DAC CODE

1657 F01

Figure 1. Effect of Negative Offset

INL (In LSꢀs) = [V

(code/65535)]

– V – (V – V )

OS FS OS

OUT

The offset of the part is measured at the code that cor-

responds to the maximum offset specification:

V

= The output voltage of the DAC measured at

OUT

the given input code

n

V

= V

– [(Code)(V )/(2 – 1)]

OS

OUT

FS

Differential Nonlinearity (DNL): DNL is the difference

between the measured change and the ideal one LSꢀ

change between any two adjacent codes. The DNL error

between any two codes is calculated as follows:

Least Significant Bit (LSB): One LSꢀ is the ideal voltage

difference between two successive codes.

LSꢀ = G • V /65536

REF

DNL = (∆V

– LSꢀ)/LSꢀ

OUT

G = 1 for X1/X2 connected to V

OUT

∆V

= The measured voltage difference between

OUT

G = 2 for X1/X2 connected to GND

two adjacent codes

Nominal LSBs: (V

tie to V

, REFLO tie to GND,

REFOUT

REFHI

Digital Feedthrough: The glitch that appears at the analog

outputcausedbyACcouplingfromthedigitalinputswhen

theychangestate.TheareaoftheglitchisspecifiedinnV•s.

G = 2)

LTC1657 LSꢀ = 4.096V/65536 = 62.5µV

LTC1657L LSꢀ = 2.5V/65536 = 38.1µV

1657lfa

10

For more information www.linear.com/LTC1657

LTC1657/LTC1657L

OPERATION

Parallel Interface

the resistor ladder can be driven by an external source in

multiplying applications. The external reference or source

must be capable of driving the 16k (minimum) DAC lad-

der resistance.

The data on the input of the DAC is written into the DAC’s

input registers when Chip Select (CSLSB and/or CSMSB)

and WR are at a logic low. The data that is written into the

input registers will depend on which of the Chip Selects Internal reference output noise can be reduced with a

are at a logic low (see Digital Interface Truth Table). If WR bypass capacitor to ground. (Note: The reference does

and CSLSB are both low and CSMSB is high, then only not require a bypass capacitor to ground for nominal

data on the eight LSꢀs (D0 to D7) is written into the input operation.) When bypassing the reference, a small value

registers. Similarly, if WR and CSMSB are both low and resistor in series with the capacitor is recommended to

CSLSB is high, then only data on the eight MSꢀs (D8 to helpreducepeakingontheoutput.A10Ωresistorinseries

D15) is written into the input registers. Data is written with a 4.7µF capacitor is optimum for reducing reference

into both the Least Significant Data ꢀits (D0 to D7) and generated noise. Internal reference output voltage noise

the Most Significant ꢀits (D8 to D15) at the same time if spectraldensityat1kHzistypically150nV/√Hz(LTC1657),

WR, CSLSB and CSMSB are low. If WR is high or both 90nV/√Hz (LTC1657L).

CSMSB and CSLSB are high, then no data is written into

the input registers.

DAC Resistor Ladder

The high and low end of the DAC ladder resistor string

(REFHI and REFLO, respectively) are not connected in-

ternally on this part. Typically, REFHI will be connected

to REFOUT and REFLO will be connected to GND. X1/X2

connected to GND will give the LTC1657/LTC1657L a

full-scale output swing of 4.096V/2.5V.

Once data is written into the input registers, it can be

written into the DAC register. This will update the analog

voltage output of the DAC. The DAC register is written by

a logic low on LDAC. The data in the DAC register will be

held when LDAC is high.

When WR, CSLSB, CSMSB and LDAC are all low, the

registers are transparent and data on pins D0 to D15 flows

directly into the DAC register.

Either of these pins can be driven up to V – 1.5V when

CC

using the buffer in the gain-of-1 configuration. The resis-

tor string pins can be driven to V /2 when the buffer is

CC

For an 8-bit data bus connection, tie the MSꢀ byte data

pins to their corresponding LSꢀ byte pins (D15 to D7,

D14 to D6, etc).

in the gain of 2 configuration. The resistance between

these two pins is typically 25k (16k min) (LTC1657), 23k

(16k min) (LTC1657L).

Power-On Reset

Voltage Output

The LTC1657/LTC1657L have an internal power-on reset

that resets all internal registers to 0’s on power-up and

OUT

The output buffer for the LTC1657/LTC1657L can be

configured for two different gain settings. ꢀy tying the

X1/X2 pin to GND, the gain is set to 2. ꢀy tying the X1/X2

V

pinforcestoGND(equivalenttotheCLRpinfunction).

pin to V , the gain is set to unity.

OUT

Reference

The LTC1657/LTC1657L rail-to-rail buffered output can

source or sink 5mA within 500mV of the positive supply

voltage or ground at room temperature. The output stage

is equipped with a deglitcher that results in a midscale

glitch impulse of 8nV•s. The output swings to within a

few millivolts of either supply rail when unloaded and has

an equivalent output resistance of 40Ω (LTC1657), 120Ω

(LTC1657L) when driving a load to the rails.

The LTC1657/LTC1657L include an internal 2.048V/1.25V

reference, giving the LTC1657/LTC1657L a full-scale

range of 4.096V/2.5V in the gain-of-2 configuration. The

onboard reference in the LTC1657/LTC1657L is not in-

ternally connected to the DAC’s reference resistor string

but is provided on an adjacent pin for flexibility. ꢀecause

the internal reference is not internally connected to the

DAC resistor ladder, an external reference can be used or

1657lfa

11

For more information www.linear.com/LTC1657

LTC1657/LTC1657L

APPLICATION INFORMATION

Rail-to-Rail Output Considerations

Similarly, limiting can occur near full scale when the REF

pin is tied to V /2. If V = V /2 and the DAC full-scale

CC

REF

CC

In any rail-to-rail DAC, the output swing is limited to volt-

ages within the supply range.

error (FSE) is positive, the output for the highest codes

limits at V as shown in Figure 1c. No full-scale limiting

CC

If the DAC offset is negative, the output for the lowest

codes limits at 0V as shown in Figure 1b.

can occur if V is less than (V – FSE)/2.

REF

CC

Offset and linearity are defined and tested over the region

of the DAC transfer function where no output limiting

can occur.

POSITIVE

FSE

V

CC

V

REF

= V /2

CC

OUTPUT

VOLTAGE

INPUT CODE

(c)

V

CC

V

REF

= V /2

CC

OUTPUT

VOLTAGE

0

32768

65535

INPUT CODE

(a)

OUTPUT

VOLTAGE

0V

NEGATIVE

OFFSET

INPUT CODE

(b)

1657 F02

Figure 2. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for

Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When V_REF= V_CC/2

1657lfa

12

For more information www.linear.com/LTC1657

LTC1657/LTC1657L

APPLICATIONS INFORMATION

This circuit shows how to make a bipolar output 16-bit

DAC with a wide output swing using an LTC1657 and an

LT1077. R1 and R2 resistively divide down the LTC1657

output and an offset is summed in using the LTC1657

onboard 2.048V reference and R3 and R4. R5 ensures

that the onboard reference is always sourcing current and

never has to sink any current even when V

is at full

OUT

scale. The LT1077 output will have a wide bipolar output

swing of –4.096V to 4.096V as shown in the figure below.

With this output swing, 1LSꢀ = 125µV.

A Wide Swing, Bipolar Output 16-Bit DAC

5V

0.1µF

24

5:19

2

V

CC

DATA (0:15)

CSLSB

CSMSB

WR

3

25

µP

V

LTC1657

OUT

1

R1

100k

1%

28

27

5V

LDAC

CLR

3

2

X1/X2 REFLO GND REFHI REFOUT

26 21 20 22 23

7

+

–

6

(2)(D )(4.096)

IN

R2

200k

1%

LT1077

4

V

:

– 4.096V

OUT

65536

R3

100k

1%

R4

200k

1%

–5V

1657 TA05

R5

100k

1%

TRANSFER CURVE

32768

4.096

65535

0

V

D

OUT

IN

–4.096

1657lfa

13

For more information www.linear.com/LTC1657

LTC1657/LTC1657L

TYPICAL APPLICATIONS

Thiscircuitshowsadigitallyprogrammablecurrentsource

from an external voltage source using an external op amp,

an LT1218 and an NPN transistor (2N3440). Any digital

word from 0 to 65535 is loaded into the LTC1657 and

its output correspondingly swings from 0V to 4.096V.

is chosen to be 412Ω, the output current will range from

0mA at zero scale to 10mA at full scale. The minimum

voltage for V is determined by the load resistor R and

S

L

Q1’s V

voltage. With a load resistor of 50Ω, the volt-

CESAT

age source can be 5V.

This voltage will be forced across the resistor R . If R

A

Digitally Programmable Current Source

5V

22

23

5V < V < 100V

S

FOR R ≤ 50Ω

L

0.1μF

5:19

2

REFHI REFOUT

V

CC

DATA (0:15)

CSLSB

CSMSB

WR

(D )(4.096)

IN

3

R

L

I

=

7

OUT

25

3

(65536)(R )

µP

A

LTC1657

V

OUT

+

1

≈ 0mA TO 10mA

6

Q1

2N3440

28

27

LT1218

LDAC

2

CLR

–

X1/X2 REFLO GND

26 21 20

4

R

A

412Ω

1%

1657 TA04

1657lfa

14

For more information www.linear.com/LTC1657

LTC1657/LTC1657L

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

GN Package

28-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641 Rev B)

.386 – .393*

(9.804 – 9.982)

.045 .005

.033

(0.838)

REF

28 27 26 25 24 23 22 21 20 19 18 17 1615

.254 MIN

.150 – .165

.229 – .244

.150 – .157**

(5.817 – 6.198)

(3.810 – 3.988)

.0165 .0015

.0250 BSC

1

2

3

4

5

6

7

8

9 10 11 12 13 14

RECOMMENDED SOLDER PAD LAYOUT

.015 .004

.0532 – .0688

(1.35 – 1.75)

× 45°

.004 – .0098

(0.102 – 0.249)

(0.38 0.10)

.0075 – .0098

(0.19 – 0.25)

0° – 8° TYP

.016 – .050

(0.406 – 1.270)

.008 – .012

.0250

(0.635)

BSC

GN28 REV B 0212

(0.203 – 0.305)

TYP

NOTE:

1. CONTROLLING DIMENSION: INCHES

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

3. DRAWING NOT TO SCALE

4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

1657lfa

15

For more information www.linear.com/LTC1657

LTC1657/LTC1657L

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

N Package

28-Lead Plastic PDIP (Narrow .300 Inch)

(Reference LTC DWG # 05-08-1510 Rev I)

1.400*

(35.560)

MAX

28

27 26 25 24

23 22 21 20

19 18 17 16

15

14

.240 – .295*

(6.096 – 7.493)

5

6

7

8

9

10 11 12 13

1

2

3

4

.045 – .065

.130 ±.005

(1.143 – 1.651)

(3.302 ±0.127)

.020

(0.508)

MIN

.065

(1.651)

TYP

N28 REV I 0711

.120

(3.048)

MIN

.005

(0.127)

MIN

.018 ±.003

(0.457 ±0.076)

.100

(2.54)

BSC

NOTE:

1. DIMENSIONS ARE

INCHES

MILLIMETERS

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)

OBSOLETE PACKAGE

1657lfa

16

For more information www.linear.com/LTC1657

LTC1657/LTC1657L

REVISION HISTORY

REV

DATE

DESCRIPTION

PAGE NUMBER

A

07/15 Obsoleted 28-Lead PDIP Package

2, 16

1657lfa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

17

For more information www.linear.com/LTC1657

LTC1657/LTC1657L

TYPICAL APPLICATION

This circuit shows how to measure negative offset. Since

LTC1657/LTC1657L operate on a single supply, if their

offset is negative, the output for code 0 limits at 0V. To

measure this negative offset, a negative supply is needed,

connect resistor R1 as shown in the figure. The output

voltage is the offset when code 0 is loaded in.

Negative Offset Measurement

5V

22

23

24

0.1µF

5:19

2

REFHI REFOUT

V

CC

DATA (0:15)

CSLSB

CSMSB

WR

3

25

µP

LTC1657/LTC1657L

V

1

OUT

R1

100k

28

27

LDAC

CLR

X1/X2 REFLO GND

–5V

26

21

20

1657 TA06

Although LTC1657 output is up to 4.096V with its internal

reference, higher voltages can be achieved with the help

of another op amp. The following circuit shows how to

increasetheoutputswingofLTC1657byusinganLT1218.

As shown in the configuration, the output of LTC1657 is

amplified by 8 for an output swing of 0V to 32.768V, or a

convenient 0.5mV/LSꢀ.

A Higher Voltage Output DAC

5V

24

36V

22

23

0.1µF

TRANSFER CURVE

5:19

2

REFHI REFOUT

V

CC

32.768 (V)

DATA (0:15)

CSLSB

CSMSB

WR

0.1µF

3

7

25

3

2

µP

LTC1657

V

+

1

OUT

6

V

28

27

OUT

LT1218

LDAC

(D )(4.096)

IN

65536

R2

R1

CLR

–

X1/X2 REFLO GND

26 21 20

V

=

1 +

OUT

4

(

)

0

D

IN

65535

R1

R2

6.98k

1%

1k

1%

1657 TA07

RELATED PARTS

PART NUMBER DESCRIPTION

COMMENTS

LTC1446(L)

LTC1450(L)

LTC1458(L)

LTC1650

Dual 12-ꢀit V

DACs in SO-8 Package

V

CC

V

CC

V

CC

V

CC

= 5V (3V), V

= 0V to 4.095V (0V to 2.5V)

OUT

Single 12-ꢀit V

DACs with Parallel Interface

OUT

Quad 12-ꢀit Rail-to-Rail Output DACs with Added Functionality

Single 16-ꢀit V

Industrial DAC in 16-Pin SO

= 5V, Low Power, Deglitched, 4-Quadrant Multiplying V

OUT

LTC1654

Dual 14-ꢀit V

DAC

Programmable Speed/Power, SO-8 Footprint

OUT

LTC1655(L)

Single 16-ꢀit V

DAC with Serial Interface in SO-8

V

= 5V (3V), Low Power, Deglitched, V

= 0V to 4.096V

OUT

CC

OUT

(0V to 2.5V)

LTC1658

Single 14-ꢀit V

DAC in MSOP Package

2.7V to 5.5V Operation, Low Power

OUT

1657lfa

LT 0715 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy ꢀlvd., Milpitas, CA 95035-7417

18

For more information www.linear.com/LTC1657

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC1657

●

 LINEAR TECHNOLOGY CORPORATION 1999


型号：	LTC1657LCGN#TRPBF
厂家：	Linear
描述：	LTC1657 - Parallel 16-Bit Rail-to-Rail Micropower DAC; Package: SSOP; Pins: 28; Temperature Range: 0°C to 70°C 光电二极管转换器
文件：	总18页 (文件大小：275K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC1657LCGN#TRPBF [Linear]

相关型号：

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LTC1657LCN#TRPBF

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LTC1657LIGN

LTC1657LIGN#PBF

LTC1657LIGN#TR

LTC1657LIN

LTC1657LIN#PBF

LTC1657L_15

LTC1657_15

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