LTC2974CUP-PBF [Linear]
4-Channel PMBus Power System Manager; 4通道的PMBus电源系统管理器型号: | LTC2974CUP-PBF |
厂家: | Linear |
描述: | 4-Channel PMBus Power System Manager |
文件: | 总98页 (文件大小:1552K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC2974
4-Channel PMBus Power System Manager
Featuring Accurate Output Current Measurement
FEATURES
DESCRIPTION
TheLTC®2974isa4-channelPowerSystemManagerused
to sequence, trim (servo), margin, supervise, manage
faults, provide telemetry and create fault logs. PMBus
commands support power supply sequencing, precision
point-of-loadvoltageadjustmentandmargining.DACsuse
a proprietary soft-connect algorithm to minimize supply
disturbances.Supervisoryfunctionsincludeoverandunder
current, voltage and temperature threshold limits for four
power supply output channels as well as over and under
voltage threshold limits for a single power supply input
channel. Programmable fault responses can disable the
power supplies with optional retry after a fault is detected.
Faultsthatdisableapowersupplycanautomaticallytrigger
black box EEPROM storage of fault status and associated
telemetry. An internal 16-bit ADC monitors four output
voltages,fouroutputcurrents,fourexternaltemperatures,
one input voltage and die temperature. Output power is
also calculated. A programmable watchdog timer moni-
tors microprocessor activity for a stalled condition and
resets the microprocessor if necessary. A single wire bus
synchronizes power supplies across multiple LTC power
systemmanagementdevices.ConfigurationEEPROMsup-
ports autonomous operation without additional software.
n
Sequence, Trim, Margin and Supervise Four Power
Supplies
n
n
n
n
n
n
n
Manage Faults, Monitor Telemetry and Create Fault Logs
PMBus Compliant Command Set
TM
Supported by LTpowerPlay GUI
Margin or Trim Supplies to 0.25% Accuracy
Fast OV/UV Supervisors Per Channel
Fast Output Current Supervisors Per Channel
Coordinate Sequencing and Fault Management
Across Multiple Chips
n
n
n
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Automatic Fault Logging to Internal EEPROM
Operate Autonomously without Additional Software
External Temperature and Input Voltage Supervisors
Accurate Monitoring of Four Output Voltages, Four
Output Currents, Four External Temperatures, Input
Voltage and Internal Die Temperature
2
n
n
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I C/SMBus Serial Interface
Can Be Powered from 3.3V, or 4.5V to 15V
Available in 64-Lead 9mm × 9mm QFN Package
APPLICATIONS
n
Computers and Network Servers
n
Industrial Test and Measurement
L, LT, LTC, LTM, Linear Technology, the Linear logo, and PolyPhase are registered trademarks
and LTpowerPlay is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents including 7382303, 7420359 and
7940091.
n
High Reliability Systems
Medical Imaging
Video
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TYPICAL APPLICATION
ADC Total Unadjusted Error
4-Channel PMBus Power System Manager
vs Temperature
V
4.5V < V
IBUS
< 15V**
0.07
IN
–
I
I
**
V
PWR
V
IN_SNS
SENSEP0
0.06
+
DC/DC
I
CONVERTER
0.05
0.04
0.03
0.02
0.01
0
TG
I
SENSEM0
OV
AUXFAULTB
SW
BG
V
DAC0
**
V
DD33
V
R30
SENSEP0
R20
R10
SDA
PMBus
INTERFACE
LTC2974*
V
LOAD
FB
SCL
ALERTB
CONTROL0
V
V
SGND
RUN/SS
–0.01
–0.02
–0.03
SENSEM0
OUT_EN0
TO/FROM
OTHER
DEVICES
FAULTB0
MMBT3906
GND
FAULTB1
T
THREE TYPICAL PARTS
–50 –25 25
TEMPERATURE (°C)
SENSE0
PWRGD
SHARE_CLK
TO µP
RESETB
INPUT
0
100
50
75
ASEL0
ASEL1
*SOME DETAILS OMITTED FOR CLARITY
ONLY ONE OF FOUR CHANNELS SHOWN
0.1µF
2974 TA01b
WATCHDOG
WP
WDI/RESETB
GND
TIMER INTERRUPT
**LTC2974 MAY BE POWERED FROM
3.3V OR 4.5V TO 14V
2974 TA01
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LTC2974
TABLE OF CONTENTS
Features........................................................... 1
Applications ...................................................... 1
Typical Application .............................................. 1
Description........................................................ 1
Absolute Maximum Ratings.................................... 4
Order Information................................................ 4
Pin Configuration ................................................ 4
Electrical Characteristics....................................... 5
PMBus Timing Diagram......................................... 9
Typical Performance Characteristics ........................ 10
Pin Functions.................................................... 13
Block Diagram................................................... 15
Operation......................................................... 16
LTC2974 Operation Overview......................................... 16
EEPROM .................................................................... 17
AUXFAULTB ................................................................... 17
RESETB.......................................................................... 18
PMBus Serial Digital Interface ....................................... 18
PMBus....................................................................... 18
Device Address.......................................................... 18
Processing Commands.............................................. 19
PMBUS Command Summary.................................. 22
Summary Table..........................................................22
Data Formats.............................................................27
PMBus Command Description ................................ 28
Addressing and Write Protect ........................................28
PAGE..........................................................................28
WRITE_PROTECT......................................................28
WRITE-PROTECT Pin ................................................29
MFR_PAGE_FF_MASK ..............................................29
MFR_I2C_BASE_ADDRESS......................................29
On/Off Control, Margining and Configuration ................30
OPERATION...............................................................30
ON_OFF_CONFIG.......................................................31
MFR_CONFIG_LTC2974 ............................................32
Cascade Sequence ON with Time-Based
Input Voltage Commands and Limits.............................43
VIN_ON, VIN_OFF, VIN_OV_FAULT_LIMIT, VIN_OV_
WARN_LIMIT, VIN_UV_WARN_LIMIT and
VIN_UV_FAULT_LIMIT ..............................................43
Output Voltage Commands and Limits ..........................44
VOUT_MODE .............................................................44
VOUT_COMMAND, VOUT_MAX, VOUT_MARGIN_
HIGH, VOUT_MARGIN_LOW, VOUT_OV_FAULT_LIMIT,
VOUT_OV_WARN_LIMIT, VOUT_UV_WARN_LIMIT,
VOUT_UV_FAULT_LIMIT, POWER_GOOD_ON and
POWER_GOOD_OFF..................................................45
MFR_VOUT_DISCHARGE_THRESHOLD....................45
MFR_DAC..................................................................45
Output Current Commands and Limits ..........................46
IOUT_CAL_GAIN .......................................................46
IOUT_OC_FAULT_LIMIT, IOUT_OC_WARN_LIMIT and
IOUT_UC_FAULT_LIMIT ............................................47
MFR_IOUT_CAL_GAIN_TC........................................47
External Temperature Commands And Limits................48
OT_FAULT_LIMIT, OT_WARN_LIMIT, UT_WARN_
LIMIT and UT_FAULT_LIMIT .....................................48
MFR_TEMP_1_GAIN and MFR_TEMP_1_OFFSET......48
MFR_T_SELF_HEAT, MFR_IOUT_CAL_GAIN_TAU_INV
and MFR_IOUT_CAL_GAIN_THETA ..........................49
Sequencing Timing Limits and Clock Sharing................ 51
TON_DELAY, TON_RISE, TON_MAX_FAULT_LIMIT
and TOFF_DELAY....................................................... 51
MFR_RESTART_DELAY............................................. 51
Watchdog Timer and Power Good .................................52
MFR_PWRGD_EN .....................................................52
Clock Sharing ............................................................52
MFR_POWERGOOD_ASSERTION_DELAY................53
Watchdog Operation..................................................53
MFR_WATCHDOG_T_FIRST and
MFR_WATCHDOG_T..................................................53
Fault Responses.............................................................54
Clearing Latched Faults .............................................54
VOUT_OV_FAULT_RESPONSE and VOUT_UV_FAULT_
RESPONSE ................................................................55
IOUT_OC_FAULT_RESPONSE and IOUT_UC_FAULT_
RESPONSE ................................................................56
OT_FAULT_RESPONSE, UT_FAULT_RESPONSE,
Sequence OFF............................................................33
MFR_CONFIG2_LTC2974 ..........................................35
MFR_CONFIG3_LTC2974 ..........................................35
Tracking Supplies On and Off....................................37
Tracking Implementation...........................................38
MFR_CONFIG_ALL_LTC2974....................................39
Programming User EEPROM Space...............................40
STORE_USER_ALL and RESTORE_USER_ALL........ 41
Bulk Programming the User EEPROM Space ............ 41
MFR_EE_UNLOCK..................................................... 41
MFR_EE_ERASE .......................................................42
MFR_EE_DATA ..........................................................42
Response When Part Is Busy ....................................43
MFR_EE Erase and Write Programming Time...........43
VIN_OV_FAULT_RESPONSE and VIN_UV_FAULT_
RESPONSE ................................................................57
TON_MAX_FAULT_RESPONSE.................................58
MFR_RETRY_DELAY.................................................58
MFR_RETRY_COUNT................................................58
Shared External Faults ...................................................59
MFR_FAULTB0_PROPAGATE and MFR_FAULTB1_
PROPAGATE ..............................................................59
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LTC2974
TABLE OF CONTENTS
MFR_FAULTB0_RESPONSE and MFR_FAULTB1_
RESPONSE ................................................................60
Fault Warning and Status...............................................61
CLEAR_FAULTS.........................................................61
STATUS_BYTE...........................................................61
STATUS_WORD.........................................................62
STATUS_VOUT ..........................................................62
STATUS_IOUT ...........................................................63
STATUS_INPUT.........................................................63
STATUS_TEMPERATURE...........................................63
STATUS_CML ............................................................64
STATUS_MFR_SPECIFIC...........................................64
MFR_PADS................................................................65
MFR_COMMON.........................................................65
Telemetry .......................................................................66
READ_VIN .................................................................67
READ_VOUT ..............................................................67
READ_IOUT...............................................................67
READ_TEMPERATURE_1 ..........................................67
READ_TEMPERATURE_2..........................................67
READ_POUT..............................................................67
MFR_READ_IOUT .....................................................67
MFR_IOUT_SENSE_VOLTAGE...................................68
MFR_VIN_PEAK ........................................................69
MFR_VOUT_PEAK .....................................................69
MFR_IOUT_PEAK......................................................69
MFR_TEMPERATURE_1_PEAK .................................69
MFR_VIN_MIN ..........................................................69
MFR_VOUT_MIN .......................................................69
MFR_IOUT_MIN ........................................................69
MFR_TEMPERATURE_1_MIN ...................................69
Fault Logging .................................................................70
Fault Log Operation...................................................70
MFR_FAULT_LOG_STORE ........................................70
MFR_FAULT_LOG_RESTORE....................................70
MFR_FAULT_LOG_CLEAR ........................................71
MFR_FAULT_LOG_STATUS.......................................71
MFR_FAULT_LOG......................................................71
MFR_FAULT_LOG Read Example .............................. 74
Identification/Information ..............................................78
CAPABILITY...............................................................79
PMBus_REVISION.....................................................79
MFR_SPECIAL_ID.....................................................79
MFR_SPECIAL_LOT..................................................79
User Scratchpad.............................................................79
USER_DATA_00, USER_DATA_01, USER_DATA_02,
USER_DATA_03, USER_DATA_04, MFR_LTC_
Powering the LTC2974 ...................................................80
Setting Command Register Values.................................80
Sequence, Servo, Margin and Restart Operations .........80
Command Units On or Off.........................................80
On Sequencing ..........................................................80
On State Operation ....................................................81
Servo Modes .............................................................81
DAC Modes................................................................82
Margining ..................................................................82
Off Sequencing..........................................................82
VOUT Off Threshold Voltage.......................................82
Automatic Restart via MFR_RESTART_DELAY
Command and CONTROL pin ....................................82
Fault Management..........................................................82
Output Overvoltage, Undervoltage, Overcurrent, and
Undercurrent Faults...................................................82
Output Overvoltage, Undervoltage, and Overcurrent
Warnings ...................................................................83
Configuring the AUXFAULTB Output..........................83
Multi-Channel Fault Management..............................84
Interconnect Between Multiple LTC2974’s .....................84
Application Circuits........................................................85
Trimming and Margining DC/DC Converters with
External Feedback Resistors .....................................85
Four-Step Resistor Selection Procedure for DC/DC
Converters with External Feedback Resistors ...........85
Trimming and Margining DC/DC Converters with a
TRIM Pin....................................................................86
Two-Step Resistor and DAC Full-Scale Voltage
Selection Procedure for DC/DC Converters with a
TRIM Pin....................................................................87
Measuring Current with a Sense Resistor .................87
Measuring Current with Inductor DCR ......................87
Single Phase Design Example ...................................88
Measuring Multiphase Currents ................................88
Multiphase Design Example ......................................89
Anti-aliasing Filter Considerations.............................89
Sensing Negative Voltages........................................89
Connecting the DC1613 USB to I2C/SMBus/PMBus
Controller to the LTC2974 in System.........................90
Accurate DCR Temperature Compensation....................91
LTpowerPlay: An Interactive GUI for Power Managers...93
PCB Assembly and Layout Suggestions ........................94
Bypass Capacitor Placement.....................................94
Exposed Pad Stencil Design......................................94
Unused ADC Sense Inputs.........................................94
PCB Board Layout .....................................................94
Package Description ........................................... 95
Typical Application ............................................. 96
RESERVED_1 and MFR_LTC_RESERVED_2 .............79
Applications Information ...................................... 80
Overview ........................................................................80
Related Parts.................................................... 96
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LTC2974
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
Supply Voltages:
V
V
V
to GND ......................................... –0.3V to 15V
to GND ....................................... –0.3V to 3.6V
to GND ..................................... –0.3V to 2.75V
PWR
DD33
DD25
V
1
2
3
4
5
6
48 I
47 I
46 I
45 I
44 I
43 I
42 I
41 I
40 REFM
39 GND
38 REFP
37 GND
SENSEP0
SENSEM3
SENSEP3
SENSEM2
SENSEP2
SENSEM1
SENSEP1
SENSEM0
SENSEP0
Digital Input/Output Voltages:
V
SENSEM0
V
V
V
V
OUT_EN0
OUT_EN1
OUT_EN2
OUT_EN3
ALERTB, SDA, SCL, CONTROL0, CONTROL1,
CONTROL2, CONTROL3 to GND........... –0.3V to 3.6V
PWRGD, SHARE_CLK, WDI/RESETB, WP,
FAULTB0, FAULTB1 to GND ................. –0.3V to 3.6 V
ASEL0, ASEL1 to GND .......................... –0.3V to 3.6V
Analog Voltages:
AUXFAULTB 7
DNC 8
65
GND
V
9
IN_SNS
V
PWR
10
11
12
13
14
15
16
V
DD33
DD33
DD25
DD25
V
V
V
REFP................................................... –0.3V to 1.35V
REFM to GND........................................ –0.3V to 0.3V
V
V
V
36 ASEL1
35 ASEL0
34 T
T
T
SENSE0
SENSE1
SENSE3
to GND...................................... –0.3V to 15V
33 CONTROL1
IN_SNS
to GND................................. –0.3V to 6V
to GND ................................ –0.3V to 6V
SENSEP[3:0]
SENSEM[3:0]
I
I
V
V
T
to GND .................................. –0.3V to 6V
to GND ................................. –0.3V to 6V
, AUXFAULTB to GND.......... –0.3V to 15V
SENSEP[3:0]
SENSEM[3:0]
OUT_EN[3:0]
UP PACKAGE
64-LEAD (9mm × 9mm) PLASTIC QFN
to GND...................................... –0.3V to 6V
DAC[3:0]
T
= 125°C, θ
= 7°C/W, θ
= 1°C/W
JMAX
JCtop
JCbottom
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
to GND................................ –0.3V to 3.6V
SENSE[3:0]
Operating Junction Temperature Range:
LTC2974C ................................................ 0°C to 70°C
LTC2974I..............................................–40°C to 85°C
Storage Temperature Range .................. –65°C to 125°C
Maximum Junction Temperature ........................ 125°C*
*See OPERATION section for detailed EEPROM de-
rating information for junction temperatures in excess
of 85°C.
ORDER INFORMATION
LEAD FREE FINISH
LTC2974CUP#PBF
LTC2974IUP#PBF
TAPE AND REEL
PART MARKING*
LTC2974UP
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LTC2974CUP#TRPBF
LTC2974IUP#TRPBF
64-Lead (9mm × 9mm) Plastic QFN
64-Lead (9mm × 9mm) Plastic QFN
LTC2974UP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LTC2974
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ = 25°C. VPWR = VIN_SNS = 12V, VDD33, VDD25, REFP and REFM pins floating,
unless otherwise indicated. CVDD33 = 100nF, CVDD25 = 100nF and CREF = 100nF.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply Characteristics
l
l
l
l
V
V
V
V
V
V
Supply Input Operating Range
Supply Current
V Floating (Note 2)
DD33
4.5
15
13
13
2.8
V
mA
mA
V
PWR
PWR
PWR
DD33
DD33
DD33
I
I
4.5V ≤ V
≤ 15V, V
Floating (Note 2)
10
10
PWR
PWR
DD33
Supply Current
3.13V ≤ V
≤ 3.47V, V
= V
PWR
VDD33
DD33
DD33
V
Undervoltage Lockout
Undervoltage Lockout
Hysteresis
V
Ramping Up, V = V
PWR
2.25
2.55
120
UVLO_VDD33
DD33
DD33
mV
l
l
l
l
l
V
Supply Input Operating Range
Regulator Output Voltage
Regulator Output Short-Circuit Current
Regulator Output Voltage
Regulator Output Short-Circuit Current
Initialization Time
V
= V
3.13
3.13
75
3.47
3.47
140
2.6
V
V
DD33
PWR
DD33
4.5V ≤ V
≤ 15V
3.26
90
PWR
V
PWR
= 4.5V, V
= 0V
DD33
mA
V
V
3.13V ≤ V
≤ 3.47V
2.35
30
2.5
55
DD25
DD33
DD33
V
PWR
= V
= 3.47V, V
= 0V
DD25
80
mA
ms
t
Time from V applied until the TON_DELAY
timer starts
30
INIT
IN
Voltage Reference Characteristics
l
V
Output Voltage
V
= V
– V
, 0 < I
REFM
< 100µA
1.220
1.232
3
1.244
V
ppm/°C
ppm
REF
REF
REFP
REFP
Temperature Coefficient
Hysteresis
(Note 3)
100
ADC Characteristics
l
V
Voltage Sense Input Range
Differential Voltage:
= (V
0
6
V
IN_ADC
V
– V
)
IN_ADC
SENSEPn
SENSEMn
l
l
l
Single-Ended Voltage: V
Single-Ended Voltage: I
–0.1
–0.1
–170
0.1
6
V
V
SENSEMn
Current Sense Input Range
, I
SENSEPn SENSEMn
Differential Current Sense Voltage:
170
mV
V
= (I
– I
)
SENSEMn
IN_ADC
SENSEPn
N_ADC
Voltage Sense Resolution
Current Sense Resolution
0V ≤ V
≤ 6V, READ_VOUT
122
µV/LSB
IN_ADC
0mV ≤ |V
| < 16mV (Note 4)
15.625
31.25
62.5
125
250
µA/LSB
µA/LSB
µA/LSB
µA/LSB
µA/LSB
IN_ADC
16mV ≤ |V
32mV ≤ |V
| < 32mV
IN_ADC
IN_ADC
| < 63.9mV
| < 127.9mV
63.9mV ≤ |V
IN_ADC
127.9mV ≤ |V
|
IN_ADC
IOUT_CAL_GAIN = 1000mΩ
l
l
l
TUE_ADC_
VOLT_SNS
Total Unadjusted Error
Total Unadjusted Error
Voltage Sense Inputs V
≥ 1V
0.25
2.5
%
mV
%
IN_ADC
Voltage Sense Inputs 0 ≤ V
≤ 1V
IN_ADC
TUE_ADC_
CURR_SNS
Current Sense Inputs 20mV ≤ V
170mV
≤
0.3
IN_ADC
l
l
Current Sense Inputs V
≤ 20mV
60
35
µV
µV
IN_ADC
V
Offset Error
I
and I Inputs, V • IOUT_
SENSEMn OS
OS_ADC
SENSEPn
CAL_GAIN, IOUT_CAL_GAIN = 1Ω
t
Conversion Time
V
, V , V Inputs (Note 5)
6.15
24.6
24.6
ms
ms
ms
CONV_ADC
SENSEPn SENSEMn IN_SNS
I
and I
Inputs (Note 5)
SENSEPn
SENSEMn
Internal Temperature
(READ_TEMPERATURE_2) (Note 5)
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LTC2974
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ = 25°C. VPWR = VIN_SNS = 12V, VDD33, VDD25, REFP and REFM pins floating,
unless otherwise indicated. CVDD33 = 100nF, CVDD25 = 100nF and CREF = 100nF.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
160
1
MAX
UNITS
ms
t
Maximum Update Time
Input Sampling Capacitance
Input Sampling Frequency
Input Leakage Current
(Note 5)
UPDATE_ADC
C
pF
IN_ADC
IN_ADC
IN_ADC
f
I
62.5
kHz
µA
l
I
, I
IN_ADC
,V
, and V
COMMONMODE
0.5
SENSEPn SENSEMn SENSEPn
SENSEMn
Inputs, V
= 0V, 0V ≤ V
≤ 6V
l
l
Differential Input Current
V
, and V
Inputs, V
= 6V
10
15
µA
µA
SENSEPn
SENSEMn
IN_ADC
I
, and I
Inputs,
0.3
0.5
SENSEPn
SENSEMn
V
= 0.17V
IN_ADC
DAC Output Characteristics
N_V
Resolution
10
Bits
DAC
l
l
V
Full-Scale Output Voltage
(Programmable)
DAC Code = 0x3FF Buffer Gain Setting_0
1.3
2.5
1.38
2.65
1.44
2.77
V
V
FS_VDAC
DAC Polarity = 1
Buffer Gain Setting_1
l
l
l
INL_V
Integral Nonlinearity
Differential Nonlinearity
Offset Voltage
(Note 6)
2
LSB
LSB
DAC
DNL_V
(Note 6)
2.4
12
DAC
OS_VDAC
V
V
(Note 6)
mV
Load Regulation
V
DACn
V
DACn
= 2.65V, I Sourcing = 2mA
VDACn
100
100
60
ppm/mA
ppm/mA
dB
DAC
= 0.1V, I
Sinking = 2mA
VDACn
PSRR
DC: 3.13V ≤ V
≤ 3.47V, V = V
PWR DD33
DD33
l
l
l
Leakage Current
V
V
V
V
Hi-Z, 0V ≤ V
≤ 6V
100
–4
nA
DACn
DACn
DACn
DACn
DACn
Short-Circuit Current Low
Short-Circuit Current High
Output Capacitance
DAC Output Update Rate
Shorted to GND
–12
4
mA
Shorted to V
Hi-Z
12
mA
DD33
C
OUT
10
pF
t
Fast Servo Mode
250
µs
S_VDAC
Voltage Supervisor Characteristics
l
l
V
IN_VS
Input Voltage Range (Programmable)
V
= (V
SENSEMn
Low Resolution Mode
High Resolution Mode
0
0
6
3.8
V
V
IN_VS
SENSEPn
)
– V
l
Single-Ended Voltage: V
–0.1
0.1
V
mV/LSB
mV/LSB
%
SENSEMn
N_VS
Voltage Sensing Resolution
Total Unadjusted Error
0V to 3.8V Range: High Resolution Mode
0V to 6V Range: Low Resolution Mode
4
8
l
l
l
TUE_VS
2V ≤ V
≤ 6V, Low Resolution Mode
1.25
1.0
IN_VS
1.5V < V
0.8V ≤ V
≤ 3.8V, High Resolution Mode
≤ 1.5V, High Resolution Mode
%
IN_VS
IN_VS
1.5
%
t
Update Rate
12.21
400
µs
S_VS
Current Supervisor Characteristics
l
l
V
Current Sense Input Range
Single-Ended Voltage: I
, I
SENSEPn SENSEMn
–0.1
6
V
IN_CS
Differential Voltage:
–170
170
mV
V
= (I
– I
)
SENSEMn
IN_CS
SENSEPn
N_CS
Current Sense Resolution
Total Unadjusted Error
IOUT_OC_FAULT_LIMIT • IOUT_CAL_GAIN
IOUT_UC_FAULT_LIMIT • IOUT_CAL_GAIN
µV/LSB
l
l
TUE_CS
50mV ≤ V
≤ 170mV
3
%
IN_CS
V
IN_CS
< 50mV
1.5
mV
2974fa
6
For more information www.linear.com/LTC2974
LTC2974
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ = 25°C. VPWR = VIN_SNS = 12V, VDD33, VDD25, REFP and REFM pins floating,
unless otherwise indicated. CVDD33 = 100nF, CVDD25 = 100nF and CREF = 100nF.
SYMBOL
PARAMETER
CONDITIONS
|V | = 0.8mV
MIN
TYP
MAX
UNITS
µV
l
V
Offset Error
600
OS_CS
OS_CS
IN_CS
I
Differential Input Offset Current
OC = Positive Full-Scale, UC = 0A, VIN_CS
= 0V
117
nA
OC = UC = Positive Full-Scale, VIN_CS = 0V
OC = 0A, UC < 0A, VIN_CS = 0V
244
0
nA
nA
µs
t
Update Rate
12.21
S_CS
V
Input Characteristics
IN_SNS
l
l
l
l
l
l
V
V
Input Voltage Range
0
15
110
2.0
1.0
1.5
1.0
V
kΩ
%
IN_SNS
IN_SNS
IN_SNS
R
V
Input Resistance
70
90
VIN_SNS
TUE
VIN_ON, VIN_OFF Threshold Total
Unadjusted Error
3V ≤ V
≤ 8V
≤ 8V
VIN_SNS
VIN_SNS
V
> 8V
%
VIN_SNS
READ_VIN Total Unadjusted Error
3V ≤ V
%
VIN_SNS
V
> 8V
%
VIN_SNS
DAC Soft-Connect Comparator Characteristics
Offset Voltage
External Temperature Sensor Characteristics (READ_TEMPERATURE_1)
l
V
3
18
mV
ms
OS_CMP
t
Conversion Time
For One Channel, (Total Latency For All
Channels Is 4 • 66ms)
66
CONV_TSENSE
l
l
l
I
I
T
T
High Level Current
Low Level Current
–90
–64
–4
–40
–2.5
3
µA
µA
°C
TSENSE_HI
SENSE
SENSE
–5.5
TSENSE_LOW
TUE_TS
N_TS
Total Unadjusted Error
Ideal Diode Assumed
Maximum Ideality Factor
READ_TEMPERATURE_1 = 175°C
MFR_TEMP1_GAIN = 1/N_TS
1.10
NA
Internal Temperature Sensor Characteristics (READ_TEMPERATURE_2)
TUE_TS2 Total Unadjusted Error
1
°C
V
Enable Output (V ) Characteristics
OUT_EN[3:0]
OUT
l
l
l
V
Output High Voltage
I
= –5µA, V = 3.13V
DD33
12
–5
3
13
–7
5
14.7
–9
8
V
µA
VOUT_ENn
VOUT_ENn
VOUT_ENn
I
Output Sourcing Current
Output Sinking Current
V
Pull-Up Enabled, V
= 1V
VOUT_ENn
VOUT_ENn
Strong Pull-Down Enabled,
= 0.4V
mA
V
VOUT_ENn
l
l
Weak Pull-Down Enabled, V
= 0.4V
33
50
65
1
µA
µA
VOUT_ENn
Output Leakage Current
Internal Pull-Up Disabled,
0V ≤ V
≤ 15V
VOUT_ENn
General Purpose Output (AUXFAULTB) Characteristics
l
l
V
Output High Voltage
I
= –5µA, V = 3.13V
DD33
12
–5
13
–7
14.7
–9
V
AUXFAULTB
AUXFAULTB
AUXFAULTB
I
Output Sourcing Current
AUXFAULTB Pull-Up Enabled, V
1V
=
µA
AUXFAULTB
l
l
Output Sinking Current
Output Leakage Current
Strong Pull-Down Enabled, V
= 0.4V
3
5
8
1
mA
µA
AUXFAULTB
Internal Pull-Up Disabled, 0V ≤ V
≤ 15V
AUXFAULTB
EEPROM Characteristics
Endurance (Note 7)
l
0°C < T < 85°C During EEPROM Write
10,000
Cycles
J
Operations
2974fa
7
For more information www.linear.com/LTC2974
LTC2974
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ = 25°C. VPWR = VIN_SNS = 12V, VDD33, VDD25, REFP and REFM pins floating,
unless otherwise indicated. CVDD33 = 100nF, CVDD25 = 100nF and CREF = 100nF.
SYMBOL
PARAMETER
CONDITIONS
T < 85°C
MIN
TYP
MAX
UNITS
Years
ms
l
l
Retention
(Note 7)
10
J
t
Mass Write Operation Time (Note 8)
STORE_USER_ALL, 0°C < T < 85°C During
EEPROM Write Operations
440
4100
MASS_WRITE
J
Digital Inputs SCL, SDA, CONTROL0, CONTROL1, CONTROL2, CONTROL3, WDI/RESETB, FAULTB0, FAULTB1, WP
l
V
V
V
High Level Input Voltage
Low Level Input Voltage
FAULTB0, FAULTB1, SDA, SCL, WDI/RESETB,
WP
2.1
V
IH
l
l
CONTROLn
1.85
V
V
FAULTB0, FAULTB1, SDA, SCL, WDI/RESETB,
WP
1.5
1.6
IL
l
l
CONTROLn
V
mV
µA
µs
Input Hysteresis
20
HYST
LEAK
SP
I
t
Input Leakage Current
Pulse Width of Spike Suppressed
0V ≤ V ≤ 3.6V
2
PIN
FAULTB0, FAULTB1, CONTROLn
10
98
SDA, SCL
ns
t
Minimum Low Pulse Width for
Externally Generated Faults
180
ms
FAULT_MIN
l
l
l
t
t
f
Pulse Width to Assert Reset
V
V
≤ 1.5V
≤ 1.5V
300
0.3
µs
µs
RESETB
WDI/RESETB
Pulse Width to Reset Watchdog Timer
200
1
WDI
WDI/RESETB
Watchdog Timer Interrupt Input
Frequency
MHz
WDI
C
Input Capacitance
10
pF
IN
Digital Input SHARE_CLK
l
l
l
l
l
l
V
V
High Level Input Voltage
Low Level Input Voltage
Input Frequency Operating Range
Assertion Low Time
Rise Time
1.6
V
V
IH
0.8
110
1.11
450
1
IL
f
t
t
I
90
kHz
µs
SHARE_CLK_IN
LOW
V
V
< 0.8V
0.825
SHARE_CLK
< 0.8V to V
> 1.6V
ns
RISE
SHARE_CLK
SHARE_CLK
Input Leakage Current
Input Capacitance
0V ≤ V
≤ V
+ 0.3V
µA
pF
LEAK
SHARE_CLK
DD33
C
10
IN
Digital Outputs SDA, ALERTB, SHARE_CLK, FAULTB0, FAULTB1, PWRGD
l
l
V
Digital Output Low Voltage
I
= 3mA
0.4
V
OL
SINK
f
Output Frequency Operating Range
5.49kΩ Pull-Up to V
90
100
110
kHz
SHARE_CLK_OUT
DD33
Digital Inputs ASEL0,ASEL1
l
l
l
l
V
V
Input High Threshold Voltage
Input Low Threshold Voltage
High, Low Input Current
Hi-Z Input Current
V
DD33
– 0.5
V
V
IH
0.5
95
24
IL
I
I
ASEL[1:0] = 0, V
µA
µA
pF
IH,IL
IH,Z
DD33
C
Input Capacitance
10
IN
Serial Bus Timing Characteristics
l
l
l
f
t
t
Serial Clock Frequency (Note 9)
Serial Clock Low Period (Note 9)
Serial Clock High Period (Note 9)
10
1.3
0.6
400
kHz
µs
SCL
LOW
HIGH
µs
2974fa
8
For more information www.linear.com/LTC2974
LTC2974
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ = 25°C. VPWR = VIN_SNS = 12V, VDD33, VDD25, REFP and REFM pins floating,
unless otherwise indicated. CVDD33 = 100nF, CVDD25 = 100nF and CREF = 100nF.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
t
Bus Free Time Between Stop and Start
(Note 10)
1.3
µs
BUF
l
l
l
l
t
t
t
t
Start Condition Hold Time (Note 9)
Start Condition Setup Time (Note 9)
Stop Condition Setup Time (Note 9)
600
600
600
0
ns
ns
ns
ns
HD,STA
SU,STA
SU,STO
HD,DAT
Data Hold Time (LTC2974 Receiving
Data) (Note 9)
l
l
Data Hold Time (LTC2974 Transmitting
Data) (Note 9)
300
100
900
ns
t
t
Data Setup Time (Note 9)
ns
ns
SU,DAT
Pulse Width of Spike Suppressed
(Note 9)
98
SP
l
l
t
Time Allowed to Complete any PMBus Longer Timeout = 0
Command After Which Time SDA Will Longer Timeout = 1
Be Released and Command Terminated
25
200
35
280
ms
ms
TIMEOUT_BUS
Additional Digital Timing Characteristics
Minimum Off Time for Any Channel
t
100
ms
OFF_MIN
–2
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
the resolution for 1LSB in this range is 2 mA = 250µA. Each successively
lower range improves resolution by cutting the LSB size in half.
Note 5: The nominal time between successive ADC conversions (latency of
the ADC) for any given channel is t
.
UPDATE_ADC
Note 2: All currents into device pins are positive. All currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
Note 6: Nonlinearity is defined from the first code that is greater than or
equal to the maximum offset specification to full-scale code, 1023.
specified. If power is supplied to the chip via the V
pin only, connect
DD33
Note 7: EEPROM endurance and retention are guaranteed by design,
characterization and correlation with statistical process controls. The
minimum retention specification applies for devices whose EEPROM has
been cycled less than the minimum endurance specification.
Note 8: The LTC2974 will not acknowledge any PMBus commands,
except for MFR_COMMON, when a STORE_USER_ALL command is being
executed. See also OPERATION section.
V
PWR
and V
pins together.
DD33
Note 3: Hysteresis in the output voltage is created by package stress
that differs depending on whether IC was previously at a higher or lower
temperature. Output voltage is always measured at 25°C, but the IC is
cycled to 85°C or –40°C before successive measurements. Hysteresis is
roughly proportional to the square of the temperature change.
Note 4: The current sense resolution is determined by the L11 format and
Note 9: Maximum capacitive load, C , for SCL and SDA is 400pF. Data and
B
the mV units of the returned value. For example, a full-scale value of 170mV
clock risetime (t ) and falltime (t ) are: (20 + 0.1• C ) (ns) < t < 300ns and
r
f
B
r
–2
returns a L11 value of 0xF2A8 = 680 • 2 = 170. This is the lowest range
(20 + 0.1 • C ) (ns) < t < 300ns. C = capacitance of one bus line in pF.
B
f
B
that can represent this value without overflowing the L11 mantissa and
SCL and SDA external pull-up voltage, V , is 3.13V < V < 3.6V.
IO
IO
PMBUS TIMING DIAGRAM
SDA
t
r
t
SU(DAT)
t
t
SP
t
HD(STA)
r
t
f
t
t
f
t
BUF
LOW
SCL
t
t
t
SU(STO)
HD(STA)
SU(STA)
t
t
HIGH
HD(DAT)
2974 TD
START
CONDITION
REPEATED START
CONDITION
STOP
START
CONDITION CONDITION
2974fa
9
For more information www.linear.com/LTC2974
LTC2974
TYPICAL PERFORMANCE CHARACTERISTICS
Reference Voltage vs
Temperature
ADC READ_VOUT Total Unadjusted
Error vs Temperature
ADC READ_IOUT Input Referred
Offset Voltage vs Temperature
1.2322
1.2320
1.2318
1.2316
1.2314
1.2312
1.2310
1.2308
1.2306
1.2304
0.07
0.06
5
4
THREE TYPICAL PARTS
0.05
3
0.04
2
0.03
1
0.02
0
0.01
–1
–2
–3
–4
–5
0.00
–0.01
–0.02
–0.03
THREE TYPICAL PARTS
THREE TYPICAL PARTS
–50
–25
0
25
100
–50
–25
0
25
100
–50
–25
0
25
100
50
75
50
75
50
75
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
2974 G01
2974 G02
2974 G03
ADC READ_IOUT Error
vs READ_IOUT
ADC READ_VOUT-INL
ADC READ_VOUT-DNL
5
4
5
4
75
IOUT_CAL_GAIN = 2.1875mΩ
122µV/LSB
122µV/LSB
50
25
3
3
2
2
1
1
0
0
0
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
–25
–50
–75
0.001
0.01
0.1
1
10
100
0
1
2
3
4
5
0
1
2
3
4
5
6
6
READ_VOUT (V)
READ_VOUT (V)
READ_IOUT (A)
2974 G04
2974 G05
2974 G06
Input Sampling Current vs
Differential Input Voltage:
Voltage Sense Inputs
Input Sampling Current vs
ADC READ_IOUT Input Referred
Noise vs Temperature
Differential Input Voltage: Current
Sense Inputs
4.50
4.25
4.00
3.75
3.50
3.25
3.00
2.75
2.50
7
6
5
4
3
2
1
0
400
350
300
250
200
150
100
50
V
CM
= 2.5V
0
–50
–25
0
25
100
0
1
2
3
6
0
25
DIFFERENTIAL INPUT VOLTAGE (mV)
2974 G09
50
75
175
50
75
4
5
100 125 150
TEMPERATURE (°C)
DIFFERENTIAL INPUT VOLTAGE (V)
2974 G07
2974 G08
2974fa
10
For more information www.linear.com/LTC2974
LTC2974
TYPICAL PERFORMANCE CHARACTERISTICS
Voltage Supervisor Total
Unadjusted Error vs Temperature
Current Supervisor Total
Unadjusted Error vs Temperature
DAC Full-Scale Voltage
vs Temperature, Gain = 0
0.25
0.20
0.15
0.10
0.05
0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.405
1.400
1.395
1.390
1.385
1.380
1.375
1.370
1.365
1.360
HIGH RES MODE
IN
GAIN SETTING = 0
V
= 1.5V
50mV
–0.05
–0.10
–0.15
–0.20
20mV
THREE TYPICAL PARTS
–50 –25 25
TEMPERATURE (°C)
THREE TYPICAL PARTS
–50 –25 25
TEMPERATURE (°C)
0
100
–50
–25
0
25
100
0
100
50
75
50
75
50
75
TEMPERATURE (°C)
2974 G10
2974 G11
2974 G12
DAC Full-Scale Voltage
vs Temperature, Gain = 1
DAC Offset Voltage
DAC Offset Voltage
vs Temperature, Gain = 0
vs Temperature, Gain = 1
2.70
2.69
2.68
2.67
2.66
2.65
2.64
2.63
2.62
0.0025
0.0020
0.0015
0.0010
0.0005
0
0.0040
0.0035
0.0030
0.0025
0.0020
0.0015
0.0010
0.0005
0
GAIN SETTING = 1
GAIN SETTING = 0
GAIN SETTING = 1
THREE TYPICAL PARTS
–50 –25 25
TEMPERATURE (°C)
THREE TYPICAL PARTS
–50 –25 25
TEMPERATURE (°C)
THREE TYPICAL PARTS
–50 –25 25
TEMPERATURE (°C)
0
100
0
100
0
100
50
75
50
75
50
75
2974 G13
2974 G14
2974 G15
VDD33 Regulator Output Voltage
vs Temperature
DAC-INL
DAC-DNL
3.285
3.280
3.275
3.270
3.265
3.260
3.255
3.250
3.245
3.240
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
–1.00
–0.25
–0.50
–0.75
–1.00
THREE TYPICAL PARTS
0
256
512
768
1024
0
256
512
768
1024
–50
–25
0
25
100
50
75
TEMPERATURE (°C)
DAC CODE
DAC CODE
2974 G16
2974 G17
2974 G18
2974fa
11
For more information www.linear.com/LTC2974
LTC2974
TYPICAL PERFORMANCE CHARACTERISTICS
V
VOUT_ENn and VAUXFAULTB Output
VVOUT_ENn and VAUXFAULTB Output
VOL vs Current Sinking
VDD33 Regulator Load Regulation
VOH vs Current Sourcing
0
–1000
–2000
–3000
–4000
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
9.5
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
85°C
25°C
–40°C
85°C
25°C
–40°C
9.0
8
12
0
2
4
6
10
0
10
20
50
0
1
2
3
6
7
8
30
40
4
5
LOAD CURRENT SOURCING (mA)
CURRENT SOURCING (µA)
CURRENT SINKING (mA)
2974 G21
2974 G19
2974 G20
PWRGD and FAULTBn VOL vs
Current Sinking
ALERTB VOL vs Current Sinking
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
85°C
25°C
–40°C
85°C
25°C
–40°C
20
15
0
5
10
15
0
5
10
CURRENT SINKING (mA)
CURRENT SINKING (mA)
2974 G22
2974 G23
External Temperature READ_
TEMPERATURE_1 Error vs
Temperature
READ_TEMPERATURE_2 Error vs
Temperature
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
MMBT3906 DIODE CONNECTED BJTS
MFR_TEMP_1_GAIN_ADJ = 0.987
MFR_EXT_TEMP_1_ADC_OFF = –2°C
V
DD33
= V
= 3.3V
PWR
–0.25
–0.50
–0.75
–1.00
–0.25
–0.50
–0.75
–1.00
THREE TYPICAL PARTS
THREE TYPICAL PARTS
–50 –25 25
TEMPERATURE (°C)
–50
–25
0
25
100
0
100
50
75
50
75
TEMPERATURE (°C)
2974 G24
2974 G25
2974fa
12
For more information www.linear.com/LTC2974
LTC2974
PIN FUNCTIONS
PIN NAME
PIN NUMBER
PIN TYPE
In
DESCRIPTION
V
V
V
V
V
V
1*
2*
3
DC/DC Converter Differential (+) Output Voltage-0 Sensing Pin
DC/DC Converter Differential (–) Output Voltage-0 Sensing Pin
SENSEP0
SENSEM0
OUT_EN0
OUT_EN1
OUT_EN2
OUT_EN3
In
Out
DC/DC Converter Enable-0 Pin. Output High Voltage Optionally Pulled-Up to 12V by 5µA
DC/DC Converter Enable-1 Pin. Output High Voltage Optionally Pulled-Up to 12V by 5µA
DC/DC Converter Enable-2 Pin. Output High Voltage Optionally Pulled-Up to 12V by 5µA
DC/DC Converter Enable-3 Pin. Output High Voltage Optionally Pulled-Up to 12V by 5µA
4
Out
5
Out
6
Out
AUXFAULTB
7
Out
Auxillary Fault Output Pin. Output High Voltage Optionally Pulled-Up to 12V by 5µA. Can Be
Configured to Pull Low When OV/UV/OC/UC Detected
DNC
8
9
Do Not Connect Do Not Connect to this Pin
V
V
In
V SENSE Input. This Voltage is Compared Against the V On and Off Voltage Thresholds In Order to
IN IN
Determine When to Enable and Disable, Respectively, the Downstream DC/DC Converters
IN_SNS
10
11
In
V
Serves as the Unregulated Power Supply Input to the Chip (4.5 to 15V). If a 4.5V to 15V Supply
PWR
PWR
Voltage Is Unavailable, Short V
to GND with 0.1µF Capacitor.
to V
and Power the Chip Directly from a 3.3V Supply. Bypass
DD33
PWR
V
DD33
In/Out
If Shorted to V
, It Serves as 3.13 to 3.47V Supply Input Pin. Otherwise It Is a 3.3V Internally
PWR
Regulated Voltage Output (Use 0.1µF Decoupling Capacitor to GND)
Input for Internal 2.5V Sub-Regulator. Short this Pin to Pin 11
2.5V Internally Regulated Voltage Output. Bypass to GND with a 0.1µF Capacitor
2.5V Supply Voltage Input. Short this Pin to Pin 13
V
V
V
12
13
In
DD33
In/Out
In
DD25
14
DD25
T
15*
In/Out
External Temperature Current Output and Voltage Input for Channel 0. Maximum allowed capacitance
is 1µF
SENSE0
T
16*
17
In/Out
Out
External Temperature Current Output and Voltage Input for Channel 1. Maximum allowed capacitance
is 1µF
SENSE1
PWRGD
Power-Good Open Drain Output. Indicates When Selected Outputs Are Power Good. Can be Used as
System Power-on Reset
SHARE_CLK
GND
18
19
20
21
22
23
24
In/Out
Ground
Ground
Ground
In
Bidirectional Clock Sharing Pin. Connect a 5.49kΩ Pull-Up Resistor to V
Chip Ground. Must Be Soldered to PCB
Chip Ground. Must Be Soldered to PCB
Chip Ground. Must Be Soldered to PCB
Control Pin 2 Input
DD33
GND
GND
CONTROL2
CONTROL3
WDI/RESETB
In
Control Pin 3 Input
In
Watchdog Timer Interrupt and Chip Reset Input. Connect a 10kΩ Pull-Up Resistor to V
. Rising
DD33
Edge Resets Watchdog Counter. Holding this Pin Low for More than t
Resets the Chip
RESETB
FAULTB0
FAULTB1
25
26
In/Out
In/Out
In/Out
Open-Drain Output and Digital Input. Active Low Bidirectional Fault Indicator-0. Connect a 10kΩ
Pull-Up Resistor to V
DD33
Open-Drain Output and Digital Input. Active Low Bidirectional Fault Indicator-1. Connect a 10kΩ
Pull-Up Resistor to V
DD33
T
27*
External Temperature Current Output and Voltage Input for Channel 2. Maximum allowed capacitance
is 1µF
SENSE2
WP
28
29
30
31
32
33
In
In/Out
In
Digital Input. Write-Protect Input Pin, Active High
PMBus Bidirectional Serial Data Pin
SDA
SCL
PMBus Serial Clock Input Pin (400kHz Maximum)
Open-Drain Output. Generates an Interrupt Request in a Fault/Warning Situation
Control Pin 0 Input
ALERTB
CONTROL0
CONTROL1
Out
In
In
Control Pin 1 Input
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LTC2974
PIN FUNCTIONS
PIN NAME
PIN NUMBER
PIN TYPE
DESCRIPTION
T
34*
In/Out
External Temperature Current Output and Voltage Input for Channel 3. Maximum allowed capacitance
is 1µF
SENSE3
ASEL0
ASEL1
GND
35
36
In
Ternary Address Select Pin 0 Input. Connect to V
Ternary Address Select Pin 1 Input. Connect to V
Chip Ground. Must Be Soldered to PCB
, GND or Float to Encode 1 of 3 Logic States
, GND or Float to Encode 1 of 3 Logic States
DD33
In
DD33
37
Ground
REFP
GND
38
Out
Reference Voltage Output. Needs 0.1µF Decoupling Capacitor to REFM
Chip Ground. Must Be Soldered to PCB
39
Ground
REFM
40
Out
Reference Return Pin. Needs 0.1µF Decoupling Capacitor to REFP
DC/DC Converter Differential (+) Output Current-0 Sensing Pin
DC/DC Converter Differential (–) Output Current-0 Sensing Pin
DC/DC Converter Differential (+) Output Current-1 Sensing Pin
DC/DC Converter Differential (–) Output Current-1 Sensing Pin
DC/DC Converter Differential (+) Output Current-2 Sensing Pin
DC/DC Converter Differential (–) Output Current-2 Sensing Pin
DC/DC Converter Differential (+) Output Current-3 Sensing Pin
DC/DC Converter Differential (–) Output Current-3 Sensing Pin
DC/DC Converter Differential (+) Output Voltage-3 Sensing Pin
DC/DC Converter Differential (–) Output Voltage-3 Sensing Pin
No Connect
I
I
I
I
I
I
I
I
41*
42*
43*
44*
45*
46*
47*
48*
49*
50*
51
In
SENSEP0
SENSEM0
SENSEP1
SENSEM1
SENSEP2
SENSEM2
SENSEP3
SENSEM3
In
In
In
In
In
In
In
V
V
In
SENSEP3
In
No Connect
No Connect
Out
SENSEM3
NC
NC
52
No Connect
V
DAC0
V
DAC1
53
DAC0 Output
54
Out
DAC1 Output
NC
NC
55
No Connect
No Connect
Out
No Connect
56
No Connect
V
V
57
DAC2 Output
DAC2
DAC3
58
Out
DAC3 Output
NC
NC
59
No Connect
No Connect
In
No Connect
60
No Connect
V
V
V
V
61*
62*
63*
64*
65
DC/DC Converter Differential (+) Output Voltage-2 Sensing Pin
DC/DC Converter Differential (–) Output Voltage-2 Sensing Pin
DC/DC Converter Differential (+) Output Voltage-1 Sensing Pin
DC/DC Converter Differential (–) Output Voltage-1 Sensing Pin
Exposed Pad. Must Be Soldered to PCB
SENSEP2
SENSEM2
SENSEP1
SENSEM1
In
In
In
GND
Ground
*Any unused V
/I
, V
/I
or T
pins should be tied to GND.
SENSEn
SENSEPn SENSEPn SENSEMn SENSEMn
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LTC2974
BLOCK DIAGRAM
3.3V REGULATOR
IN
V
10
11
V
V
OUT
PWR
V
V
V
DD33
DD33(OUT)
2.5V REGULATOR
IN
V
12
13
V
DD33(IN)
V
OUT
DD25(OUT)
V
14
9
V
DD25
DD25(IN)
3R
V
V
SENSEP0
SENSEM0
V
IN_SNS
DNC
R
20Ω
I
I
SENSEP0
1
V
V
I
SENSEP0
SENSEM0
8
SENSEM0
2
V
V
SENSEP1
SENSEM1
41
42
63
64
43
44
61
62
45
46
49
50
47
48
SENSEP0
SENSEM0
I
I
I
SENSEP1
V
V
I
–
+
+
–
SENSEM1
SENSEP1
SENSEM1
V
V
SENSEP2
SENSEM2
ICMP
INTERNAL
TEMP
SENSOR
+
–
10-BIT
VDAC
SENSEP1
SENSEM1
MUX
I
I
SENSEP2
I
SENSEM2
–
+
+
–
V
V
I
SENSEP2
SENSEM2
V
V
SENSEP3
SENSEM3
VCMP
+
–
GND 19
GND 20
GND 21
GND 37
GND 39
GND 65
10-BIT
VDAC
SENSEP2
SENSEM2
I
I
SENSEP3
I
SENSEM3
V
V
I
SENSEP3
SENSEM3
+
–
16-BIT
∆∑ ADC
SENSEP3
SENSEM3
I
ADC
CLOCKS
10-BIT
DAC
53
54
57
58
V
V
V
V
VBUF
DAC0
DAC1
DAC2
DAC3
V
DD33
REFERENCE
1.232V
(TYP)
REFP 38
REFM 40
51 NC
52 NC
55 NC
56 NC
59 NC
60 NC
ALERTB 31
SCL 30
PAGE 0
PAGE 1
PAGE 2
PAGE 3
PMBus
EEPROM
INTERFACE
SDA 29
2
(400kHz I C
RAM
COMPATIBLE)
ASEL0 35
ASEL1 36
ADC_RESULTS
MONITOR LIMITS
SERVO TARGETS
3
4
5
6
7
V
V
V
V
OUT_EN0
OUT_EN1
OUT_EN2
OUT_EN3
WP 28
MASKING
CLOCK
GENERATION
OSCILLATOR
PWRGD 17
SHARE_CLK
18
V
AUXFAULTB
DD
WDI/RESETB 24
FAULTB0 25
CONTROLLER
PMBus ALGORITHM
FAULT PROCESSOR
WATCHDOG
PORB
UVLO
FAULTB1 26
15
16
27
34
T
T
T
T
SENSE0
SENSE1
SENSE2
SENSE3
SEQUENCER
CONTROL0 32
EXTERNAL
TEMPERATURE
SENSOR
CONTROL1
33
CONTROL2 22
CONTROL3 23
2974 BD
2974fa
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For more information www.linear.com/LTC2974
LTC2974
OPERATION
LTC2974 OPERATION OVERVIEW
• Optionally stop trimming the DC/DC converter output
voltage after it reaches the initial margin or nominal
target. Optionally allow servo to resume if target drifts
The LTC2974 is a PMBus programmable power supply
controller, monitor, sequencer and voltage and current
supervisor that can perform the following operations:
outside of V
warning limits.
OUT
• StorecommandregistercontentswithCRCtoEEPROM
• Accept PMBus compatible programming commands.
through PMBus programming.
• Provide DC/DC converter input voltage, output voltage,
outputcurrent,output temperature,andinternaljunction
temperature readback through the PMBus interface.
• Restore EEPROM contents through PMBus program-
ming or when VDD33 is applied on power-up.
• Report the DC/DC converter output voltage status
• Control the output of DC/DC converters that set the
output voltage with a trim pin or DC/DC converters
that set the output voltage using an external resistor
feedback network.
through the power good output.
• GenerateinterruptrequestsbyassertingtheALERTBpin
in response to supported PMBus faults and warnings.
• Sequence the startup of DC/DC converters via PMBus
programming and the CONTROL input pins. The LTC
2974 supports time-based sequencing and tracking
sequencing. Cascade sequence on with time based
sequence off is also supported.
• Coordinate system wide fault responses for all DC/DC
converters connected to the LTC2974 FAULTB0 and
FAULTB1 pins.
• Synchronizesequencingdelaysorshutdownformultiple
devices using the SHARE_CLK pin.
• Trim the DC/DC converter output voltage (typically in
0.02% steps), in closed-loop servo operating mode,
autonomously or through PMBus programming.
• Software and hardware write protect the command
registers.
• Disable the input voltage to the supervised DC/DC
converters in response to output OV, UV, OC and UC
faults.
• Margin the DC/DC converter output voltage to PMBus
programmed limits.
• TrimormargintheDC/DCconverteroutputvoltagewith
• Log telemetry and status data to EEPROM in response
direct access to the margin DAC.
to a faulted-off condition.
• Supervise the DC/DC converter input voltage, output
voltage, load current and the inductor temperatures
for overvalue/undervalue conditions with respect to
PMBus programmed limits and generate appropriate
faults and warnings.
• Supervise an external microcontroller’s activity for a
stalled condition with a programmable watchdog timer
and reset it if necessary.
• Prevent a DC/DC converter from re-entering the on
state after a power cycle until a programmable interval
(MFR_RESTART_DELAY) has elapsed and its output
has decayed below a programmable threshold voltage
(MFR_VOUT_DISCHARGE_THRESHOLD).
• Accuratelyhandleinductorself-heatingtransientsusing
a proprietary algorithm. These self-heating effects are
combined with external temperature sensor readings
to improve accuracy of current supervisors and ADC
current measurement.
• Record minimum and maximum observed values of
input voltage, output voltages, output currents and
output temperatures.
• Respond to a fault condition by continuing operation
indefinitely, latching-off after a programmable deglitch
period, latching-off immediately or sequencing off
after TOFF_DELAY. Use retry mode to automatically
recoverfromalatched-offcondition.Withretryenabled,
MFR_RETRY_COUNT programs the number of retries
(0 to 6 or infinite) for all pages.
• Access user EEPROM data directly, without alter-
ing RAM space (Mfr_ee_unlock, Mfr_ee_erase, and
Mfr_ee_data). Facilitates in-house bulk programming.
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For more information www.linear.com/LTC2974
LTC2974
OPERATION
EEPROM
So the overall rentention of the EEPROM was degraded by
34 hours as a result of operation at a junction temperature
of 95°C for 10 hours. Note that the effect of this overstress
is negligible when compared to the overall EEPROM
rentention rating of 87,600 hours at a maximum junction
temperature of 85°C.
The LTC2974 contains internal EEPROM (Non-Volatile
Memory) to store configuration settings and fault log
information. EEPROM endurance, retention and mass
write operation time are specified over the operating tem-
peraturerange.SeeElectricalCharacteristicsandAbsolute
Maximum Ratings sections.
AUXFAULTB
Non destructive operation above T = 85°C is possible
J
The AUXFAULTB pin can be commanded to one of two
output levels at any time via the PMBUS. If desired, the
AUXFAULTB pin can also be configured to indicate when
some fault conditions have been detected, using a third
output level. See Figure 1 for a conceptual view of this
multiplexing.
although the Electrical Characteristics are not guaranteed
and the EEPROM will be degraded.
Operating the EEPROM above 85°C may result in a deg-
radation of retention characteristics. The fault logging
function, which is useful in debugging system problems
that may occur at high temperatures, only writes to fault
log EEPROM locations. If occasional writes to these reg-
isters occur above 85°C, a slight degradation in the data
retention characteristics of the fault log may occur.
PMBUS
COMMAND
HI-Z
WEAK 12V PULL-UP
AUXFAULTB
FAST
PULL-DOWN
It is recommended that the EEPROM not be written using
STORE_USER_ALLorbulkprogrammingwhenT >85°C.
OV/UV/OC/UC
(MASKABLE)
J
SET
fault_seen
Q
The degradation in EEPROM retention for temperatures
>85°C can be approximated by calculating the dimension-
less acceleration factor using the following equation.
RESET
2974 F01
OFF_THEN_ON
OR
FAULT_RETRY
FOR ANY CHANNEL
Ea
k
1
1
•
–
AF = e
Figure 1: AUXFAULTB MUX
T
USE +273 TSTRESS +273
The MFR_CONFIG2_LTC2974 and MFR_CONFIG3_
LTC2974 commands can be used on a per channel basis
to select which, if any, fault conditions will cause the
AUXFAULTB pin to be driven to its third output level (fast
pull-down to GND). The only fault types which can be
propagated to the AUXFAULTB pin are over/under voltage
faults and over/under current faults.
Where:
AF = acceleration factor
Ea = activation energy = 1.4eV
–5
k = 8.625 • 10 eV/°K
T
T
= 85°C specified junction temperature
USE
Mfr_config_all_auxfaultb_wpu selects whether the
AUXFAULTB pin is in the hi-Z state, or weakly pulled-up
to approximately 12V, using a 5µA current. As shown in
Figure 1, the pulldown to GND overrides if any enabled
faults are detected.
= actual junction temperature °C
STRESS
Example: Calculate the effect on retention when operating
at a junction temperature of 95°C for 10 hours.
T
T
= 95°C
STRESS
= 85°C
USE
AF = 3.4
Equivalent operating time at 85°C = 34 hours.
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LTC2974
OPERATION
RESETB
The PMBus two wire interface is an incremental extension
2
of the SMBus. SMBus is built upon I C with some minor
Holding the WDI/RESETB pin low for more than t
RESETB
differences in timing, DC parameters and protocol. The
will cause the LTC2974 to enter the power-on reset state.
2
SMBus protocols are more robust than simple I C byte
While in the power-on reset state, the device will not
commands because they provide timeouts to prevent
bus hangs and optional Packet Error Checking (PEC) to
ensure data integrity. In general, a master device that
2
communicate on the I C bus. Following the subsequent
rising-edge of the WDI/RESETB pin, the LTC2974 will
execute its power-on sequence per the user configuration
stored in EEPROM. Connect WDI/RESETB to VDD33 with
a 10k resistor. WDI/RESETB includes an internal 256μs
deglitch filter so additional filter capacitance on this pin
is not recommended.
2
can be configured for I C communication can be used
for PMBus communication with little or no change to
hardware or firmware.
For a description of the minor extensions and exceptions
PMBusmakestoSMBus,refertoPMBusSpecificationPart
1 Revision 1.1: Section 5: Transport. This can be found at:
PMBus SERIAL DIGITAL INTERFACE
www.pmbus.org
TheLTC2974communicateswithahost(master)usingthe
standard PMBus serial bus interface. The PMBus Timing
Diagram shows the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources are required on these lines.
2
ForadescriptionofthedifferencesbetweenSMBusandI C,
refer to System Management Bus (SMBus) Specification
Version 2.0: Appendix B – Differences between SMBus
2
and I C. This can be found at:
www.smbus.org
TheLTC2974isaslavedevice.Themastercancommunicate
with the LTC2974 using the following formats:
2
WhenusinganI CcontrollertocommunicatewithaPMBus
part it is important that the controller be able to write a
byte of data without generating a stop. This will allow the
controller to properly form the repeated start of a PMBus
read command by concatenating a start command byte
• Master transmitter, slave receiver
• Master receiver, slave transmitter
The following SMBus commands are supported:
• Write Byte, Write Word, Send Byte
• Read Byte, Read Word, Block Read
• Alert Response Address
2
write with an I C read.
Device Address
2
The I C/SMBus address of the LTC2974 equals the base
address + N where N is a number from 0 to 8. N can be
configured by setting the ASEL0 and ASEL1 pins to V
,
Figures1to12illustratetheaforementionedSMBusproto-
cols. AlltransactionssupportPEC (parityerrorcheck)and
GCP(groupcommandprotocol).TheBlockReadsupports
255 bytes of returned data. For this reason, the SMBus
timeout may be extended using the Mfr_config_all_lon-
ger_pmbus_timeout setting.
DD33
GND or FLOAT. See Table 1. Using one base address and
the nine values of N, nine LTC2974s can be connected
together to control thirty six outputs. The base address is
storedintheMFR_I2C_BASE_ADDRESSregister.Thebase
address can be written to any value, but generally should
not be changed unless the desired range of addresses
overlap existing addresses. Watch that the address range
PMBus
2
does not overlap with other I C/SMBus device or global
PMBus is an industry standard that defines a means
of communication with power conversion devices. It is
comprised of an industry standard SMBus serial interface
and the PMBus command language.
2
addresses, including I C/SMBus multiplexers and bus
buffers. This will bring you great happiness.
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LTC2974
OPERATION
TheLTC2974alwaysrespondstoitsglobaladdressandthe
SMBus Alert Response address regardless of the state of
itsASELpinsandtheMFR_I2C_BASE_ADDRESSregister.
exceptions where the part will NACK a subsequent com-
mandbecauseitisstillprocessingthepreviouscommand.
Thesearesummarizedinthefollowingtables. MFR_COM-
MON is a special command that may always be read even
when the part is busy. This provides an alternate method
for a host to determine if the LTC2974 is busy.
Processing Commands
The LTC2974 uses a dedicated processing block to ensure
quick response to all of its commands. There are a few
EEPROM Related Commands
COMMAND
TYPICAL DELAY* COMMENT
STORE_USER_ALL
t
See Electrical Characterization table. The LTC2974 will not accept any commands while it is transferring
register contents to the EEPROM. The command byte will be NACKed. MFR_COMMON may always be
read.
MASS_WRITE
RESTORE_USER_ALL
MFR_FAULT_LOG_CLEAR
MFR_FAULT_LOG_STORE
Internal Fault log
30ms
175ms
20ms
20ms
The LTC2974 will not accept any commands while it is transferring EEPROM data to command registers.
The command byte will be NACKed. MFR_COMMON may always be read.
The LTC2974 will not accept any commands while it is initializing the fault log EEPROM space. The
command byte will be NACKed. MFR_COMMON may always be read.
The LTC2974 will not accept any commands while it is transferring fault log RAM buffer to EEPROM
space. The command byte will be NACKed. MFR_COMMON may always be read.
An internal fault log event is a one time event that uploads the contents of the fault log to EEPROM in
response to a fault. Internal fault logging may be disabled. Commands received during this EEPROM
write are NACKed. MFR_COMMON may always be read.
MFR_FAULT_LOG_RESTORE
2ms
The LTC2974 will not accept any commands while it is transferring EEPROM data to the fault log RAM
buffer. The command byte will be NACKed. MFR_COMMON may always be read.
*The typical delay is measured from the command’s stop to the next command’s start.
Other Commands
COMMAND
DELAY*
COMMENT
MFR_CONFIG
<50µs
The LTC2974 will not accept any commands while it is completing this command. The command byte
will be NACKed. MFR_COMMON may always be read.
IOUT_CAL_GAIN
<500µs
The LTC2974 will not accept any commands while it is completing this command. The command byte
will be NACKed. MFR_COMMON may always be read.
*The typical delay is measured from the command’s stop to the next command’s start.
Other PMBus Timing Notes
COMMAND
COMMENT
CLEAR_FAULTS
The LTC2974 will accept commands while it is completing this command but the affected status flags will not be cleared for
up to 500µs.
2974fa
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For more information www.linear.com/LTC2974
LTC2974
OPERATION
Table 1. LTC2974 Address Look-Up Table with MFR_I2C_BASE_ADDRESS Set to 7bit 0x5C
HEX DEVICE
ADDRESS
DESCRIPTION
BINARY DEVICE ADDRESS
ADDRESS PINS
7-Bit
8-Bit
19
6
0
1
1
1
1
1
1
1
1
1
1
5
0
0
0
0
0
0
1
1
1
1
1
4
0
1
1
1
1
1
0
0
0
0
0
3
1
1
1
1
1
1
0
0
0
0
0
2
1
0
1
1
1
1
0
0
0
0
1
1
0
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
R/W
1
ASEL1
ASEL0
Alert Response
Global
N = 0
0C
5B
5C*
5D
5E
5F
X
X
X
X
B6
B8
BA
BC
BE
C0
C2
C4
C6
C8
0
0
L
L
N = 1
0
L
NC
H
N = 2
0
L
N = 3
0
NC
NC
NC
H
L
N = 4
60
61
62
63
64
0
NC
H
N = 5
0
N = 6
0
L
N = 7
0
H
NC
H
N = 8
0
H
H = Tie to V
, NC = No Connect = Open or Float, L = Tie to GND, X = Don’t Care
DD33
*MFR_I2C_BASE_ADDRESS = 7bit 0x5C (Factory Default)
1
7
1
1
A
x
8
1
A
x
1
S
SLAVE ADDRESS Wr
DATA BYTE
P
S
START CONDITION
Sr
REPEATED START CONDITION
Rd READ (BIT VALUE OF 1)
Wr WRITE (BIT VALUE OF 0)
x
SHOWN UNDER A FIELD INDICATES THAT THAT
FIELD IS REQUIRED TO HAVE THE VALUE OF x
A
P
ACKNOWLEDGE (THIS BIT POSITION MAY BE 0
FOR AN ACK OR 1 FOR A NACK)
STOP CONDITION
PEC PACKET ERROR CODE
MASTER TO SLAVE
SLAVE TO MASTER
...
CONTINUATION OF PROTOCOL
2974 F02
Figure 2. PMBus Packet Protocol Diagram Element Key
1
7
1
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
DATA BYTE
A
P
2974 F03
Figure 3. Write Byte Protocol
1
7
1
1
8
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
DATA BYTE LOW
A
DATA BYTE HIGH
A
P
2974 F04
Figure 4. Write Word Protocol
1
7
1
1
8
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
DATA BYTE
A
PEC
A
P
2974 F05
Figure 5. Write Byte Protocol with PEC
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LTC2974
OPERATION
1
7
1
1
8
1
8
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
DATA BYTE LOW
A
DATA BYTE HIGH
A
PEC
A
P
2974 F06
Figure 6. Write Word Protocol with PEC
1
7
1
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
P
2974 F07
Figure 7. Send Byte Protocol
1
7
1
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
PEC
A
P
2974 F08
Figure 8. Send Byte Protocol with PEC
1
7
1
1
8
1
1
7
1
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
Sr SLAVE ADDRESS Rd
A
DATA BYTE LOW
A
DATA BYTE HIGH
A
P
1 2974 F09
Figure 9. Read Word Protocol
1
7
1
1
8
1
1
7
1
1
8
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
Sr SLAVE ADDRESS Rd
A
DATA BYTE LOW
A
DATA BYTE HIGH
A
PEC
A
P
1 2974 F10
Figure 10. Read Word Protocol with PEC
1
7
1
1
8
1
1
7
1
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
Sr SLAVE ADDRESS Rd
A
DATA BYTE
A
P
1 2974 F11
Figure 11. Read Byte Protocol
1
7
1
1
8
1
1
7
1
1
8
1
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
Sr SLAVE ADDRESS Rd
A
DATA BYTE
A
PEC
A
P
1 2974 F12
Figure 12. Read Byte Protocol with PEC
1
7
1
1
8
1
1
7
1
1
8
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
Sr SLAVE ADDRESS Rd
A
BYTE COUNT = N
A
• • •
8
1
8
1
8
1
1
DATA BYTE 1
A
DATA BYTE 2
A
• • •
DATA BYTE N
A
P
1 2974 F13
Figure 13. Block Read
1
7
1
1
8
1
1
7
1
1
8
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
Sr SLAVE ADDRESS Rd
A
BYTE COUNT = N
A
• • •
8
1
8
1
8
1
8
1
1
DATA BYTE 1
A
DATA BYTE 2
A
• • •
DATA BYTE N
A
PEC
A
P
1 2974 F14
Figure 14. Block Read with PEC
2974fa
21
For more information www.linear.com/LTC2974
LTC2974
PMBUS COMMAND SUMMARY
Summary Table
DEFAULT
VALUE:
FLOAT
HEX
CMD
DATA
REF
PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM
PAGE
0x00 Channel or page currently selected for any R/W Byte
command that supports paging.
N
Y
Y
Reg
Reg
Reg
0x00
0x00
0x12
28
30
30
OPERATION
0x01 Operating mode control. On/Off, Margin
High and Margin Low.
R/W Byte
R/W Byte
Send Byte
Y
Y
ON_OFF_CONFIG
0x02 CONTROL pin and PMBus on/off
command setting.
CLEAR_FAULTS
0x03 Clear any fault bits that have been set.
Y
N
NA
61
28
WRITE_PROTECT
0x10 Level of protection provided by the device R/W Byte
against accidental changes.
Reg
Y
0x00
STORE_USER_ALL
RESTORE_USER_ALL
CAPABILITY
0x15 Store entire operating memory to
EEPROM.
Send Byte
Send Byte
R Byte
N
N
N
NA
NA
40
40
78
0x16 Restore entire operating memory from
EEPROM.
0x19 Summary of PMBus optional
communication protocols supported by
this device.
Reg
0xB0
VOUT_MODE
VOUT_COMMAND
VOUT_MAX
0x20 Output voltage data format and mantissa
R Byte
Y
Y
Y
Reg
L16
L16
0x13
44
44
44
–13
exponent (2 ).
0x21 Servo target. Nominal DC/DC converter
output voltage setpoint.
R/W Word
V
V
Y
Y
1.0
0x2000
0x24 Upper limit on the output voltage the unit R/W Word
can command regardless of any other
commands.
4.0
0x8000
VOUT_MARGIN_HIGH
VOUT_MARGIN_LOW
VIN_ON
0x25 Margin high DC/DC converter output
voltage setting.
R/W Word
R/W Word
R/W Word
R/W Word
Y
Y
N
N
L16
L16
L11
L11
V
V
V
V
Y
Y
Y
Y
1.05
44
44
43
43
0x219A
0x26 Margin low DC/DC converter output
voltage setting.
0.95
0x1E66
0x35 Input voltage (V
) above which
10.0
0xD280
IN_SNS
power conversion can be enabled.
VIN_OFF
0x36 Input voltage (V ) below which
9.0
0xD240
IN_SNS
power conversion is disabled. All V
OUT_EN
pins go off immediately or sequence off
after TOFF_DELAY (See Mfr_config_track_
enn).
IOUT_CAL_GAIN
0x38 The nominal resistance of the current
sense element in mΩ.
R/W Word
R/W Word
R/W Byte
R/W Word
R/W Word
R/W Word
Y
Y
Y
Y
Y
Y
L11
L16
Reg
L16
L16
L16
mΩ
V
Y
Y
Y
Y
Y
Y
1.0
46
44
54
44
44
44
0xBA00
VOUT_OV_FAULT_LIMIT
0x40 Output overvoltage fault limit.
1.1
0x2333
VOUT_OV_FAULT_RESPONSE 0x41 Action to be taken by the device when an
output overvoltage fault is detected.
0x80
VOUT_OV_WARN_LIMIT
VOUT_UV_WARN_LIMIT
VOUT_UV_FAULT_LIMIT
0x42 Output overvoltage warning limit.
V
V
V
1.075
0x2266
0x43 Output undervoltage warning limit.
0.925
0x1D9A
0x44 Output undervoltage fault limit. Used for
Ton_max_fault and power good de-
assertion.
0.9
0x1CCD
Note: The data format abbreviations are detailed at the end of this table
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For more information www.linear.com/LTC2974
LTC2974
PMBUS COMMAND SUMMARY
Summary Table
DEFAULT
VALUE:
FLOAT
HEX
CMD
DATA
REF
PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM
VOUT_UV_FAULT_RESPONSE 0x45 Action to be taken by the device when an
output undervoltage fault is detected.
R/W Byte
Y
Y
Y
Y
Y
Reg
L11
Reg
L11
L11
Y
Y
Y
Y
Y
0x7F
54
46
54
46
46
IOUT_OC_FAULT_LIMIT
IOUT_OC_FAULT_RESPONSE
IOUT_OC_WARN_LIMIT
IOUT_UC_FAULT_LIMIT
0x46 Output overcurrent fault limit.
R/W Word
R/W Byte
R/W Word
R/W Word
A
10.0
0xD280
0x47 Action to be taken by the device when an
output overcurrent fault is detected.
0x00
0x4A Output overcurrent warning limit.
A
A
5.0
0xCA80
0x4B Output undercurrent fault limit. Used to
detect a reverse current and must be a
negative value.
-1.0
0xBE00
IOUT_UC_FAULT_RESPONSE
OT_FAULT_LIMIT
0x4C Action to be taken by the device when an
output undercurrent fault is detected.
R/W Byte
Y
Y
Y
Reg
L11
Reg
Y
Y
Y
0x00
54
48
54
0x4F Overtemperature fault limit for the external R/W Word
temperature sensor.
°C
65.0
0xEA08
OT_FAULT_RESPONSE
0x50 Action to be taken by the device when an
overtemperature fault is detected on the
external temperature sensor.
R/W Byte
0xB8
OT_WARN_LIMIT
UT_WARN_LIMIT
UT_FAULT_LIMIT
UT_FAULT_RESPONSE
0x51 Overtemperature warning limit for the
external temperature sensor
R/W Word
R/W Word
R/W Word
R/W Byte
Y
Y
Y
Y
L11
L11
L11
Reg
°C
°C
°C
Y
Y
Y
Y
60.0
48
48
48
54
0xE3C0
0x52 Undertemperature warning limit for the
external temperature sensor.
0
0x8000
0x53 Undertemperature fault limit for the
external temperature sensor.
–5.0
0xCD80
0x54 Action to be taken by the device when an
undertemperature fault is detected on the
external temperature sensor.
0xB8
VIN_OV_FAULT_LIMIT
VIN_OV_FAULT_RESPONSE
VIN_OV_WARN_LIMIT
VIN_UV_WARN_LIMIT
VIN_UV_FAULT_LIMIT
VIN_UV_FAULT_RESPONSE
POWER_GOOD_ON
0x55 Input overvoltage fault limit measured at
VIN_SNS pin.
R/W Word
R/W Byte
N
N
N
N
N
N
Y
Y
L11
Reg
L11
L11
L11
Reg
L16
L16
V
Y
Y
Y
Y
Y
Y
Y
Y
15.0
43
54
43
43
43
54
44
44
0xD3C0
0x56 Action to be taken by the device when an
input overvoltage fault is detected.
0x80
0x57 Input overvoltage warning limit measured R/W Word
at VIN_SNS pin.
V
V
V
14.0
0xD380
0x58 Input undervoltage warning limit
measured at VIN_SNS pin.
R/W Word
0
0x8000
0x59 Input undervoltage fault limit measured at R/W Word
VIN_SNS pin.
0
0x8000
0x5A Action to be taken by the device when an
input undervoltage fault is detected.
R/W Byte
0x00
0x5E Output voltage at or above which a power R/W Word
good should be asserted.
V
V
0.96
0x1EB8
POWER_GOOD_OFF
0x5F Output voltage at or below which a power R/W Word
good should be de-asserted when Mfr_
0.94
0x1E14
config_all_pwrgd_off_uses_uv is clear.
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For more information www.linear.com/LTC2974
LTC2974
PMBUS COMMAND SUMMARY
Summary Table
DEFAULT
VALUE:
FLOAT
HEX
CMD
DATA
REF
PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM
TON_DELAY
0x60 Time from CONTROL pin and/or
OPERATION command = ON to V
pin = ON.
R/W Word
Y
L11
mS
Y
1.0
0xBA00
51
OUT_EN
TON_RISE
0x61 Time from when the V
pin goes
R/W Word
R/W Word
Y
L11
mS
Y
10.0
51
OUT_ENn
high until the LTC2974 optionally soft-
connects its DAC and begins to servo the
output voltage to the desired value.
0xD280
TON_MAX_FAULT_LIMIT
0x62 Maximum time from V
pin on
Y
L11
mS
mS
Y
15.0
0xD3C0
51
OUT_EN
assertion that an UV condition will be
tolerated before a TON_MAX_FAULT
condition results.
TON_MAX_FAULT_RESPONSE 0x63 Action to be taken by the device when a
TON_MAX_FAULT event is detected.
R/W Byte
Y
Y
Reg
L11
Y
Y
0xB8
54
51
TOFF_DELAY
0x64 Time from CONTROL pin and/or
OPERATION command = OFF to V
pin = OFF.
R/W Word
1.0
0xBA00
OUT_EN
STATUS_BYTE
0x78 One byte summary of the unit’s fault
condition.
R Byte
Y
Y
Reg
Reg
NA
NA
61
61
STATUS_WORD
0x79 Two byte summary of the unit’s fault
condition.
R Word
STATUS_VOUT
0x7A Output voltage fault and warning status.
0x7B Output current fault and warning status.
0x7C Input supply fault and warning status.
R Byte
R Byte
R Byte
R Byte
Y
Y
N
Y
Reg
Reg
Reg
Reg
NA
NA
NA
NA
61
61
61
61
STATUS_IOUT
STATUS_INPUT
STATUS_TEMPERATURE
0x7D External temperature fault and warning
status for READ_TEMPERATURE_1.
STATUS_CML
0x7E Communication and memory fault and
warning status.
R Byte
R Byte
N
Y
Reg
Reg
NA
NA
61
61
STATUS_MFR_SPECIFIC
0x80 Manufacturer specific fault and state
information.
READ_VIN
0x88 Input supply voltage.
R Word
R Word
R Word
R Word
N
Y
Y
Y
L11
L16
L11
L11
V
V
NA
NA
NA
NA
66
66
66
66
READ_VOUT
0x8B DC/DC converter output voltage.
0x8C DC/DC converter output current.
READ_IOUT
A
READ_TEMPERATURE_1
0x8D External diode junction temperature.
This is the value used for all temperature
related processing, including IOUT_CAL_
GAIN.
°C
READ_TEMPERATURE_2
READ_POUT
0x8E Internal junction temperature.
0x96 DC/DC converter output power.
R Word
R Word
R Byte
N
Y
N
L11
L11
Reg
°C
W
NA
NA
66
66
78
PMBUS_REVISION
0x98 PMBus revision supported by this device.
Current revision is 1.1.
0x11
USER_DATA_00
USER_DATA_01
USER_DATA_02
0xB0 Manufacturer reserved for LTpowerPlay.
0xB1 Manufacturer reserved for LTpowerPlay.
0xB2 OEM Reserved.
R/W Word
R/W Word
R/W Word
N
Y
N
Reg
Reg
Reg
Y
Y
Y
N/A
N/A
N/A
79
79
79
2974fa
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For more information www.linear.com/LTC2974
LTC2974
PMBUS COMMAND SUMMARY
Summary Table
DEFAULT
VALUE:
FLOAT
HEX
CMD
DATA
REF
PAGE
COMMAND NAME
USER_DATA_03
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM
0xB3 Scratchpad location.
0xB4 Scratchpad location.
0xB5 Manufacturer reserved.
R/W Word
R/W Word
R/W Word
R Word
Y
N
Y
Y
Reg
Reg
Reg
L11
Y
Y
Y
0x00
0x00
NA
79
79
79
48
USER_DATA_04
MFR_LTC_RESERVED_1
MFR_T_SELF_HEAT
0xB8 Calculated temperature rise due to
self-heating of output current sense
device above value measured by external
temperature sensor.
°C
NA
MFR_IOUT_CAL_GAIN_TAU_
INV
0xB9 Inverse of time constant for Mfr_t_self_
R/W Word
Y
Y
L11
L11
Y
Y
0.0
48
48
heat changes scaled by 4 • t
.
0x8000
CONV_SENSE
MFR_IOUT_CAL_GAIN_THETA 0xBA Thermal resistance from inductor core to R/W Word
°C/W
0.0
0x8000
point measured by external temperature
sensor.
MFR_READ_IOUT
0xBB Alternate data format for READ_IOUT. One R Word
LSB = 2.5mA.
Y
CF
2.5mA
NA
66
MFR_LTC_RESERVED_2
MFR_EE_UNLOCK
0xBC Manufacturer reserved.
R/W Word
R/W Byte
Y
N
Reg
Reg
NA
NA
79
40
0xBD Unlock user EEPROM for access by
MFR_EE_ERASE and MFR_EE_DATA
commands.
MFR_EE_ERASE
MFR_EE_DATA
0xBE Initialize user EEPROM for bulk
programming by MFR_EE_DATA.
R/W Byte
N
N
Reg
Reg
NA
NA
40
40
0xBF Data transferred to and from EEPROM
using sequential PMBus word reads or
writes. Supports bulk programming.
R/W Word
MFR_CONFIG_LTC2974
0xD0 Configuration bits that are channel
specific.
R/W Word
Y
N
Y
Reg
Reg
Reg
Y
Y
Y
0x0080
0x0F7B
0x00
30
30
59
MFR_CONFIG_ALL_LTC2974
MFR_FAULTB0_PROPAGATE
0xD1 Configuration bits that are common to all R/W Word
pages.
0xD2 Configuration that determines if a
channels faulted off state is propagated to
the FAULTB0 pin.
R/W Byte
R/W Byte
R/W Word
MFR_FAULTB1_PROPAGATE
MFR_PWRGD_EN
0xD3 Configuration that determines if a
channels faulted off state is propagated to
the FAULTB1 pin.
Y
N
Reg
Reg
Y
Y
0x00
59
52
0xD4 Configuration that maps WDI/RESETB
status and individual channel power good
to the PWRGD pin.
0x0000
MFR_FAULTB0_RESPONSE
MFR_FAULTB1_RESPONSE
0xD5 Action to be taken by the device when the R/W Byte
FAULTB0 pin is asserted low.
N
N
Reg
Reg
Y
Y
0x00
0x00
59
59
0xD6 Action to be taken by the device when the R/W Byte
FAULTB1 pin is asserted low.
MFR_IOUT_PEAK
0xD7 Maximum measured value of READ_IOUT.
0xD8 Minimum measured value of READ_IOUT.
R Word
R Word
Y
Y
N
L11
L11
Reg
A
A
NA
NA
66
66
30
MFR_IOUT_MIN
MFR_CONFIG2_LTC2974
0xD9 Configuration bits that are channel
specific
R/W Byte
Y
0x00
2974fa
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For more information www.linear.com/LTC2974
LTC2974
PMBUS COMMAND SUMMARY
Summary Table
DEFAULT
VALUE:
FLOAT
HEX
CMD
DATA
REF
PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM
MFR_CONFIG3_LTC2974
0xDA Configuration bits that are channel
specific
R/W Byte
N
N
N
Reg
L11
L11
Y
Y
Y
0x00
30
54
51
MFR_RETRY_DELAY
0xDB Retry interval during FAULT retry mode.
R/W Word
R/W Word
mS
mS
200
0xF320
MFR_RESTART_DELAY
0xDC Delay from actual CONTROL active edge
to virtual CONTROL active edge.
400
0xFB20
MFR_VOUT_PEAK
MFR_VIN_PEAK
0xDD Maximum measured value of READ_VOUT. R Word
Y
N
Y
L16
L11
L11
V
V
NA
NA
NA
66
66
66
0xDE Maximum measured value of READ_VIN.
R Word
R Word
MFR_TEMPERATURE_1_PEAK 0xDF Maximum measured value of READ_
TEMPERATURE_1.
°C
MFR_DAC
0xE0 Manufacturer register that contains the
code of the 10-bit DAC.
R/W Word
R/W Word
R/W Word
R/W Word
R/W Byte
Y
N
N
N
N
Reg
L11
L11
L11
Reg
N
Y
Y
Y
Y
0x0000
44
52
52
52
28
MFR_POWERGOOD_
ASSERTION_DELAY
0xE1 Power-good output assertion delay.
0xE2 First watchdog timer interval.
0xE3 Watchdog timer interval.
mS
mS
mS
100
0xEB20
MFR_WATCHDOG_T_FIRST
0
0x8000
MFR_WATCHDOG_T
0
0x8000
MFR_PAGE_FF_MASK
0xE4 Configuration defining which channels
respond to global page commands
(PAGE=0xFF).
0xF
MFR_PADS
0xE5 Current state of selected digital I/O pads. R/W Word
N
N
Reg
Reg
NA
61
28
2
MFR_I2C_BASE_ADDRESS
0xE6 Base value of the I C/SMBus address
byte.
R/W Byte
R Word
R Byte
Y
Y
Y
0x5C
MFR_SPECIAL_ID
MFR_SPECIAL_LOT
0xE7 Manufacturer code for identifying the
LTC2974.
N
Y
Reg
Reg
0x0213
78
78
0xE8 Customer dependent codes that
identify the factory programmed user
configuration stored in EEPROM. Contact
factory for default value.
MFR_VOUT_DISCHARGE_
THRESHOLD
0xE9 Coefficient used to multiply VOUT_
R/W Word
Y
L11
Y
2.0
0xC200
44
COMMAND in order to determine V
threshold voltage.
off
OUT
MFR_FAULT_LOG_STORE
0xEA Command a transfer of the fault log from Send Byte
RAM to EEPROM.
N
N
NA
NA
70
70
MFR_FAULT_LOG_RESTORE
0xEB Command a transfer of the fault log
previously stored in EEPROM back to
RAM.
Send Byte
MFR_FAULT_LOG_CLEAR
0xEC Initialize the EEPROM block reserved for
fault logging and clear any previous fault
logging locks.
Send Byte
N
NA
70
MFR_FAULT_LOG_STATUS
MFR_FAULT_LOG
0xED Fault logging status.
R Byte
N
N
Reg
Reg
Y
Y
NA
NA
70
70
0xEE Fault log data bytes. This sequentially
retrieved data is used to assemble a
complete fault log.
R Block
2974fa
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For more information www.linear.com/LTC2974
LTC2974
PMBUS COMMAND SUMMARY
Summary Table
DEFAULT
VALUE:
FLOAT
HEX
CMD
DATA
REF
PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM
MFR_COMMON
0xEF Manufacturer status bits that are common
across multiple LTC chips.
R Byte
N
Y
N
Y
Y
Y
Reg
CF
NA
61
46
54
48
48
66
MFR_IOUT_CAL_GAIN_TC
MFR_RETRY_COUNT
MFR_TEMP_1_GAIN
0xF6 Temperature coefficient applied to IOUT_ R/W Word
CAL_GAIN.
ppm
Y
Y
Y
Y
0x0
0xF7 Retry count for all faulted off conditions
that enable retry.
R/W Byte
Reg
CF
0x00
0xF8 Inverse of external diode temperature non R/W Word
1
–14
ideality factor. One LSB = 2
.
0x4000
MFR_TEMP_1_OFFSET
0xF9 Offset value for the external temperature. R/W Word
L11
CF
°C
0
0x8000
MFR_IOUT_SENSE_VOLTAGE 0xFA Absolute value of V
One LSB = 3.05µV.
– V
.
R Word
3.05µV
NA
ISENSEP
ISENSEM
MFR_VOUT_MIN
MFR_VIN_MIN
0xFB Minimum measured value of READ_VOUT. R Word
Y
N
Y
L16
L11
L11
V
V
NA
NA
NA
66
66
66
0xFC Minimum measured value of READ_VIN.
R Word
R Word
MFR_TEMPERATURE_1_MIN 0xFD Minimum measured value of READ_
TEMPERATURE_1.
°C
Data Formats
L11
Linear_5s_11s PMBus data field b[15:0]
N
Value = Y • 2
where N = b[15:11] is a 5-bit two’s complement integer and Y = b[10:0] is an 11-bit two’s complement integer
Example:
READ_VIN = 10V
For b[15:0] = 0xD280 = 1101_0010_1000_0000b
–6
Value = 640 • 2 = 10
See PMBus Spec Part II: Paragraph 7.1
L16
Linear_16u
Register
PMBus data field b[15:0]
N
Value = Y • 2 where Y = b[15:0] is an unsigned integer and N = Vout_mode_parameter is a 5-bit two’s complement exponent
that is hardwired to –13 decimal.
Example:
VOUT_COMMAND = 4.75V
For b[15:0] = 0x9800 = 1001_1000_0000_0000b
–13
Value = 38912 • 2 = 4.75
See PMBus Spec Part II: Paragraph 8.3.1
Reg
CF
PMBus data field b[15:0] or b[7:0].
Bit field meaning is defined in detailed PMBus Command Register Description.
Custom Format PMBus data field b[15:0]
Value is defined in detailed PMBus Command Register Description. This is often an unsigned or two’s complement integer
scaled by an MFR specific constant.
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For more information www.linear.com/LTC2974
LTC2974
PMBUS COMMAND DESCRIPTION
ADDRESSING AND WRITE PROTECT
CMD
DEFAULT REF
PAGED FORMAT UNITS EEPROM VALUE PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGE
0x00 Channel or page currently selected for any R/W Byte
command that supports paging.
N
Reg
0x00
0x00
28
28
WRITE_PROTECT
0x10 Level of protection provided by the device
against accidental changes.
R/W Byte
N
Reg
Y
2
MFR_I2C_BASE_ADDRESS
MFR_PAGE_FF_MASK
0xE6 Base value of the I C/SMBus address byte. R/W Byte
N
N
Reg
Reg
Y
Y
0x5C
0xF
29
29
0xE4 Configuration defining which channels
respond to global page commands
(PAGE=0xFF).
R/W Byte
PAGE
The LTC2974 has four pages that correspond to the four DC/DC converter channels that can be managed. Each DC/DC
converter channel can be uniquely programmed by first setting the appropriate page.
Setting PAGE = 0xFF allows a simultaneous write to all pages for PMBus commands that support global page pro-
gramming. The only commands that support PAGE = 0xFF are CLEAR_FAULTS, OPERATION and ON_OFF_CONFIG.
See MFR_PAGE_FF_MASK for additional options. Reading any paged PMBus register with PAGE = 0xFF returns un-
predictable data and will trigger a CML fault. Writes to pages that do not support PAGE = 0xFF with PAGE = 0xFF will
be ignored and generate a CML fault.
PAGE Data Contents
BIT(S) SYMBOL OPERATION
b[7:0] Page
Page operation.
0x00: All PMBus commands address channel/page 0.
0x01: All PMBus commands address channel/page 1.
0x02: All PMBus commands address channel/page 2.
0x03: All PMBus commands address channel/page 3.
0xXX: All non specified values reserved.
0xFF: A single PMBus write/send to commands that support this mode will simultaneously address all channel/pages with
MFR_PAGE_FF_MASK enabled.
WRITE_PROTECT
The WRITE_PROTECT command provides protection against accidental programming of the LTC2974 command reg-
isters. All supported commands may have their parameters read, regardless of the WRITE_PROTECT setting, and the
EEPROM contents can also be read regardless of the WRITE_PROTECT settings.
There are two levels of protection:
• Level 1: Nothing can be changed except the level of write protection itself. Values can be read from all pages. This
setting can be stored to EEPROM.
• Level 2: Nothing can be changed except for the level of protection, channel on/off state, and clearing of faults. Values
can be read from all pages. This setting can be stored to EEPROM.
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LTC2974
PMBUS COMMAND DESCRIPTION
WRITE_PROTECT Data Contents
BIT(S) SYMBOL
OPERATION
b[7:0] Write_protect[7:0] 1000_0000b: Level 1 Protection - Disable all writes except to the WRITE_PROTECT, PAGE, MFR_EE_UNLOCK, and STORE_
USER_ALL commands.
0100_0000b: Level 2 Protection – Disable all writes except to the WRITE_PROTECT, PAGE, MFR_EE_UNLOCK, STORE_
USER_ALL, OPERATION, MFR_PAGE_FF_MASK and CLEAR_FAULTS commands.
0000_0000b: Enable writes to all commands.
xxxx_xxxxb: All other values reserved.
WRITE-PROTECT Pin
The WP pin allows the user to write-protect the LTC2974’s configuration registers. The WP pin is active high, and when
asserted it provides Level 2 protection: all writes are disabled except to the WRITE_PROTECT, PAGE, MFR_EE_UNLOCK,
STORE_USER_ALL, OPERATION, MFR_PAGE_FF_MASK and CLEAR_FAULTS commands. The most restrictive setting
between the WP pin and WRITE_PROTECT command will override. For example if WP = 1 and WRITE_PROTECT =
0x80, then the WRITE_PROTECT command overrides, since it is the most restrictive.
MFR_PAGE_FF_MASK
The MFR_PAGE_FF_MASK command is used to select which channels respond when the global page command
(PAGE=0xFF) is in use.
MFR_PAGE_FF_MASK Data Contents
BIT(S) SYMBOL
OPERATION
b[7:4] Reserved
Always returns 0000b
b[3] Mfr_page_ff_mask_chan3
Channel 3 masking of global page command (PAGE=0xFF) accesses
0 = ignore global page command accesses
1 = fully respond to global page command accesses
Channel 2 masking of global page command (PAGE=0xFF) accesses
0 = ignore global page command accesses
b[2] Mfr_page_ff_mask_chan2
b[1] Mfr_page_ff_mask_chan1
b[0] Mfr_page_ff_mask_chan0
1 = fully respond to global page command accesses
Channel 1 masking of global page command (PAGE=0xFF) accesses
0 = ignore global page command accesses
1 = fully respond to global page command accesses
Channel 0 masking of global page command (PAGE=0xFF) accesses
0 = ignore global page command accesses
1 = fully respond to global page command accesses
MFR_I2C_BASE_ADDRESS
2
The MFR_I2C_BASE_ADDRESS command determines the base value for the I C/SMBus address byte. Offsets of 0 to
2
9 are added to this base address to generate the device I C/SMBus address. The part responds to the device address.
MFR_I2C_BASE_ADDRESS Data Contents
BIT(S) SYMBOL
OPERATION
b[7] Reserved
Read only, always returns 0.
2
b[6:0] i2c_base_address This 7-bit value determines the base value of the 7-bit I C/SMBus address. See Operation Section: Device Address.
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LTC2974
PMBUS COMMAND DESCRIPTION
ON/OFF CONTROL, MARGINING AND CONFIGURATION
CMD
DEFAULT REF
PAGED FORMAT UNITS EEPROM VALUE PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
OPERATION
0x01 Operating mode control. On/Off, Margin
High and Margin Low.
R/W Byte
Y
Y
Y
N
N
N
Reg
Reg
Reg
Reg
Reg
Reg
Y
Y
Y
Y
Y
Y
0x00
0x12
30
31
32
35
35
39
ON_OFF_CONFIG
0x02 CONTROL pin and PMBus on/off
command setting.
R/W Byte
R/W Word
R/W Byte
R/W Byte
MFR_CONFIG_LTC2974
MFR_CONFIG2_LTC2974
MFR_CONFIG3_LTC2974
MFR_CONFIG_ALL_LTC2974
0xD0 Configuration bits that are channel
specific.
0x0080
0x00
0xD9 Configuration bits that are channel
specific
0xDA Configuration bits that are channel
specific
0x00
0xD1 Configuration bits that are common to all R/W Word
pages.
0x0F7B
OPERATION
The OPERATION command is used to turn the unit on and off in conjunction with the CONTROL pin and ON_OFF_CON-
FIG. This command register responds to the global page command (PAGE=0xFF). The contents and functions of the
data byte are shown in the following tables. A minimum t
wait time must be observed between any OPERATION
OFF_MIN
commands used to turn the unit off and then back on to give the ADC telemetry loop time to complete a full cycle.
OPERATION Data Contents (On_off_config_use_pmbus=1)
SYMBOL
BITS
Action
Operation_control[1:0] Operation_margin[1:0]
Operation_fault[1:0]
Reserved (read only)
b[7:6]
00
b[5:4]
XX
b[3:2]
XX
b[1:0]
00
Turn off immediately
Sequence on
10
00
XX
00
Margin low (ignore faults and
warnings)
10
01
01
00
Margin low
10
10
01
10
10
01
00
00
Margin high (ignore faults and
warnings
Margin high
10
01
10
00
10
00
00
FUNCTION
Sequence off with margin to
nominal
XX
Sequence off with margin low
(ignore faults and warnings)
01
01
01
00
Sequence off with margin low
01
01
01
10
10
01
00
00
Sequence off with margin high
(ignore faults and warnings)
Sequence off with margin high
Reserved
01
10
10
00
All remaining combinations
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LTC2974
PMBUS COMMAND DESCRIPTION
OPERATION Data Contents (On_off_config_use_pmbus=0)
On or Off
SYMBOL
BITS
Action
Operation_control[1:0] Operation_margin[1:0]
Operation_fault[1:0]
Reserved (read only)
b[7:6]
b[5:4]
00
b[3:2]
XX
b[1:0]
00
Output at nominal
00, 01 or 10
00, 01 or 10
Margin low (ignore faults and
warnings)
01
01
00
Margin low
00, 01 or 10
00, 01 or 10
01
10
10
01
00
00
FUNCTION
Margin high (ignore faults and
warnings
Margin high
Reserved
00, 01 or 10
10
10
00
All remaining combinations
ON_OFF_CONFIG
The ON_OFF_CONFIG command configures the combination of CONTROL pin input and PMBus commands needed
to turn the LTC2974 on/off, including the power-on behavior, as shown in the following table. This command register
responds to the global page command (PAGE=0xFF). After the part has initialized, an additional comparator monitors
VIN_SNS. The VIN_ON threshold must be exceeded before the output power sequencing can begin. After V is initially
IN
applied, the part will typically require t
and currents may require an additional wait for tUPDATE_ADC. A minimum t
any CONTROL pin toggle used to turn the unit off and then back on.
time to initialize and begin the TON_DELAY timer. The readback of voltages
INIT
wait time must be observed for
OFF_MIN
ON_OFF_CONFIG Data Contents
BIT(S) SYMBOL
OPERATION
b[7:5] Reserved
Don’t care. Always returns 0.
Control default autonomous power up operation.
b[4] On_off_config_controlled_on
0: Unit powers up regardless of the CONTROL pin or OPERATION value. Unit always powers up with
sequencing. To turn unit on without sequencing, set TON_DELAY = 0.
1: Unit does not power up unless commanded by the CONTROL pin and/or the OPERATION command on the
serial bus. If On_off_config[3:2] = 00, the unit never powers up.
b[3] On_off_config_use_pmbus
b[2] On_off_config_use_control
b[1] Reserved
Controls how the unit responds to commands received via the serial bus.
0: Unit ignores the Operation_control[1:0].
1: Unit responds to Operation_control[1:0]. Depending on On_off_config_use_control, the unit may also
require the CONTROL pin to be asserted for the unit to start.
Controls how unit responds to the CONTROL pin.
0: Unit ignores the CONTROL pin.
1: Unit requires the CONTROL pin to be asserted to start the unit. Depending on On_off_config_use_pmbus
the OPERATION command may also be required to instruct the device to start.
Not supported. Always returns 1.
b[0] On_off_config_control_fast_off CONTROL pin turn off action when commanding the unit to turn off
0: Use the programmed TOFF_DELAY.
1: Turn off the output and stop transferring energy as quickly as possible. The device does not sink current in
order to decrease the output voltage fall time.
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LTC2974
PMBUS COMMAND DESCRIPTION
MFR_CONFIG_LTC2974
This command is used to configure various manufacturer specific operating parameters for each channel.
MFR_CONFIG_LTC2974 Data Contents
BIT(S) SYMBOL
OPERATION
b[15] Reserved
Don’t care. Always returns 0.
b[14] Mfr_config_cascade_on
Configures channel’s control pin for cascade sequence ON. There is no provision for cascade sequence
OFF. See description for time based sequence OFF options.
b[13:12] Mfr_config_controln_sel[1:0]
Selects the active control pin input (CONTROL0 , CONTROL1, CONTROL2 or CONTROL3) for this channel.
0: Select CONTROL0 pin.
1: Select CONTROL1 pin.
2: Select CONTROL2 pin.
3: Select CONTROL3 pin.
b[11] Mfr_config_fast_servo_off
Disables fast servo when margining or trimming output voltages:
0: fast-servo enabled.
1: fast-servo disabled.
b[10] Mfr_config_supervisor_resolution Selects voltage supervisor resolution:
0: high resolution = 4mV / LSB, range for V
– V
is 0 to 3.8V
is 0 to 6.0V
VSENSEPn
VSENSEMn
1: low resolution = 8mV / LSB, range for V
Always returns 0.
– V
VSENSEMn
VSENSEPn
b[9:8] Reserved
b[7]
Mfr_config_servo_continuous
Select whether the UNIT should continuously servo VOUT after it has reached a new margin or nominal
target. Only applies when Mfr_ config _dac_mode = 00b.
0: Do not continuously servo VOUT after reaching initial target.
1: Continuously servo VOUT to target.
b[6]
Mfr_config_servo_on_warn
Control re-servo on warning feature. Only applies when Mfr_config_dac_mode = 00b and Mfr_config_
servo_continuous = 0.
0: Do not allow the unit to re-servo when a VOUT warning threshold is met or exceeded.
1: Allow the unit to re-servo VOUT to nominal target if
VOUT ≥ V(Vout_ov_warn_limit) or
VOUT ≤ V(Vout_uv_warn_limit).
b[5:4] Mfr_config_dac_mode
Determines how DAC is used when channel is in the ON state and TON_RISE has elapsed.
00: Soft-connect (if needed) and servo to target.
01: DAC not connected.
10: DAC connected immediately using value from MFR_DAC command. If this is the configuration after a
reset or RESTORE_USER_ALL, MFR_DAC will be undefined and must be written to desired value.
11: DAC is soft-connected. After soft-connect is complete MFR_DAC may be written.
b[3]
b[2]
Mfr_config_vo_en_wpu_en
Mfr_config_vo_en_wpd_en
V
pin charge-pumped, current-limited pull-up enable.
OUT_EN
0: Disable weak pull-up. V
pin driver is three-stated when channel is on.
OUT_EN
1: Use weak current-limited pull-up on V
pin when the channel is on.
OUT_EN
V
pin current-limited pull-down enable.
OUT_EN
0: Use a fast N-channel device to pull down V
pin when the channel is off for any reason.
OUT_EN
1: Use weak current-limited pull-down to discharge V
pin when channel is off due to soft stop by
OUT_EN
the CONTROL pin and/or OPERATION command. If the channel is off due to a fault, use the fast pull-down
on the V pin.
OUT_EN
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LTC2974
PMBUS COMMAND DESCRIPTION
MFR_CONFIG_LTC2974 Data Contents
BIT(S) SYMBOL
OPERATION
b[1]
Mfr_config_dac_gain
DAC buffer gain.
0: Select DAC buffer gain dac_gain_0 (1.38V full-scale)
1: Select DAC buffer gain dac_gain_1 (2.65V full-scale)
DAC output polarity.
b[0]
Mfr_config_ dac_pol
0: Encodes negative (inverting) DC/DC converter trim input.
1: Encodes positive (non-inverting) DC/DC converter trim input.
Cascade Sequence ON with Time-Based Sequence OFF
Cascade sequence ON allows a master power supply to sequence on a series of slave supplies by connecting each
power supply’s power good output to the control pin of the next power supply in the chain. Please note that the power
good signal is that of the power supply and not derived from the LTC2974’s internal power good processing. Power
good based cascade sequence OFF is not supported, OFF sequencing must be managed using immediate or time based
sequence OFF. See also “Tracking Based Sequencing”.
Cascade sequence ON is illustrated in Figure 15. For each slave channel Mfr_config_cascade_on is asserted high and
the associated control input is connected to the power good output of the previous power supply. In this configuration
each slave channel’s startup is delayed until the previous supply has powered up.
Cascade sequence OFF is not directly supported. Options for reversing the sequence when turning the supplies off
include:
• Using the OPERATION command to turn off all the channels with an appropriate off delay.
• Using the FAULT pin to bring all the channels down immediately or in sequence with an appropriate off delay.
When asserted, Mfr_config_cascade_on enables a slave channel to honor fault retries even when its control pin is
low. Additionally, if the system has faulted off after zero or a finite number of retries, an OPERATION command may
CONTROL0
LTC2974
FAULTB0
CONTROL0
FAULTB0
RUN
V
V
SENSEP0
V
OUTP
OUT_EN0
RECOMMENDED CONNECTION
WHEN HARDWARE ON/OFF
CONTROL IS REQUIRED
DC/DC
LOAD
V
MASTER
POWERGOOD0
V
V
V
V
CONTROL1
OUTM
SENSEM0
RUN
V
V
SENSEP1
V
OUTP
OUT_EN1
DC/DC
LOAD
V
POWERGOOD1
CONTROL2
OUTM
SENSEM1
RUN
V
V
SENSEP2
V
OUTP
OUT_EN2
DC/DC
LOAD
V
SLAVES
POWERGOOD2
CONTROL3
OUTM
SENSEM2
RUN
V
V
V
OUTP
SENSEP3
LOAD
OUT_EN3
DC/DC
POWERGOOD3
V
SENSEM3
OUTM
TO NEXT CONTROL PIN
2974 F15
Figure 15. LTC2974 Configured to Cascade Sequence ON and Time-Base Sequence OFF
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LTC2974
PMBUS COMMAND DESCRIPTION
be used to turn all cascade channels off then on to clear the faulted off state when the slave’s control pin is low. For
this reason we refer to the control pin as being redefined as a sequence pin.
The waveform of Figure 16 illustrates cascade sequence ON and time based sequence OFF using the configuration
illustrated in Figure 15. In this example the FAULTB0 pin is used as a broadcast off signal. Turning the system off with
the FAULTB0 requires all slave channels to be configured with Mfr_faultb0_response_chann asserted high. After the
system is turned off, the LTC2974 will assert ALERTB with all slave channels indicating a Status_mfr_fault0_in event.
TOFF_DELAY3
TOFF_DELAY2
TOFF_DELAY1
TOFF_DELAY0
V
V
V
OUT0
OUT1
OUT2
V
OUT3
CONTROL-FAULTB0
POWERGOOD0
POWERGOOD1
POWERGOOD2
POWERGOOD3
2974 F16
Figure 16. Cascade Sequence ON with Time Based Sequence Down on FAULT0
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LTC2974
PMBUS COMMAND DESCRIPTION
MFR_CONFIG2_LTC2974
This command register determines whether V
AUXFAULTB pin to be pulled low.
overvoltage or overcurrent faults from a given channel cause the
OUT
MFR_CONFIG2_LTC2974 Data Contents
BIT(S) SYMBOL
OPERATION
b[7] Mfr_auxfaultb_oc_fault_response_ Response to channel 3 IOUT_OC_FAULT.
chan3
1 = Pull AUXFAULTB low via fast pull-down.
0 = Do not pull AUXFAULTB low.
b[6] Mfr_auxfaultb_oc_fault_response_ Response to channel 2 IOUT_OC_FAULT.
chan2
1 = Pull AUXFAULTB low via fast pull-down.
0 = Do not pull AUXFAULTB low.
b[5] Mfr_auxfaultb_oc_fault_response_ Response to channel 1 IOUT_OC_FAULT.
chan1
1 = Pull AUXFAULTB low via fast pull-down.
0 = Do not pull AUXFAULTB low.
b[4] Mfr_auxfaultb_oc_fault_response_ Response to channel 0 IOUT_OC_FAULT.
chan0
1 = Pull AUXFAULTB low via fast pull-down.
0 = Do not pull AUXFAULTB low.
b[3] Mfr_auxfaultb_ov_fault_response_ Response to channel 3 VOUT_OV_FAULT.
chan3
1 = Pull AUXFAULTB low via fast pull-down.
0 = Do not pull AUXFAULTB low.
b[2] Mfr_auxfaultb_ov_fault_response_ Response to channel 2 VOUT_OV_FAULT.
chan2
1 = Pull AUXFAULTB low via fast pull-down.
0 = Do not pull AUXFAULTB low.
b[1] Mfr_auxfaultb_ov_fault_response_ Response to channel 1 VOUT_OV_FAULT.
chan1
1 = Pull AUXFAULTB low via fast pull-down.
0 = Do not pull AUXFAULTB low.
b[0] Mfr_auxfaultb_ov_fault_response_ Response to channel 0 VOUT_OV_FAULT.
chan0
1 = Pull AUXFAULTB low via fast pull-down.
0 = Do not pull AUXFAULTB low.
MFR_CONFIG3_LTC2974
This command register determines whether V
undercurrent faults from a given channel cause the AUXFAULTB pin
OUT
to be pulled low. This command also allows tracking to be enabled on any channel.
MFR_CONFIG3_LTC2974 Data Contents
BIT(S) SYMBOL
OPERATION
b[7] Mfr_auxfaultb_uc_fault_response_ Response to channel 3 IOUT_UC_FAULT.
chan3
1 = Pull AUXFAULTB low via fast pull-down.
0 = Do not pull AUXFAULTB low.
b[6] Mfr_auxfaultb_uc_fault_response_ Response to channel 2 IOUT_UC_FAULT.
chan2
1 = Pull AUXFAULTB low via fast pull-down.
0 = Do not pull AUXFAULTB low.
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LTC2974
PMBUS COMMAND DESCRIPTION
b[5] Mfr_auxfaultb_uc_fault_response_ Response to channel 1 IOUT_UC_FAULT.
chan1
1 = Pull AUXFAULTB low via fast pull-down.
0 = Do not pull AUXFAULTB low.
b[4] Mfr_auxfaultb_uc_fault_response_ Response to channel 0 IOUT_UC_FAULT.
chan0
1 = Pull AUXFAULTB low via fast pull-down.
0 = Do not pull AUXFAULTB low.
b[3] Mfr_track_en_chan3
b[2] Mfr_track_en_chan2
b[1] Mfr_track_en_chan1
b[0] Mfr_track_en_chan0
Select if channel 3 is a slave in a tracked power supply system.
0: Channel is not a slave in a tracked power supply system.
1: Channel is a slave in a tracked power supply system.
Select if channel 2 is a slave in a tracked power supply system.
0: Channel is not a slave in a tracked power supply system.
1: Channel is a slave in a tracked power supply system.
Select if channel 1 is a slave in a tracked power supply system.
0: Channel is not a slave in a tracked power supply system.
1: Channel is a slave in a tracked power supply system.
Select if channel 0 is a slave in a tracked power supply system.
0: Channel is not a slave in a tracked power supply system.
1: Channel is a slave in a tracked power supply system.
LTC2974
CONTROL0
FAULTB0
CONTROL0
FAULTB0
RUN
V
V
SENSEP0
V
V
V
V
OUTP
OUT_EN0
V
V
DC/DC
DC/DC
DC/DC
DC/DC
LOAD
FB
DAC0
TRACK
V
V
V
V
V
OUTM
SENSEM0
RUN
V
V
OUTP
SENSEP1
OUT_EN1
V
V
LOAD
FB
DAC1
TRACK
V
OUTM
SENSEM1
R1_1
R1_2
R1_3
R2_1
R2_2
R2_3
RUN
V
V
OUTP
SENSEP2
OUT_EN2
V
V
LOAD
FB
DAC2
TRACK
V
OUTM
SENSEM2
RUN
V
V
OUTP
SENSEP3
OUT_EN3
V
V
LOAD
FB
DAC3
TRACK
V
SENSEM3
OUTM
2974 F17
Figure 17. LTC2974 Configured to Control, Supervise and Monitor Power Supplies Equipped with Tracking Pin
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LTC2974
PMBUS COMMAND DESCRIPTION
Tracking Supplies On and Off
The LTC2974 supports tracking power supplies that are equipped with a tracking pin and configured for tracking.
A tracking power supply uses a secondary feedback terminal (TRACK) to allow its output voltage to be scaled to an
external master voltage. Typically the external voltage is generated by the supply with the highest voltage in the sys-
tem, which is fed to the slave track pins (see Figure 17). Supplies that track a master supply must be enabled before
the master supply comes up and disabled after the master supply comes down. Enabling the slave supplies when the
master is down requires supervisors monitoring the slaves to disable UV detection. Slave UC detection must also be
TON_RISE EXPIRES
TOFF_DELAY ENTERED
FOR ALL CHANNELS.
UV AND UC DETECT DISABLED
ON ALL CHANNELS
FOR ALL CHANNELS.
UV AND UC DETECT ENABLED
ON ALL CHANNELS
V
V
V
V
OUT0
OUT1
OUT2
MASTER BRINGS DOWN
NEXT HIGHEST SLAVE
OUT3
CONTROL
VOUT_EN0
VOUT_EN(3:1)
2974 F18
SLAVE OUTPUT ENABLES TURN ON FIRST
SLAVE OUTPUT ENABLES TURN OFF LAST
Figure 18. Control Pin Tracking All Supplies Up And Down
TON_RISE EXPIRES
TOFF_DELAY ENTERED
FOR ALL CHANNELS.
UV AND UC DETECT DISABLED
ON ALL CHANNELS
FOR ALL CHANNELS.
UV AND UC DETECT ENABLED
ON ALL CHANNELS
V
V
V
V
OUT0
OUT1
OUT2
OUT3
UV FAULT ON CHANNEL 1 BRINGS DOWN MASTER
VIA FAULTB0. ALL SLAVE CHANNELS INCLUDING
THE ONE WITH THE UV FAULT ENTER TOFF_DELAY
MASTER BRINGS DOWN
NEXT HIGHEST SLAVE
CONTROL
FAULTB0
VOUT_EN0
VOUT_EN(3:1)
2974 F19
SLAVE OUTPUT ENABLES TURN ON FIRST
SLAVE OUTPUT ENABLES TURN OFF LAST
Figure 19. Fault on Channel 1 Tracking All Supplies Down
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LTC2974
PMBUS COMMAND DESCRIPTION
TON_RISE EXPIRES
TOFF_DELAY ENTERED
FOR ALL CHANNELS.
UV AND UC DETECT DISABLED
ON ALL CHANNELS
FOR ALL CHANNELS.
UV AND UC DETECT ENABLED
ON ALL CHANNELS
UV FAULT ON CHANNEL 1 BRINGS DOWN MASTER
VIA FAULTB0. ALL SLAVES WITH ENABLED RUN
PINS TRACK DOWN CORRECTLY
V
V
V
V
OUT0
OUT1
OUT2
OUT3
DISABLING VOUT_EN1
IMMEDIATELY IN RESPONSE
TO THE UV FAULT CAUSES
VOUT1 TO SHUT DOWN
OUT OF SEQUENCE
CONTROL
FAULTB0
VOUT_EN0
VOUT_EN1
VOUT_EN(3:2)
2974 F20
SLAVE OUTPUT ENABLES TURN ON FIRST
SLAVE OUTPUT ENABLES TURN OFF LAST
Figure 20. Improperly Configured Fault Response on Faulting Channel Disrupts Tracking
disabled when the slaves are tracking the master down to prevent false UC events. All channels configured for track-
ing must track off together in response to a fault on any channel or any other condition that can bring one or more of
the channels down. Prematurely disabling a slave channel via its RUN pin may cause that channel to shut down out
of sequence (see Figure 20)
An important feature of the LTC2974 is the ability to control, monitor and supervise DC/DC converters that are config-
ured to track a master supply on and off.
The LTC2974 supports the following tracking features:
• Track channels on and off without issuing false UV/UC events when the slave channels are tracking up or down.
• Track all channels down in response to a fault from a slave or master.
• Track all channels down when VIN_SNS drops below VIN_OFF, share clock is held low or Restore_user_all is issued.
• Ability to to reconfigure selected channels that are part of a tracking group to sequence up after the group has
tracked up or sequence down before the group has tracked down.
Tracking Implementation
The LTC2974 supports tracking through the coordinated programing of Ton_delay, Ton_rise,Toff_delay and Mfr_track_
en_chann. The master channel must be configured to turn on after all the slave channels have turned on and to turn
off before all the slave channels turn off. Slaves that are enabled before the master will remain off until the tracking pin
allows them to turn on. Slaves will be turned off via the tracking pin even though their run pin is still asserted. Ton_rise
must be extended on the slaves so that it ends relative to the rise of the TRACK pin and not the rise of the V
pin.
OUT_EN
When Mfr_track_en_chann is enabled the channel is reconfigured to:
• Sequence down on fault, VIN_OFF, SHARE_CLK low or RESTORE_USER_ALL.
• Ignore UV and UC during TOFF_DELAY. Note that ignoring UV and UC during TON_RISE and TON_MAX_FAULT
always happens regardless of how this bit is set.
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LTC2974
PMBUS COMMAND DESCRIPTION
The following example illustrates configuring an LTC2974 with one master channel and three slaves.
Master channel 0
TON_DELAY = Ton_delay_master
TON_RISE = Ton_rise_master
TOFF_DELAY = Toff_delay_master
Mfr_track_en_chan0 = 0
Slave channel n
TON_DELAY = Ton_delay_slave
TON_RISE = Ton_delay_master + Ton_rise_slave
TOFF_DELAY = Toff_delay_master + T_off_delay_slave
Mfr_track_en_chan0 = 1
Where:
Ton_delay_master – Ton_delay_slave > RUN to TRACK setup time
Toff_delay_slave > time for master supply to fall.
The system response to a control pin toggle is illustrated in Figure 18.
The system response to a UV fault on a slave channel is illustrated in Figure 19.
MFR_CONFIG_ALL_LTC2974
This command is used to configure parameters that are common to all channels on the IC. They may be set or reviewed
from any PAGE setting.
MFR_CONFIG_ALL_LTC2974 Data Contents
BIT(S) SYMBOL
OPERATION
b[15:12] Reserved
Don’t care. Always returns 0.
Selects PWRGD de-assertion source for all channels.
b[11] Mfr_config_all_pwrgd_off_uses_uv
0: PWRGD is de-asserted based on V
being below or equal to POWER_GOOD_OFF. This option
OUT
uses the ADC. Response time is approximately 100ms to 200ms.
1: PWRGD is de-asserted based on V
being below or equal to VOUT_UV_LIMIT. This option uses
OUT
the high speed supervisor. Response time is approximately 12µs.
b[10] Mfr_config_all_fast_fault_log
Controls number of ADC readings completed before transferring fault log memory to EEPROM.
0: All ADC telemetry values will be updated before transferring fault log to EEPROM. Slower.
1: Telemetry values will be transferred from fault log to EEPROM within 24ms after detecting fault.
Faster.
b[9]
b[8]
Mfr_config_all_control3_pol
Mfr_config_all_control2_pol
Selects active polarity of CONTROL3 pin
0: Active low (pull pin low to start unit).
1: Active high (pull pin high to start unit).
Selects active polarity of CONTROL2 pin
0: Active low (pull pin low to start unit).
1: Active high (pull pin high to start unit).
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PMBUS COMMAND DESCRIPTION
MFR_CONFIG_ALL_LTC2974 Data Contents
BIT(S) SYMBOL
OPERATION
b[7]
b[6]
b[5]
b[4]
b[3]
Mfr_config_all_fault_log_enable
Enable fault logging to EEPROM in response to Fault.
0: Fault logging to EEPROM is disabled.
1: Fault logging to EEPROM is enabled.
Mfr_config_all_vin_on_clr_faults_en
Mfr_config_all_control1_pol
Allow V rising above VIN_ON to clear all latched faults.
IN
0: VIN_ON clear faults feature is disabled.
1: VIN_ON clear faults feature is enabled.
Selects active polarity of CONTROL1 pin
0: Active low (pull pin low to start unit).
1: Active high (pull pin high to start unit).
Selects active polarity of CONTROL0 pin
0: Active low (pull pin low to start unit).
1: Active high (pull pin high to start unit).
Mfr_config_all_control0_pol
Mfr_config_all_vin_share_enable
Allow this unit to hold SHARE_CLK pin low when V has not risen above VIN_ON or has fallen
IN
below VIN_OFF. When enabled this unit will also turn all channels off in response to Share-clock
being held low.
0: SHARE_CLK inhibit is disabled.
1: SHARE_CLK inhibit is enabled.
PMBus packet error checking enable.
0: PEC is accepted but not required.
1: PEC is enabled.
b[2]
b[1]
b[0]
Mfr_config_all_pec_en
Mfr_config_all_longer_pmbus_timeout Increase PMBus timeout interval by a factor of 8. Recommended for fault logging.
0: PMBus timeout is multiplied by a factor of 8.
1: PMBus timeout is not multiplied by a factor of 8.
Mfr_config_all_auxfaultb_wpu_dis
AUXFAULTB charge-pumped, current-limited pull-up disable.
0: Use weak current-limited pull-up on AUXFAULTB after power-up, as long as no faults have forced
AUXFAULTB off.
1: Disable weak pull-up. AUXFAULTB driver is tri-stated after power-up as long as no faults have
forced AUXFAULTB off.
PROGRAMMING USER EEPROM SPACE
CMD
DEFAULT REF
PAGED FORMAT UNITS EEPROM VALUE PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
STORE_USER_ALL
0x15 Store entire operating memory to
EEPROM.
Send Byte
N
N
N
NA
NA
NA
41
41
41
RESTORE_USER_ALL
MFR_EE_UNLOCK
0x16 Restore entire operating memory from
EEPROM.
Send Byte
R/W Byte
0xBD Unlock user EEPROM for access by
MFR_EE_ERASE and MFR_EE_DATA
commands.
Reg
MFR_EE_ERASE
MFR_EE_DATA
0xBE Initialize user EEPROM for bulk
programming by MFR_EE_DATA.
R/W Byte
N
N
Reg
Reg
NA
NA
42
42
0xBF Data transferred to and from EEPROM
using sequential PMBus word reads or
writes. Supports bulk programming.
R/W Word
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PMBUS COMMAND DESCRIPTION
STORE_USER_ALL and RESTORE_USER_ALL
STORE_USER_ALL, RESTORE_USER_ALL commands provide access to User EEPROM space. Once a command is
stored in User EEPROM, it will be restored with explicit restore command or when the part emerges from power-on
reset after power is applied. While either of these commands is being processed, the part will indicate it is busy, see
Response When Part Is Busy on page 43.
STORE_USER_ALL. Issuing this command will store all operating memory commands with a corresponding EEPROM
memory location.
RESTORE_USER_ALL. Issuing this command will restore all commands from EEPROM Memory. It is recommended
that this command not be executed while a unit is enabled since all monitoring is suspended while the EEPROM is
transferred to operating memory, and intermediate values from EEPROM may not be compatible with the values initially
stored in operating memory.
Bulk Programming the User EEPROM Space
The MFR_EE_UNLOCK, MFR_EE_ERASE and MFR_EE_DATA commands provide a method for 3rd party EEPROM
programming houses and end users to easily program the LTC2974 independent of any order dependencies or delays
between PMBus commands. All data transfers are directly to and from the EEPROM and do not affect the volatile RAM
space currently configuring the device.
Thefirststepistoprogramamasterreferencepartwiththedesiredconfiguration.MFR_EE_UNLOCKandMFR_EE_DATA
are then used to read back all the data in User EEPROM space as sequential words. This information is stored to the
master programming HEX file. Subsequent parts may be cloned to match the master part using MFR_EE_UNLOCK,
MFR_EE_ERASE and MFR_EE_DATA to transfer data from the master HEX file. These commands operate directly on
the EEPROM independent of the part configurations stored in RAM space. During EEPROM access the part will indicate
that it is busy as described below.
In order to support simple programming fixtures the bulk programming features only uses PMBus word and byte com-
mands. The MFR_UNLOCK configures the appropriate access mode and resets an internal address pointer allowing
a series of word commands to behave as a block read or write with the address pointer being incremented after each
operation. PEC use is optional and is configured by the MFR_EE_UNLOCK operation.
MFR_EE_UNLOCK
The MFR_EE_UNLOCK command prevents accidental EEPROM access in normal operation and configures the required
EEPROM bulk programming mode for bulk initialization, sequential writes, or reads. MFR_EE_UNLOCK augments the
protection provided by write protect. Upon unlocking the part for the required operation, an internal address pointer is
reset allowing a series of MFR_EE_DATA reads or writes to sequentially transfer data, similar to a block read or block
write. The MFR_EE_UNLOCK command can clear or set PEC mode based on the desired level of error protection. An
MFR_EE_UNLOCK sequence consists of writing two unlock codes using two byte-write commands. The following
table documents the allowed sequences. Writing a non-supported sequence locks the part. Reading MFR_EE_UNLOCK
returns the last byte written or zero if the part is locked.
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PMBUS COMMAND DESCRIPTION
MFR_EE_UNLOCK Data Contents
BIT(S) SYMBOL
OPERATION
b[7:0] Mfr_ee_unlock[7:0] To unlock user EEPROM space for Mfr_ee_erase and Mfr_ee_data read or write operations with PEC allowed:
Write 0x2b followed by 0xd4.
To unlock user EEPROM space for Mfr_ee_erase and Mfr_ee_data read or write operations with PEC required:
Write 0x2b followed by 0xd5.
To unlock user and manufacturer EEPROM space for Mfr_ee_data read only operations with PEC allowed:
Write 0x2b, followed by 0x91 followed by 0xe4.
To unlock user and manufacturer EEPROM space for Mfr_ee_data read only operations with PEC required:
Write 0x2b, followed by 0x91 followed by 0xe5.
MFR_EE_ERASE
The MFR_EE_ERASE command is used to erase the entire contents of the user EEPROM space and configures this
space to accept new program data. Writing values other than 0x2B will lock the part. Reads return the last value written.
MFR_EE_ERASE Data contents
BIT(S) SYMBOL
b[7:0] Mfr_ee_erase[7:0] To erase the user EEPROM space and configure to accept new data:
1) Use the appropriate Mfr_ee_unlock sequence to configure for Mfr_ee_erase commands with or without PEC.
OPERATION
2) Write 0x2B to Mfr_ee_erase.
The part will indicate it is busy erasing the EEPROM by the mechanism detailed below.
MFR_EE_DATA
The MFR_EE_DATA command allows the user to transfer data directly to or from the EEPROM without affecting RAM
space.
To read the user EEPROM space issue the appropriate Mfr_ee_unlock command and perform Mfr_ee_data reads until
the EEPROM has been completely read. Extra reads will lock the part and return zero. The first read returns the 16-bit
EEPROM packing revision ID that is stored in ROM. The second read returns the number of 16-bit words available;
this is the number of reads or writes to access all memory locations. Subsequent reads return EEPROM data starting
with lowest address.
To write to the user EEPROM space issue the appropriate Mfr_ee_unlock and Mfr_ee_erase commands followed by
successive Mfr_ee_data word writes until the EEPROM is full. Extra writes will lock the part. The first write is to the
lowest address.
Mfr_ee_data reads and writes must not be mixed.
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PMBUS COMMAND DESCRIPTION
MFR_EE_DATA Data Contents
BIT(S) SYMBOL
b[7:0] Mfr_ee_data[7:0] To read user space
1) Use the appropriate Mfr_ee_unlock sequence to configure for Mfr_ee_data commands with or without PEC.
OPERATION
2) Read Mfr_ee_data[0] = PackingId (MFR Specific ID).
3) Read Mfr_ee_data[1] = NumberOfUserWords (total number of 16-bit word available).
4) Read Mfr_ee_data[2] through Mfr_ee_data[NumberOfWord+1] (User EEPROM data contents)
To write user space
1) Initialize the user memory using the sequence described for the MFR_EE_ERASE command.
2) Use the appropriate Mfr_ee_unlock sequence to configure for Mfr_ee_data commands with or without PEC.
3) Write Mfr_ee_data[0] through Mfr_ee_data[NumberOfWord-1] (User EEPROM data content to be wriiten)
The part will indicate it is busy erasing the EEPROM by the mechanism detailed below.
Response When Part Is Busy
The part will indicate it is busy accessing the EEPROM by the following mechanism:
1) Clearing Mfr_common_busyb of the MFR_COMMON register. This byte can always be read and will never NACK a
byte read request even if the part is busy.
2) NACKing commands other than MFR_COMMON.
MFR_EE Erase and Write Programming Time
2
The program time per word is typically 0.17ms and will require spacing the I C/SMBus writes at greater than 0.17ms
to guarantee the write has completed. The Mfr_ee_erase command takes approximately 400ms. We recommend using
MFR_COMMON for handshaking.
INPUT VOLTAGE COMMANDS AND LIMITS
CMD
DEFAULT REF
PAGED FORMAT UNITS EEPROM VALUE PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
VIN_ON
0x35 Input voltage (VIN_SNS) above which power
conversion can be enabled.
R/W Word
N
L11
V
Y
10.0
0xD280
43
VIN_OFF
0x36 Input voltage (VIN_SNS) below which power
R/W Word
N
L11
V
Y
9.0
0xD240
43
conversion is disab
ll VOUT_EN pins go
led. A
off immediately or sequence off after TOFF_
DELAY (See Mfr_config_track_enn).
VIN_OV_FAULT_LIMIT
VIN_OV_WARN_LIMIT
VIN_UV_WARN_LIMIT
VIN_UV_FAULT_LIMIT
0x55 Input overvoltage fault limit measured at
VIN_SNS pin.
R/W Word
R/W Word
N
N
N
N
L11
L11
L11
L11
V
V
V
V
Y
Y
Y
Y
15.0
43
43
43
43
0xD3C0
0x57 Input overvoltage warning limit measured at
VIN_SNS pin.
14.0
0xD380
0x58 Input undervoltage warning limit measured at R/W Word
VIN_SNS pin.
0
0x8000
0x59 Input undervoltage fault limit measured at
VIN_SNS pin.
R/W Word
0
0x8000
VIN_ON, VIN_OFF, VIN_OV_FAULT_LIMIT, VIN_OV_WARN_LIMIT, VIN_UV_WARN_LIMIT and
VIN_UV_FAULT_LIMIT
These commands provide voltage supervising limits for the input voltage V
.
IN_SNS
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PMBUS COMMAND DESCRIPTION
OUTPUT VOLTAGE COMMANDS AND LIMITS
CMD
DEFAULT REF
PAGED FORMAT UNITS EEPROM VALUE PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
VOUT_MODE
0x20 Output voltage data format and mantissa
R Byte
Y
Y
Y
Reg
L16
L16
0x13
44
45
45
13)
exponent (2–
.
VOUT_COMMAND
VOUT_MAX
0x21 Servo target. Nominal DC/DC converter
output voltage setpoint.
R/W Word
R/W Word
V
V
Y
Y
1.0
0x2000
0x24 Upper limit on the output voltage the unit
can command regardless of any other
commands.
4.0
0x8000
VOUT_MARGIN_HIGH
VOUT_MARGIN_LOW
VOUT_OV_FAULT_LIMIT
VOUT_OV_WARN_LIMIT
VOUT_UV_WARN_LIMIT
VOUT_UV_FAULT_LIMIT
0x25 Margin high DC/DC converter output voltage R/W Word
setting.
Y
Y
Y
Y
Y
Y
L16
L16
L16
L16
L16
L16
V
V
V
V
V
V
Y
Y
Y
Y
Y
Y
1.05
45
45
45
45
45
45
0x219A
0x26 Margin low DC/DC converter output voltage R/W Word
setting.
0.95
0x1E66
0x40 Output overvoltage fault limit.
0x42 Output overvoltage warning limit.
0x43 Output undervoltage warning limit.
R/W Word
R/W Word
R/W Word
R/W Word
1.1
0x2333
1.075
0x2266
0.925
0x1D9A
0x44 Output undervoltage fault limit. Used for
Ton_max_fault and power good de-
assertion.
0.9
0x1CCD
POWER_GOOD_ON
POWER_GOOD_OFF
0x5E Output voltage at or above which a power
good should be asserted.
R/W Word
R/W Word
Y
Y
L16
L16
V
V
Y
Y
0.96
45
45
0x1EB8
0x5F Output voltage at or below which a power
good should be de-asserted when Mfr_
config_all_pwrgd_off_uses_uv is clear.
0.94
0x1E14
MFR_VOUT_DISCHARGE_ 0xE9 Coefficient used to multiply VOUT_
R/W Word
Y
Y
L11
Reg
Y
N
2.0
45
45
THRESHOLD
COMMAND in order to determine V
threshold voltage.
off
0xC200
OUT
MFR_DAC
0xE0 Manufacturer register that contains the code R/W Word
of the 10-bit DAC.
0x0000
VOUT_MODE
This command is read only and specifies the mode and exponent for all commands with a L16 data format. See
Data Formats on page 27.
VOUT_MODE Data Contents
BIT(S) SYMBOL
OPERATION
b[7:5] Vout_mode_type
Reports linear mode. Hard-wired to 000b.
b[4:0] Vout_mode_parameter Linear mode exponent. 5-bit two’s complement integer. Hardwired to 0x13 (–13 decimal).
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PMBUS COMMAND DESCRIPTION
VOUT_COMMAND, VOUT_MAX, VOUT_MARGIN_HIGH, VOUT_MARGIN_LOW, VOUT_OV_FAULT_LIMIT,
VOUT_OV_WARN_LIMIT, VOUT_UV_WARN_LIMIT, VOUT_UV_FAULT_LIMIT, POWER_GOOD_ON and
POWER_GOOD_OFF
These commands provide various servo, margining and supervising limits for a channel’s output voltage.
MFR_VOUT_DISCHARGE_THRESHOLD
This register contains the coefficient that multiplies VOUT_COMMAND in order to determine the OFF threshold volt-
age for the associated output. If the output voltage has not decayed below MFR_VOUT_DISCHARGE_THRESHOLD •
VOUT_COMMAND prior to the channel being commanded to enter/re-enter the ON state, the Status_mfr_discharge bit
in the STATUS_MFR_SPECIFIC register will be set and the ALERTB pin will be asserted low. In addition, the channel
will not enter the ON state until the output has decayed below its off-threshold voltage. Setting this to a value greater
than 1.0 effectively disables DISCHARGE_THRESHOLD checking, allowing the channel to turn back on even if it has
not decayed at all.
Other channels can be held-off if a particular output has failed to discharge by using the bidirectional FAULTBn pins
(refer to the MFR_FAULTBn_RESPONSE and MFR_FAULTBn_PROPOGATE registers).
MFR_DAC
This command register allows the user to directly program the 10-bit DAC. Manual DAC writes require the channel
to be in the ON state,TON_RISE to have expired and MFR_CONFIG_LTC2974 b[5:4] = 10b or 11b. Writing MFR_
CONFIG_LTC2974 b[5:4] = 10b commands the DAC to hard connect with the value in Mfr_dac_direct_val. Writing
b[5:4] = 11b commands the DAC to soft-connect. Once the DAC has soft-connected, Mfr_dac_direct_val returns the
value that allowed the DAC to be connected without perturbing the power supply. MFR_DAC writes are ignored when
MFR_CONFIG_LTC2974 b[5:4] = 00b or 01b.
MFR_DAC Data Contents
BIT(S) SYMBOL
OPERATION
b[15:10] Reserved
Read only, always returns 0.
b[9:0] Mfr_dac_direct_val DAC code value.
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PMBUS COMMAND DESCRIPTION
OUTPUT CURRENT COMMANDS AND LIMITS
CMD
DEFAULT REF
PAGED FORMAT UNITS EEPROM VALUE PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
IOUT_CAL_GAIN
0x38 The nominal resistance of the current sense R/W Word
element in mΩ.
Y
Y
Y
Y
L11
L11
L11
L11
mΩ
Y
Y
Y
Y
1.0
46
47
47
47
0xBA00
IOUT_OC_FAULT_LIMIT
IOUT_OC_WARN_LIMIT
IOUT_UC_FAULT_LIMIT
0x46 Output overcurrent fault limit.
R/W Word
R/W Word
R/W Word
A
10.0
0xD280
0x4A Output overcurrent warning limit.
A
5.0
0xCA80
0x4B Output undercurrent fault limit. Used to
detect a reverse current and must be a
negative value.
A
-1.0
0xBE00
MFR_IOUT_CAL_GAIN_TC 0xF6 Temperature coefficient applied to IOUT_
CAL_GAIN.
R/W Word
Y
CF
ppm
Y
0x0
47
IOUT_CAL_GAIN
The IOUT_CAL_GAIN command is used to set the ratio of the voltage at the current sense pins to the sensed current.
For devices using a fixed current sense resistor, it is the same value as the resistance of the resistor (units are expressed
in mΩ). IOUT_CAL_GAIN is internally limited to values between 0.01mΩ to 1,000mΩ. The register readback value
always returns what was last written and does not reflect internal limiting.
Calculations using IOUT_CAL_GAIN are:
V
V
= IOUT_OC_FAULT_LIMIT • IOUT_CAL_GAIN • T
= IOUT_UC_FAULT_LIMIT • IOUT_CAL_GAIN • T
IOUT_OC_FAULT_LIMIT
IOUT_UC_FAULT_LIMIT
CORRECTION
CORRECTION
Where:
T
= (1 + MFR_IOUT_CAL_GAIN_TC • 1E-6 • (READ_TEMPERATURE_1 + MFR_T_SELF_HEAT – 25.0))
CORRECTION
V
IOUT _ SNSPn – V
IOUT _ SNSMn
READ_IOUT =
(IOUT_CAL_GAIN)• TCORRECTION
Note:
T
is limited by hardware to a value between 0.25 and 4.0.
CORRECTION
READ_TEMPERATURE_2 is substituted for READ_TEMPERATURE_1 if the associated T
a valid temperature. See READ_TEMPERATURE_1 for more information.
network fails to detect
SENSE
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PMBUS COMMAND DESCRIPTION
IOUT_OC_FAULT_LIMIT, IOUT_OC_WARN_LIMIT and IOUT_UC_FAULT_LIMIT
I
supervisor fault and warning limits.
OUT
IOUT_OC_FAULT_LIMITED is internally limited to values greater or equal to zero. The register readback value always
returns what was last written and does not reflect internal limiting.
IOUT_UC_FAULT_LIMITED is internally limited to values less than zero. The register readback value always returns
what was last written and does not reflect internal limiting.
MFR_IOUT_CAL_GAIN_TC
The MFR_IOUT_CAL_GAIN_TC is a paged command that sets the temperature coefficient of the IOUT_CAL_GAIN
register value in ppm/°C. This command uses the temperature measured by the external temperature diode for the
associated page.
Refer to IOUT_CAL_GAIN for details on proper usage.
MFR_IOUT_CAL_GAIN_TC Data Contents
BIT(S) SYMBOL
OPERATION
b[15:0] Mfr_iout_cal_gain_tc 16-bit twos complement integer representing the temperature coefficient.
Value = Y where Y = b[15:0] is a twos complement.
Example:
Mfr_iout_cal_gain_tc = 3900ppm
For b[15:0] = 0x0F3C
Value = 3900
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PMBUS COMMAND DESCRIPTION
EXTERNAL TEMPERATURE COMMANDS AND LIMITS
CMD
DEFAULT REF
PAGED FORMAT UNITS EEPROM VALUE PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
OT_FAULT_LIMIT
0x4F Overtemperature fault limit setting for R/W Word
the external temperature sensor.
Y
Y
Y
Y
Y
Y
Y
L11
L11
L11
L11
CF
°C
°C
°C
°C
Y
Y
Y
Y
Y
Y
65.0
48
48
48
48
48
48
49
0xEA08
OT_WARN_LIMIT
UT_WARN_LIMIT
UT_FAULT_LIMIT
0x51 Overtemperature warning limit for the R/W Word
external temperature sensor
60.0
0xE3C0
0x52 Undertemperature warning limit for
the external temperature sensor.
R/W Word
0
0x8000
0x53 Undertemperature fault limit for the
external temperature sensor.
R/W Word
–5.0
0xCD80
MFR_TEMP_1_GAIN
MFR_TEMP_1_OFFSET
MFR_T_SELF_HEAT
0xF8 Inverse of external diode temperature R/W Word
1
–14
non ideality factor. One LSB = 2
.
0x4000
0xF9 Offset value for the external
temperature.
R/W Word
R Word
L11
L11
°C
°C
0
0x8000
0xB8 Calculated temperature rise due to
NA
self-heating of output current sense
device above value measured by
external temperature sensor.
MFR_IOUT_CAL_GAIN_TAU_INV
MFR_IOUT_CAL_GAIN_THETA
0xB9 Inverse of time constant for Mfr_t_
self_heat changes scaled by 4 •
tCONV_SENSE.
R/W Word
R/W Word
Y
Y
L11
L11
Y
Y
0.0
49
49
0x8000
0xBA Thermal resistance from inductor
core to point measured by external
temperature sensor.
°C/W
0.0
0x8000
OT_FAULT_LIMIT, OT_WARN_LIMIT, UT_WARN_LIMIT and UT_FAULT_LIMIT
These commands provide supervising limits for temperature as measured by the external diode.
MFR_TEMP_1_GAIN and MFR_TEMP_1_OFFSET
The MFR_TEMP_1_GAIN command specifies the inverse of the temperature sensor ideality factor. The MFR_TEMP_1_
OFFSET allows an offset to be applied to the measured temperature.
Calculations using these paged commands are:
READ_TEMPERATURE_1 = T • MFR_TEMP_1_GAIN – 273.15 + MFR_TEMP_1_OFFSET
EXT
Where:
T
EXT
= Measured external temperature in degrees Kelvin.
READ_TEMPERATURE_2 is substituted for READ_TEMPERATURE_1 if the associated T
network fails to detect
SENSE
a valid temperature. Under these conditions MFR_TEMP1_GAIN and MFR_TEMP1_OFFSET will have no effect. See
READ_TEMPERATURE_1 for more information.
MFR_TEMP_1_GAIN Data Contents
BIT(S) SYMBOL
OPERATION
14
b[15:0] Mfr_temp_1_gain[15:0]
16-bit integer representing inverse of temperature non-ideality factor. Value = Y • 2 where Y = b[15:0] is an
unsigned integer. Example:
MFR_TEMP_1_GAIN = 1.0
For b[15:0] = 0x4000
–14
Value = 16384 • 2 = 1.0
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PMBUS COMMAND DESCRIPTION
MFR_T_SELF_HEAT, MFR_IOUT_CAL_GAIN_TAU_INV and MFR_IOUT_CAL_GAIN_THETA
The LTC2974 uses an innovative (patent pending) algorithm to dynamically model the temperature rise from the external
temperature sensor to the inductor core. This temperature rise is called MFR_T_SELF_HEAT and is used to calculate the
final temperature correction required by IOUT_CAL_GAIN. The temperature rise is a function of the power dissipated
in the inductor DCR, the thermal resistance from the inductor core to the remote temperature sensor and the thermal
time constant of the inductor to board system. The algorithm simplifies the placement requirements for the external
temperature sensor and compensates for the significant steady state and transient temperature error from the inductor
core to the primary inductor heat sink.
P = CURRENT REPRESENTING THE POWER DISSIPATED BY THE INDUCTOR
I
(V
DCR
• READ_IOUT WHERE V
= (V
– V
ISENSM
))
DCR
ISENSEP
I = P
I
C = CAPACITANCE REPRESENTING THERMAL HEAT CAPACITY OF THE INDUCTOR
τ
V = T
I
I
(INCLUDED IN MFR_IOUT_CAL_GAIN_TAU_INV)
T = VOLTAGE REPRESENTING THE TEMPERATURE OF THE INDUCTOR
I
R = θ
C = C
IS
τ
θ
IS
= RESISTANCE REPRESENTING THE THERMAL RESISTANCE FROM THE DCR
TO THE REMOTE TEMPERATURE SENSOR (MFR_IOUT_CAL_GAIN_THETA)
T
=
VOLTAGE REPRESENTING THE TEMPERATURE AT THE REMOTE
TEMPERATURE SENSOR
V
= T
S
S
S
2974 F21
Figure 21. Electronic Analogy for Inductor Temperature Model
The best way to understand the self-heating effect inside the inductor is to model the system using the circuit analogy
of Figure 21. The 1st order differential equation for the above model may be approximated by the following difference
equation:
P – T /θ = C ∆T /∆t (Eq1) (when T = 0)
I
I
IS
τ
I
S
from which:
∆T = ∆t (P θ – T )/(θ C ) (Eq2) or
I
I
IS
I
IS
τ
∆T = (P θ – T ) • τ (Eq3)
I
I
IS
I
INV
where
τ
= ∆t/(θ C ) (Eq4)
IS τ
INV
and ∆t is the sample period of the external temperature ADC.
The LTC2974 implements the self-heating algorithm using Eq3 and Eq4 where:
∆T =∆MFR_T_SELF_HEAT
I
P = READ_IOUT • (V
– V
)
I
ISENSEP
ISENSEM
T = READ_TEMPERATURE_1
S
T = MFR_T_SELF_HEAT + T
I
S
∆t = 4 • t . (One complete external temperature loop period)
CONV_SENSE
τ
= MFR_IOUT_CAL_GAIN_TAU_INV
INV
ꢀ θ = MFR_IOUT_CAL_GAIN_THETA
IS
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LTC2974
PMBUS COMMAND DESCRIPTION
Initially self heat is set to zero. After each temperature measurement self heat is updated to be the previous value of
self heat incremented or decremented by ∆MFR_T_SELF_HEAT.
The actual value of C is not required. The important quantity is the thermal time constant τ = (θ C ). For example,
τ
INV
IS τ
if an inductor has a thermal time constant τ = 5 seconds then:
INV
MFR_IOUT_CAL_GAIN_TAU_INV = (4 • t )/5 = 4 • 66ms/5s = 0.0528
CONV_SENSE
Refer to the application section for more information on calibrating θ and τ
.
IS
INV
READ_TEMPERATURE_2 is substituted for READ_TEMPERATURE_1 if the associated T
network fails to detect
SENSE
a valid temperature. Under these conditions T = READ_TEMPERATURE_2 and the self-heating correction is applied
S
using the internal die temperature. See READ_TEMPERATURE_1 for more information.
MFR_T_SELF_HEAT Data Content
Bit(s) Symbol
Operation
b[15:0] Mfr_t_self_heat
Values are limited to the range 0°C to 50°C.
MFR_IOUT_CAL_GAIN_THETA Data Content
Bit(s) Symbol
Operation
Values ≤ 0 set MFR_T_SELF_HEAT to zero.
b[15:0] Mfr_iout_cal_gain_theta
MFR_IOUT_CAL_GAIN_TAU_INV Data Content
Bit(s) Symbol
Operation
b[15:0] Mfr_iout_cal_gain_tau_inv
Values ≤ 0 set MFR_T_SELF_HEAT to zero.
Values ≥ 1 set MFR_T_SELF_HEAT to MFR_IOUT_CAL_GAIN_THETA • READ_IOUT • (V
– V
).
ISENSEP
ISENSEM
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LTC2974
PMBUS COMMAND DESCRIPTION
SEQUENCING TIMING LIMITS AND CLOCK SHARING
CMD
DEFAULT REF
PAGED FORMAT UNITS EEPROM VALUE PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
TON_DELAY
0x60 Time from CONTROL pin and/or OPERATION
R/W Word
Y
L11
mS
Y
1.0
51
51
command = ON to V
pin = ON.
0xBA00
OUT_EN
TON_RISE
0x61 Time from when the V
pin goes high
R/W Word
Y
L11
mS
Y
10.0
0xD280
OUT_ENn
until the LTC2974 optionally soft-connects its
DAC and begins to servo the output voltage to
the desired value.
TON_MAX_FAULT_LIMIT 0x62 Maximum time from V
pin on assertion R/W Word
Y
L11
mS
Y
15.0
0xD3C0
51
OUT_EN
that an UV condition will be tolerated before a
TON_MAX_FAULT condition results.
TOFF_DELAY
0x64 Time from CONTROL pin and/or OPERATION
R/W Word
R/W Word
Y
N
L11
L11
mS
mS
Y
Y
1.0
51
51
command = OFF to V
pin = OFF.
0xBA00
OUT_EN
MFR_RESTART_DELAY
0xDC Delay from actual CONTROL active edge to
virtual CONTROL active edge.
400
0xFB20
TON_DELAY, TON_RISE, TON_MAX_FAULT_LIMIT and TOFF_DELAY
These commands share the same format and provide sequencing and timer fault and warning delays in ms.
TON_DELAY sets the amount of time in milliseconds that a channel waits following the start of an ON sequence before
its V pin enables a DC/DC converter. This delay is counted using SHARE_CLK only.
OUT_EN
TON_RISE sets the amount of time in ms that elapses after the power supply has been enabled until the LTC2974’s
DAC soft-connects and servos the output voltage to the desired level if Mfr_dac_mode = 00b. This delay is counted
using SHARE_CLK only.
TON_MAX_FAULT_LIMIT is the maximum amount of time that the power supply being controlled by the LTC2974 can
attempt to power up the output without reaching the VOUT_UV_FAULT_LIMIT. If it does not, then a TON_MAX_FAULT
is declared. If the output reaches VOUT_UV_FAULT_LIMIT prior to TON_MAX_FAULT_LIMIT, the LTC2974 unmasks the
VOUT_UV_FAULT_LIMIT threshold. (Note that a value of zero means there is no limit to how long the power supply
can attempt to bring up its output voltage.) This delay is counted using SHARE_CLK only.
TOFF_DELAY is the amount of time that elapses after the CONTROL pin and/or OPERATION command is de-asserted
until the channel is disabled (soft-off). This delay is counted using SHARE_CLK if available, otherwise the internal
oscillator is used.
All of the above TON and TOFF delays are internally limited to 655ms, and rounded to the nearest 10µs. The read value
of these commands always returns what was last written and does not reflect internal limiting.
MFR_RESTART_DELAY
This command essentially sets the off time of a CONTROL pin initiated restart. If the CONTROL pin is toggled off for at
least 10µs then on, all dependent channels are disabled, held off for a time = Mfr_restart_delay, then sequenced back
on. CONTROL pin transitions whose OFF time exceeds Mfr_restart_delay are not affected by this command. A value
of all zeros disables this feature. This delay is counted using SHARE_CLK only.
This delay is internally limited to 13.1 seconds, and rounded to the nearest 200µs. The read value of this command
always returns what was last written and does not reflect internal limiting.
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LTC2974
PMBUS COMMAND DESCRIPTION
Clock Sharing
Multiple LTC PMBus devices can synchronize their clocks in an application by connecting together the open-drain
SHARE_CLK input/outputs to a pull-up resistor as a wired OR. In this case the fastest clock will take over and syn-
chronize all other chips to its falling edge.
SHARE_CLK can optionally be used to synchronize ON/OFF dependency on V across multiple chips by setting the
IN
Mfr_config_all_vin_share_enable bit of the MFR_CONFIG_ALL register. When configured this way the chip will hold
SHARE_CLK low when the unit is off for insufficient input voltage, and upon detecting that SHARE_CLK is held low
the chip will disable all channels after a brief deglitch period. When the SHARE_CLK pin is allowed to rise, the chip
will respond by beginning a start sequence. In this case the slowest VIN_ON detection will take over and synchronize
other chips to its start sequence.
WATCHDOG TIMER AND POWER GOOD
CMD
DEFAULT REF
PAGED FORMAT UNITS EEPROM VALUE PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
MFR_PWRGD_EN
0xD4 Configuration that maps WDI/
RESETB status and individual
channel power good to the
PWRGD pin.
R/W Word
N
Reg
Y
0x0000
52
MFR_POWERGOOD_ASSERTION_DELAY 0xE1 Power-good output assertion
delay.
R/W Word
R/W Word
R/W Word
N
N
N
L11
L11
L11
mS
mS
mS
Y
Y
Y
100
53
53
53
0xEB20
MFR_WATCHDOG_T_FIRST
0xE2 First watchdog timer interval.
0
0x8000
MFR_WATCHDOG_T
0xE3 Watchdog timer interval.
0
0x8000
MFR_PWRGD_EN
This command register controls the mapping of the watchdog and channel power good status to the PWRGD pin.
MFR_PWRGD_EN Data Contents
BIT(S) SYMBOL
OPERATION
b[15:9] Reserved
Read only, always returns 0s.
b[8] Mfr_pwrgd_en_wdog Watchdog.
1 = Watchdog timer not-expired status is ANDed with PWRGD status for any similarly enabled channels to determine
when the PWRGD pin gets asserted.
0 = Watchdog timer does not affect the PWRGD pin.
Always returns 0000b.
b[7:4] Reserved
b[3] Mfr_pwrgd_en_chan3 Channel 3.
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine when
the PWRGD pin gets asserted.
0 = PWRGD status for this channel does not affect the PWRGD pin.
b[2] Mfr_pwrgd_en_chan2 Channel 2.
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine when
the PWRGD pin gets asserted.
0 = PWRGD status for this channel does not affect the PWRGD pin.
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LTC2974
PMBUS COMMAND DESCRIPTION
b[1] Mfr_pwrgd_en_chan1 Channel 1.
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine when
the PWRGD pin gets asserted.
0 = PWRGD status for this channel does not affect the PWRGD pin.
b[0] Mfr_pwrgd_en_chan0 Channel 0.
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine when
the PWRGD pin gets asserted.
0 = PWRGD status for this channel does not affect the PWRGD pin.
MFR_POWERGOOD_ASSERTION_DELAY
This command register allows the user to program the delay from when the internal power-good signal becomes valid
until the power-good output is asserted. This delay is counted using SHARE_CLK if available, otherwise the internal
oscillator is used. This delay is internally limited to 13.1 seconds, and rounded to the nearest 200µs. The read value
of this command always returns what was last written and does not reflect internal limiting.
The power good de-assertion delay and threshold source is controlled by Mfr_config_all_pwrgd_off_uses_uv. Sys-
tems that require a fast power good de-assertion should set Mfr_config_all_pwrgd_off_uses_uv=1. This uses the
VOUT_UV_FAULT_LIMIT and the high speed comparator to de-assert the PWRGD pin. Systems that require a separate
power good off threshold should set Mfr_config_all_pwrgd_off_uses_uv=0. This uses the slower ADC polling loop
and POWER_GOOD_OFF to de-assert the PWRGD pin.
Watchdog Operation
A non-zero write to the MFR_WATCHDOG_T register will reset the watchdog timer. Low-to-high transitions on the
WDI/RESETB pin also reset the watchdog timer. If the timer expires, ALERTB is asserted and the PWRGD output
is optionally de-asserted and then reasserted after MFR_PWRGD_ASSERTION_DELAY ms. Writing 0 to either the
MFR_WATCH_DOG_T or MFR_WATCHDOG_T_FIRST registers will disable the timer.
MFR_WATCHDOG_T_FIRST and MFR_WATCHDOG_T
The MFR_WATCHDOG_T_FIRST register allows the user to program the duration of the first watchdog timer interval
following assertion of the PWRGD pin, assuming the PWRGD pin reflects the status of the watchdog timer. If asser-
tion of PWRGD is not conditioned by the watchdog timer’s status, then MFR_WATCHDOG_T_FIRST applies to the first
timing interval after the timer is enabled. Writing a value of 0ms to the MFR_WATCHDOG_T_FIRST register disables
the watchdog timer. This delay is internally limited to 65 seconds and rounded to the nearest 1ms.
The MFR_WATCHDOG_T register allows the user to program watchdog timer intervals subsequent to the MFR_WATCH-
DOG_T_FIRST timing interval. Writing a value of 0ms to the MFR_WATCHDOG_T register disables the watchdog timer.
This delay is internally limited to 655ms and rounded to the nearest 10µs.
Both timers operate on an internal clock independent of SHARE_CLK. The read value of both commands always returns
what was last written and does not reflect internal limiting.
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LTC2974
PMBUS COMMAND DESCRIPTION
FAULT RESPONSES
CMD
DEFAULT REF
PAGED FORMAT UNITS EEPROM VALUE PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
VOUT_OV_FAULT_RESPONSE
0x41 Action to be taken by the device when an R/W Byte
output overvoltage fault is detected.
Y
Y
Y
Y
Y
Reg
Reg
Reg
Reg
Reg
Y
Y
Y
Y
Y
0x80
0x7F
0x00
0x00
0xB8
55
55
56
56
57
VOUT_UV_FAULT_RESPONSE
IOUT_OC_FAULT_RESPONSE
IOUT_UC_FAULT_RESPONSE
OT_FAULT_RESPONSE
0x45 Action to be taken by the device when an R/W Byte
output undervoltage fault is detected.
0x47 Action to be taken by the device when an R/W Byte
output overcurrent fault is detected.
0x4C Action to be taken by the device when an R/W Byte
output undercurrent fault is detected.
0x50 Action to be taken by the device when an R/W Byte
overtemperature fault is detected on the
external temperature sensor.
UT_FAULT_RESPONSE
0x54 Action to be taken by the device when an R/W Byte
undertemperature fault is detected on the
external temperature sensor.
Y
Reg
Y
0xB8
57
VIN_OV_FAULT_RESPONSE
VIN_UV_FAULT_RESPONSE
TON_MAX_FAULT_RESPONSE
MFR_RETRY_DELAY
0x56 Action to be taken by the device when an R/W Byte
input overvoltage fault is detected.
N
N
Y
N
N
Reg
Reg
Reg
L11
Reg
Y
Y
Y
Y
Y
0x80
0x00
0xB8
57
57
58
58
58
0x5A Action to be taken by the device when an R/W Byte
input undervoltage fault is detected.
0x63 Action to be taken by the device when a
TON_MAX_FAULT event is detected.
R/W Byte
0xDB Retry interval during FAULT retry mode. R/W Word
mS
200
0xF320
MFR_RETRY_COUNT
0xF7 Retry count for all faulted off conditions
that enable retry.
R/W Byte
0x00
Clearing Latched Faults
Latched faults are reset by toggling the CONTROL pin, using the OPERATION command, or removing and reapplying
the bias voltage to the V pin. All fault and warning conditions result in the ALERTB pin being asserted low and
IN_SNS
the corresponding bits being set in the status registers. The CLEAR_FAULTS command resets the contents of the
status registers and de-asserts the ALERTB output. The CLEAR_FAULTS does not clear a faulted off state nor allow a
channel to turn back on.
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LTC2974
PMBUS COMMAND DESCRIPTION
VOUT_OV_FAULT_RESPONSE and VOUT_UV_FAULT_RESPONSE
The fault response documented here is for voltages that are measured by the high speed supervisor. These voltages
are measured over a short period of time and may require a deglitch period. Note that in addition to the response
described by these commands, the LTC2974 will also:
• Set the appropriate bit(s) in the STATUS_BYTE.
• Set the appropriate bit(s) in the STATUS_WORD.
• Set the appropriate bit in the corresponding STATUS_VOUT register, and
• Notify the host by pulling the ALERTB pin low.
VOUT_OV_FAULT_RESPONSE and VOUT_UV_FAULT_RESPONSE Data Contents
BIT(S) SYMBOL
OPERATION
b[7:6] Vout_ov_fault_response_action, Response action:
Vout_uv_fault_response_action
00b: The unit continues operation without interruption.
01b: The unit continues operating for the delay time specified by bits[2:0] in increments of t
. See
S_VS
Electrical Characteristics Table. If the fault is still present at the end of the delay time, the unit shuts down
immediately or sequences off after TOFF_DELAY (See Mfr_config_track_enn). After shutting down, the device
responds according to the retry settings in bits [5:3].
10b-11b: The unit shuts down immediately or sequences off after TOFF_DELAY (See Mfr_config_track_enn).
After shutting down, the device responds according to the retry settings in bits [5:3].
b[5:3] Vout_ov_fault_response_retry, Response retry behavior:
Vout_uv_fault_response_retry
000b: A zero value for the retry setting means that the unit does not attempt to restart. The output remains
disabled until the fault is cleared.
001b-111b: The PMBus device attempts to restart the number of times specified by the global Mfr_retry_
count[2:0] until it is commanded OFF (by the CONTROL pin or OPERATION command or both), bias power is
removed, or another fault condition causes the unit to shut down.
Changing the value might not take effect until the next off-then-on sequence on that channel.
b[2:0] Vout_ov_fault_response_delay, This sample count determines the amount of time a unit is to ignore a fault after it is first detected. Use this
Vout_uv_fault_response_delay delay to deglitch fast faults.
000b: There is no additional deglitch delay applied to fault detection.
001b-111b: The fault is deglitched for deglitch period of b[2:0] samples at a sampling period of tS_VS
(12.2µs typical).
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LTC2974
PMBUS COMMAND DESCRIPTION
IOUT_OC_FAULT_RESPONSE and IOUT_UC_FAULT_RESPONSE
The fault response documented here is for currents that are measured by the high speed supervisor. These currents
are measured over a short period of time and may require a deglitch period. Note that in addition to the response
described by these commands, the LTC2974 will also:
• Set the appropriate bit in the STATUS_BYTE.
• Set the appropriate bit in the STATUS_WORD.
• Set the appropriate bit in the corresponding STATUS_IOUT register, and
• Notify the host by pulling the ALERTB pin low.
IOUT_OC_FAULT_RESONSE and IOUT_UC_FAULT_RESPONSE Data Contents
BIT(S) SYMBOL
OPERATION
b[7:6] Iout_oc_fault_response_action, Response action:
Iout_uc_fault_response_action
00b and 01b: The unit continues operation without interruption. Note that the current will not be limited to the
value of Iout_oc_fault_limit or Iout_uc_fault_limit.
10b: The unit continues operating for the delay time specified by bits [2:0]. If the fault is still present at the
end of the delay time, the unit shuts down immediately or sequences off after TOFF_DELAY (See Mfr_config_
track_enn). After shutting down, the device responds according to the retry settings in bits [5:3]. Note that
the current will not be limited to the value of Iout_oc_fault_limit or Iout_uc_fault_limit.
11b: The unit shuts down immediately or sequences off after TOFF_DELAY (See Mfr_config_track_enn). After
shutting down, the device responds according to the retry settings in bits [5:3].
b[5:3] Iout_oc_fault_response_retry,
Iout_uc_fault_response_retry
Response retry behavior:
000b: A zero value for the retry setting means that the unit does not attempt to restart. The output remains
disabled until the fault is cleared.
001-111b: The PMBus device attempts to restart the number of times specified by the global Mfr_retry_
count[2:0] until it is commanded off (by the control pin or operation command or both), bias power is
removed, or another fault condition causes the unit to shut down.
Changing the value might not take effect until the next off-then-on sequence on that channel.
b[2:0] Iout_oc_fault_response_delay, This sample count determines the amount of time a unit is to ignore a fault after it is first detected. Use this
Iout_uc_fault_response_delay
delay to deglitch fast faults.
000b: There is no additional deglitch delay applied to fault detection.
001b-111b: The fault is deglitched for the interval selected by b[2:0] as follows.
b[2:0]
001b
010b
011b
100b
101b
110b
111b
Deglitch interval
100µs
1ms
5ms
10ms
20ms
50ms
100ms
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LTC2974
PMBUS COMMAND DESCRIPTION
OT_FAULT_RESPONSE, UT_FAULT_RESPONSE, VIN_OV_FAULT_RESPONSE and VIN_UV_FAULT_RESPONSE
The fault response documented here is for values that are measured by the ADC. Note that in addition to the response
described by these commands, the LTC2974 will also:
• Set the appropriate bit(s) in the STATUS_BYTE.
• Set the appropriate bit(s) in the STATUS_WORD.
• Set the appropriate bit in the corresponding STATUS_VIN or STATUS_TEMPERATURE register, and
• Notify the host by pulling the ALERTB pin low.
OT_FAULT_RESPONSE, UT_FAULT_RESPONSE, VIN_OV_FAULT_RESPONSE, VIN_UV_FAULT_RESPONSE Data Contents
BIT(S) SYMBOL
OPERATION
b[7:6] Ot_fault_response_action,
Ut_fault_response_action,
Response action:
00b: The unit continues operation without interruption.
Vin_ov_fault_response_action,
Vin_uv_fault_response_action
01b-11b: The unit shuts down immediately or sequences off after TOFF_DELAY (See Mfr_config_track_enn).
After shutting down, the device responds according to the retry settings in bits [5:3].
b[5:3] Ot_fault_response_retry,
Ut_fault_response_retry,
Response retry behavior:
000b: A zero value for the retry setting means that the unit does not attempt to restart. The output remains
disabled until the fault is cleared.
Vin_ov_fault_response_retry,
Vin_uv_fault_response_retry
001b-111b: The PMBus device attempts to restart the number of times specified by the global Mfr_retry_
count[2:0] until it is commanded OFF (by the CONTROL pin or OPERATION command or both), bias power is
removed, or another fault condition causes the unit to shut down.
Changing the value might not take effect until the next off-then-on sequence on that channel.
Hard coded to 000b: There is no additional deglitch delay applied to fault detection.
b[2:0] Ot_fault_response_delay,
Ut_fault_response_delay,
Vin_ov_fault_response_delay,
Vin_uv_fault_response_delay
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LTC2974
PMBUS COMMAND DESCRIPTION
TON_MAX_FAULT_RESPONSE
This command defines the LTC2974 response to a TON_MAX_FAULT. It may be used to protect against a short-circuited
output at startup. After startup use VOUT_UV_FAULT_RESPONSE to protect against a short-circuited output.
The device also:
• Sets the HIGH_BYTE bit in the STATUS_BYTE,
• Sets the VOUT bit in the STATUS_WORD,
• Sets the TON_MAX_FAULT bit in the STATUS_VOUT register, and
• Notifies the host by asserting ALERTB.
TON_MAX_FAULT_RESPONSE Data Contents
BIT(S) SYMBOL
b[7:6] Ton_max_fault_response_action Response action:
00b: The unit continues operation without interruption.
OPERATION
01b-11b: The unit shuts down immediately or sequences off after TOFF_DELAY (See Mfr_config_track_enn).
After shutting down, the device responds according to the retry settings in bits [5:3].
b[5:3] Ton_max_fault_response_retry Response retry behavior:
000b: A zero value for the retry setting means that the unit does not attempt to restart. The output remains
disabled until the fault is cleared.
001b-111b: The PMBus device attempts to restart the number of times specified by the global Mfr_retry_
count[2:0] until it is commanded OFF (by the CONTROL pin or OPERATION command or both), bias power is
removed, or another fault condition causes the unit to shut down.
Changing the value might not take effect until the next off-then-on sequence on that channel.
b[2:0] Ton_max_fault_response_delay Hard coded to 000b: There is no additional deglitch delay applied to fault detection.
MFR_RETRY_DELAY
This command determines the retry interval when the LTC2974 is in retry mode in response to a fault condition. This
delay is counted using SHARE_CLK only. This delay is internally limited to 13.1 seconds, and rounded to the nearest
200µs. The read value of this command always returns what was last written and does not reflect internal limiting.
MFR_RETRY_COUNT
The MFR_RETRY_COUNT is a global command that sets the number of retries attempted when any channel faults off
with its fault response retry field set to a non zero value.
In the event of multiple or recurring retry faults on the same channel the total number of retries equals MFR_RETRY_
COUNT. If a channel has not been faulted off for 6 seconds, its retry counter is cleared. Toggling a channel’s CONTROL
pin off then on or issuing OPERATION off then on commands will synchronously clear the retry count.
MFR_RETRY_COUNT Data Contents
BIT(S) SYMBOL
OPERATION
b[7:3] Reserved
Always returns zero.
b[2:0] Mfr_retry_count [2:0]
0: No retries:
1-6: Number of retries.
7: Infinite retries.
Changing the value might not take effect until the next off-then-on sequence on that channel.
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LTC2974
PMBUS COMMAND DESCRIPTION
SHARED EXTERNAL FAULTS
CMD
DEFAULT REF
PAGED FORMAT UNITS EEPROM VALUE PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
MFR_FAULTB0_PROPAGATE 0xD2 Configuration that determines if a channels R/W Byte
Y
Reg
Y
0x00
59
faulted off state is propagated to the
FAULTB0 pin.
MFR_FAULTB1_PROPAGATE 0xD3 Configuration that determines if a channels R/W Byte
Y
Reg
Y
0x00
59
faulted off state is propagated to the
FAULTB1 pin.
MFR_FAULTB0_RESPONSE
MFR_FAULTB1_RESPONSE
0xD5 Action to be taken by the device when the
FAULTB0 pin is asserted low.
R/W Byte
R/W Byte
N
N
Reg
Reg
Y
Y
0x00
0x00
60
60
0xD6 Action to be taken by the device when the
FAULTB1 pin is asserted low.
MFR_FAULTB0_PROPAGATE and MFR_FAULTB1_PROPAGATE
These manufacturer specific commands enable channels that have faulted off to propagate that state to the appro-
priate fault pin. MFR_FAULTB0_PROPAGATE allows any channel’s faulted off state to propagate to the FAULTB0 pin.
MFR_FAULTB1_PROPAGATE allows any channel’s faulted off state to propagate to the FAULTB1 pin.
Note that pulling a fault pin low will have no effect for channels that have MFR_FAULTBn_RESPONSE set to 0. The
channel continues operation without interruption. This fault response is called Ignore (0x0) in LTpowerPlay.
MFR_FAULT0_PROPAGATE Data Contents
BIT(S) SYMBOL
OPERATION
b[7:1] Reserved
Don’t care. Always returns 0.
b[0] Mfr_faultb0_propagate Enable fault propagation.
0: Channel’s faulted off state does not assert FAULTB0 low.
1 :Channel’s faulted off state asserts FAULTB0 low.
MFR_FAULT1_PROPAGATE Data Contents
BIT(S) SYMBOL
OPERATION
b[7:1] Reserved
Don’t care. Always returns 0.
b[0] Mfr_faultb1_propagate Enable fault propagation.
0: Channel’s faulted off state does not assert FAULTB1 low.
1: Channel’s faulted off state asserts FAULTB1 low.
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LTC2974
PMBUS COMMAND DESCRIPTION
MFR_FAULTB0_RESPONSE and MFR_FAULTB1_RESPONSE
These manufacturer specific commands share the same format and specify the response to assertions of the FAULTB
pins. MFR_FAULTB0_RESPONSE determines which channels shut off when the FAULTB0 pin is asserted low and
MFR_FAULTB1_RESPONSE determines which channels shut off when the FAULTB1 pin is asserted low.When a chan-
nel shuts off in response to a FAULTBn pin, the ALERTB pin is asserted low and the appropriate bit is set in the STA-
TUS_MFR_SPECIFIC register. For a graphical explanation, see the switches on the left hand side of Figure 28: Channel
Fault Management Block Diagram.
Faults will not propagate for channels that have MFR_FAULTBn_RESPONSE set to 0: The channel continues operation
without interruption. Note that this fault response is called No Action in LTpowerPlay.
MFR_FAULTB0_RESPONSE and MFR_FAULTB1_RESPONSE Data Contents
BIT(S) SYMBOL
OPERATION
b[7:4] Reserved
Read only, always returns 0000b.
b[3] Mfr_faultb0_response_chan3, Channel 3 response.
Mfr_faultb1_response_chan3
0: The channel continues operation without interruption
1: The channel shuts down if the corresponding FAULTB pin is still asserted after 10µs. When the FAULTB pin
subsequently de-asserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
b[2] Mfr_faultb0_response_chan2, Channel 2 response.
Mfr_faultb1_response_chan2
0: The channel continues operation without interruption
1: The channel shuts down if the corresponding FAULTB pin is still asserted after 10µs. When the FAULTB pin
subsequently de-asserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
b[1] Mfr_faultb0_response_chan1, Channel 1 response.
Mfr_faultb1_response_chan1
0: The channel continues operation without interruption
1: The channel shuts down if the corresponding FAULTB pin is still asserted after 10µs. When the FAULTB pin
subsequently de-asserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
b[0] Mfr_faultb0_response_chan0, Channel 0 response.
Mfr_faultb1_response_chan0
0: The channel continues operation without interruption
1: The channel shuts down if the corresponding FAULTB pin is still asserted after 10µs. When the FAULTB pin
subsequently de-asserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
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LTC2974
PMBUS COMMAND DESCRIPTION
FAULT WARNING AND STATUS
CMD
DEFAULT REF
COMMAND NAME
CLEAR_FAULTS
STATUS_BYTE
STATUS_WORD
STATUS_VOUT
STATUS_IOUT
STATUS_INPUT
CODE DESCRIPTION
TYPE
Send Byte
R Byte
PAGED FORMAT UNITS EEPROM VALUE PAGE
0x03 Clear any fault bits that have been set.
0x78 One byte summary of the unit’s fault condition.
0x79 Two byte summary of the unit’s fault condition.
0x7A Output voltage fault and warning status.
0x7B Output current fault and warning status.
0x7C Input supply fault and warning status.
Y
Y
Y
Y
Y
N
Y
NA
NA
NA
NA
NA
NA
NA
61
61
62
62
63
63
63
Reg
Reg
Reg
Reg
Reg
Reg
R Word
R Byte
R Byte
R Byte
STATUS_TEMPERATURE 0x7D External temperature fault and warning status
for READ_TEMPERATURE_1.
R Byte
STATUS_CML
0x7E Communication and memory fault and warning
status.
R Byte
R Byte
N
Y
Reg
Reg
NA
NA
64
64
STATUS_MFR_SPECIFIC 0x80 Manufacturer specific fault and state
information.
MFR_PADS
0xE5 Current state of selected digital I/O pads.
R/W Word
R Byte
N
N
Reg
Reg
NA
NA
65
65
MFR_COMMON
0xEF Manufacturer status bits that are common
across multiple LTC chips.
CLEAR_FAULTS
The CLEAR_FAULTS command is used to clear status bits that have been set. This command clears all fault and warn-
ing bits in all unpaged status registers, and paged status registers selected by the current PAGE setting. At the same
time, the device negates (clears, releases) its contribution to ALERTB.
The CLEAR_FAULTS command does not cause a unit that has latched off for a fault condition to restart. See Clearing
Latched Faults for more information.
If the fault is present after the fault is cleared, the fault status bit shall be set again and the host notified by the usual
means.
Note: this command responds to the global page command. (PAGE=0xFF)
STATUS_BYTE
The STATUS_BYTE command returns the summary of the most critical faults or warnings which have occurred, as
shown in the following table. STATUS_BYTE is a subset of STATUS_WORD and duplicates the same information.
STATUS_BYTE Data Contents
BIT(S) SYMBOL
OPERATION
b[7] Status_byte_busy
b[6] Status_byte_off
Same as Status_word_busy.
Same as Status_word_off.
b[5] Status_byte_vout_ov Same as Status_word_vout_ov.
b[4] Status_byte_iout_oc
b[3] Status_byte_vin_uv
b[2] Status_byte_temp
b[1] Status_byte_cml
Same as Status_word_iout_oc.
Same as Status_word_vin_uv.
Same as Status_word_temp.
Same as Status_word_cml.
b[0] Status_byte_high_byte Same as Status_word_high_byte.
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LTC2974
PMBUS COMMAND DESCRIPTION
STATUS_WORD
The STATUS_WORD command returns two bytes of information with a summary of the unit’s fault condition. Based on
the information in these bytes, the host can get more information by reading the appropriate detailed status register.
The low byte of the STATUS_WORD is the same register as the STATUS_BYTE command.
STATUS_WORD Data Contents
BIT(S) SYMBOL
OPERATION
b[15] Status_word_vout
b[14] Status_word_iout
b[13] Status_word_input
b[12] Status_word_mfr
An output voltage fault or warning has occurred. See STATUS_VOUT.
An output current fault or warning has occurred. See STATUS_IOUT.
An input voltage fault or warning has occurred. See STATUS_INPUT.
A manufacturer specific fault has occurred. See STATUS_MFR._SPECIFIC.
b[11] Status_word_power_not_good The PWRGD pin, if enabled, is negated. Power is not good.
b[10] Status_word_fans
b[9] Status_word_other
b[8] Status_word_unknown
Not supported. Always
returns 0.
Not supported. Always
returns 0.
Not supported. Always
returns 0.
b[7] Status_word_busy
b[6] Status_word_off
Device busy when PMBus command received. See OPERATION: Processing Commands.
This bit is asserted if the unit is not providing power to the output, regardless of the reason, including simply
not being enabled. The off-bit is clear if unit is allowed to provide power to the output.
b[5] Status_word_vout_ov
b[4] Status_word_iout_oc
b[3] Status_word_vin_uv
b[2] Status_word_temp
b[1] Status_word_cml
An output overvoltage fault has occurred.
An output overcurrent fault has occurred.
A V undervoltage fault has occurred.
IN
A temperature fault or warning has occurred. See STATUS_TEMPERATURE.
A communication, memory or logic fault has occurred. See STATUS_CML.
A fault/warning not listed in b[7:1] has occurred.
b[0] Status_word_high_byte
STATUS_VOUT
The STATUS_VOUT command returns the summary of the output voltage faults or warnings which have occurred, as
shown in the following table:
STATUS_VOUT Data Contents
BIT(S) SYMBOL
OPERATION
b[7] Status_vout_ov_fault
b[6] Status_vout_ov_warn
b[5] Status_vout_uv_warn
b[4] Status_vout_uv_fault
b[3] Status_vout_max_fault
Overvoltage fault.
Overvoltage warning.
Undervoltage warning
Undervoltage fault.
VOUT_MAX fault. An attempt has been made to set the output voltage to a value higher than allowed by the
VOUT_MAX command. After being cleared, Status_vout_max_fault will not report additional faults until a channel
state transition (off-then-on) has been performed or a valid output voltage, lower than allowed by VOUT_MAX, has
been set.
b[2] Status_vout_ton_max_fault TON_MAX_FAULT sequencing fault.
b[1] Status_vout_toff_max_warn Not supported. Always returns 0.
b[0] Status_vout_tracking_error Not supported. Always returns 0.
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PMBUS COMMAND DESCRIPTION
STATUS_IOUT
The STATUS_IOUT command returns the summary of the output current faults or warnings which have occurred, as
shown in the following table:
STATUS_IOUT Data Contents
BIT(S) SYMBOL
OPERATION
b[7] Status_iout_oc_fault
b[6] Status_iout_oc_uv_fault
b[5] Status_iout_oc_warn
b[4] Status_iout_uc_fault
Overcurrent fault.
Not Supported. Always returns 0.
Overcurrent warning
Undercurrent fault.
b[3] Status_iout_curr_share_fault Not Supported. Always returns 0.
b[2] Status_pout_power_limiting Not Supported. Always returns 0.
b[1] Status_pout_overpower_fault Not Supported. Always returns 0.
b[0] Status_pout_overpower_warn Not Supported. Always returns 0.
STATUS_INPUT
The STATUS_INPUT command returns the summary of the V faults or warnings which have occurred, as shown in
IN
the following table:
STATUS_INPUT Data Contents
BIT(S) SYMBOL
OPERATION
b[7] Status_input_ov_fault
b[6] Status_input_ov_warn
b[5] Status_input_uv_warn
b[4] Status_input_uv_fault
b[3] Status_input_off
V
V
V
V
overvoltage fault
IN
IN
IN
IN
overvoltage warning
undervoltage warning
undervoltage fault
Unit is off for insufficient input voltage.
Not supported. Always returns 0.
Not supported. Always returns 0.
Not supported. Always returns 0.
b[2] IIN overcurrent fault
b[1] IIN overcurrent warn
b[0] PIN overpower warn
STATUS_TEMPERATURE
The STATUS_TEMPERATURE command returns the summary of the temperature faults or warnings which have oc-
curred, as shown in the following table. Note that this information is paged and refers to the temperature of the as-
sociated external diode.
STATUS_TEMPERATURE Data Contents
BIT(S) SYMBOL
OPERATION
b[7] Status_temperature_ot_fault
Overtemperature fault.
b[6] Status_temperature_ot_warn Overtemperature warning.
b[5] Status_temperature_ut_warn Undertemperature warning.
b[4] Status_temperature_ut_fault
b[3] Reserved
Undertemperature fault.
Reserved. Always returns 0.
Reserved. Always returns 0.
Reserved. Always returns 0.
Reserved. Always returns 0.
b[2] Reserved
b[1] Reserved
b[0] Reserved
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PMBUS COMMAND DESCRIPTION
STATUS_CML
The STATUS_CML command returns the summary of the communication, memory and logic faults or warnings which
have occurred, as shown in the following table:
STATUS_CML Data Contents
BIT(S) SYMBOL
OPERATION
b[7] Status_cml_cmd_fault
1 = An illegal or unsupported command fault has occurred.
0 = No fault has occurred.
b[6] Status_cml_data_fault
b[5] Status_cml_pec_fault
1 = Illegal or unsupported data received.
0 = No fault has occurred.
1 = A packet error check fault has occurred. Note: PEC checking is always active in the LTC2974. Any extra byte
received before a STOP will set Status_cml_pec_fault unless the extra byte is a matching PEC byte.
0 = No fault has occurred.
b[4] Status_cml_memory_fault 1 = A fault has occurred in the EEPROM.
0 = No fault has occurred.
b[3] Status_cml_processor_fault Not supported, always returns 0.
b[2] Reserved
Reserved, always returns 0.
b[1] Status_cml_pmbus_fault
1 = A communication fault other than ones listed in this table has occurred. This is a catch all category for illegally
2
formed I C/SMBus commands (Example: An address byte with read =1 received immediately after a START).
0 = No fault has occurred.
b[0] Status_cml_unknown_fault Not supported, always returns 0.
STATUS_MFR_SPECIFIC
The STATUS_MFR_SPECIFIC command returns manufacturer specific status flags. Bits marked CHANNEL = All are
not paged. Bits marked STICKY = Yes stay set until a CLEAR_FAULTS is issued or the channel is commanded on by
the user. Bits marked ALERT = Yes pull ALERTB low when the bit is set. Bits marked OFF = Yes indicate that the event
can be configured elsewhere to turn the channel off.
STATUS_MFR_SPECIFIC Data Contents
BIT(S) SYMBOL
OPERATION
CHANNEL STICKY ALERT OFF
b[7] Status_mfr_discharge
1 = A V
state.
discharge fault occurred while attempting to enter the ON Current Page Yes
Yes Yes
OUT
0 = No V
discharge fault has occurred.
OUT
b[6] Status_mfr_fault1_in
b[5] Status_mfr_fault0_in
This channel attempted to turn on while the FAULTB1 pin was
asserted low, or this channel has shut down at least once in
response to a FAULTB1 pin asserting low since the last CONTROL
pin toggle, OPERATION command ON/OFF cycle or CLEAR_FAULTS
command. If Mfr_track_en_chann is set, Status_mfr_fault1_in may
also be set for the channel causing the fault.
Current Page Yes
Current Page Yes
Yes Yes
This channel attempted to turn on while the FAULTB0 pin was
asserted low, or this channel has shut down at least once in
response to a FAULTB0 pin asserting low since the last CONTROL
pin toggle, OPERATION command ON/OFF cycle or CLEAR_FAULTS
command. If Mfr_track_en_chann is set, Status_mfr_fault0_in may
also be set for the channel causing the fault.
Yes Yes
b[4] Status_mfr_servo_target_reached Servo target has been reached.
Current Page
Current Page
No
No
No
No
No
No
b[3] Status_mfr_dac_connected
DAC is connected and driving V
pin.
DAC
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PMBUS COMMAND DESCRIPTION
b[2] Status_mfr_dac_saturated
A previous servo operation terminated with maximum or minimum
DAC value.
Current Page Yes
No
No
b[1] Status_mfr_auxfaultb_faulted_off AUXFAULTB has been de-asserted due to a V
or I
fault.
All
All
No
No
No
No
OUT
OUT
b[0] Status_mfr_watchdog_fault
1 = A watchdog fault has occurred.
0 = No watchdog fault has occurred.
Yes
Yes
MFR_PADS
The MFR_PADS command provides read-only access of digital pads (pins). The input values are before any deglitch-
ing logic.
MFR_PADS Data Contents
BIT(S) SYMBOL
OPERATION
b[15] Mfr_pads_pwrgd_drive
0 = PWRGD pad is being driven low by this chip.
1 = PWRGD pad is not being driven low by this chip.
0 = ALERTB pad is being driven low by this chip.
1 = ALERTB pad is not being driven low by this chip.
bit[1] used for FAULTB0 pad, bit[0] used for FAULTB1 pad as follows:
0 = FAULTB pad is being driven low by this chip.
1 = FAULTB pad is not being driven low by this chip.
Always returns 00b.
b[14] Mfr_pads_alertb_drive
b[13:12] Mfr_pads_faultb_drive[1:0]
b[11:10] Reserved[1:0]
b[9:8] Mfr_pads_asel1[1:0]
11: Logic high detected on ASEL1 input pad.
10: ASEL1 input pad is floating.
01: Reserved.
00: Logic low detected on ASEL1 input pad.
11: Logic high detected on ASEL0 input pad.
10: ASEL0 input pad is floating.
b[7:6] Mfr_pads_asel0[1:0]
01: Reserved.
00: Logic low detected on ASEL0 input pad.
1: Logic high detected on CONTROL1 pad.
0: Logic low detected on CONTROL1 pad.
1: Logic high detected on CONTROL0 pad.
0: Logic low detected on CONTROL0 pad.
bit[1] used for FAULTB0 pad, bit[0] used for FAULTB1 pad as follows:
1: Logic high detected on FAULTB pad.
0: Logic low detected on FAULTB pad.
1: Logic high detected on CONTROL2 pad.
0: Logic low detected on CONTROL2 pad.
1: Logic high detected on CONTROL3 pad.
0: Logic low detected on CONTROL3 pad.
b[5]
b[4]
Mfr_pads_control1
Mfr_pads_control0
b[3:2] Mfr_pads_faultb[1:0]
b[1]
b[0]
Mfr_pads_control2
Mfr_pads_control3
MFR_COMMON
This command returns status information for the alert, device busy, share-clock pin (SHARE_CLK) and the write-protect
pin (WP).
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PMBUS COMMAND DESCRIPTION
This is the only command that may still be read when the LTC2974 is busy processing an EEPROM or other command.
It may be polled by the host to determine when the LTC2974 is available to process a PMBus command. A busy device
will always acknowledge its address but will NACK the command byte and set Status_byte_busy and Status_word_busy
when it receives a command that it cannot immediately process. ALERTB will not be asserted low in this case.
MFR_COMMON Data Contents
BIT(S) SYMBOL
OPERATION
b[7] Mfr_common_alertb
Returns alert status.
1: ALERTB is de-asserted high.
0: ALERTB is asserted low.
b[6] Mfr_common_busyb
Returns device busy status.
1: The device is available to process PMBus commands.
0: The device is busy and will NACK PMBus commands.
Read only, always returns 1s.
b[5:2] Reserved
b[1] Mfr_common_share_clk
Returns the status of the share-clock pin.
1: Share-clock pin is being held low.
0: Share-clock pin is active.
b[0] Mfr_common_write_protect Returns the status of the write-protect pin.
1: Write-protect pin is high.
0: Write-protect pin is low.
TELEMETRY
CMD
DEFAULT REF
COMMAND NAME
READ_VIN
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM VALUE PAGE
0x88 Input supply voltage.
R Word
R Word
R Word
R Word
N
Y
Y
Y
L11
L16
L11
L11
V
V
NA
NA
NA
NA
67
67
67
67
READ_VOUT
0x8B DC/DC converter output voltage.
0x8C DC/DC converter output current.
READ_IOUT
A
READ_TEMPERATURE_1
0x8D External diode junction temperature. This
is the value used for all temperature related
processing, including IOUT_CAL_GAIN.
°C
READ_TEMPERATURE_2
READ_POUT
0x8E Internal junction temperature.
0x96 DC/DC converter output power.
R Word
R Word
R Word
N
Y
Y
L11
L11
CF
°C
W
NA
NA
NA
67
67
67
MFR_READ_IOUT
0xBB Alternate data format for READ_IOUT. One
LSB = 2.5mA.
2.5mA
MFR_IOUT_SENSE_VOLTAGE 0xFA Absolute value of VISENSEP – VISENSEM. R Word
One LSB = 3.05µV.
Y
CF
3.05µV
NA
68
MFR_VIN_PEAK
MFR_VOUT_PEAK
MFR_IOUT_PEAK
0xDE Maximum measured value of READ_VIN.
R Word
N
Y
Y
Y
L11
L16
L11
L11
V
V
NA
NA
NA
NA
69
69
69
69
0xDD Maximum measured value of READ_VOUT. R Word
0xD7 Maximum measured value of READ_IOUT.
R Word
R Word
A
MFR_TEMPERATURE_1_PEAK 0xDF Maximum measured value of READ_
TEMPERATURE_1.
°C
MFR_VIN_MIN
MFR_VOUT_MIN
MFR_IOUT_MIN
0xFC Minimum measured value of READ_VIN.
0xFB Minimum measured value of READ_VOUT.
0xD8 Minimum measured value of READ_IOUT.
R Word
R Word
R Word
R Word
N
Y
Y
Y
L11
L16
L11
L11
V
V
NA
NA
NA
NA
69
69
69
69
A
MFR_TEMPERATURE_1_MIN 0xFD Minimum measured value of READ_
TEMPERATURE_1.
°C
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PMBUS COMMAND DESCRIPTION
READ_VIN
This command returns the most recent ADC measured value of the input voltage at the V
pin.
IN_SNS
READ_VOUT
This command returns the most recent ADC measured value of the channel’s output voltage.
READ_IOUT
This command returns the most recent ADC measured value of the channel’s output current.
READ_TEMPERATURE_1
This command returns the most recent measured value of the external diode temperature in °C. This value is used for
all temperature related operations and calculations. This command is paged. READ_TEMPERATURE_2 is substituted
for READ_TEMPERATURE_1 if the associated T
network fails to detect a valid temperature.
SENSE
The T
network will fail to detect a valid temperature under the following conditions:
SENSE
The T
pin is shorted to a constant voltage.
SENSE
The sense diode has an ideality factor greater than N_TS max.
Floating the T pin is not recommended and may return unpredictable temperature values.
SENSE
READ_TEMPERATURE_2
This command returns the most recent ADC measured value of junction temperature in °C as determined by the
LTC2974’s internal temperature sensor. This register is for information purposes and does not generate any faults,
warnings, or affect any other registers or internal calculations unless it is used as READ_TEMPERATURE_1. This
command is not paged.
READ_TEMPERATURE_2 is substituted for READ_TEMPERATURE_1 if a channel’s T
valid temperature.
network fails to detect a
SENSE
READ_POUT
This command returns the most recent ADC measured value of the channel’s output power in watts.
MFR_READ_IOUT
This command returns the most recent ADC measured value of the channel’s output current, using a custom format
that provides better numeric representation granularity than the READ_IOUT command for currents whose absolute
value is between 2A and 82A.
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PMBUS COMMAND DESCRIPTION
MFR_READ_IOUT Data Contents
BIT(S) SYMBOL
OPERATION
b[15:0] Mfr_read_iout[15:0]
Channel output current expressed in custom format for improved resolution at high currents.
Value = Y • 2.5 where Y = b[15:0] is a signed two’s-complement number.
Example:
MFR_READ_IOUT = 5mA
For b[15:0] = 0x0002
Value = 2 • 2.5 = 5mA
The granularity of the returned value is always 2.5mA, and the return value is limited to 81.92A. Use the READ_IOUT
command for larger currents. Note that the accuracy of the returned value is always limited by the ADC Characteristics
listed in the Electrical Characteristics section.
Comparison of Granularity Due to Numeric Format
READ_IOUT
MFR_READ_IOUT
GRANULARITY
CURRENT RANGE
31.25mA ≤ I < 62.5mA
GRANULARITY
61µA
122µA
244µA
488µA
977µA
1.95mA
3.9mA
7.8mA
15.6mA
31.3mA
62.5mA
125mA
125mA
250mA
2.5mA
2.5mA
2.5mA
2.5mA
2.5mA
2.5mA
2.5mA
2.5mA
2.5mA
2.5mA
2.5mA
2.5mA
Saturated
Saturated
OUT
62.5mA ≤ I
< 125mA
< 250mA
< 500mA
OUT
OUT
OUT
125mA ≤ I
250mA ≤ I
0.5A ≤ I
< 1A
OUT
1A ≤ I
2A ≤ I
4A ≤ I
8A ≤ I
< 2A
< 4A
< 8A
OUT
OUT
OUT
OUT
< 16A
16A ≤ I
32A ≤ I
64A ≤ I
82A ≤ I
< 32A
< 64A
< 82A
< 128A
OUT
OUT
OUT
OUT
128A ≤ I
< 256A
OUT
MFR_IOUT_SENSE_VOLTAGE
This command returns the absolute value of the voltage measured between I
READ_IOUT ADC conversion without any temperature correction.
and I
during the last
SENSEPn
SENSEMn
MFR_IOUT_SENSE_VOLTAGE Data Contents
BIT(S) SYMBOL
OPERATION
b[15:0] Mfr_iout_sense_voltage Absolute value of raw voltage conversion measured between I
and I
.
SENSEPn
SENSEMn
–13
Value = Y • 0.025 • 2 where Y = b[15:0] is an unsigned integer.
Example:
MFR_IOUT_SENSE_VOLTAGE = 1.544mV
For b[15:0] = 0x1FA=506
–13
Value = 506 • 0.025 • 2 = 1.544mV
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PMBUS COMMAND DESCRIPTION
MFR_VIN_PEAK
This command returns the maximum ADC measured value of the input voltage. This register is reset to 0x7C00
25
(–2 ) when the LTC2974 emerges from power-on reset or when a CLEAR_FAULTS command is executed.
MFR_VOUT_PEAK
This command returns the maximum ADC measured value of the channel’s output voltage. This register is reset to
0xF800 (0.0) when the LTC2974 emerges from power-on reset or when a CLEAR_FAULTS command is executed.
MFR_IOUT_PEAK
This commands returns the maximum ADC measured value of the channel’s output current. This register is reset to
25
0x7C00 (–2 ) when the LTC2974 emerges from power-on reset or when a CLEAR_FAULTS command is executed.
MFR_TEMPERATURE_1_PEAK
This command returns the maximum measured value of the external diode temperature in °C. This register is reset
25
to 0x7C00 (–2 ) when the LTC2974 emerges from power-on reset or when a CLEAR_FAULTS command is executed.
MFR_VIN_MIN
This command returns the minimum ADC measured value of the input voltage. This register is reset to 0x7BFF (ap-
25
proximately 2 ) when the LTC2974 emerges from power-on reset or when a CLEAR_FAULTS command is executed.
MFR_VOUT_MIN
This command returns the minimum ADC measured value of the channel’s output voltage. This register is reset to
0xFFFF (7.9999) when the LTC2974 emerges from power-on reset or when a CLEAR_FAULTS command is executed.
Updates are disabled when Margin Low (Ignore Faults and Warnings) is enabled.
MFR_IOUT_MIN
This command returns the minimum ADC measured values of the channel’s output current. This register is reset to
25
0x7BFF (approximately 2 ) when the LTC2974 emerges from power-on reset or when a CLEAR_FAULTS command
is executed.
MFR_TEMPERATURE_1_MIN
This command returns the minimum measured value of the external diode temperature in °C. This register is reset to
25
0x7BFF (approximately 2 ) when the LTC2974 emerges from power-on reset or when a CLEAR_FAULTS command
is executed.
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LTC2974
PMBUS COMMAND DESCRIPTION
FAULT LOGGING
CMD
DEFAULT REF
PAGED FORMAT UNITS EEPROM VALUE PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
MFR_FAULT_LOG_STORE
0xEA Command a transfer of the fault log from
RAM to EEPROM.
Send Byte
N
N
N
NA
NA
NA
70
70
71
MFR_FAULT_LOG_RESTORE 0xEB Command a transfer of the fault log
previously stored in EEPROM back to RAM.
Send Byte
Send Byte
MFR_FAULT_LOG_CLEAR
0xEC Initialize the EEPROM block reserved for
fault logging and clear any previous fault
logging locks.
MFR_FAULT_LOG_STATUS
MFR_FAULT_LOG
0xED Fault logging status.
R Byte
N
N
Reg
Reg
Y
Y
NA
NA
71
71
0xEE Fault log data bytes. This sequentially
retrieved data is used to assemble a
complete fault log.
R Block
Fault Log Operation
A conceptual diagram of the fault log is shown in Figure 22. The fault log provides black box capability for the LTC2974.
During normal operation the contents of the status registers, the output voltage/current/temperature readings, the
input voltage readings, as well as peak and min values of these quantities, are stored in a continuously updated buffer
in RAM. You can think of the operation as being similar to a strip chart recorder. When a fault occurs, the contents are
written into EEPROM for non volatile storage. The EEPROM fault log is then locked. The part can be powered down
with the fault log available for reading at a later time.
RAM 255 BYTES
EEPROM 255 BYTES
8
ADC READINGS
CONTINUOUSLY
FILL BUFFER
TIME OF FAULT
TRANSFER TO
EEPROM AND
LOCK
.
.
.
.
.
.
AFTER FAULT
READ FROM
EEPROM AND
LOCK BUFFER
2974 F22
Figure 22: Fault Logging
MFR_FAULT_LOG_STORE
This command allows the user to transfer data from the RAM buffer to EEPROM.
MFR_FAULT_LOG_RESTORE
This command allows the user to transfer a copy of the fault-log data from the EEPROM to the RAM buffer. After a
restore the RAM buffer is locked until a successful MFR_FAULT_LOG read.
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LTC2974
PMBUS COMMAND DESCRIPTION
MFR_FAULT_LOG_CLEAR
This command initializes the EEPROM block reserved for fault logging. Any previous fault log stored in EEPROM will
be erased by this operation and logging of the fault log RAM to EEPROM will be enabled. Make sure that Mfr_fault_
log_status_ram = 0 before issuing the MFR_FAULT_LOG_CLEAR command.
MFR_FAULT_LOG_STATUS
This register is used to manage fault log events. The Mfr_fault_log_status_eeprom bit is set after a MFR_FAULT_LOG_
STORE command or a faulted-off event triggers a transfer of the fault log from RAM to EEPROM. This bit is cleared
by a MFR_FAULT_LOG_CLEAR command.
Mfr_fault_log_status_ram is set after a MFR_FAULT_ LOG_RESTORE to indicate that the data in the RAM has been
restored from EEPROM and not yet read using a MFR_FAULT_LOG command. This bit is cleared only by a successful
execution of an MFR_FAULT_LOG command.
MFR_FAULT_LOG_STATUS Data Contents
BIT(S) SYMBOL
OPERATION
b[7:2] Reserved
Read only, always returns 0s.
b[1] Mfr_fault_log_status_ram
Fault log RAM status:
0: The fault log RAM allows updates.
1: The fault log RAM is locked until the next MFR_FAULT_LOG read.
b[0] Mfr_fault_log_status_eeprom Fault log EEPROM status:
0: The transfer of the fault log RAM to the EEPROM is enabled.
1: The transfer of the fault log RAM to the EEPROM is inhibited.
MFR_FAULT_LOG
Read only. This 2040-bit (255 byte) data block contains a copy of the RAM buffer fault log. The RAM buffer is continu-
ously updated after each ADC conversion as long as Mfr_fault_log_status_ram is clear.
With Mfr_config_all_fault_log_enable = 1 and Mfr_fault_log_status_eeprom = 0, the RAM buffer is transferred to EE-
PROM whenever an LTC2974 fault causes a channel to latch off or a MFR_FAULT_LOG_STORE command is received.
This transfer is delayed until the ADC has updated its READ values for all channels when Mfr_config_all_fast_fault_log
is clear, otherwise it happens within 24ms. This optional delay can be used to ensure that the slower ADC monitored
values are all updated for the case where a fast supervisor detected fault initiates the transfer to EEPROM.
Mfr_fault_log_status_eeprom is set high after the RAM buffer is transferred to EEPROM and not cleared until a
MFR_FAULT_LOG_CLEAR is received, even if the LTC2974 is reset or powered down. Fault log EEPROM transfers are
not initiated as a result of Status_mfr_discharge events.
During a MFR_FAULT_LOG read, data is returned one byte at a time as defined in Table 2. The fault log data is parti-
tioned into two sections. The first section is referred to as the preamble and contains the Position_last pointer, time
information and peak and min values. The second section contains a chronological record of telemetry and requires
Position_last for proper interpretation. The fault log stores approximately 300ms of telemetry. To prevent timeouts
during block reads, it is recommended that Mfr_config_all_longer_pmbus_timeout be set to 1.
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LTC2974
PMBUS COMMAND DESCRIPTION
Table 2. Data Block Contents
Table 2. Data Block Contents
DATA
DATA
BYTE* DESCRIPTION
BYTE* DESCRIPTION
Position_last[7:0]
0
Position of fault log pointer when
Mfr_temperature_peak2[7:0]
Mfr_temperature_peak2[15:8]
Mfr_temperature_min2[7:0]
Mfr_temperature_min2[15:8]
Mfr_iout_peak2[7:0]
Mfr_iout_peak2[15:8]
Mfr_iout_min2[7:0]
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
fault occurred.
SharedTime[7:0]
1
41-bit share-clock counter value
when fault occurred. Counter
LSB is in 200μs increments.
SharedTime[15:8]
2
SharedTime[23:16]
3
SharedTime[31:24]
4
Mfr_iout_min2[15:8]
Mfr_vout_peak3[7:0]
Mfr_vout_peak3[15:8]
Mfr_vout_min3[7:0]
SharedTime[39:32]
5
SharedTime[40]
6
Mfr_vout_peak0[7:0]
Mfr_vout_peak0[15:8]
Mfr_vout_min0[7:0]
Mfr_vout_min0[15:8]
Mfr_temperature_peak0[7:0]
Mfr_temperature_peak0[15:8]
Mfr_temperature_min0[7:0]
Mfr_temperature_min0[15:8]
Mfr_iout_peak0[7:0]
Mfr_iout_peak0[15:8]
Mfr_iout_min0[7:0]
7
8
Mfr_vout_min3[15:8]
Mfr_temperature_peak3[7:0]
Mfr_temperature_peak3[15:8]
Mfr_temperature_min3[7:0]
Mfr_temperature_min3[15:8]
Mfr_iout_peak3[7:0]
Mfr_iout_peak3[15:8]
Mfr_iout_min3[7:0]
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Mfr_iout_min3[15:8]
Status_vout0[7:0]
Mfr_iout_min0[15:8]
Mfr_vin_peak[7:0]
Status_iout0[7:0]
Status_mfr_specific0[7:0]
Status_vout1[7:0]
Mfr_vin_peak[15:8]
Mfr_vin_min[7:0]
Status_iout1[7:0]
Mfr_vin_min[15:8]
Status_mfr_specific1[7:0]
Status_vout2[7:0]
Mfr_vout_peak1[7:0]
Mfr_vout_peak1[15:8]
Mfr_vout_min1[7:0]
Mfr_vout_min1[15:8]
Mfr_temperature_peak1[7:0]
Mfr_temperature_peak1[15:8]
Mfr_temperature_min1[7:0]
Mfr_temperature_min1[15:8]
Mfr_iout_peak1[7:0]
Mfr_iout_peak1[15:8]
Mfr_iout_min1[7:0]
Status_iout2[7:0]
Status_mfr_specific2[7:0]
Status_vout3[7:0]
Status_iout3[7:0]
Status_mfr_specific3[7:0]
71 bytes for preamble
Fault_log [Position_last]
71
72
Fault_log [Position_last-1]
.
.
Mfr_iout_min1[15:8]
Mfr_vout_peak2[7:0]
Mfr_vout_peak2[15:8]
Mfr_vout_min2[7:0]
Mfr_vout_min2[15:8]
.
Fault_log [Position_last-170]
Reserved
237
238-
254
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LTC2974
PMBUS COMMAND DESCRIPTION
Table 2. Data Block Contents
POSITION
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
DATA
DATA
BYTE* DESCRIPTION
Number of loops: (238 – 71)/54
= 3.1
Read_vout1[15:8]
Status_vout1[7:0]
Status_mfr_specific1[7:0]
Read_temperature_1_1[7:0]
Read_temperature_1_1[15:8]
Status_temperature1[7:0]
Status_iout1[7:0]
*Note that PMBus data byte numbers start at 1 rather than 0.
See Figure 13 Block Read.
The data returned between bytes 71 and 237 of the
previous table is interpreted using Position_last and the
following table. The key to identifying the data located in
byte 71 is to locate the DATA corresponding to POSITION
= Position_last in the next table. Subsequent bytes are
identified by decrementing the value of POSITION. For
example: If Position_last = 8 then the first data returned
in a block read is Status_temperature of page 0 followed
by Read_temperature_1[15:8] of page 0 followed by
Read_temperature_1[7:0]ofpage0andsoon.SeeTable3.
Read_iout1[7:0]
Read_iout1[15:8]
Read_pout1[7:0]
Read_pout1[15:8]
Read_vout2[7:0]
Read_vout2[15:8]
Status_vout2[7:0]
Status_mfr_specific2[7:0]
Read_temperature_1_2[7:0]
Read_temperature_1_2[15:8]
Status_temperature2[7:0]
Status_iout2[7:0]
Table 3. Interpreting Cyclical Loop Data
POSITION
DATA
0
1
Read_temperature_2[7:0]
Read_temperature_2[15:8]
Read_vout0[7:0]
Read_iout2[7:0]
2
Read_iout2[15:8]
3
Read_vout0[15:8]
Status_vout0[7:0]
Status_mfr_specific0[7:0]
Read_temperature_1_0[7:0]
Read_temperature_1_0[15:8]
Status_temperature0[7:0]
Status_iout0[7:0]
Read_iout0[7:0]
Read_pout2[7:0]
4
Read_pout2[15:8]
5
Read_vout3[7:0]
6
Read_vout3[15:8]
7
Status_vout3[7:0]
8
Status_mfr_specific3[7:0]
Read_temperature_1_3[7:0]
Read_temperature_1_3[15:8]
Status_temperature3[7:0]
Status_iout3[7:0]
9
10
11
12
13
14
15
16
17
18
Read_iout0[15:8]
Read_pout0[7:0]
Read_pout0[15:8]
Read_vin[7:0]
Read_iout3[7:0]
Read_iout3[15:8]
Read_vin[15:8]
Read_pout3[7:0]
Status_input[7:0]
0x0
Read_pout3[15:8]
Total Bytes = 54
Read_vout1[7:0]
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PMBUS COMMAND DESCRIPTION
MFR_FAULT_LOG Read Example
PREAMBLE INFORMATION
BYTE BYTE
The following table fully decodes a sample fault log read
with Position_last = 13 to help clarify the cyclical nature
of the operation.
NUMBER NUMBER
DECIMAL
HEX
DATA
DESCRIPTION
28
1C
Mfr_temperature_
peak1[15:8]
Data Block Contents
29
30
1D
1E
Mfr_temperature_
min1[7:0]
PREAMBLE INFORMATION
BYTE
BYTE
Mfr_temperature_
min1[15:8]
NUMBER NUMBER
DECIMAL
HEX
DATA
DESCRIPTION
31
32
33
34
35
36
37
38
39
1F
20
21
22
23
24
25
26
27
Mfr_iout_peak1[7:0]
Mfr_iout_peak1[15:8]
Mfr_iout_min1[7:0]
Mfr_iout_min1[15:8]
Mfr_vout_peak2[7:0]
Mfr_vout_peak2[15:8]
Mfr_vout_min2[7:0]
Mfr_vout_min2[15:8]
0
00
Position_last[7:0] = 13 Position of fault-
log pointer when
fault occurred.
1
2
01
02
03
04
05
06
07
08
09
0A
0B
SharedTime[7:0]
41-bit share-
clock counter
value when fault
occurred. Counter
LSB is in 200µs
increments.
SharedTime[15:8]
SharedTime[23:16]
SharedTime[31:24]
SharedTime[39:32]
SharedTime[40]
3
4
5
Mfr_temperature_
peak2[7:0]
6
7
Mfr_vout_peak0[7:0]
Mfr_vout_peak0[15:8]
Mfr_vout_min0[7:0]
Mfr_vout_min0[15:8]
40
41
42
28
29
2A
Mfr_temperature_
peak2[15:8]
8
9
Mfr_temperature_
min2[7:0]
10
11
Mfr_temperature_
peak0[7:0]
Mfr_temperature_
min2[15:8]
12
13
14
0C
0D
0E
Mfr_temperature_
peak0[15:8]
43
44
45
46
47
48
49
50
51
2B
2C
2D
2E
2F
30
31
32
33
Mfr_iout_peak2[7:0]
Mfr_iout_peak2[15:8]
Mfr_iout_min2[7:0]
Mfr_iout_min2[15:8]
Mfr_vout_peak3[7:0]
Mfr_vout_peak3[15:8]
Mfr_vout_min3[7:0]
Mfr_vout_min3[15:8]
Mfr_temperature_
min0[7:0]
Mfr_temperature_
min0[15:8]
15
16
17
18
19
20
21
22
23
24
25
26
27
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
Mfr_iout_peak0[7:0]
Mfr_iout_peak0[15:8]
Mfr_iout_min0[7:0]
Mfr_iout_min0[15:8]
Mfr_vin_peak_[7:0]
Mfr_vin_peak_[15:8]
Mfr_vin_min_[7:0]
Mfr_vin_min_[15:8]
Mfr_vout_peak1[7:0]
Mfr_vout_peak1[15:8]
Mfr_vout_min1[7:0]
Mfr_vout_min1[15:8]
Mfr_temperature_
peak3[7:0]
52
53
54
34
35
36
Mfr_temperature_
peak3[15:8]
Mfr_temperature_
min3[7:0]
Mfr_temperature_
min3[15:8]
55
56
57
58
59
37
38
39
3A
3B
Mfr_iout_peak3[7:0]
Mfr_iout_peak3[15:8]
Mfr_iout_min3[7:0]
Mfr_iout_min3[15:8]
Status_vout0[7:0]
Mfr_temperature_
peak1[7:0]
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PMBUS COMMAND DESCRIPTION
PREAMBLE INFORMATION
CYCLICAL MUX LOOP DATA
LOOP
BYTE
BYTE
BYTE
NUMBER NUMBER
BYTE
BYTE
DECIMAL
HEX
DATA
DESCRIPTION
NUMBER NUMBER NUMBER
54 BYTES PER
LOOP
DECIMAL
HEX DECIMAL
MUX LOOP 1
Read_pout3[15:8]
Read_pout3[7:0]
Read_iout3[15:8]
Read_iout3[7:0]
Status_iout3[7:0]
60
61
3C
Status_iout0[7:0]
85
86
87
88
89
90
55
56
57
58
59
5A
53
52
51
50
49
48
3D
Status_
temperature0[7:0]
62
63
64
3E
3F
40
Status_vout1[7:0]
Status_iout1[7:0]
Status_
temperature1[7:0]
Status_
65
66
67
41
42
43
Status_vout2[7:0]
Status_iout2[7:0]
temperature3[7:0]
91
92
93
5B
5C
5D
47
46
45
Read_
temperature_1_3[15:8]
Status_
temperature2[7:0]
Read_
temperature_1_3[7:0]
68
69
70
44
45
46
Status_vout3[7:0]
Status_iout3[7:0]
Status_mfr_
specific3[7:0]
Status_
temperature3[7:0]
End of Preamble
94
95
5E
5F
60
61
62
63
64
65
66
44
43
42
41
40
39
38
37
36
Status_vout3[7:0]
Read_vout3[15:8]
Read_vout3[7:0]
Read_pout2[15:8]
Read_pout2[7:0]
Read_iout2[15:8]
Read_iout2[7:0]
Status_iout2[7:0]
CYCLICAL MUX LOOP DATA
LOOP
BYTE
96
BYTE
BYTE
97
NUMBER NUMBER NUMBER
54 BYTES PER
LOOP
98
DECIMAL
HEX DECIMAL
MUX LOOP 0
Read_pout0[15:8]
Read_pout0[7:0]
Read_iout0[15:8]
Read_iout0[7:0]
Status_iout0[7:0]
99
71
72
73
74
75
76
47
48
49
4A
4B
4C
13
12
11
10
9
Position_last
100
101
102
Status_
temperature2[7:0]
103
104
105
67
78
69
35
34
33
Read_
temperature_1_2[15:8]
8
Status_
temperature0[7:0]
Read_
temperature_1_2[7:0]
77
78
79
4D
4E
4F
7
6
5
Read_
temperature_1_0[15:8]
Status_mfr_
specific2[7:0]
Read_
temperature_1_0[7:0]
106
107
108
109
110
111
112
113
114
6A
6B
6C
6D
6E
6F
70
71
72
32
31
30
29
28
27
26
25
24
Status_vout2[7:0]
Read_vout2[15:8]
Read_vout2[7:0]
Read_pout1[15:8]
Read_pout1[7:0]
Read_iout1[15:8]
Read_iout1[7:0]
Status_iout1[7:0]
Status_mfr_
specific0[7:0]
80
81
82
83
50
51
52
53
4
3
2
1
Status_vout0[7:0]
Read_vout0[15:8]
Read_vout0[7:0]
Read_
temperature_2[15:8]
84
54
0
Read_
temperature_2[7:0]
Status_
temperature2[7:0]
115
73
23
Read_
temperature_1_1[15:8]
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PMBUS COMMAND DESCRIPTION
CYCLICAL MUX LOOP DATA
CYCLICAL MUX LOOP DATA
LOOP
BYTE
LOOP
BYTE
BYTE
BYTE
BYTE
BYTE
NUMBER NUMBER NUMBER
54 BYTES PER
LOOP
NUMBER NUMBER NUMBER
54 BYTES PER
LOOP
DECIMAL
HEX DECIMAL
MUX LOOP 1
DECIMAL
HEX DECIMAL
MUX LOOP 2
116
74
75
22
21
Read_
144
90
91
92
93
48
47
46
45
Status_
temperature_1_1[7:0]
temperature3[7:0]
117
Status_mfr_
specific1[7:0]
145
146
147
Read_
temperature_1_3[15:8]
118
119
120
121
122
123
124
125
126
127
128
129
130
76
77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
20
19
18
17
16
15
14
13
12
11
10
9
Status_vout1[7:0]
Read_vout1[15:8]
Read_vout1[7:0]
0x0
Read_
temperature_1_3[7:0]
Status_mfr_
specific3[7:0]
148
149
150
151
152
153
154
155
156
94
95
96
97
98
99
9A
9B
9C
44
43
42
41
40
39
38
37
36
Status_vout3[7:0]
Read_vout3[15:8]
Read_vout3[7:0]
Read_pout2[15:8]
Read_pout2[7:0]
Read_iout2[15:8]
Read_iout2[7:0]
Status_iout2[7:0]
Status_input[7:0]
Read_vin[15:8]
Read_vin[7:0]
Read_pout0[15:8]
Read_pout0[7:0]
Read_iout0[15:8]
Read_iout0[7:0]
Status_iout0[7:0]
Status_
temperature2[7:0]
8
Status_
temperature0[7:0]
157
158
159
9D
9E
9F
35
34
33
Read_
temperature_1_2[15:8]
131
132
133
83
84
85
7
6
5
Read_
temperature_1_0[15:8]
Read_
temperature_1_2[7:0]
Read_
temperature_1_0[7:0]
Status_mfr_
specific2[7:0]
Status_mfr_
specific0[7:0]
160
161
162
163
164
165
166
167
168
A0
A1
A2
A3
A4
A5
A6
A7
A8
32
31
30
29
28
27
26
25
24
Status_vout2[7:0]
Read_vout2[15:8]
Read_vout2[7:0]
Read_pout1[15:8]
Read_pout1[7:0]
Read_iout1[15:8]
Read_iout1[7:0]
Status_iout1[7:0]
134
135
136
137
86
87
88
89
4
3
2
1
Status_vout0[7:0]
Read_vout0[15:8]
Read_vout0[7:0]
Read_
temperature_2[15:8]
138
8A
0
Read_
temperature_2[7:0]
CYCLICAL MUX LOOP DATA
LOOP
BYTE
NUMBER NUMBER NUMBER
Status_
temperature2[7:0]
BYTE
BYTE
54 BYTES PER
LOOP
169
170
171
A9
AA
AB
23
22
21
Read_
temperature_1_1[15:8]
DECIMAL
HEX DECIMAL
MUX LOOP 2
Read_pout3[15:8]
Read_pout3[7:0]
Read_iout3[15:8]
Read_iout3[7:0]
Status_iout3[7:0]
139
8B
8C
8D
8E
8F
53
52
51
50
49
Read_
temperature_1_1[7:0]
140
141
Status_mfr_
specific1[7:0]
142
172
173
AC
AD
20
19
Status_vout1[7:0]
Read_vout1[15:8]
143
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LTC2974
PMBUS COMMAND DESCRIPTION
CYCLICAL MUX LOOP DATA
CYCLICAL MUX LOOP DATA
LOOP
BYTE
LOOP
BYTE
BYTE
BYTE
BYTE
BYTE
NUMBER NUMBER NUMBER
54 BYTES PER
LOOP
NUMBER NUMBER NUMBER
54 BYTES PER
LOOP
DECIMAL
174
HEX DECIMAL
MUX LOOP 2
Read_vout1[7:0]
0x0
DECIMAL
HEX DECIMAL
MUX LOOP 3
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
18
17
16
15
14
13
12
11
10
9
201
C9
45
Status_mfr_
specific3[7:0]
175
202
203
204
205
206
207
208
209
210
CA
CB
CC
CD
CE
CF
44
43
42
41
40
39
38
37
36
Status_vout3[7:0]
Read_vout3[15:8]
Read_vout3[7:0]
Read_pout2[15:8]
Read_pout2[7:0]
Read_iout2[15:8]
Read_iout2[7:0]
Status_iout2[7:0]
176
Status_input[7:0]
Read_vin[15:8]
Read_vin[7:0]
177
178
179
Read_pout0[15:8]
Read_pout0[7:0]
Read_iout0[15:8]
Read_iout0[7:0]
Status_iout0[7:0]
180
181
D0
D1
D2
182
183
Status_
temperature2[7:0]
184
8
Status_
temperature0[7:0]
211
212
213
D3
D4
D5
35
34
33
Read_
185
186
187
B9
BA
BB
7
6
5
Read_
temperature_1_2[15:8]
temperature_1_0[15:8]
Read_
temperature_1_2[7:0]
Read_
temperature_1_0[7:0]
Status_mfr_
specific2[7:0]
Status_mfr_
specific0[7:0]
214
215
216
217
218
219
220
221
222
D6
D7
D8
D9
DA
DB
DC
DD
DE
32
31
30
29
28
27
26
25
24
Status_vout2[7:0]
Read_vout2[15:8]
Read_vout2[7:0]
Read_pout1[15:8]
Read_pout1[7:0]
Read_iout1[15:8]
Read_iout1[7:0]
Status_iout1[7:0]
188
189
190
191
BC
BD
BE
BF
4
3
2
1
Status_vout0[7:0]
Read_vout0[15:8]
Read_vout0[7:0]
Read_
temperature_2[15:8]
192
C0
0
Read_
temperature_2[7:0]
CYCLICAL MUX LOOP DATA
LOOP
BYTE
NUMBER NUMBER NUMBER
Status_
temperature2[7:0]
BYTE
BYTE
54 BYTES PER
LOOP
223
224
225
DF
E0
E1
23
22
21
Read_
temperature_1_1[15:8]
DECIMAL
HEX DECIMAL
MUX LOOP 3
Read_pout3[15:8]
Read_pout3[7:0]
Read_iout3[15:8]
Read_iout3[7:0]
Status_iout3[7:0]
193
C1
C2
C3
C4
C5
C6
53
52
51
50
49
48
Read_
temperature_1_1[7:0]
194
195
Status_mfr_
specific1[7:0]
196
197
226
227
228
229
230
231
232
E2
E3
E4
E5
E6
E7
E8
20
19
18
17
16
15
14
Status_vout1[7:0]
Read_vout1[15:8]
Read_vout1[7:0]
0x0
198
Status_
temperature_3[7:0]
199
200
C7
C8
47
46
Read_
temperature_1_3[15:8]
Status_input[7:0]
Read_vin[15:8]
Read_vin[7:0]
Read_
temperature_1_3[7:0]
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LTC2974
PMBUS COMMAND DESCRIPTION
CYCLICAL MUX LOOP DATA
LOOP
BYTE
BYTE
BYTE
NUMBER NUMBER NUMBER
54 BYTES PER
LOOP
DECIMAL
233
HEX DECIMAL
MUX LOOP 3
Read_pout0[15:8]
Read_pout0[7:0]
Read_iout0[15:8]
Read_iout0[7:0]
Status_iout0[7:0]
E9
EA
EB
EC
ED
13
12
11
10
9
234
235
236
237
Last valid fault
log byte
238
EE
0x00
Bytes EE - FE
return 0x00
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
This is PMBUS
byte 255. It must
be read to clear
Mfr_fault_log_
status_ram.
IDENTIFICATION/INFORMATION
CMD
DEFAULT REF
PAGED FORMAT UNITS EEPROM VALUE PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
CAPABILITY
0x19 Summary of PMBus optional communication
protocols supported by this device.
R Byte
N
Reg
0xB0
0x11
79
79
PMBUS_REVISION
0x98 PMBus revision supported by this device.
Current revision is 1.1.
R Byte
N
Reg
MFR_SPECIAL_ID
MFR_SPECIAL_LOT
0xE7 Manufacturer code for identifying the LTC2974. R Word
N
Y
Reg
Reg
Y
Y
0x0213
79
79
0xE8 Customer dependent codes that identify the
factory programmed user configuration stored
in EEPROM. Contact factory for default value.
R Byte
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LTC2974
PMBUS COMMAND DESCRIPTION
CAPABILITY
The CAPABILITY command provides a way for a host system to determine some key capabilities of the LTC2974.
CAPABILITY Data Contents
BIT(S) SYMBOL
OPERATION
b[7] Capability_pec
Hard coded to 1 indicating Packet Error Checking is supported. Reading the Mfr_config_all_pec_en bit will indicate
whether PEC is currently required.
b[6:5] Capability_scl_max Hard coded to 01b indicating the maximum supported bus speed is 400kHz.
b[4] Capability_smb_alert Hard coded to 1 indicating this device does have an ALERTB pin and does support the SMBus Alert Response Protocol.
b[3:0] Reserved
Always returns 0.
PMBus_REVISION
PMBus_REVISION Data Contents
BIT(S) SYMBOL
OPERATION
Reports the PMBus standard revision compliance. This is hard-coded to 0x11 for revision 1.1.
b[7:0] PMBus_rev
MFR_SPECIAL_ID
This register contains the manufacturer ID for the LTC2974. Always returns 0x0213.
MFR_SPECIAL_LOT
These paged registers contain information that identifies the user configuration that was programmed at the factory.
Contact the factory to request a custom factory programmed user configuration and special lot number.
USER SCRATCHPAD
CMD
DEFAULT REF
COMMAND NAME
USER_DATA_00
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM VALUE PAGE
0xB0 Manufacturer reserved for LTpowerPlay.
0xB1 Manufacturer reserved for LTpowerPlay.
0xB2 OEM Reserved.
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word
N
Y
N
Y
N
Y
Y
Reg
Reg
Reg
Reg
Reg
Reg
Reg
Y
Y
Y
Y
Y
Y
N/A
N/A
N/A
0x00
0x00
NA
79
79
79
79
79
79
79
USER_DATA_01
USER_DATA_02
USER_DATA_03
0xB3 Scratchpad location.
USER_DATA_04
0xB4 Scratchpad location.
MFR_LTC_RESERVED_1
MFR_LTC_RESERVED_2
0xB5 Manufacturer reserved.
0xBC Manufacturer reserved.
NA
USER_DATA_00, USER_DATA_01, USER_DATA_02, USER_DATA_03, USER_DATA_04, MFR_LTC_RESERVED_1
and MFR_LTC_RESERVED_2
These registers are provided as user scratchpad and additional manufacturer reserved locations.
USER_DATA_03 and USER_DATA_04 are available for user scratch pad use. These 10 bytes (1 unpaged word plus
4 paged words) might be used for traceability or revision information such as serial number, board model number,
assembly location, or assembly date.
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LTC2974
APPLICATIONS INFORMATION
OVERVIEW
V
pins. All functionality is available when using this
DD33
alternate power method. The higher voltages needed for
the V pins and bias for the V pins are charge
The LTC2974 is a power management IC that is capable
of sequencing, margining, trimming, supervising output
voltage for OV/UV conditions, supervising output current
for OC/UC conditions, fault management, and voltage/
current/temperature readback for four DC/DC converter
channels.InputvoltageandLTC2974junctiontemperature
readback are also available. Linear Technology Power
System Managers can coordinate operation among mul-
tiple devices using common SHARE_CLK, FAULTB, and
CONTROL pins. The LTC2974 utilizes a PMBus compliant
interface and command set.
OUT_EN
SENSE
pumped from V
.
DD33
SETTING COMMAND REGISTER VALUES
The command register settings described herein are in-
tendedasareferenceandforthepurposeofunderstanding
the registers in a software development environment. In
actualpractice,theLTC2974canbecompletelyconfigured
for stand-alone operation with the LTC USB to I C/SMBus/
PMBus controller (DC1613) and software GUI using intui-
tive menu driven objects.
2
POWERING THE LTC2974
SEQUENCE, SERVO, MARGIN AND RESTART
OPERATIONS
The LTC2974 can be powered two ways. The first method
requires that a voltage between 4.5V and 15V be applied
to the V
pin. See Figure 23. An internal linear regula-
PWR
tor converts V
internal circuitry of the LTC2974.
Command Units On or Off
down to 3.3V which drives all of the
PWR
Threecontrolparametersdeterminehowaparticularchan-
nelisturnedonandoff:TheCONTROLpins,theOPERATION
commandandthevalueoftheinputvoltagemeasuredatthe
Alternatively, power from an external 3.3V supply may be
applieddirectlytotheV
pins11and12usingavoltage
DD33
V
pin(V ). Inallcases,VINmustexceedVIN_ONin
IN_SNS
IN
between 3.13V and 3.47V. See Figure 24. Tie V
to the
PWR
ordertoenablethedevicetorespondtotheCONTROLpins
orOPERATIONcommands.WhenV dropsbelowVIN_OFF
IN
4.5V < V
< 15V
PWR
animmediateOFForsequenceoffafterTOFF_DELAYofall
channels will result (See Mfr_config_track_enn). Refer
to the OPERATION section in the data sheet for a detailed
descriptionoftheON_OFF_CONFIGcommand.
V
V
IN_SNS
PWR
0.1µF
0.1µF
0.1µF
V
V
V
V
DD33
DD33
DD25
DD25
LTC2974*
GND
Some examples of typical ON/OFF configurations are:
1. A DC/DC converter may be configured to turn on any
*SOME DETAILS
OMITTED FOR CLARITY
2978 F23
time V exceeds VIN_ON.
IN
2. A DC/DC converter may be configured to turn on only
when it receives an OPERATION command.
Figure 23. Powering LTC2974 Directly from an Intermediate Bus
3. A DC/DC converter may be configured to turn on only
via the CONTROL pin.
EXTERNAL 3.3V
0.1µF
V
PWR
V
V
V
V
DD33
DD33
DD25
DD25
4. A DC/DC converter may be configured to turn on only
when it receives an OPERATION command and the
CONTROL pin is asserted.
LTC2974*
GND
0.1µF
*SOME DETAILS
OMITTED FOR CLARITY
2978 F24
On Sequencing
Figure 24. Powering LTC2974 from External 3.3V Supply
The TON_DELAY command sets the amount of time that
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LTC2974
APPLICATIONS INFORMATION
a channel will wait following the start of an ON sequence
can be placed in a high impedance state thus allowing the
DC/DC converter output voltage to go to its nominal value,
DCn(NOM)
before its V
pin will enable a DC/DC converter. Once
OUT_EN
theDC/DCconverterhasbeenenabled,theTON_RISEvalue
determines the time at which the device soft-connects
the DAC and servos the DC/DC converter output to the
VOUT_COMMAND value. The TON_MAX_FAULT_LIMIT
value determines the time at which the device checks
for an undervoltage condition. If a TON_MAX_FAULT oc-
curs, the channel can be configured to disable the DC/DC
converter and propagate the fault to other channels using
the bidirectional FAULTB pins. Figure 25 shows a typical
on-sequence using the CONTROL pin. Note that overvolt-
agefaultsarecheckedagainsttheVOUT_OV_FAULT_LIMIT
value at all times the device is powered up and not in a
reset state nor margining while ignoring OVs.
V
.RefertotheMFR_CONFIG_LTC2974command
for details on how to configure the output voltage servo.
Servo Modes
The ADC, DAC and internal processor comprise a digital
servo loop that can be configured to operate in several
usefulmodes.Theservotargetreferstothedesiredoutput
voltage.
Continuous/non-continuous trim mode: MFR_
CONFIG_LTC2974 b[7]. In continuous trim mode, the
servo will update the DAC in a closed loop fashion each
timeittakesaV reading.Theupdaterateisdetermined
OUT
bythetimeittakestostepthroughtheADCMUXwhichis
no more than t
. See Electrical Characteristics
UPDATE_ADC
On State Operation
tableNote5. Innon-continuoustrimmode, theservowill
drive the DAC until the ADC measures the output voltage
desired and then stop updating the DAC.
Once a channel has reached the ON state, the OPERA-
TION command can be used to command the DC/DC
converter’s output to margin high, margin low, or return to
a nominal output voltage indicated by VOUT_COMMAND.
The user also has the option of configuring a channel to
continuouslytrimtheoutputoftheDC/DCconvertertothe
Non-continuous servo on warn mode: MFR_CONFIG_
LTC2974 b[7] = 0, b[6] = 1. When in non-continuous
mode, the LTC2974 will re-trim (re-servo) the output if
the output drifts beyond the OV or UV warn limits.
VOUT_COMMAND voltage, or the channel’s V
output
DACn
V
CONTROL
V
OUT_EN
VOUT_OV_FAULT_LIMIT
V
OUT_COMMAND
V
DC(NOM)
VOUT_UV_FAULT_LIMIT
V
OUT
2974 F25
TON_RISE
TON_DELAY
TON_MAX_FAULT_LIMIT
Figure 25. Typical ON Sequence Using Control Pin
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LTC2974
APPLICATIONS INFORMATION
DAC Modes
V
Off Threshold Voltage
OUT
The DACs that drive the V
pins can operate in several
The MFR_VOUT_DISCHARGE_THRESHOLD command
register allows the user to specify the OFF threshold that
the output voltage must decay below before the channel
can enter/re-enter the ON state. The OFF threshold voltage
is specified by multiplying MFR_VOUT_DISCHARGE_
THRESHOLD and VOUT_COMMAND. In the event that an
output voltage has not decayed below its OFF threshold
before attempting to enter the ON state, the channel will
continue to be held off, the appropriate bit is set in the
STATUS_MFR_SPECIFICregister, andtheALERTBpinwill
be asserted low. When the output voltage has decayed
belowitsOFFthreshold,thechannelcanentertheONstate.
DACn
useful modes. See MFR_CONFIG_LTC2974.
• Soft-connect. Using the LTC patented soft-connect
feature, the DAC output is driven to within 1 LSB of
the voltage at the DC/DC’s feedback node before con-
necting, to avoid introducing transients on the output.
This mode is used when servoing the output voltage.
During startup, the LTC2974 waits until TON_RISE has
expired before connecting the DAC. This is the most
common operating mode.
• Disconnected. DAC output is high Z.
• DAC manual with soft-connect. Non servo mode. The
DAC soft-connects to the feedback node. Soft-connect
drivestheDACcodetomatchthevoltageatthefeedback
node. After connection, the DAC is moved by writing
DAC codes to the MFR_DAC register.
Automatic Restart via MFR_RESTART_DELAY
Command and CONTROL pin
An automatic restart sequence can be initiated by driving
the CONTROL pin to the off state for >10μs and then re-
leasing it. The automatic restart disables all V
pins
OUT_EN
• DAC manual with hard connect. Non servo mode. The
DAC hard connects to the feedback node using the cur-
rent value in MFR_DAC. After connection, the DAC is
moved by writing DAC codes to the MFR_DAC register.
that are mapped to a particular CONTROL pin for a time
period = MFR_RESTART_DELAY and then starts all DC/
DCConvertersaccordingtotheirrespectiveTON_DELAYs.
(see Figure 26). V
pins are mapped to one of the
OUT_EN
CONTROLpinsbytheMFR_CONFIG_LTC2974command.
This feature allows a host that is about to reset to restart
the power in a controlled manner after it has recovered.
Margining
The LTC2974 margins and trims the output of a DC/DC
converter by forcing a voltage across an external resistor
connectedbetweentheDACoutputandthefeedbacknode
or the trim pin. Preset limits for margining are stored in
the VOUT_MARGIN_HIGH/LOW registers. Margining is
actuated by writing the appropriate bits to the OPERA-
TION register.
CONTROL
PIN BOUNCE
V
CONTROL
V
OUT_EN0
2974 F26
TOFF_DELAY0
MFR_RESTART_DELAY
TON_DELAY0
Margining requires the DAC to be connected. Margin
requests that occur when the DAC is disconnected will
be ignored.
Figure 26. Off Sequence with Automatic Restart
FAULT MANAGEMENT
Off Sequencing
Output Overvoltage, Undervoltage, Overcurrent, and
Undercurrent Faults
An off sequence is initiated using the CONTROL pin or the
OPERATIONcommand.TheTOFF_DELAYvaluedetermines
the amount of time that elapses from the beginning of the
off sequence until each channel’s V
low, thus disabling its DC/DC converter.
Thehigh-speedvoltagesupervisorOVandUVfaultthresh-
olds are configured using the VOUT_OV_FAULT_LIMIT
and VOUT_UV_FAULT_LIMIT commands, respectively.
TheVOUT_OV_FAULT_RESPONSEandVOUT_UV_FAULT_
pin is pulled
OUT_EN
RESPONSE registers determine the responses to
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LTC2974
APPLICATIONS INFORMATION
OV/UV faults. In addition, the high-speed current supervi-
sor OC and UC fault thresholds are configured using the
IOUT_OC_FAULT_LIMITandIOUT_UC_FAULT_LIMITcom-
mands, respectively. The IOUT_OC_FAULT_RESPONSE
and IOUT_UC_FAULT_RESPONSE commands determine
the responses to OC/UC faults. Fault responses can range
from disabling the DC/DC converter immediately, waiting
to see if the fault condition persists for some interval be-
fore disabling the DC/DC converter, or allowing the DC/DC
converter to continue operating in spite of the fault. If a
DC/DC converter is disabled, the LTC2974 can be config-
ured to retry one to six times, retry continuously without
limitation, or latch-off. The retry interval is specified using
the MFR_RETRY_DELAY command. Latched faults are
resetbytogglingtheCONTROLpin, usingtheOPERATION
command, or removing and reapplying the bias voltage to
VOUT_OV_WARN_LIMIT, VOUT_UV_WARN_LIMIT, and
IOUT_OC_WARN_LIMIT registers, respectively. Note that
thereisnoI
UCwarningthreshold. Ifawarningoccurs,
OUT
the corresponding bits are set in the status registers and
the ALERTB output is asserted low. Note that a warning
will never cause a V
converter.
output pin to disable a DC/DC
OUT_EN
Configuring the AUXFAULTB Output
The AUXFAULTB output may be used to indicate an output
OV, OC, or UC fault. Use the MFR_CONFIG2_LTC2974
and MFR_CONFIG3_LTC2974 registers to configure the
AUXFAULTB pin to assert low in response to VOUT_OV,
IOUT_OC or IOUT_UC fault conditions. The AUXFAULTB
output will stop pulling low when the LTC2974 is com-
manded to re-enter the ON state following a faulted-off
condition.
the V
pin. All fault and warning conditions result in
IN_SNS
the ALERTB pinbeing asserted lowandthecorresponding
bits being set in the status registers. The CLEAR_FAULTS
command resets the contents of the status registers and
de-asserts the ALERTB output.
A charge-pumped 5µA pull-up to 12V is also available on
the AUXFAULTB output. Refer to the MFR_CONFIG_ALL_
LTC2974 register description in the PMBUS COMMAND
DESCRIPTION section for more information.
Output Overvoltage, Undervoltage, and Overcurrent
Warnings
Figure 27 shows an application circuit where the AUX-
FAULTB output is used to trigger a SCR crowbar on the
intermediate bus in order to protect the DC/DC converter’s
load from a catastrophic fault such as a stuck top-gate.
OV, UV, and OC warning thresholds are processed by
the LTC2974’s ADC. These thresholds are set by the
R
Q1
SENSE
0.007Ω
Si4894BDY
V
IN
4.5V < V
< 15V
IBUS
C
BYPASS
V
V
OUT
IN_SNS
V
V
PWR
DAC0
DC/DC
CONVERTER
100Ω
68Ω
V
V
SENSE
GATE
LTC4210-1
SENSEP0
CC
0.1µF
LTC2974*
24.3k
V
FB
LOAD
10k
0.01µF
ON
0.01µF
MCR12DC
MMBT2907
220Ω
TIMER GND
V
10k
SGND
SENSEM0
V
RUN/SS
0.22µF
OUT_EN0
4.99k
0.01µF
GND
2974 F27
REFP
AUXFAULTB
REFM
GND
V
V
V
V
DD25 DD25
DD33 DD33
*SOME DETAILS OMITTED FOR CLARITY
ONLY ONE OF FOUR CHANNELS SHOWN
0.1µF
0.1µF
Figure 27. Application Circuit with Crowbar Protection on Intermediate Bus
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LTC2974
APPLICATIONS INFORMATION
Multi-Channel Fault Management
command. In multi-part applications that are sensitive to
timingdifferences, itisrecommendedthattheVin_share_
enable bit of the MFR_CONFIG_ALL_LTC2974 register be
set high in order to allow SHARE_CLK to synchronize on/
off sequencing in response to the VIN_ON and VIN_OFF
thresholds.
Multi-channel fault management is handled using the
bidirectional FAULTB pins. Figure 28 illustrates the con-
nections between channels and the FAULTB pins.
• The MFR_FAULTBn_PROPAGATE register acts like a
programmableswitchthatallowsfaulted_offconditions
from a particular channel (PAGE) to propagate to either
FAULTBoutput.TheMFR_FAULTBn_RESPONSEregister
controls similar switches on the inputs to each channel
that allow any channel to shut down in response to any
combination of the FAULTB pins. Channels responding
to a FAULTB pin pulling low will attempt a new start
sequence when the FAULTB pin in question is released
by the faulted channel.
• Connecting all AUXFAULTB lines together will allow
selected faults on any DC/DC converter’s output in the
array to shut off a common input switch.
• ALERTB is typically one line in an array of PMBus con-
verters.TheLTC2974allowsarichcombinationoffaults
and warnings to be propagated to the ALERTB pin.
• WDI/RESETB can be used to put the LTC2974 in the
power-on reset state. Pull WDI/RESETB low for at least
t
to enter this state.
• A FAULTB pin can also be asserted low by an external
driver in order to initiate an immediate off-sequence
after a 10μs deglitch delay.
RESETB
• The FAULTB lines can be connected together to create
fault dependencies. Figure 29 shows a configuration
where a fault on any FAULTB will pull all others low.
This is useful for arrays where it is desired to abort
a startup sequence in the event any channel does not
come up (see Figure 30).
INTERCONNECT BETWEEN MULTIPLE LTC2974’S
Figure 29 shows how to interconnect the pins in a typical
multi-LTC2974 array.
• PWRGD reflects the status of the outputs that are
mapped to it by the MFR_PWRGD_EN command. Fig-
ure 29 shows all the PWRGD pins connected together,
but any combination may be used.
• All V
lines should be tied together in a star
IN_SNS
type connection at the point where V is to be sensed.
IN
This will minimize timing errors for the case where the
ON_OFF_CONFIGisconfiguredtostarttheLTC2974based
on V and ignore the CONTROL line and the OPERATION
IN
Mfr_faultb0_response, page = 0
Mfr_faultb0_propagate_chan0
FAULTED_OFF
CHANNEL 0
EVENT PROCESSOR
PAGE = 0
FAULTB0
FAULTB1
Mfr_faultb1_response, page = 0
Mfr_faultb1_propagate_chan0
Mfr_faultb0_response, page = 1
Mfr_faultb1_response, page = 1
Mfr_faultb0_propagate_chan1
Mfr_faultb1_propagate_chan1
FAULTED_OFF
FAULTED_OFF
FAULTED_OFF
CHANNEL 1
EVENT PROCESSOR
PAGE = 1
Mfr_faultb0_response, page = 2
Mfr_faultb1_response, page = 2
Mfr_faultb0_propagate_chan2
Mfr_faultb1_propagate_chan2
CHANNEL 2
EVENT PROCESSOR
PAGE = 2
Mfr_faultb0_response, page = 3
Mfr_faultb1_response, page = 3
Mfr_faultb0_propagate_chan3
Mfr_faultb1_propagate_chan3
CHANNEL 3
EVENT PROCESSOR
PAGE = 3
2974 F28
Figure 28. Channel Fault Management Block Diagram
2974fa
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LTC2974
APPLICATIONS INFORMATION
TO V OF
IN
TO INPUT
SWITCH
TO HOST CONTROLLER
DC/DCs
LTC2974 #1
VIN_SNS
LTC2974 #n
VIN_SNS
AUXFAULTB
AUXFAULTB
SDA
SCL
SDA
SCL
ALERTB
CONTROL0
ALERTB
CONTROL0
WDI/RESETB
FAULTB0
WDI/RESETB
FAULTB0
SHARE_CLK
PWRGD
SHARE_CLK
PWRGD
GND
GND
2974 F29
TO OTHER LTC2974s–10k EQUIVALENT PULL-UP RECOMMENDED
ON EACH LINE EXCEPT SHARE_CLK (USE 5.49k)
Figure 29. Typical Connections between Multiple LTC2974s
V
CONTROL
V
OUT0
TON_DELAY0
TON_DELAY1
V
V
OUT1
OUT2
TON_DELAY2
•
•
•
•
•
•
V
OUTn
TON_DELAYn
BUSSED
FAULTBn
V
PINS
2974 F30
TON_MAX_FAULT1
Figure 30. Aborted On-Sequence Due to Channel 1 Short
APPLICATION CIRCUITS
Four-Step Resistor Selection Procedure for DC/DC
Converters with External Feedback Resistors
Trimming and Margining DC/DC Converters with
External Feedback Resistors
The following four-step procedure should be used to
calculate the resistor values required for the application
circuit shown in Figure 31.
Figure 31 shows a typical application circuit for trimming/
margining a power supply with an external feedback
1. AssumevaluesforfeedbackresistorR20andthenominal
network. The V
and V
differential inputs
SENSEP0
SENSEM0
DC/DC converter output voltage V
for R10.
, and solve
DC(NOM)
sense the load voltage directly, and a correction voltage
is developed on the V pin by the closed-loop servo
DAC0
algorithm. The V
output is connected to the DC/DC
V
is the output voltage of the DC/DC converter
DAC0
DC(NOM)
when the LTC2974’s V
converter’s feedback node through resistor R30. For this
configuration, set Mfr_config_dac_pol to 0.
pin is in a high impedance
DAC0
2974fa
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LTC2974
APPLICATIONS INFORMATION
V
V
4.5V < V
< 15V
IN
IBUS
V
V
IN_SNS
PWR
OUT
0.1µF
V
DAC0
V
SENSEP0
DC/DC
CONVERTER
R30
V
V
V
V
DD33
DD33
DD25
DD25
R20
R10
LTC2974*
V
LOAD
FB
0.1µF
V
SGND
SENSEM0
V
RUN/SS
OUT_EN0
GND
GND
2974 F31
*SOME DETAILS OMITTED FOR CLARITY
ONLY ONE OF FOUR CHANNELS SHOWN
Figure 31. Application Circuit for DC/DC Converters with External Feedback Resistors
state. R10 is a function of R20, V
, the voltage at
4. Re-calculate the minimum, nominal, and maximum
DC/DC converter output voltages and the resulting
margining resolution.
DC(NOM)
the feedback node (V ) when the loop is in regulation,
FB
and the feedback node’s input current (I ).
FB
R20 • VFB
R10 =
R20
R10
(1)
VDC(NOM) = VFB • 1+
+IFB •R20
(4)
VDC(NOM) –IFB • R20 – V
FB
R20
R30
R20
R30
VDC(MIN) = VDC(NOM)
–
• V
– V
(5)
(6)
2. Solve for the value of R30 that yields the maximum
required DC/DC converter output voltage V
(
)
FB
DAC0(F /S)
.
DC(MAX)
VDC(MAX) = VDC(NOM)
+
• V
FB
When V
is at 0V, the output of the DC/DC converter
DAC0
is at its maximum voltage.
R20
• VDAC0(F /S)
R20 • VFB
R30 ≤
R30
(2)
VRES
=
V/DAC LSB
(7)
VDC(MAX) – VDC(NOM)
1024
3. Solve for the minimum value of V
that is needed
DAC0
Trimming and Margining DC/DC Converters with a
TRIM Pin
to yield the minimum required DC/DC converter output
voltage V
.
DC(MIN)
Figure 32 illustrates a typical application circuit for trim-
ming/margining the output voltage of a DC/DC converter
TheDAChastwofull-scalesettings, 1.38Vand2.65V. In
ordertoselecttheappropriatefull-scalesetting,calculate
with a TRIM Pin. The LTC2974’s V
pin connects to
DAC0
the minimum required V
output voltage:
DAC0(F/S)
the TRIM pin through resistor R30. For this configuration,
settheDACpolaritybitMfr_config_dac_polinMFR_CON-
FIG_LTC2974 to 1.
R30
VDAC0(F/S) > VDC(NOM) – VDC(MIN)
•
+ VFB (3)
(
)
R20
2974fa
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LTC2974
APPLICATIONS INFORMATION
V
V
4.5V < V
< 15V
IN
IBUS
+
O
V
V
IN_SNS
PWR
R30
0.1µF
TRIM
V
V
DAC0
V
SENSEP0
+
V
V
V
V
SENSE
DD33
DD33
DD25
DD25
DC/DC
LTC2974*
LOAD
CONVERTER
0.1µF
–
V
V
SENSEM0
SENSE
V
ON/OFFB
OUT_EN0
–
V
O
GND
2974 F32
*SOME DETAILS OMITTED FOR CLARITY
ONLY ONE OF FOUR CHANNELS SHOWN
Figure 32. Application Circuit for DC/DC Converters with Trim Pin
DC/DC converters with a TRIM pin may be margined
high or low by connecting an external resistor between
Two-Step Resistor and DAC Full-Scale Voltage Selection
Procedure for DC/DC Converters with a TRIM Pin
the TRIM pin and either the V
or V
pin. The
SENSEP
SENSEM
The following two-step procedure should be used to cal-
culatetheresistorvalueforR30andtherequiredfull-scale
DAC voltage (refer to Figure 32).
relationships between these resistors and the ∆% change
in the output voltage of the DC/DC converter are typically
expressed as:
1. Solve for R30:
RTRIM • 50
RTRIM_DOWN
=
– RTRIM
(8)
50 – ∆DOWN
%
∆
%
DOWN
R30 ≤ RTRIM
•
(10)
∆
%
DOWN
RTRIM_UP
=
2. Calculate the maximum required output voltage for
DAC0
V • 100 + ∆ %
2 • VREF • ∆UP %
50
∆UP %
(
)
–
UP
DC
V
:
RTRIM
•
– 1 (9)
∆UP %
VDAC ≥ 1+
• VREF
(11)
0
∆
%
where R
is the resistance looking into the TRIM pin,
DOWN
TRIM
V
V
is the TRIM pin’s open-circuit output voltage and
is the DC/DC converter’s nominal output voltage.
REF
DC
∆ % and ∆
UP
Note:NotallDC/DCconvertersfollowthesetrimequations,
especially newer bricks. Consult LTC Field Application
Engineering.
% denote the percentage change in the
DOWN
converter’s output voltage when margining up or down,
respectively.
2974fa
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LTC2974
APPLICATIONS INFORMATION
Measuring Current with a Sense Resistor
C
CM1
=L/(DCR•R ).C
shouldbeselectedtoprovide
CM1
CM2
a second stage corner frequency at < 1/10 of the DC/DC
converter’sswitchingfrequency.Inaddition,C needsto
A circuit for measuring current with a sense resistor is
shown in Figure 33. The balanced filter rejects both com-
mon mode and differential mode noise from the output
of the DC/DC converter. The filter is placed directly across
the sense resistor in series with the DC/DC converter’s in-
ductor. Note that the current sense inputs must be limited
CM2
be much smaller than C
in order to prevent significant
CM1
loading of the filter’s first stage.
Single Phase Design Example
As a design example for a DCR current sense application,
to less than 6V with respect to ground. Select R and
CM
assume L = 2.2μH, DCR = 10mΩ, and F = 500kHz.
C
such that the filter’s corner frequency is < 1/10 the
SW
CM
DC/DC converter’s switching frequency. This will result in
a current sense waveform that offers a good compromise
between the voltage ripple and the delay through the filter.
Let R
= 1kΩ and solve for C
:
CM1
CM1
2.2µH
10mΩ •1kΩ
CCM1
≥
= 220nF
Avalue1kΩforR issuggestedinordertominimizegain
CM
errors due to the current sense inputs’ internal resistance.
Let R
= 1kΩ. In order to get a second pole at
CM2
F /10 = 50kHz:
SW
Measuring Current with Inductor DCR
1
Figure 34 shows the circuit for applications that require
DCR current sense. A second order R-C filter is required
in these applications in order to minimize the ripple volt-
age seen at the current sense inputs. A value of 1kΩ
CCM2
≅
= 3.18nF
2π •50kHz •1kΩ
Let C
= 3.3nF. Note that since C
the loading effects of the second stage filter on the
matched first stage are not significant. Consequently, the
delay time constant through the filter for the current sense
waveform will be approximately 3μs.
is much less than
CM2
CM2
C
CM1
is suggested for R
and R
in order to minimize
CM1
CM2
gain errors due the current sense inputs’ internal resis-
tance. C should be selected to provide cancellation
CM1
of the zero created by the DCR and inductance, i.e.
Measuring Multiphase Currents
R
CM
CM
I
I
SENSEP
For current sense applications with more than one phase,
R-C averaging may be employed. Figure 35 shows an
example of this approach for a 3-phase system with DCR
current sensing. The current sense waveforms are aver-
aged together prior to being applied to the second stage of
C
C
CM
LTC2974
R
CM
SENSEM
L
R
SNS
2974 F33
LOAD CURRENT
Figure 33.Sense Resistor Current Sensing Circuits
the filter consisting of R
and C . Because the R
CM2
CM2 CM1
resistors for the three phases are in parallel, the value of
R
CM2
R
CM1
must be multiplied by the number of phases. Also
I
I
SENSEP
C
C
CM2
note that since the DCRs are effectively in parallel, the
value for IOUT_CAL_GAIN will be equal to the inductor’s
DCR divided by the number of phases. Care should be
taken in the layout of the multiphase inductors to keep the
PCB trace resistance from the DC side of each inductor to
the summing node balanced in order to provide the most
accurate results.
LTC2974
C
C
CM1
CM1
R
CM2
CM2
SENSEM
2974 F34
R
R
CM1
CM1
L
SWX0
DCR
Figure 34. DCR Current Sensing Circuits
2974fa
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LTC2974
APPLICATIONS INFORMATION
SWX1
R
CM1
R
CM1
R
CM1
R
CM2
C
CM2
C
CM2
I
I
SENSEP
L
LTC2974
SENSEM
DCR
2974 F35
R
CM1/3
R
CM2
C
CM1
C
CM2
DCR
L
DCR
L
TO LOAD
SWX2
SWX3
Figure 35. Multiphase DCR Current Sensing Circuits
Multiphase Design Example
Sensing Negative Voltages
Figure 37 shows the LTC2974 sensing a negative power
supply (V ). The R1/R2 resistor divider translates the
Using the same values for inductance and DCR from
the previous design example, the value for R
3kΩ for a three phase DC/DC converter if C
220nF. Similarly, the value for IOUT_CAL_GAIN will be
DCR/3 = 3.33mΩ.
will be
CM1
EE
is left at
negative supply voltage to the LTC2974’s V
input
CM1
SENSEM1
while the V
input is tied to the REFP pin which has
SENSEP1
a typical output voltage of 1.23V. Read_vout is determined
from the following equation:
Anti-aliasing Filter Considerations
R2
R1
VEE = VREFP – READ_ VOUT •
+ 1 –
(
)
Noisy environments require an anti-aliasing filter on
the input to the LTC2974’s ADC. The R-C circuit shown
in Figure 36 is adequate for most situations. Keep
R40=R50≤200ΩtominimizeADCgainerrors, andselect
a value for capacitors C10 and C20 that does not add too
much additional response time to the OV/UV supervisor,
e.g. τ = 10μs (R = 100Ω, C = 0.10μF).
(14)
1µA •R2
Where READ_VOUT returns V
– V
SENSEP
SENSEM
Thevoltagedividershouldbeconfiguredinordertopresent
about 0.5V to the voltage sense inputs when the negative
supply reaches its POWER_GOOD_ON threshold so that
V
4.5V < V
IBUS
< 15V
IN
V
V
IN_SNS
V
PWR
OUT
0.1µF
V
DAC0
V
SENSEP0
DC/DC
R30
V
V
V
V
DD33
DD33
DD25
DD25
CONVERTER
R40
R50
R20
R10
C10
C20
LTC2974*
GND
V
LOAD
FB
0.1µF
V
SGND
SENSEM0
V
RUN/SS
OUT_EN0
GND
*SOME DETAILS OMITTED FOR CLARITY
ONLY ONE OF FOUR CHANNELS SHOWN
2974 F36
Figure 36. Anti-Aliasing Filter on VSENSE Lines
2974fa
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LTC2974
APPLICATIONS INFORMATION
4.5V < V
IBUS
< 15V
V
V
IN_SNS
PWR
LTC2974
1.23V TYP
0.1µF
REFP
REFM
SDA
V
SENSEP1
SCL
PMBus
INTERFACE
1µA AT 0.5V
0.1µF
R1 = 4.99k
R2 = 120k
ALERTB
CONTROL
V
SENSEM1
WDI/RESETB
FAULTB
V
= –12V
EE
SHARE_CLK
ASEL0
POWER_GOOD_ON = 0.5V FOR V POWER_GOOD = –11.414V
EE
PWRGD
WHERE V POWER_GOOD =
EE
ASEL1
V
REFP
– POWER_GOOD_ON (R2/R1 + 1) – 1µA • R2
WDI/RESETB
WP GND
ONLY ONE OF FOUR CHANNELS SHOWN,
SOME DETAILS OMITTED FOR CLARITY
2974 F37
Figure 37. Sensing Negative Voltages
the current flowing out of the V
pin is minimized
Figure39showstherecommendedschematictousewhen
the LTC2974 is powered by the system 3.3V through its
SENSEMn
to~1µA.TherelationshipbetweenthePOWER_GOOD_ON
registervalueandthecorrespondingnegativesupplyvalue
can be determined using equation 14.
V
and V
pins. The LTC4412 ideal OR’ing circuit
DD33
PWR
allowseitherthecontrollerorsystemtopowertheLTC2974.
Becauseofthecontroller’slimitedcurrentsourcingcapabil-
ity, only the LTC2974s, their associated pull up resistors
2
Connecting the DC1613 USB to I C/SMBus/PMBus
Controller to the LTC2974 in System
2
and the I C/SMBus pull-up resistors should be powered
2
The DC1613 USB to I C/SMBus/PMBus Controller can
fromtheORed3.3Vsupply.Inaddition,anydevicesharing
2
be interfaced to the LTC2974s on the user’s board for
programming, telemetry and system debug. The control-
ler, when used in conjunction with LTpowerPlay software,
providesapowerfulwaytodebuganentirepowersystem.
Failuresarequicklydiagnosedusingtelemetry,faultstatus
registers and the fault log. The final configuration can be
quickly developed and stored to the LTC2974’s EEPROM.
I C/SMBus bus connections with the LTC2974 should not
have body diodes between the SDA/SCL pins and its V
DD
node because this will interfere with bus communication
in the absence of system power.
2
TheDC1613controller’sI C/SMBusconnectionsareopto-
isolated from the PC’s USB port. The 3.3V supply from the
controller and the LTC2974’s V
pin can be paralleled
DD33
Figure 38 and Figure 39 illustrate application schematics
for powering, programming and communicating with one
or more LTC2974’s via the DC1613 I C/SMBus/PMBus
controller regardless of whether or not system power is
present.
because the LTC LDOs that generate these voltages can be
backdriven and draw <10μA. The controller’s 3.3V current
limit is 100mA.
2
Figure38showstherecommendedschematictousewhen
the LTC2974 is powered by the system intermediate bus
through its V
pin.
PWR
2974fa
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LTC2974
APPLICATIONS INFORMATION
REPEAT OUTLINED CIRCUIT FOR EVERY LTC2974
150k
49.9k
4.5V TO 15V
0.1µF
V
PWR
LTC2974*
Si1303
ISOLATED 3.3V
V
V
DD33
DD33
SCL
0.1µF
0.1µF
GND
SDA
V
V
DD25
DD25
TO DC1613
I C/SMBUS/PMBUS
CONTROLLER
2
10k
10k
5.49k
SCL
SDA
SHARE_CLK
WP GND
2974 F38
*PIN CONNECTIONS
OMITTED FOR CLARITY
TO/FROM OTHER
LTC2974s
Figure 38. DC1613 Controller Connections When VPWR Is Used
TP0101K-SOT23
OR’D 3.3V
V
SYSTEM 3.3V
PWR
0.1µF
0.1µF
LTC4412
SENSE
V
V
DD33
DD33
V
IN
GND
CTL
GATE
STAT
V
V
DD25
DD25
IDEAL DIODE
LTC2974*
ISOLATED 3.3V
SCL
SCL
SDA
GND
SHARE_CLK
SDA
WP GND
TO DC1613
I C/SMBUS/PMBUS
CONTROLLER
2
2974 F39
TO/FROM OTHER
LTC2974s
*PIN CONNECTIONS
OMITTED FOR CLARITY
2
NOTE: DC1613 CONTROLLER I C CONNECTIONS ARE OPTO-ISOLATED
ISOLATED 3.3V FROM LTC CONTROLLER CAN BE BACK DRIVEN AND WILL ONLY DRAW <10µA
ISOLATED 3.3V CURRENT LIMIT IS 100mA
Figure 39. DC1613 Controller Connections When LTC2974 Is Powered Directly from 3.3V
2974fa
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LTC2974
APPLICATIONS INFORMATION
ACCURATE DCR TEMPERATURE COMPENSATION
board temperature sensor, and the inductor thermal time
constant τ. The thermal resistance θ [°C/W], is used to
IS
Using the DC resistance of the inductor as a current shunt
element has several advantages – no additional power
loss, lower circuit complexity and cost. However, the
strongtemperaturedependenceoftheinductorresistance
and the difficulty in measuring the exact inductor core
temperatureintroduceerrorsinthecurrentmeasurement.
For copper, a change of inductor temperature of only 1°C
correspondstoapproximately0.39%currentgainchange.
Figure 40 shows a sample layout using the integrated
DC/DC converter LTC3601 (right) and its corresponding
thermalimage(left). Theconverterisproviding1.8V, 1.5A
to the output load.
calculate the steady state difference between the sensed
temperature T and the internal inductor temperature T
S
I
for a given power dissipated in the inductor P :
I
T – T = θ P = θ V I
IS DCR OUT
(1.1)
I
S
IS
I
Theadditionaltemperatureriseisusedforamoreaccurate
estimate of the inductor DC resistance R :
I
R = R0 (1 + a [T – T + θ V I ])
(1.2)
is the inductor DC voltage
is the RMS value of the output current, R0 is
I
S
REF
IS DCR OUT
In the equations above, V
drop, I
DCR
OUT
the inductor DC resistance at the reference temperature
T
andaisthetemperaturecoefficientoftheresistance.
Heat dissipation in the inductor under high load condi-
tions creates transient and steady state thermal gradients
between the inductor and the temperature sensor, and the
sensed temperature does not accurately represent the
inductor core temperature. This temperature gradient is
clearlyvisibleinthethermalimageofFigure40.Inaddition,
transient heating/cooling effects have to be accounted for
in order to reduce the transient errors introduced when
load current changes are faster than heat transfer time
constants of the inductor. Both of these problems are
addressed by introducing two additional parameters: the
REF
Since most inductors are made of copper, we can expect
a temperature coefficient close to a = 3900ppm/°C.
CU
For a given a, the remaining parameters θ and R0 can
IS
be calibrated at a single temperature using only two load
currents:
R2–R1 P2+P1 – R2+R1 P2–P1
(
)(
)
(
)(
)
R0=
(1.3)
(1.4)
a T2– T1 P2+P1 – P2–P1 2+ a T1+ T2– 2T
(
)(
)
(
)
(
)
REF
a R1+R2 T2– T1 – R2–R1 2+ a T1+ T2– 2T
(
(
)(
)(
)
)
(
(
)
(
)
1
aR0
REF
θIS
=
a T2– T1 P2+P1 – P2–P1 2+ a T1+ T2– 2T
)
(
)
REF
thermal resistance θ from the inductor core to the on-
IS
LTC3601
INDUCTOR
TEMPERATURE
SENSOR
2974 F40
Figure 40. Thermal Image of a DC/DC Converter Showing the Difference Between
the Actual Inductor Temperature and the Temperature Sensing Point
2974fa
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LTC2974
APPLICATIONS INFORMATION
The inductor resistance, R = V
/I
, power dis-
nominal DC resistance R0, and the settling characteristic
K
DCR(K) OUT(K)
sipation P = V
K
I and the sensed temperature
is used to measure the inductor thermal time constant τ.
K
DCR(K) OUT(K)
T ,(K=1,2)arerecordedforeachloadcurrent.Toincrease
To get the best performance, the temperature sensor has
to be as close as possible to the inductor and away from
other significant heat sources. For example in Figure 40,
the bipolar sense transistor is close to the inductor and
away from the switcher. Connecting the collector of the
PNPtothelocalpowergroundplaneassuresgoodthermal
contact to the inductor, while the base and emitter should
be routed to the LTC2974 separately, and the base con-
nected to the signal ground close to LTC2974.
theaccuracyincalculatingθ ,thetwoloadcurrentsshould
IS
be chosen around I1 = 10% and I2 = 90% of the current
range of the system.
Theinductorthermaltimeconstantτmodelsthefirstorder
thermalresponseoftheinductorandallowsaccurateDCR
compensation during load transients. During a transition
from low to high load current, the inductor resistance
increases due to the self-heating. If we apply a single load
step from the low current I1 to the higher current I2, the
voltage across the inductor will change instantaneously
from I1R1 to I2R1 and then slowly approach I2R2. Here
R1 is the steady state resistance at the given temperature
and load current I1, and R2 is the slightly higher DC resis-
tance at I2, due to the inductor self-heating. Note that the
LTpowerPlay: AN INTERACTIVE GUI FOR POWER
MANAGERS
LTpowerPlay is a powerful Windows based development
environment that supports Linear Technology Power Sys-
tem Manager ICs with EEPROM, including the LTC2974
4-channel PMBus Power System Manager. The software
supports a variety of different tasks. You can use LTpow-
erPlay to evaluate Linear Technology ICs by connecting
to a demo board system. LTpowerPlay can also be used
in an offline mode (with no hardware present) in order
to build a multi-chip configuration file that can be saved
and re-loaded at a later time. LTpowerPlay provides un-
precedented diagnostic and debug features. It becomes a
valuablediagnostictoolduringboardbring-uptoprogram
thepowermanagementschemeinasystem. LTpowerPlay
electrical time constant τ = L/R is several orders of mag-
EL
nitude shorter than the thermal one, and “instantaneous”
is relative to the thermal time constant. The two settled
regions give us the data sets (I1, T1, R1, P1) and (I2, T2,
R2, P2) and the two-point calibration technique (1.3-1.4)
is used to extract the steady-state parameters θ and R0
IS
(given a previously characterized average a). The relative
current error calculated using the steady-state expression
(1.2) will peak immediately after the load step, and then
decay to zero with the inductor thermal time constant τ.
∆I
I
2
(t)= a θIS V2•I2– V1•I1 e–t/τ
(1.5)
utilizes Linear Technology’s DC1613 USB-to-I C/SMBus/
(
)
PMBus Controller to communicate with one of many
potential targets, including the DC1809/DC1810 demo
board set, the DC1735 socketed programming board, or
a customer target system. The software also provides an
automatic update feature to keep the software current
with the latest set of device drivers and documentation.
A great deal of context sensitive help is available within
LTpowerPlay along with several tutorial demos. Complete
information is available at:
The time constant τ is calculated from the slope of the
best-fit line y = ln(∆I/I) = a1 + a2t:
1
a2
τ = –
(1.6)
In summary, a single load current step is all that is needed
tocalibratetheDCRcurrentmeasurement. Thestablepor-
tionsoftheresponsegiveusthethermalresistanceθ and
IS
www.linear.com/ltpowerplay
2974fa
93
For more information www.linear.com/LTC2974
LTC2974
APPLICATIONS INFORMATION
PCB ASSEMBLY AND LAYOUT SUGGESTIONS
down to the PCB or mother board substrate. It is a good
practice to minimize the presence of voids within the
exposed pad inter-connection. Total elimination of voids
is difficult, but the design of the exposed pad stencil is
key. Figure 42 shows a suggested screen print pattern.
The proposed stencil design enables out-gassing of the
solderpasteduringreflowaswellasregulatingthefinished
solder thickness. See IPC7525A
Bypass Capacitor Placement
The LTC2974 requires 0.1µF bypass capacitors between
the V
pins and GND, the V
pin and GND, and the
DD33
DD25
REFP pin and REFM pin. If the chip is being powered from
the V input, then that pin should also be bypassed to
PWR
GND by a 0.1µF capacitor. In order to be effective, these
capacitors should be made of a high quality ceramic
dielectric such as X5R or X7R and be placed as close to
the chip as possible.
Unused ADC Sense Inputs
Connect all unused ADC sense inputs (V
,
SENSEPn
) to GND. In a system
V
, I
or I
SENSEMn SENSEPn
SENSEMn
Exposed Pad Stencil Design
where the inputs are connected to removable cards and
maybeleftfloatingincertainsituations,connecttheinputs
to GND using 100k resistors. Place the 100k resistors
The LTC2974’s package is thermally and electrically ef-
ficient. This is enabled by the exposed die attach pad on
the under side of the package which must be soldered
before any filter components, as shown in Figure 41, to
2974fa
94
For more information www.linear.com/LTC2974
LTC2974
APPLICATIONS INFORMATION
V
SENSEP
LTC2974
SENSEM
QFN PACKAGE
APERATURE DESIGN 50% TO 80% REDUCTION
100k
GROUND PLANE
V
100k
2974 F41
Figure 41. Connecting Unused Inputs to GND
prevent loading of the filter. The temperature sense inputs
(T
)maybeleftfloating. Thetemperturereportedon
SENSEn
SENSEn
floating T
inputs will be the internal die temperature
(READ_TEMPERATURE_2).
PCB Board Layout
2974 F42
Mechanical stress on a PC board and soldering-induced
stress can cause the LTC2974’s reference voltage and the
voltage drift to shift. A simple way to reduce the stress-
related shifts is to mount the IC near the short edge of
the PC board, or in a corner. The board acts as a stress
boundary, or a region where the flexure of the board is
minimal.
Figure 42. Suggested Screen Pattern for Die Attach Pad
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95
For more information www.linear.com/LTC2974
LTC2974
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UP Package
64-Lead Plastic QFN (9mm × 9mm)
(Reference LTC DWG # 05-08-1705 Rev C)
0.70 ±0.05
7.15 ±0.05
7.50 REF
8.10 ±0.05 9.50 ±0.05
(4 SIDES)
7.15 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.75 ± 0.05
R = 0.115
TYP
9 .00 ± 0.10
(4 SIDES)
R = 0.10
TYP
63 64
0.40 ± 0.10
PIN 1 TOP MARK
(SEE NOTE 5)
1
2
PIN 1
CHAMFER
C = 0.35
7.15 ± 0.10
7.50 REF
(4-SIDES)
7.15 ± 0.10
(UP64) QFN 0406 REV C
0.200 REF
0.25 ± 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
6. DRAWING NOT TO SCALE
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96
For more information www.linear.com/LTC2974
LTC2974
REVISION HISTORY
REV
DATE DESCRIPTION
PAGE NUMBER
A
5/13 Title, Features and Description revised.
1
5, 9
6
Added specifications: t , t
, t
.
INIT UPDATE_ADC OFF_MIN
Changed V
minimums to 1.3 and 2.5 from 1.32 and 2.53.
FS_VDAC
Curve G08: Corrected Y-axis units from mA to µA.
Block Diagram revised.
10
15
2
RESETB section: Clarified I C disabled, 10k resistor and capacitance.
18
Typical Delay numbers in EEPROM Related Commands table updated.
19
TON_RISE Description: Changed “output starts to rise” to “V
pin goes high.”
24, 51
26, 44
OUT_ENn
Changed data format for MFR_DAC and MFR_I2C_BASE_ADDRESS to Reg from U16. Changed default value for
MFR_SPECIAL_ID to 0x0213 from 0x0212.
Removed U16 row from Data Formats table.
27
30, 31
32
Operation, ON_OFF_CONFIG sections: Added sentence on waiting a t
b[5:4] Operation: Added warning about undefined MFR_DAC.
.
OFF_MIN
b[3] to b[0] Operation: Clarified that setting these bits disables UV and UC.
Changed Format for MFR_RETRY_COUNT to Reg from U16.
36
54
STATUS_VOUT b[3] Operation: Clarified behavior after bit is cleared.
62
STATUS_MFR_SPECIFIC section: Added STICKY, ALERT, OFF columns; removed FAULT column. Added column
definitions above table.
64
STATUS_MFR_SPECIFIC b[6] and b[5]: Clarified behavior if MFR_TRACK_EN_CHANn is set.
MFR_VOUT_MIN: Clarified when updates are disabled.
64
69
MFR_FAULT_LOG_CLEAR: Clarified conditions before issuing this command.
MFR_SPECIAL_ID: Changed value from 0x0210 to 0x0213.
Added section: Unused ADC Sense Inputs.
71
78, 79
94
2974fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
97
LTC2974
TYPICAL APPLICATION
0.1µF
3.3V
0.1µF
9
65 28 13 14 11 12 10 36 35 51 52 55 56 59 60
8
330nF
330nF
MMBT3906
15
27
V
IN
V
IN
T
T
SENSE2
SENSE0
TG
TG
MMBT3906
SWX
SWX
53
1
57
61
V
V
V
DAC0
DAC2
BG
BG
V
SENSEP0
SENSEP2
DC/DC
CONVERTER
V
DC/DC
CONVERTER
V
LOAD
LOAD
FB
FB
2
62
V
V
I
RUN/SS SGND
PGND
SGND RUN/SS
PGND
SENSEM0
SENSEM2
SENSEM2
42
41
3
46
45
5
I
I
SENSEM0
SENSEP0
I
SENSEP2
V
OUT_EN2
V
OUT_EN0
19
20
21
37
39
GND
GND
GND
GND
GND
38
40
REFP
0.1µF
LTC2974
REFM
330nF
MMBT3906
330nF
MMBT3906
16
34
V
V
IN
IN
T
T
SENSE3
SENSE1
TG
TG
SWX
SWX
54
63
58
49
V
V
V
DAC1
DAC3
BG
BG
V
SENSEP1
SENSEP3
DC/DC
CONVERTER
V
DC/DC
CONVERTER
V
LOAD
LOAD
FB
FB
64
50
V
V
I
RUN/SS SGND
PGND
SGND RUN/SS
PGND
SENSEM1
SENSEM3
SENSEM3
44
43
4
48
47
6
I
I
SENSEM1
SENSEP1
I
SENSEP3
V
OUT_EN3
V
OUT_EN1
7
AUXFAULTB
0V
INTERMEDIATE
BUS
2974 TA02
3.3V
26 25 18 29 30 31 17 23 22 33 32
24
10k
10k
10k
10k
3.3V
3.3V
10k
10k
10k
10k
10k
10k
5.49k
10k
TO/FROM OTHER LTC2974s, LTC2978s AND MICROCONTROLLER
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
2
LTC2970
LTC2977
LTC3880
LTC3883
Dual I C Power Supply Monitor and Margining Controller 5V to 15V, 0.5% TUE 14-Bit ADC, 8-Bit DAC, Temperature Sensor
8-Channel PMBus Power System Manager
0.25% TUE 16-Bit ADC, Voltage/Temperature Monitoring and Supervision
0.5% TUE 16-Bit ADC, Voltage/Current/Temperature Monitoring and Supervision
Dual Output PolyPhase Step-Down DC/DC Controller
Single Output PolyPhase Step-Down DC/DC Controller 0.5% TUE 16-Bit ADC, Voltage/Current/Temperature Monitoring and Supervision
2974fa
LT 0513 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
98
●
●
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC2974
ꢀLINEAR TECHNOLOGY CORPORATION 2012
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