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LTC3788IUH [Linear]

2-Phase, Dual Output Synchronous Boost Controller; 两相双路输出同步升压型控制器
LTC3788IUH
型号： LTC3788IUH
厂家： Linear    Linear
描述：

2-Phase, Dual Output Synchronous Boost Controller
两相双路输出同步升压型控制器

控制器
文件： 总32页 (文件大小：422K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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LTC3788  
2-Phase, Dual Output  
Synchronous Boost Controller  
FEATURES  
DESCRIPTION  
The LTC®3788 is a high performance 2-phase dual  
synchronous boost converter controller that drives all  
N-channel power MOSFETs. Synchronous rectification  
increases efficiency, reduces power losses and eases  
thermal requirements, allowing the LTC3788 to be used  
in high power boost applications.  
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Synchronous Operation for Highest Efficiency and  
Reduced Heat Dissipation  
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Wide Input Range: 4.5V to 38V (40V Abs Max) and  
Operates Down to 2.5V After Start-Up  
Output Voltages Up to 60V  
±±1 ±.2V Reference Voltage  
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R
or Inductor DCR Current Sensing  
SENSE  
A constant-frequency current mode architecture allows a  
phase-lockable frequency of up to 850kHz. OPTI-LOOP®  
compensationallowsthetransientresponsetobeoptimized  
over a wide range of output capacitance and ESR values.  
The LTC3788 features a precision 1.2V reference and dual  
power good output indicators. A 4.5V to 38V input supply  
range encompasses a wide range of system architectures  
and battery chemistries.  
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±001 Duty Cycle Capability for Synchronous MOSFET  
Low Quiescent Current: 125μA  
Phase-Lockable Frequency (75kHz to 850kHz)  
Programmable Fixed Frequency (50kHz to 900kHz)  
Selectable Current Limit  
Adjustable Output Voltage Soft-Start  
Power Good Output Voltage Monitors  
Low Shutdown Current I : <8ꢀA  
Internal LDO Powers Gate Drive from VBIAS or EXTV  
Thermally Enhanced Low Profile 32-Pin 5mm × 5mm  
QFN Package  
Q
Independent SS pins for each controller ramp the output  
CC  
voltages during start-up. The PLLIN/MODE pin selects  
among Burst Mode operation, pulse-skipping mode or  
continuous inductor current mode at light loads.  
APPLICATIONS  
For a leaded 28-lead SSOP package with a fixed current  
limit and one PGOOD output, without phase modulation  
or a clock output, see the LTC3788-1 data sheet.  
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Industrial  
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Automotive  
L, LT, LTC, LTM, Linear Technology, Burst Mode, OPTI-LOOP, PolyPhase and the Linear logo  
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Medical  
are registered trademarks and No R  
and ThinSOT are trademarks of Linear Technology  
SENSE  
Corporation. All other trademarks are the property of their respective owners. Protected by  
U. S. Patents, including 5408150, 5481178, 5705919, 5929620, 6144194, 6177787, 6580258.  
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Military  
V
4.5V TO 12V START-UP VOLTAGE  
IN  
OPERATES THROUGH TRANSIENTS DOWN TO 2.5V  
TYPICAL APPLICATION  
V
IN  
Efficiency and Power Loss  
vs Output Current  
4.7μF  
TG2  
4.7μF  
220μF  
3mΩ  
4mΩ  
100  
90  
10000  
1000  
100  
10  
TG1 VBIAS INTV  
BOOST1  
CC  
3.3μH  
1.25μH  
BOOST2  
SW2  
V
V
OUT  
12V AT 5A  
OUT  
24V AT 3A  
80  
0.1μF  
0.1μF  
SW1  
70  
LTC3788  
BG1  
BG2  
60  
50  
+
+
SENSE1  
SENSE2  
40  
30  
20  
10  
0
–
–
SENSE1  
SENSE2  
RUN1  
PGND  
V
V
= 12V  
IN  
OUT  
110k  
1
= 24V  
RUN2  
VFB2  
VFB1  
232k  
Burst Mode OPERATION  
FIGURE 9 CIRCUIT  
PGOOD1  
FREQ  
PLLIN/MODE  
EXTV  
0.1  
CC  
0.00001 0.0001 0.001 0.01  
0.1  
1
10  
OUTPUT CURRENT (A)  
ITH1 SS1 SGND SS2 ITH2  
3788 TA01b  
15nF  
220μF  
220μF  
15nF  
2.7k  
100pF  
0.1μF  
220pF  
12.1k  
8.66k  
12.1k  
0.1μF  
3788 TA01a  
3788f  
1
LTC3788  
ABSOLUTE MAXIMUM RATINGS  
PIN CONFIGURATION  
(Note ±)  
TOP VIEW  
VBIAS......................................................... –0.3V to 40V  
BOOST1, BOOST2...................................... –0.3V to 76V  
SW1, SW2 ................................................. –0.3V to 70V  
RUN1, RUN2................................................ –0.3V to 8V  
Maximum Current Sourced into Pin  
32 31 30 29 28 27 26 25  
–
SENSE1  
FREQ  
1
2
3
4
5
6
7
8
24 BOOST1  
23 BG1  
from Source > 8V..............................................100μA  
PGOOD1, PGOOD2, PLLIN/MODE ............... –0.3V to 6V  
PHASMD  
CLKOUT  
PLLIN/MODE  
SGND  
VBIAS  
PGND  
22  
21  
33  
GND  
INTV , (BOOST1-SW1, BOOST2-SW2) ...... –0.3V to 6V  
CC  
20 EXTV  
CC  
CC  
EXTV ......................................................... –0.3V to 6V  
CC  
INTV  
19  
18 BG2  
17 BOOST2  
+
+
+
+
–
–
SENSE1 , SENSE1 ,  
RUN1  
SENSE2 , SENSE2 .................................... –0.3V to 40V  
RUN2  
–
–
SENSE1 – SENSE1 ,  
9
10 11 12 13 14 15 16  
SENSE2 – SENSE2 ................................. –0.3V to 0.3V  
, SS1, SS2, ITH1, ITH2, FREQ,  
I
LIM  
PHASMD, VFB1, VFB2 .......................... –0.3V to INTV  
CC  
UH PACKAGE  
32-LEAD (5mm s 5mm) PLASTIC QFN  
Operating Junction Temperature Range... –40°C to 125°C  
T
= 125°C, θ = 34°C/W  
JA  
EXPOSED PAD (PIN 33) IS GND, MUST BE SOLDERED TO PCB  
JMAX  
Storage Temperature Range...................–65°C to 125°C  
ORDER INFORMATION  
LEAD FREE FINISH  
LTC3788EUH#PBF  
LTC3788IUH#PBF  
TAPE AND REEL  
PART MARKING*  
3788  
PACKAGE DESCRIPTION  
TEMPERATURE RANGE  
LTC3788EUH#TRPBF  
LTC3788IUH#TRPBF  
–40°C to 125°C  
–40°C to 125°C  
32-Lead (5mm× 5mm) Plastic QFN  
32-Lead (5mm× 5mm) Plastic QFN  
3788  
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.  
Consult LTC Marketing for information on non-standard lead based finish parts.  
For more information on lead free part marking, go to: http://www.linear.com/leadfree/  
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/  
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating  
junction temperature range, otherwise specifications are at TA = 25°C, VBIAS = ±2V, unless otherwise noted (Note 2).  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
Main Control Loop  
VBIAS  
Chip Bias Voltage Operating Range  
Regulated Feedback Voltage  
Feedback Current  
4.5  
38  
1.212  
50  
V
V
l
V
I
= 1.2V (Note 4)  
TH  
1.188  
1.200  
5
FB1,2  
FB1,2  
I
(Note 4)  
nA  
V
Reference Line Voltage Regulation  
VBIAS = 6V to 38V  
0.002  
0.02  
%/V  
REFLNREG  
3788f  
2
LTC3788  
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating  
junction temperature range, otherwise specifications are at TA = 25°C, VBIAS = ±2V, unless otherwise noted (Note 2).  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
V
Output Voltage Load Regulation  
(Note 4)  
LOADREG  
l
l
Measured in Servo Loop;  
TH  
0.01  
–0.01  
2
0.1  
%
%
ΔI Voltage = 1.2V to 0.7V  
Measured in Servo Loop;  
–0.1  
ΔI Voltage = 1.2V to 2V  
TH  
g
Error Amplifier Transconductance  
Input DC Supply Current  
I
= 1.2V  
TH  
mmho  
m1,2  
I
Q
(Note 5)  
Pulse-Skipping or Forced Continuous Mode RUN1 = 5V and RUN2 = 0V or RUN1 = 0V  
(One Channel On) and RUN2 = 5V; V = 1.25V (No Load)  
0.9  
1.2  
mA  
mA  
μA  
FB1(2)  
Pulse-Skipping or Forced Continuous Mode RUN1,2 = 5V; V  
(Both Channels On)  
= 1.25V (No Load)  
FB1,2  
Sleep Mode  
(One Channel On)  
RUN1 = 5V and RUN2 = 0V or RUN1 = 0V  
and RUN2 = 5V; V = 1.25V (No Load)  
125  
200  
190  
300  
FB1(2)  
Sleep Mode  
(Both Channels On)  
RUN1,2 = 5V; V  
= 1.25V (No Load)  
μA  
FB1,2  
Shutdown  
RUN1,2 = 0V  
8
20  
μA  
V
l
l
l
UVLO  
INTV Undervoltage Lockout Thresholds  
V
V
V
Ramping Up  
4.1  
3.8  
1.28  
100  
4.5  
0.5  
10  
4.3  
CC  
INTVCC  
Ramping Down  
3.6  
V
INTVCC  
V
V
RUN Pin On Threshold  
RUN Pin Hysteresis  
Rising  
1.18  
1.38  
V
RUN1,2  
RUNHYS  
RUN1,2  
RUN1,2  
SS1,2  
RUN  
mV  
μA  
μA  
μA  
mV  
mV  
mV  
V
I
I
I
RUN Pin Hysteresis Current  
RUN Pin Current  
V
V
V
V
V
V
> 1.28V  
RUN  
< 1.28V  
RUN  
Soft-Start Charge Current  
Maximum Current Sense Threshold  
= GND  
7
13  
110  
82  
SS  
FB  
FB  
FB  
l
l
l
V
= 1.1V, I = INTV  
CC  
90  
68  
42  
2.5  
100  
75  
SENSE(MAX)  
LIM  
= 1.1V, I = Float  
LIM  
= 1.1V, I = GND  
50  
56  
LIM  
V
SENSE Pins Common Mode Range (BOOST  
Converter Input Supply Voltage V )  
38  
SENSE(CM)  
IN  
+
I
I
t
t
t
t
+
–
SENSE Pin Current  
V
V
C
C
C
C
= 1.1V, I = Float  
200  
300  
1
μA  
μA  
ns  
ns  
ns  
ns  
Ω
SENSE1,2  
SENSE1,2  
r(TG1,2)  
f(TG1,2)  
r(BG1,2)  
f(BG1,2)  
FB  
LIM  
–
SENSE Pin Current  
= 1.1V, I = Float  
LIM  
FB  
Top Gate Rise Time  
= 3300pF (Note 6)  
= 3300pF (Note 6)  
= 3300pF (Note 6)  
= 3300pF (Note 6)  
20  
20  
LOAD  
LOAD  
LOAD  
LOAD  
Top Gate Fall Time  
Bottom Gate Rise Time  
20  
Bottom Gate Fall Time  
20  
R
R
R
R
Top Gate Pull-Up Resistance  
Top Gate Pull-Down Resistance  
Bottom Gate Pull-Up Resistance  
Bottom Gate Pull-Down Resistance  
1.5  
1.5  
1.5  
1.5  
70  
UP(TG1,2)  
DN(TG1,2)  
UP(TG1,2)  
DN(TG1,2)  
D(TG/BG)  
Ω
Ω
Ω
t
Top Gate Off to Bottom Gate On  
Switch-On Delay Time  
C
C
= 3300pF (Each Driver)  
= 3300pF (Each Driver)  
ns  
LOAD  
LOAD  
t
Bottom Gate Off to Top Gate On  
Switch-On Delay Time  
70  
ns  
D(BG/TG)  
3788f  
3
LTC3788  
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating  
junction temperature range, otherwise specifications are at TA = 25°C, VBIAS = ±2V, unless otherwise noted (Note 2).  
SYMBOL  
DF  
PARAMETER  
CONDITIONS  
MIN  
TYP  
96  
MAX  
UNITS  
%
Maximum BG Duty Factor  
Minimum BG On-Time  
MAX(BG1,2)  
t
(Note 7)  
110  
ns  
ON(MIN)  
INTV Linear Regulator  
CC  
V
V
V
V
V
V
Internal V Voltage  
6V < VBIAS < 38V, V = 0V  
EXTVCC  
5.2  
5.2  
4.5  
5.4  
0.5  
5.4  
0.5  
4.8  
250  
5.6  
2
V
%
V
INTVCCVIN  
LDOVIN  
CC  
INTV Load Regulation  
I
= 0mA to 50mA, V  
= 0V  
CC  
CC  
EXTVCC  
Internal V Voltage  
V = 6V  
EXTVCC  
5.6  
2
INTVCCEXT  
LDOEXT  
CC  
INTV Load Regulation  
I
= 0mA to 40mA, V  
CC  
= 6V  
%
V
CC  
EXTVCC  
EXTV Switchover Voltage  
EXTV Ramping Positive  
5
EXTVCC  
CC  
CC  
EXTV Hysteresis  
mV  
LDOHYS  
CC  
Oscillator and Phase-Locked Loop  
f
Programmable Frequency  
R
R
R
= 25k  
= 60k  
= 100k  
= 0V  
105  
400  
760  
350  
535  
kHz  
kHz  
kHz  
kHz  
kHz  
kHz  
PROG  
FREQ  
FREQ  
FREQ  
FREQ  
FREQ  
335  
465  
f
f
f
Lowest Fixed Frequency  
Highest Fixed Frequency  
Synchronizable Frequency  
V
V
320  
485  
75  
380  
585  
850  
LOW  
HIGH  
SYNC  
= INTV  
CC  
l
PLLIN/MODE = External Clock  
PGOOD± and PGOOD2 Outputs  
V
PGOOD Voltage Low  
PGOOD Leakage Current  
PGOOD Trip Level  
I
= 2mA  
= 5V  
0.2  
0.4  
1
V
PGL  
PGOOD  
I
V
V
V
μA  
PGOOD  
PGOOD  
V
PG  
with Respect to Set Regulated Voltage  
Ramping Negative  
FB  
FB  
–12  
8
–10  
2.5  
10  
–8  
12  
%
%
%
%
μs  
Hysteresis  
Ramping Positive  
V
FB  
Hysteresis  
2.5  
25  
t
PGOOD Delay  
PGOOD Going High to Low  
PGOOD(DELAY)  
BOOST± and BOOST2 Charge Pump  
I
BOOST Charge Pump Available  
Output Current  
V
= 12V; V  
– V = 4.5V;  
SW1,2  
55  
μA  
BOOST1,2  
SW1,2  
BOOST1,2  
FREQ = 0V, Forced Continuous or  
Pulse-Skipping Mode  
Note ±: Stresses beyond those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. Exposure to any Absolute  
Maximum Rating condition for extended periods may affect device  
reliability and lifetime.  
Note 4: The LTC3788 is tested in a feedback loop that servos V to the  
FB  
output of the error amplifier while maintaining I at the midpoint of the  
TH  
current limit range.  
Note 5: Dynamic supply current is higher due to the gate charge being  
Note 2: The LTC3788E is guaranteed to meet specifications from 0°C  
to 85°C. Specifications over the –40°C to 125°C operating junction  
temperature range are assured by design, characterization and correlation  
with statistical process controls. The LTC3788I is guaranteed over the full  
–40°C to 125°C operating junction temperature range.  
delivered at the switching frequency.  
Note 6: Rise and fall times are measured using 10% and 90% levels.  
Delay times are measured using 50% levels.  
Note 7: See Minimum On-Time Considerations in the Applications  
Information section.  
Note 3: T is calculated from the ambient temperature T and power  
J
A
dissipation P according to the formula: T = T + (P • 34°C/W)  
D
J
A
D
3788f  
4
LTC3788  
TYPICAL PERFORMANCE CHARACTERISTICS  
Efficiency and Power Loss  
Efficiency and Power Loss  
vs Output Current  
vs Output Current  
100  
90  
10000  
1000  
100  
10  
100  
90  
10000  
80  
80  
1000  
100  
10  
70  
70  
60  
50  
60  
50  
40  
30  
20  
10  
0
40  
30  
20  
10  
0
V
V
= 12V  
IN  
OUT  
1
1
V
V
= 12V  
OUT  
FIGURE 9 CIRCUIT  
= 24V  
IN  
= 24V  
Burst Mode OPERATION  
FIGURE 9 CIRCUIT  
0.1  
0.1  
0.01  
0.1  
1
10  
0.00001 0.0001 0.001 0.01  
0.1  
1
10  
OUTPUT CURRENT (A)  
OUTPUT CURRENT (A)  
3788 G02  
3788 G01  
BURST EFFICIENCY  
BURST LOSS  
BURST EFFICIENCY  
BURST LOSS  
PULSE-SKIPPING  
EFFICIENCY  
PULSE-SKIPPING  
LOSS  
CCM EFFICIENCY  
CCM LOSS  
Load Step  
Forced Continuous Mode  
Efficiency vs Input Voltage  
100  
I
= 2A  
LOAD  
99 FIGURE 9 CIRCUIT  
LOAD STEP  
2A/DIV  
98  
V
= 12V  
97  
96  
95  
94  
93  
92  
91  
90  
OUT  
INDUCTOR  
CURRENT  
5A/DIV  
V
= 24V  
OUT  
V
OUT  
500mV/DIV  
3788 G04  
0
5
15  
INPUT VOLTAGE (V)  
20  
25  
10  
V
V
= 12V  
200μs/DIV  
IN  
OUT  
= 24V  
3788 G03  
FIGURE 9 CIRCUIT  
Load Step  
Pulse-Skipping Mode  
Load Step  
Burst Mode Operation  
LOAD STEP  
2A/DIV  
LOAD STEP  
2A/DIV  
INDUCTOR  
CURRENT  
5A/DIV  
INDUCTOR  
CURRENT  
5A/DIV  
V
V
OUT  
OUT  
500mV/DIV  
500mV/DIV  
3788 G05  
3788 G06  
V
V
= 12V  
200μs/DIV  
V
V
= 12V  
200μs/DIV  
IN  
OUT  
IN  
OUT  
= 24V  
= 24V  
FIGURE 9 CIRCUIT  
FIGURE 9 CIRCUIT  
3788f  
5
LTC3788  
TYPICAL PERFORMANCE CHARACTERISTICS  
Inductor Current at Light Load  
Soft Start-Up  
FORCED  
CONTINUOUS MODE  
Burst Mode  
OPERATION  
5A/DIV  
V
OUT  
5V/DIV  
PULSE-SKIPPING  
MODE  
0V  
3788 G07  
3788 G08  
V
V
LOAD  
= 12V  
5μs/DIV  
V
V
= 12V  
20ms/DIV  
IN  
IN  
OUT  
= 24V  
= 24V  
OUT  
I
= 200μA  
FIGURE 9 CIRCUIT  
FIGURE 9 CIRCUIT  
Regulated Feedback Voltage  
vs Temperature  
Soft-Start Pull-Up Current  
vs Temperature  
1.212  
11.0  
10.5  
10.0  
9.5  
1.209  
1.206  
1.203  
1.200  
1.197  
1.194  
1.191  
1.188  
9.0  
–20  
5
55  
80 105 130  
–45  
30  
–20  
5
55  
80 105 130  
–45  
30  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
3788 G09  
3788 G10  
Shutdown Current  
vs Input Voltage  
Shutdown Current vs Temperature  
11.0  
10.5  
10.0  
9.5  
9.0  
8.5  
8.0  
7.5  
7.0  
6.5  
6.0  
5.5  
5.0  
20  
15  
10  
5
V
= 12V  
IN  
0
–20  
5
55  
80 105 130  
–45  
30  
5
10  
20 25 30 35 40  
15  
INPUT VOLTAGE (V)  
0
TEMPERATURE (°C)  
3788 G11  
3788 G12  
3788f  
6
LTC3788  
TYPICAL PERFORMANCE CHARACTERISTICS  
Shutdown (RUN) Threshold  
vs Temperature  
Quiescent Current vs Temperature  
170  
160  
150  
140  
130  
120  
110  
100  
1.40  
1.35  
1.30  
1.25  
1.20  
1.15  
1.10  
V
V
= 12V  
IN  
FB  
= 1.25V  
RUN2 = GND  
RUN RISING  
RUN FALLING  
–20  
5
55  
80 105 130  
–20  
5
55  
80 105 130  
–45  
30  
–45  
30  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
3788 G13  
3788 G14  
Undervoltage Lockout Threshold  
vs Temperature  
INTVCC Line Regulation  
5.5  
5.4  
5.3  
5.2  
5.1  
5.0  
4.9  
4.8  
4.7  
4.6  
4.5  
4.4  
4.3  
4.2  
4.1  
4.0  
3.9  
3.8  
3.7  
3.6  
3.5  
3.4  
INTV RISING  
CC  
INTV FALLING  
CC  
5
10  
20 25 30 35 40  
–20  
5
55  
80 105 130  
0
15  
–45  
30  
INPUT VOLTAGE (V)  
TEMPERATURE (°C)  
3788 G16  
3788 G15  
EXTVCC Switchover and INTVCC  
Voltages vs Temperature  
INTVCC vs INTVCC Load Current  
5.50  
5.45  
5.40  
5.35  
5.30  
5.25  
5.20  
5.15  
5.10  
5.05  
5.00  
6.0  
5.8  
5.6  
5.4  
5.2  
5.0  
4.8  
4.6  
4.4  
4.2  
4.0  
V
= 12V  
IN  
EXTV = 0V  
INTV  
CC  
CC  
EXTV RISING  
CC  
EXTV = 6V  
CC  
EXTV FALLING  
CC  
40 60 80 100 120 200  
140 160 180  
0
20  
–45  
5
30  
55  
80 105 130  
–20  
INTV LOAD CURRENT (mA)  
TEMPERATURE (°C)  
CC  
3788 G17  
3788 G18  
3788f  
7
LTC3788  
TYPICAL PERFORMANCE CHARACTERISTICS  
Oscillator Frequency  
vs Temperature  
Oscillator Frequency  
vs Input Voltage  
360  
358  
356  
354  
352  
350  
348  
346  
344  
342  
340  
600  
550  
500  
450  
400  
350  
300  
FREQ = GND  
FREQ = INTV  
CC  
FREQ = GND  
5
10  
20  
25  
30  
35  
40  
15  
–45  
5
30  
55  
80 105 130  
–20  
INPUT VOLTAGE (V)  
TEMPERATURE (°C)  
3788 G20  
3788 G19  
SENSE Pin Input Current  
vs Temperature  
Maximum Current Sense  
Threshold vs ITH Voltage  
120  
100  
80  
260  
240  
220  
200  
180  
160  
140  
120  
100  
80  
V
I
= 12V  
SENSE  
LIM  
= FLOAT  
+
SENSE PIN  
PULSE SKIPPING MODE  
Burst Mode  
OPERATION  
60  
40  
20  
I
= GND  
LIM  
0
I
= FLOAT  
LIM  
LIM  
I
= INTV  
CC  
60  
40  
20  
0
–20  
–40  
–60  
FORCED CONTINUOUS MODE  
–
SENSE PIN  
0.8  
VOLTAGE (V)  
1.2 1.4  
0
0.2 0.4 0.6  
1.0  
–45  
5
30  
55  
80 105 130  
–20  
TEMPERATURE (°C)  
I
TH  
3788 G22  
3788 G21  
SENSE Pin Input Current  
vs VSENSE Voltage  
SENSE Pin Input Current  
vs ITH Voltage  
260  
240  
220  
200  
180  
160  
140  
120  
100  
80  
260  
240  
220  
200  
180  
160  
140  
120  
100  
80  
V
= 12V  
SENSE  
+
I
= INTV  
CC  
I
= INTV  
CC  
LIM  
SENSE PIN  
LIM  
I
= FLOAT  
= GND  
I
= FLOAT  
LIM  
I
LIM  
+
SENSE PIN  
LIM  
I
= GND  
LIM  
60  
40  
20  
0
60  
40  
20  
0
I
I
I
= INTV  
= FLOAT  
= GND  
I
I
I
= INTV  
CC  
= FLOAT  
= GND  
LIM  
LIM  
LIM  
CC  
LIM  
LIM  
LIM  
–
–
SENSE PIN  
SENSE PIN  
0
1
1.5  
2
2.5  
3
2.5  
17.5 22.5 27.5 32.5 37.5  
7.5 12.5  
V COMMON MODE VOLTAGE (V)  
SENSE  
0.5  
I
VOLTAGE (V)  
TH  
3788 G23  
3788 G24  
3788f  
8
LTC3788  
TYPICAL PERFORMANCE CHARACTERISTICS  
Maximum Current Sense  
Threshold vs Duty Cycle  
Charge Pump Charging Current  
vs Operating Frequency  
120  
100  
80  
60  
40  
20  
0
80  
70  
60  
50  
40  
30  
20  
10  
0
V
V
= 12V  
SW  
BOOST  
– V = 4.5V  
SW  
I
= INTV  
LIM  
CC  
T = –45°C  
T = 25°C  
I
= FLOAT  
= GND  
LIM  
I
LIM  
T = 130°C  
20 30 40 50 60  
100  
70 80 90  
0
10  
50 150 250 350 450 550 650 750  
OPERATING FREQUENCY (kHz)  
DUTY CYCLE (%)  
3788 G26  
3788 G25  
PIN FUNCTIONS  
–
–
SENSE± ,SENSE2 (Pin±,Pin9):NegativeCurrentSense  
ComparatorInput. The(–)inputtothecurrentcomparator  
is normally connected to the negative terminal of a cur-  
rent sense resistor connected in series with the inductor.  
The common mode voltage range on these pins is 2.5V  
to 38V (abs max).  
CLKOUT (Pin 4): A Digital Output Used for Daisychaining  
MultipleLTC3788ICsinMultiphaseSystems.ThePHASMD  
pinvoltagecontrolstherelationshipbetweenBG1,BG2and  
CLKOUT. This pin swings between SGND and INTV .  
CC  
PLLIN/MODE (Pin 5): Forced Continuous Mode, Burst  
Mode or Pulse-Skipping Mode Selection Pin and External  
Synchronization Input to Phase Detector Pin. Pulling this  
pin to ground selects Burst Mode operation. Tying this pin  
FREQ (Pin 2): The frequency control pin for the internal  
VCO. Connecting the pin to GND forces the VCO to a fixed  
low frequency of 350kHz. Connecting the pin to INTV  
to INTV forces continuous inductor current operation.  
CC  
CC  
forces the VCO to a fixed high frequency of 535kHz. The  
frequency can be programmed from 50kHz to 900kHz  
by connecting a resistor from the FREQ pin to GND. The  
resistor and an internal 20μA source current create a volt-  
age used by the internal oscillator to set the frequency.  
Alternatively, this pin can be driven with a DC voltage to  
vary the frequency of the internal oscillator.  
Tying this pin to a voltage greater than 1.2V and less than  
INTV –1.3V selects pulse-skipping operation. A clock  
CC  
on the pin will force the controller into pulse-skipping  
mode of operation and synchronize the internal oscillator.  
SGND (Pin 6): Signal Ground. All small-signal components  
and compensation components should connect to this  
ground, which in turn connects to PGND at a single point.  
PHASMD (Pin 3): This pin can be floated, tied to SGND, or  
RUN±,RUN2(Pin7,Pin8):RunControlInput.Anexternal  
tied to INTV to program the phase relationship between  
CC  
resistordividerconnectstoV andsetsthethresholdsfor  
IN  
the rising edges of BG1 and BG2, as well as the phase  
converteroperationwithathresholdof1.28V.Oncerunning,  
a 4.5μA current is sourced from the RUN pin allowing the  
user to program hysteresis using the resistor values.  
relationship between BG1 and CLKOUT.  
3788f  
9
LTC3788  
PIN FUNCTIONS  
PGOOD2 (Pin ±4): Power Good Indicator for Channel 2.  
Open-drain logic output that is pulled to ground when  
the output voltage is more than 10% away from the  
regulated output voltage. To avoid false trips the output  
voltage must be outside the range for 25μs before this  
output is activated.  
PGOOD± (Pin 27): Power Good Indicator for Channel 1.  
Open-drain logic output that is pulled to ground when  
the output voltage is more than 10% away from the  
regulated output voltage. To avoid false trips the output  
voltage must be outside the range for 25μs before this  
output is activated.  
INTV (Pin ±9): Output of Internal 5.4V LDO. Power  
ILIM (Pin 28): Current Comparator Sense Voltage Range  
Input. This pin is used to set the peak current sense volt-  
age in the current comparator. Connect this pin to SGND,  
CC  
supply for control circuits and gate drives. Decouple this  
pin to GND with a minimum 4.7μF low ESR tantalum or  
ceramic capacitor.  
open and INTV to set the peak current sense voltage to  
CC  
50mV, 75mV, and 100mV, respectively.  
EXTV (Pin 20): External Power Input. When this pin is  
CC  
higher than 4.8V an internal switch bypasses the inter-  
SS±, SS2 (Pin 29, Pin ±3): Output Soft-Start Input. A  
capacitor to ground at this pin sets the ramp rate of the  
output voltage during start-up.  
nal regulator and supply power to INTV directly from  
CC  
EXTV .  
CC  
PGND (Pin 2±): Driver Power Ground. Connects to the  
ITH±, ITH2 (Pin 30, Pin ±2): Current Control Threshold  
and Error Amplifier Compensation Point. The voltage on  
this pin sets the current trip threshold.  
sources of bottom (main) N-channel MOSFETs and the  
(–) terminal(s) of C and C  
.
IN  
OUT  
VBIAS (Pin 22): Main Supply Pin. It is normally tied to the  
VFB±, VFB2 (Pin 3±, Pin ±±): Error Amplifier Feedback  
Input. This pin receives the remotely sensed feedback  
voltagefromanexternalresistivedividerconnectedacross  
the output.  
input supply V or to the output of the boost converter.  
IN  
A bypass capacitor should be tied between this pin and  
the signal ground pin. The operating voltage range on this  
pin is 4.5V to 38V (40V abs max).  
+
+
SENSE± , SENSE2 (Pin 32, Pin ±0): Positive Current  
Sense Comparator Input. The (+) input to the current  
comparator is normally connected to the positive terminal  
of a current sense resistor. The current sense resistor is  
normally placed at the input of the boost controller in  
series with the inductor. This pin also supplies power to  
the current comparator.  
BG±, BG2 (Pin 23, Pin ±8): Bottom Gate. Connect to the  
gate of the main NMOS.  
BOOST±,BOOST2(Pin24,Pin±7):Floatingpowersupply  
forthesynchronousNMOS.BypasstoSWwithacapacitor  
and supply with a Schottky diode connected to INTV .  
CC  
TG±, TG2 (Pin 25, Pin ±6): Top Gate. Connect to the gate  
of the synchronous NMOS.  
GND (Exposed Pad Pin 33): Ground. The exposed pad  
must be soldered to the circuit board for rated thermal  
performance.  
SW±, SW2 (Pin 26, Pin ±5): Switch Node. Connect to the  
source of the synchronous NMOS, the drain of the main  
NMOS and the inductor.  
3788f  
10  
LTC3788  
BLOCK DIAGRAM  
INTV  
CC  
DUPLICATE FOR SECOND CONTROLLER CHANNEL  
S
D
B
PHASMD  
CLKOUT  
BOOST  
TG  
Q
R
C
B
SHDN  
SWITCHING  
LOGIC  
V
OUT  
C
SW  
BG  
AND  
CHARGE  
PUMP  
20μA  
OUT  
INTV  
CC  
FREQ  
CLK2  
CLK1  
VCO  
PFD  
+
–
0.425V  
–
SLEEP  
PGND  
L
+
+
+
–
+
–
–
–
2mV  
SENSE  
SENSE  
VFB  
2.8V  
0.7V  
PLLIN/  
MODE  
R
SENSE  
+
SLOPE COMP  
SENS LO  
SYNC  
DET  
V
IN  
C
+
IN  
100k  
–
2.5V  
+
–
–
1.2V  
SS  
EA  
ILIM  
CURRENT  
LIMIT  
+
–
VBIAS  
OV  
1.32V  
C
C
ITH  
SHDN  
0.5μA/  
4.5μA  
EXTV  
CC  
R
C
C
C2  
5.4V  
LDO  
5.4V  
LDO  
PGOOD  
10μA  
SS  
+
–
1.32V  
+
–
11V  
EN  
EN  
3.8V  
VFB  
SENS  
LO  
+
–
SHDN  
RUN  
+
–
1.08V  
4.8V  
INTV  
SGND  
CC  
3788 BD  
C
SS  
3788f  
11  
LTC3788  
OPERATION (Refer to Block Diagram)  
Main Control Loop  
5.4V from EXTV to INTV . Using the EXTV pin allows  
CC CC CC  
the INTV power to be derived from a high efficiency  
CC  
The LTC3788 uses a constant-frequency, current mode  
step-uparchitecturewiththetwocontrollerchannelsoper-  
ating 180 or 240 degrees out-of-phase (depending on the  
PHASMD pin connection). During normal operation, each  
external bottom MOSFET is turned on when the clock for  
that channel sets the RS latch, and is turned off when the  
main current comparator, ICMP, resets the RS latch. The  
peak inductor current at which ICMP trips and resets the  
latch is controlled by the voltage on the ITH pin, which is  
the output of the error amplifier EA. The error amplifier  
compares the output voltage feedback signal at the VFB  
pin, (which is generated with an external resistor divider  
external source such as one of the LTC3788 switching  
regulator outputs.  
Shutdown and Start-Up  
(RUN±, RUN2 and SS±, SS2 Pins)  
The two channels of the LTC3788 can be independently  
shutdownusingtheRUN1andRUN2pins.Pullingeitherof  
these pins below 1.28V shuts down the main control loop  
for that controller. Pulling both pins below 0.7V disables  
both controllers and most internal circuits, including the  
INTV LDOs. In this state, the LTC3788 draws only 8μA  
CC  
of quiescent current.  
connected across the output voltage, V , to ground) to  
OUT  
the internal 1.200V reference voltage. When the load cur-  
The RUN pin may be externally pulled up or driven directly  
by logic. When driving the RUN pin with a low impedance  
source, do not exceed the absolute maximum rating of  
8V. The RUN pin has an internal 11V voltage clamp that  
allows the RUN pin to be connected through a resistor to a  
rent increases, it causes a slight decrease in V relative  
FB  
to the reference, which causes the EA to increase the I  
TH  
voltage until the average inductor current matches the  
new load current.  
highervoltage(forexample, V ), aslongasthemaximum  
After the bottom MOSFET is turned off each cycle, the  
top MOSFET is turned on until either the inductor current  
starts to reverse, as indicated by the current comparator  
IR, or the beginning of the next clock cycle.  
IN  
current into the RUN pin does not exceed 100μA.  
The start-up of each controller’s output voltage V  
is  
OUT  
controlled by the voltage on the SS pin for that channel.  
When the voltage on the SS pin is less than the 1.2V  
INTV /EXTV Power  
CC  
CC  
internal reference, the LTC3788 regulates the V voltage  
FB  
Power for the top and bottom MOSFET drivers and most  
to the SS pin voltage instead of the 1.2V reference. This  
allows the SS pin to be used to program a soft-start by  
connectinganexternalcapacitorfromtheSSpintoSGND.  
An internal 10μA pull-up current charges this capacitor  
creating a voltage ramp on the SS pin. As the SS voltage  
other internal circuitry is derived from the INTV pin.  
CC  
When the EXTV pin is left open or tied to a voltage less  
CC  
than 4.8V, the VBIAS LDO (low dropout linear regulator)  
supplies 5.4V from VBIAS to INTV . If EXTV is taken  
CC  
CC  
above 4.8V, the VBIAS LDO is turned off and an EXTV  
rises linearly from 0V to 1.2V (and beyond up to INTV ),  
CC  
CC  
LDO is turned on. Once enabled, the EXTV LDO supplies  
the output voltage V  
rises smoothly to its final value.  
CC  
OUT  
3788f  
12  
LTC3788  
OPERATION  
Light Load Current Operation—Burst Mode Operation,  
Pulse-Skipping or Continuous Conduction  
(PLLIN/MODE Pin)  
When a controller is enabled for Burst Mode operation,  
the inductor current is not allowed to reverse. The reverse  
currentcomparator(IR)turnsoffthetopexternalMOSFET  
just before the inductor current reaches zero, preventing  
it from reversing and going negative. Thus, the controller  
operates in discontinuous current operation.  
The LTC3788 can be enabled to enter high efficiency Burst  
Modeoperation,constant-frequencypulse-skippingmode  
orforcedcontinuousconductionmodeatlowloadcurrents.  
To select Burst Mode operation, tie the PLLIN/ MODE pin  
to a ground (e.g., SGND). To select forced continuous  
In forced continuous operation or when clocked by an  
external clock source to use the phase-locked loop (see  
theFrequencySelectionandPhase-LockedLoopsection),  
the inductor current is allowed to reverse at light loads or  
under large transient conditions. The peak inductor cur-  
rent is determined by the voltage on the ITH pin, just as  
in normal operation. In this mode, the efficiency at light  
loads is lower than in Burst Mode operation. However,  
continuous operation has the advantages of lower output  
voltage ripple and less interference to audio circuitry, as  
it maintains constant-frequency operation independent  
of load current.  
operation, tie the PLLIN/MODE pin to INTV . To select  
CC  
pulse-skipping mode, tie the PLLIN/MODE pin to a DC  
voltage greater than 1.2V and less than INTV – 1.3V.  
CC  
WhenacontrollerisenabledforBurstModeoperation,the  
minimum peak current in the inductor is set to approxi-  
mately 30% of the maximum sense voltage even though  
the voltage on the ITH pin indicates a lower value. If the  
average inductor current is higher than the load current,  
the error amplifier EA will decrease the voltage on the ITH  
pin. When the I voltage drops below 0.425V, the internal  
TH  
sleep signal goes high (enabling sleep mode) and both  
external MOSFETs are turned off.  
When the PLLIN/MODE pin is connected for pulse-skip-  
ping mode, the LTC3788 operates in PWM pulse-skipping  
mode at light loads. In this mode, constant-frequency  
operation is maintained down to approximately 1% of  
designedmaximumoutputcurrent. Atverylightloads, the  
In sleep mode, much of the internal circuitry is turned off,  
reducing the quiescent current that the LTC3788 draws.  
If one channel is shut down and the other channel is in  
sleep mode, the LTC3788 draws only 125μA of quiescent  
current. If both channels are in sleep mode, the LTC3788  
draws only 200μA of quiescent current. In sleep mode,  
the load current is supplied by the output capacitor. As  
the output voltage decreases, the EA’s output begins to  
rise. When the output voltage drops enough, the ITH pin  
is reconnected to the output of the EA, the sleep signal  
goes low, and the controller resumes normal operation  
by turning on the bottom external MOSFET on the next  
cycle of the internal oscillator.  
current comparator I  
may remain tripped for several  
CMP  
cycles and force the external bottom MOSFET to stay off  
for the same number of cycles (i.e., skipping pulses). The  
inductor current is not allowed to reverse (discontinuous  
operation). This mode, like forced continuous operation,  
exhibits low output ripple as well as low audio noise and  
reduced RF interference as compared to Burst Mode  
operation. It provides higher low current efficiency than  
forced continuous mode, but not nearly as high as Burst  
Mode operation.  
3788f  
13  
LTC3788  
OPERATION  
Frequency Selection and Phase-Locked Loop (FREQ  
and PLLIN/MODE Pins)  
prebias the loop filter allows the PLL to lock-in rapidly  
without deviating far from the desired frequency.  
Theselectionofswitchingfrequencyisatrade-offbetween  
efficiency and component size. Low frequency opera-  
tion increases efficiency by reducing MOSFET switching  
losses, but requires larger inductance and/or capacitance  
to maintain low output ripple voltage.  
The typical capture range of the LTC3788’s PLL is from  
approximately 55kHz to 1MHz, and is guaranteed to  
lock to an external clock source whose frequency is be-  
tween 75kHz and 850kHz.  
The typical input clock thresholds on the PLLIN/MODE  
pin are 1.6V (rising) and 1.2V (falling).  
The switching frequency of the LTC3788’s controllers can  
be selected using the FREQ pin.  
PolyPhase Applications (CLKOUT and PHASMD Pins)  
If the PLLIN/MODE pin is not being driven by an external  
clock source, the FREQ pin can be tied to SGND, tied to  
The LTC3788 features two pins (CLKOUT and PHASMD)  
that allow other controller ICs to be daisychained with the  
LTC3788 in PolyPhase® applications. The clock output  
signal on the CLKOUT pin can be used to synchronize  
additional power stages in a multiphase power supply  
solution feeding a single, high current output or multiple  
separate outputs. The PHASMD pin is used to adjust the  
phase of the CLKOUT signal as well as the relative phases  
between the two internal controllers, as summarized in  
Table 1. The phases are calculated relative to the zero  
degrees phase being defined as the rising edge of the  
bottom gate driver output of controller 1 (BG1).  
INTV , or programmed through an external resistor.  
CC  
Tying FREQ to SGND selects 350kHz while tying FREQ to  
INTV selects 535kHz. Placing a resistor between FREQ  
CC  
andSGNDallowsthefrequencytobeprogrammedbetween  
50kHz and 900kHz, as shown in Figure 6.  
A phase-locked loop (PLL) is available on the LTC3788  
to synchronize the internal oscillator to an external clock  
source that is connected to the PLLIN/MODE pin. The  
LTC3788’s phase detector adjusts the voltage (through  
an internal lowpass filter) of the VCO input to align the  
turn-on of the first controller’s external bottom MOSFET  
to the rising edge of the synchronizing signal. Thus, the  
turn-onofthesecondcontroller’sexternalbottomMOSFET  
is 180 or 240 degrees out-of-phase to the rising edge of  
the external clock source.  
Table ±.  
CONTROLLER 2  
PHASE (°C)  
CLKOUT  
PHASE (°C)  
V
PHASMD  
GND  
180  
180  
240  
60  
90  
Floating  
INTV  
The VCO input voltage is prebiased to the operating fre-  
quency set by the FREQ pin before the external clock is  
applied. If prebiased near the external clock frequency,  
the PLL loop only needs to make slight changes to the  
VCO input in order to synchronize the rising edge of the  
external clock’s to the rising edge of BG1. The ability to  
120  
CC  
CLKOUT is disabled when one of the channels is in sleep  
mode and another channel is either in shutdown or in  
sleep mode.  
3788f  
14  
LTC3788  
OPERATION  
Operation When V > V  
VFB1, 2 pin voltage is not within 10% of the 1.2V refer-  
ence voltage. The PGOOD1, 2 pin is also pulled low when  
the corresponding RUN1, 2 pin is low (shut down). When  
theVFB1, 2pinvoltageiswithinthe 10%requirement,the  
MOSFET is turned off and the pin is allowed to be pulled  
up by an external resistor to a source of up to 6V.  
IN  
OUT  
WhenV risesabovetheregulatedV voltage,theboost  
IN  
OUT  
controller can behave differently depending on the mode,  
inductor current and V voltage. In forced continuous  
IN  
mode, the loop works to keep the top MOSFET on con-  
tinuously once V rises above V . The internal charge  
IN  
OUT  
pump delivers current to the boost capacitor to maintain  
Operation at Low SENSE Pin Common Voltage  
a sufficiently high TG voltage.  
The current comparator in the LTC3788 is powered di-  
In pulse-skipping mode, if V is between 100% and  
110% of the regulated V  
IN  
+
rectly from the SENSE pin. This enables the common  
voltage, TG turns on if the  
OUT  
+
–
modevoltageofSENSE andSENSE pinstooperateatas  
lowas2.5V, whichisbelowtheUVLOthreshold. Thefigure  
on the first page shows a typical application when the  
inductor current rises above a certain threshold and turns  
off if the inductor current falls below this threshold. This  
threshold current is set to approximately 6%, 4% or  
controller’s VBIAS is powered from V  
while V supply  
OUT  
IN  
3% of the maximum I  
current when the ILIM pin is  
LIM  
+
can go as low as 2.5V. If the voltage on SENSE drops  
below 2.5V, the SS pin will be held low. When the SENSE  
voltage returns to the normal operating range, the SS pin  
will be released, initiating a new soft-start cycle.  
grounded, floating or tied to INTV , respectively. If the  
CC  
controller is programmed to Burst Mode operation under  
this same V window, then TG remains off regardless of  
IN  
the inductor current.  
BOOST Supply Refresh and Internal Charge Pump  
If V rises above 110% of the regulated V  
voltage in  
IN  
OUT  
any mode, the controller turns on TG regardless of the  
inductor current. In Burst Mode operation, however, the  
internal charge pump turns off if the entire chip is asleep  
(theotherchannelisasleeporshutdown).Withthecharge  
pump off, there would be nothing to prevent the boost  
capacitor from discharging, resulting in an insufficient TG  
voltage needed to keep the top MOSFET completely on.  
To prevent excessive power dissipation across the body  
diode of the top MOSFET in this situation, the chip can be  
switched over to forced continuous mode to enable the  
charge pump, or a Schottky diode can also be placed in  
parallel to the top MOSFET.  
Each top MOSFET driver is biased from the floating  
bootstrap capacitor C , which normally recharges dur-  
B
ing each cycle through an external diode when the bot-  
tom MOSFET turns on. There are two considerations to  
keep the BOOST supply at the required bias level. During  
start-up, if the bottom MOSFET is not turned on within  
100μs after UVLO goes low, the bottom MOSFET will be  
forced to turn on for ~400ns. This forced refresh gener-  
ates enough BOOST-SW voltage to allow the top MOSFET  
ready to be fully enhanced instead of waiting for the initial  
few cycles to charge up. There is also an internal charge  
pump that keeps the required bias on BOOST. The charge  
pump always operates in both forced continuous mode  
and pulse-skipping mode. In Burst Mode operation, the  
charge pump is turned off during sleep and enabled when  
the chip wakes up. The internal charge pump can normally  
supply a charging current of 55μA.  
Power Good  
The PGOOD1, 2 pin is connected to an open-drain of an  
internal N-channel MOSFET. The MOSFET turns on and  
pulls the PGOOD1, 2 pin low when the corresponding  
3788f  
15  
LTC3788  
APPLICATIONS INFORMATION  
+
The Typical Application on the first page is a basic  
LTC3788 application circuit. LTC3788 can be configured  
to use either inductor DCR (DC resistance) sensing or a  
TheSENSE pinalsoprovidespowertothecurrentcompara-  
tor.Itdraws~200μAduringnormaloperation.Thereisasmall  
–
basecurrentoflessthan1μAthatflowsintotheSENSE pin.  
–
discrete sense resistor (R  
) for current sensing. The  
The high impedance SENSE input to the current com-  
SENSE  
choicebetweenthetwocurrentsensingschemesislargely  
a design trade-off between cost, power consumption and  
accuracy. DCR sensing is becoming popular because it  
does not require current sensing resistors and is more  
power-efficient, especially in high current applications.  
However, current sensing resistors provide the most  
accurate current limits for the controller. Other external  
component selection is driven by the load requirement,  
parators allow accurate DCR sensing.  
Filter components mutual to the sense lines should be  
placed close to the LTC3788, and the sense lines should  
run close together to a Kelvin connection underneath the  
current sense element (shown in Figure 1). Sensing cur-  
rent elsewhere can effectively add parasitic inductance  
and capacitance to the current sense element, degrading  
the information at the sense terminals and making the  
programmed current limit unpredictable. If DCR sensing  
is used (Figure 2b), sense resistor R1 should be placed  
closetotheswitchingnode,topreventnoisefromcoupling  
into sensitive small-signal nodes.  
and begins with the selection of R  
(if R  
is used)  
SENSE  
SENSE  
andinductorvalue.Next,thepowerMOSFETsareselected.  
Finally, input and output capacitors are selected.  
+
–
SENSE and SENSE Pins  
TO SENSE FILTER,  
NEXT TO THE CONTROLLER  
+
–
The SENSE and SENSE pins are the inputs to the cur-  
rent comparators. The common mode input voltage range  
of the current comparators is 2.5V to 38V. The current  
sense resistor is normally placed at the input of the boost  
controller in series with the inductor.  
V
IN  
INDUCTOR OR R  
3788 F01  
SENSE  
Figure ±. Sense Lines Placement with  
Inductor or Sense Resistor  
VBIAS  
V
IN  
VBIAS  
V
IN  
+
+
SENSE  
SENSE  
C1  
R2  
(OPTIONAL)  
DCR  
L
–
–
SENSE  
SENSE  
INTV  
INTV  
CC  
CC  
INDUCTOR  
R1  
LTC3788  
LTC3788  
BOOST  
BOOST  
TG  
TG  
V
OUT  
SW  
BG  
V
SW  
BG  
OUT  
SGND  
SGND  
3788 F02b  
3788 F02a  
L
DCR  
R2  
R1 + R2  
||  
(R1 R2) • C1 =  
R
= DCR •  
PLACE C1 NEAR SENSE PINS  
SENSE(EQ)  
(2a) Using a Resistor to Sense Current  
(2b) Using the Inductor DCR to Sense Current  
Figure 2. Two Different Methods of Sensing Current  
3788f  
16  
LTC3788  
APPLICATIONS INFORMATION  
Sense Resistor Current Sensing  
using a good RLC meter, but the DCR tolerance is not  
always the same and varies with temperature. Consult the  
manufacturer’s data sheets for detailed information.  
A typical sensing circuit using a discrete resistor is shown  
in Figure 2a. R  
output current.  
is chosen based on the required  
SENSE  
Usingtheinductorripplecurrentvaluefromtheinductorval-  
ue calculation section, the target sense resistor value is:  
The current comparator has a maximum threshold  
VSENSE(MAX)  
V
. When the ILIM pin is grounded, floating or  
CC  
SENSE(MAX)  
RSENSE(EQUIV)  
=
tied to INTV , the maximum threshold is set to 50mV,  
ΔIL  
IMAX  
+
75mV or 100mV, respectively. The current comparator  
2
threshold sets the peak of the inductor current, yielding  
To ensure that the application will deliver full load current  
over the full operating temperature range, choose the  
minimum value for the maximum current sense threshold  
a maximum average output current, I  
, equal to the  
MAX  
peak value less half the peak-to-peak ripple current, ΔI .  
L
To calculate the sense resistor value, use the equation:  
(V  
).  
SENSE(MAX)  
VSENSE(MAX)  
Next, determine the DCR of the inductor. Where provided,  
use the manufacturer’s maximum value, usually given at  
20°C. Increase this value to account for the temperature  
coefficientofresistance,whichisapproximately0.4%/°C.A  
conservativevalueforthemaximuminductortemperature  
RSENSE  
=
ΔIL  
2
IMAX  
+
When using the controller in low V and very high voltage  
IN  
outputapplications,themaximumoutputcurrentlevelwill  
be reduced due to the internal compensation required to  
meet stability criterion for boost regulators operating at  
greater than 50% duty factor. A curve is provided in the  
Typical Performance Characteristics section to estimate  
thisreductioninpeakoutputcurrentleveldependingupon  
the operating duty factor.  
(T  
) is 100°C.  
L(MAX)  
To scale the maximum inductor DCR to the desired sense  
resistor value, use the divider ratio:  
RSENSE(EQUIV)  
RD =  
DCRMAX at TL(MAX)  
C1 is usually selected to be in the range of 0.1μF to 0.47μF.  
ThisforcesR1||R2toaround2k, reducingerrorthatmight  
Inductor DCR Sensing  
+
have been caused by the SENSE pin’s 1μA current.  
For applications requiring the highest possible efficiency  
at high load currents, the LTC3788 is capable of sensing  
the voltage drop across the inductor DCR, as shown in  
Figure 2b. The DCR of the inductor can be less than 1mΩ  
for high current inductors. In a high current application  
requiring such an inductor, conduction loss through a  
sense resistor could reduce the efficiency by a few percent  
compared to DCR sensing.  
The equivalent resistance R1|| R2 is scaled to the room  
temperature inductance and maximum DCR:  
L
R1||R2 =  
(DCR at 20°C) • C1  
The sense resistor values are:  
R1•RD  
1− RD  
R1||R2  
RD  
R1=  
; R2 =  
If the external R1||R2 • C1 time constant is chosen to be  
exactly equal to the L/DCR time constant, the voltage drop  
across the external capacitor is equal to the drop across  
theinductorDCRmultipliedbyR2/(R1+R2).R2scalesthe  
voltage across the sense terminals for applications where  
the DCR is greater than the target sense resistor value.  
To properly dimension the external filter components, the  
DCR of the inductor must be known. It can be measured  
The maximum power loss in R1 is related to duty cycle,  
and will occur in continuous mode at V = 1/2 V  
:
OUT  
IN  
(VOUT − V ) • V  
IN  
IN  
PLOSS R1=  
R1  
3788f  
17  
LTC3788  
APPLICATIONS INFORMATION  
Ensure that R1 has a power rating higher than this value.  
If high efficiency is necessary at light loads, consider this  
power loss when deciding whether to use DCR sensing or  
sense resistors. Light load power loss can be modestly  
higher with a DCR network than with a sense resistor, due  
totheextraswitchinglossesincurredthroughR1.However,  
DCR sensing eliminates a sense resistor, reduces conduc-  
tion losses and provides higher efficiency at heavy loads.  
Peak efficiency is about the same with either method.  
Inductor Core Selection  
Once the value for L is known, the type of inductor must  
be selected. High efficiency converters generally cannot  
affordthecorelossfoundinlowcostpowderedironcores,  
forcingtheuseofmoreexpensiveferriteormolypermalloy  
cores. Actual core loss is independent of core size for a  
fixedinductorvalue,butitisverydependentoninductance  
selected. As inductance increases, core losses go down.  
Unfortunately, because increased inductance requires  
more turns of wire, copper losses will increase.  
Inductor Value Calculation  
Ferrite core inductors have very low core loss and are  
preferred at high switching frequencies, so design goals  
can concentrate on copper loss and preventing satura-  
tion. Ferrite core material saturates “hard,” which means  
that inductance collapses abruptly when the peak design  
current is exceeded. This results in an abrupt increase in  
inductor ripple current and consequent output voltage  
ripple. Do not allow the core to saturate!  
The operating frequency and inductor selection are inter-  
relatedinthathigheroperatingfrequenciesallowtheuseof  
smaller inductor and capacitor values. Why would anyone  
ever choose to operate at lower frequencies with larger  
components?Theanswerisefficiency.Ahigherfrequency  
generally results in lower efficiency because of MOSFET  
gate charge and switching losses. In addition to this basic  
trade-off, the effect of inductor value on ripple current and  
low current operation must also be considered.  
Power MOSFET Selection  
The inductor value has a direct effect on ripple current.  
Two external power MOSFETs must be selected for each  
controller in the LTC3788: one N-channel MOSFET for the  
bottom (main) switch, and one N-channel MOSFET for the  
top (synchronous) switch.  
The inductor ripple current ΔI decreases with higher  
L
inductance or frequency and increases with higher V :  
IN  
⎛
⎞
V
f •L  
V
VOUT  
IN  
IN  
ΔIL =  
1−  
⎜
⎟
⎝
⎠
The peak-to-peak gate drive levels are set by the INTV  
CC  
voltage. This voltage is typically 5.4V during start-up  
Accepting larger values of ΔI allows the use of low  
L
(see EXTV pin connection). Consequently, logic-level  
CC  
inductances, but results in higher output voltage ripple  
threshold MOSFETs must be used in most applications.  
and greater core losses. A reasonable starting point for  
The only exception is if low input voltage is expected (V  
IN  
setting ripple current is ΔI = 0.3(I  
). The maximum  
MAX  
L
< 5V); then, sub-logic level threshold MOSFETs (V  
GS(TH)  
ΔI occurs at V = 1/2 V .  
L
IN  
OUT  
< 3V) should be used. Pay close attention to the BV  
DSS  
The inductor value also has secondary effects. The tran-  
sition to Burst Mode operation begins when the average  
inductor current required results in a peak current below  
specification for the MOSFETs as well; many of the logic  
level MOSFETs are limited to 30V or less.  
Selection criteria for the power MOSFETs include the  
10% of the current limit determined by R  
. Lower  
SENSE  
on-resistance R , Miller capacitance C , input  
DS(ON) MILLER  
inductor values (higher ΔI ) will cause this to occur at  
L
voltage and maximum output current. Miller capacitance,  
, can be approximated from the gate charge curve  
lower load currents, which can cause a dip in efficiency in  
the upper range of low current operation. In Burst Mode  
operation, lower inductance values will cause the burst  
frequency to decrease.  
C
MILLER  
usually provided on the MOSFET manufacturer’s data  
sheet. C is equal to the increase in gate charge  
MILLER  
along the horizontal axis while the curve is approximately  
flat divided by the specified change in V . This result is  
DS  
then multiplied by the ratio of the application applied V  
DS  
to the gate charge curve specified V . When the IC is  
DS  
3788f  
18  
LTC3788  
APPLICATIONS INFORMATION  
operating in continuous mode, the duty cycles for the top  
and bottom MOSFETs are given by:  
The term (1+ δ) is generally given for a MOSFET in the  
form of a normalized R  
vs Temperature curve, but  
DS(ON)  
δ = 0.005/°C can be used as an approximation for low  
voltage MOSFETs.  
VOUT − V  
IN  
Main SwitchDuty Cycle =  
VOUT  
C and C  
Selection  
IN  
OUT  
V
VOUT  
IN  
Synchronous SwitchDuty Cycle =  
The input ripple current in a boost converter is relatively  
low(comparedwiththeoutputripplecurrent),becausethis  
The MOSFET power dissipations at maximum output  
current are given by:  
currentiscontinuous.TheinputcapacitorC voltagerating  
IN  
should comfortably exceed the maximum input voltage.  
Although ceramic capacitors can be relatively tolerant of  
overvoltage conditions, aluminum electrolytic capacitors  
are not. Be sure to characterize the input voltage for any  
possible overvoltage transients that could apply excess  
stress to the input capacitors.  
(VOUT − V )VOUT  
IN  
PMAIN  
=
•IOUT(MAX)2 • 1+ δ  
(
)
V2  
IN  
IOUT(MAX)  
• RDS(ON) + k • V3  
•
•RDR  
OUT  
V
IN  
The value of the C is a function of the source impedance,  
IN  
• CMILLER • f  
andingeneral,thehigherthesourceimpedance,thehigher  
the required input capacitance. The required amount of  
inputcapacitanceisalsogreatlyaffectedbythedutycycle.  
High output current applications that also experience high  
duty cycles can place great demands on the input supply,  
both in terms of DC current and ripple current.  
V
VOUT  
IN  
PSYNC  
=
•IOUT(MAX)2 • 1+ δ •R  
(
)
DS(ON)  
where δ is the temperature dependency of R  
and  
DS(ON)  
R
(approximately 1Ω) is the effective driver resistance  
DR  
at the MOSFET’s Miller threshold voltage. The constant k,  
which accounts for the loss caused by reverse recovery  
current, is inversely proportional to the gate drive current  
and has an empirical value of 1.7.  
Inaboostconverter,theoutputhasadiscontinuouscurrent,  
so C  
must be capable of reducing the output voltage  
OUT  
ripple.TheeffectsofESR(equivalentseriesresistance)and  
the bulk capacitance must be considered when choosing  
the right capacitor for a given output ripple voltage. The  
steady ripple voltage due to charging and discharging the  
bulk capacitance is given by:  
2
BothMOSFETshaveI RlosseswhilethebottomN-channel  
equation includes an additional term for transition losses,  
which are highest at low input voltages. For high V the  
IN  
high current efficiency generally improves with larger  
I
OUT(MAX) •(VOUT − V  
)
IN(MIN)  
MOSFETs, while for low V the transition losses rapidly  
IN  
VRIPPLE  
=
V
COUT • VOUT • f  
is the output filter capacitor.  
increasetothepointthattheuseofahigherR  
device  
DS(ON)  
with lower C  
actually provides higher efficiency.  
MILLER  
where C  
OUT  
The synchronous MOSFET losses are greatest at high  
input voltage when the bottom switch duty factor is low  
or during overvoltage when the synchronous switch is on  
close to 100% of the period.  
The steady ripple due to the voltage drop across the ESR  
is given by:  
ΔV  
= I  
• ESR  
ESR  
L(MAX)  
3788f  
19  
LTC3788  
APPLICATIONS INFORMATION  
The LTC3788 can also be configured as a 2-phase single  
output converter where the outputs of the two channels  
are connected together and both channels have the same  
duty cycle. With 2-phase operation, the two channels of  
thedualswitchingregulatorareoperated180degreesout-  
of-phase. This effectively interleaves the output capacitor  
currentpulses,greatlyreducingtheoutputcapacitorripple  
current. As a result, the ESR requirement of the capacitor  
can be relaxed. Because the ripple current in the output  
capacitorisasquarewave,theripplecurrentrequirements  
for the output capacitor depend on the duty cycle, the  
numberofphasesandthemaximumoutputcurrent.Figure  
3illustratesthenormalizedoutputcapacitorripplecurrent  
as a function of duty cycle in a 2-phase configuration. To  
choose a ripple current rating for the output capacitor,  
first establish the duty cycle range based on the output  
voltage and range of input voltage. Referring to Figure 3,  
choose the worst-case high normalized ripple current as  
a percentage of the maximum load current.  
Multiple capacitors placed in parallel may be needed to  
meet the ESR and RMS current handling requirements.  
Dry tantalum, special polymer, aluminum electrolytic  
and ceramic capacitors are all available in surface mount  
packages. Ceramic capacitors have excellent low ESR  
characteristics but can have a high voltage coefficient.  
Capacitors are now available with low ESR and high ripple  
current ratings (i.e., OS-CON and POSCAP).  
3.25  
3.00  
2.75  
2.50  
2.25  
2.00  
1.75  
1.50  
1.25  
1.00  
0.75  
0.50  
0.25  
0
1-PHASE  
2-PHASE  
0.4 0.5  
0.1 0.2 0.3  
0.6 0.7 0.8 0.9  
DUTY CYCLE OR (1-V /V  
)
IN OUT  
3788 F03  
Figure 3. Normalized Output Capacitor Ripple  
Current (RMS) for a Boost Converter  
3788f  
20  
LTC3788  
APPLICATIONS INFORMATION  
Setting Output Voltage  
INTV Regulators  
CC  
The LTC3788 features two separate internal P-channel  
low dropout linear regulators (LDO) that supply power at  
The LTC3788 output voltages are each set by an external  
feedback resistor divider carefully placed across the out-  
put, as shown in Figure 4. The regulated output voltage  
is determined by:  
the INTV pin from either the VBIAS supply pin or the  
CC  
EXTV pin depending on the connection of the EXTV  
CC  
CC  
pin. INTV powers the gate drivers and much of the  
⎛
⎞
⎟
RB  
CC  
VOUT = 1.2V 1+  
LTC3788’s internal circuitry. The VBIAS LDO and the  
⎜
⎝
RA  
⎠
EXTV LDO regulate INTV to 5.4V. Each of these can  
CC  
CC  
supply a peak current of 50mA and must be bypassed to  
ground with a minimum of 4.7μF ceramic capacitor. Good  
bypassing is needed to supply the high transient currents  
required by the MOSFET gate drivers and to prevent in-  
teraction between the channels.  
Great care should be taken to route the V line away from  
FB  
noise sources, such as the inductor or the SW line.  
Soft-Start (SS Pins)  
The start-up of each V  
is controlled by the voltage  
OUT  
High input voltage applications in which large MOSFETs  
are being driven at high frequencies may cause the maxi-  
mum junction temperature rating for the LTC3788 to be  
on the respective SS pins. When the voltage on the SS  
pin is less than the internal 1.2V reference, the LTC3788  
regulates the VFB pin voltage to the voltage on the SS pin  
instead of 1.2V.  
exceeded. The INTV current, which is dominated by the  
CC  
gate charge current, may be supplied by either the VBIAS  
Soft-startisenabledbysimplyconnectingacapacitorfrom  
the SS pin to ground, as shown in Figure 5. An internal  
10μA current source charges the capacitor, providing a  
linear ramping voltage at the SS pin. The LTC3788 will  
LDO or the EXTV LDO. When the voltage on the EXTV  
CC  
CC  
pin is less than 4.8V, the VBIAS LDO is enabled. In this  
case, power dissipation for the IC is highest and is equal  
to V • I  
. The gate charge current is dependent  
INTVCC  
IN  
regulate the VFB pin (and hence, V ) according to the  
OUT  
on operating frequency, as discussed in the Efficiency  
Considerations section. The junction temperature can  
be estimated by using the equations given in Note 3 of  
the Electrical Characteristics. For example, the LTC3788  
voltage on the SS pin, allowing V  
to rise smoothly  
OUT  
from V to its final regulated value. The total soft-start  
IN  
time will be approximately:  
1.2V  
10µA  
INTV current is limited to less than 40mA from a 40V  
CC  
tSS = CSS  
•
supply when not using the EXTV supply:  
CC  
T = 70°C + (40mA)(40V)(34°C/W) = 125°C  
J
V
OUT  
R
LTC3788  
SS  
B
A
LTC3788  
VFB  
C
SS  
R
SGND  
3788 F05  
3788 F04  
Figure 4. Setting Output Voltage  
Figure 5. Using the SS Pin to Program Soft-Start  
3788f  
21  
LTC3788  
APPLICATIONS INFORMATION  
To prevent the maximum junction temperature from being  
exceeded, the input supply current must be checked while  
operating in continuous conduction mode (PLLIN/MODE  
Fault Conditions: Overtemperature Protection  
At higher temperatures, or in cases where the internal  
power dissipation causes excessive self heating on-chip  
= INTV ) at maximum V .  
CC  
IN  
(such as an INTV short to ground), the overtemperature  
CC  
When the voltage applied to EXTV rises above 4.7V, the  
shutdown circuitry will shut down the LTC3788. When the  
CC  
V LDO is turned off and the EXTV LDO is enabled. The  
junction temperature exceeds approximately 170°C, the  
IN  
CC  
EXTV LDO remains on as long as the voltage applied to  
overtemperaturecircuitrydisablestheINTV LDO,causing  
CC  
CC  
EXTV remains above 4.55V. The EXTV LDO attempts  
the INTV supply to collapse and effectively shut down  
CC  
CC  
CC  
to regulate the INTV voltage to 5.4V, so while EXTV  
the entire LTC3788 chip. Once the junction temperature  
CC  
CC  
CC  
CC  
is less than 5.4V, the LDO is in dropout and the INTV  
dropsbacktoapproximately155°C, theINTV LDOturns  
CC  
voltage is approximately equal to EXTV . When EXTV  
back on. Long term overstress (T > 125°C) should be  
CC  
J
is greater than 5.4V, up to an absolute maximum of 6V,  
avoided as it can degrade the performance or shorten the  
INTV is regulated to 5.4V.  
life of the part.  
CC  
The following list summarizes possible connections for  
Phase-Locked Loop and Frequency Synchronization  
EXTV :  
CC  
The LTC3788 has an internal phase-locked loop (PLL)  
comprised of a phase frequency detector, a low pass filter  
and a voltage-controlled oscillator (VCO). This allows the  
turn-on of the top MOSFET of controller 1 to be locked to  
the rising edge of an external clock signal applied to the  
PLLIN/MODEpin.Theturn-onofcontroller2’stopMOSFET  
is thus 180 degrees out-of-phase with the external clock.  
The phase detector is an edge-sensitive digital type that  
provides zero degrees phase shift between the external  
and internal oscillators. This type of phase detector does  
not exhibit false lock to harmonics of the external clock.  
EXTV Left Open (or Grounded). This will cause  
CC  
INTV to be powered from the internal 5.4V regu-  
CC  
lator resulting in an efficiency penalty at high input  
voltages.  
EXTV Connected to an External Supply. If an exter-  
CC  
nal supply is available in the 5.4V to 6V range, it may  
be used to power EXTV providing it is compatible  
CC  
with the MOSFET gate drive requirements. Ensure that  
EXTV < VBIAS.  
CC  
Topside MOSFET Driver Supply (C , D )  
B
B
If the external clock frequency is greater than the internal  
External bootstrap capacitors C connected to the BOOST  
oscillator’sfrequency,f ,thencurrentissourcedcontinu-  
B
OSC  
pins supply the gate drive voltages for the topside MOS-  
ously from the phase detector output, pulling up the VCO  
FETs. CapacitorC intheBlockDiagramischargedthough  
input. When the external clock frequency is less than f  
,
B
OSC  
external diode D from INTV when the SW pin is low.  
current is sunk continuously, pulling down the VCO input.  
If the external and internal frequencies are the same but  
exhibit a phase difference, the current sources turn on for  
an amount of time corresponding to the phase difference.  
The voltage at the VCO input is adjusted until the phase  
and frequency of the internal and external oscillators are  
identical. At the stable operating point, the phase detector  
output is high impedance and the internal filter capacitor,  
B
CC  
When one of the topside MOSFETs is to be turned on, the  
driver places the C voltage across the gate-source of the  
B
desired MOSFET. This enhances the MOSFET and turns on  
the topside switch. The switch node voltage, SW, rises to  
V and the BOOST pin follows. With the topside MOSFET  
IN  
on, the boost voltage is above the input supply: V  
=
BOOST  
V + V  
. The value of the boost capacitor C needs  
IN  
INTVCC  
B
to be 100 times that of the total input capacitance of the  
C , holds the voltage at the VCO input.  
LP  
topsideMOSFET(s).Thereversebreakdownoftheexternal  
Schottky diode must be greater than V  
.
IN(MAX)  
3788f  
22  
LTC3788  
APPLICATIONS INFORMATION  
Typically, the external clock (on PLLIN/MODE pin) input  
high threshold is 1.6V, while the input low threshold is  
1.2V.  
Minimum On-Time Considerations  
Minimum on-time, t , is the smallest time duration  
that the LTC3788 is capable of turning on the bottom  
MOSFET. It is determined by internal timing delays and  
the gate charge required to turn on the top MOSFET. Low  
duty cycle applications may approach this minimum on-  
time limit.  
ON(MIN)  
Note that the LTC3788 can only be synchronized to an  
external clock whose frequency is within range of the  
LTC3788’sinternalVCO,whichisnominally55kHzto1MHz.  
This is guaranteed to be between 75kHz and 850kHz.  
RapidphaselockingcanbeachievedbyusingtheFREQpin  
to set a free-running frequency near the desired synchro-  
nization frequency. The VCO’s input voltage is prebiased  
at a frequency corresponding to the frequency set by the  
FREQ pin. Once prebiased, the PLL only needs to adjust  
the frequency slightly to achieve phase lock and synchro-  
nization. Although it is not required that the free-running  
frequency be near external clock frequency, doing so will  
prevent the operating frequency from passing through a  
large range of frequencies as the PLL locks.  
In forced continuous mode, if the duty cycle falls below  
what can be accommodated by the minimum on-time,  
the controller will begin to skip cycles but the output will  
continuetoberegulated.Morecycleswillbeskippedwhen  
V increases. Once V rises above V , the loop works  
IN  
IN  
OUT  
to keep the top MOSFET on continuously. The minimum  
on-time for the LTC3788 is approximately 110ns.  
Efficiency Considerations  
The percent efficiency of a switching regulator is equal to  
the output power divided by the input power times 100%.  
It is often useful to analyze individual losses to determine  
what is limiting the efficiency and which change would  
produce the greatest improvement. Percent efficiency  
can be expressed as:  
Table 2 summarizes the different states in which the FREQ  
pin can be used.  
Table 2.  
FREQ PIN  
PLLIN/MODE PIN  
DC Voltage  
FREQUENCY  
350kHz  
0V  
%Efficiency = 100% – (L1 + L2 + L3 + ...)  
INTV  
DC Voltage  
535kHz  
CC  
Resistor  
DC Voltage  
50kHz to 900kHz  
where L1, L2, etc., are the individual losses as a percent-  
age of input power.  
Any of the Above  
External Clock  
Phase Locked to  
External Clock  
1000  
900  
800  
700  
600  
500  
400  
300  
200  
100  
0
15 25 35 45 55 65 75 85 95 105 115 125  
FREQ PIN RESISTOR (kΩ)  
3788 F06  
Figure 6. Relationship Between Oscillator  
Frequency and Resistor Value at the FREQ Pin  
3788f  
23  
LTC3788  
APPLICATIONS INFORMATION  
Although all dissipative elements in the circuit produce  
losses, four main sources usually account for most of the  
Checking Transient Response  
The regulator loop response can be checked by looking at  
the load current transient response. Switching regulators  
take several cycles to respond to a step in DC (resistive)  
losses in LTC3788 circuits: 1) IC V current, 2) INTV  
IN  
CC  
2
regulator current, 3) I R losses, 4) Bottom MOSFET  
transition losses.  
load current. When a load step occurs, V  
shifts by an  
OUT  
1. The V current is the DC supply current given in the  
amount equal to ΔI  
(ESR), where ESR is the effective  
OUT  
generating the feedback error signal  
IN  
LOAD  
ElectricalCharacteristicstable,whichexcludesMOSFET  
series resistance of C . ΔI  
also begins to charge  
LOAD  
driver and control currents. V current typically results  
or discharge C  
IN  
OUT  
in a small (<0.1%) loss.  
thatforcestheregulatortoadapttothecurrentchangeand  
return V  
to its steady-state value. During this recovery  
can be monitored for excessive overshoot  
OUT  
2. INTV current is the sum of the MOSFET driver and  
CC  
time V  
OUT  
control currents. The MOSFET driver current results  
from switching the gate capacitance of the power MOS-  
FETs. Each time a MOSFET gate is switched from low to  
high to low again, a packet of charge, dQ, moves from  
or ringing, which would indicate a stability problem.  
OPTI-LOOP compensation allows the transient response  
to be optimized over a wide range of output capacitance  
and ESR values. The availability of the ITH pin not only  
allows optimization of control loop behavior, but it also  
provides a DC coupled and AC filtered closed loop re-  
sponse test point. The DC step, rise time and settling at  
this test point truly reflects the closed loop response.  
Assuming a predominantly second order system, phase  
margin and/or damping factor can be estimated using the  
percentage of overshoot seen at this pin. The bandwidth  
can also be estimated by examining the rise time at the  
INTV to ground. The resulting dQ/dt is a current out  
CC  
of INTV that is typically much larger than the control  
CC  
circuit current. In continuous mode, I  
= f(Q +  
GATECHG  
T
Q ),whereQ andQ arethegatechargesofthetopside  
B
T
B
and bottom side MOSFETs.  
2
3. DC I R losses. These arise from the resistances of  
the MOSFETs, sensing resistor, inductor and PC board  
traces and cause the efficiency to drop at high output  
currents.  
pin. The I external components shown in the Figure 9  
TH  
circuit will provide an adequate starting point for most  
4. Transition losses apply only to the bottom MOSFET(s),  
andbecomesignificantonlywhenoperatingatlowinput  
voltages. Transition losses can be estimated from:  
applications.  
The I series RC-CC filter sets the dominant pole-zero  
TH  
3
loop compensation. The values can be modified slightly  
(from 0.5 to 2 times their suggested values) to optimize  
transient response once the final PC layout is complete  
and the particular output capacitor type and value have  
been determined. The output capacitors must be selected  
because the various types and values determine the loop  
gain and phase. An output current pulse of 20% to 80%  
of full-load current having a rise time of 1μs to 10μs will  
produce output voltage and ITH pin waveforms that will  
give a sense of the overall loop stability without breaking  
the feedback loop.  
VOUT  
Transition Loss = (1.7)  
IO(MAX) • CRSS f  
V
IN  
Other hidden losses, such as copper trace and internal  
battery resistances, can account for an additional 5% to  
10% efficiency degradation in portable systems. It is very  
important to include these system-level losses during the  
design phase.  
Placing a power MOSFET and load resistor directly  
across the output capacitor and driving the gate with an  
appropriatesignalgeneratorisapracticalwaytoproduce  
a realistic load step condition. The initial output voltage  
stepresultingfromthestepchangeinoutputcurrentmay  
3788f  
24  
LTC3788  
APPLICATIONS INFORMATION  
not be within the bandwidth of the feedback loop, so this  
signal cannot be used to determine phase margin. This  
is why it is better to look at the ITH pin signal which is  
in the feedback loop and is the filtered and compensated  
control loop response.  
pin to GND, generating 350kHz operation. The minimum  
inductance for 30% ripple current is:  
⎛
⎞
⎟
V
V
IN  
IN  
ΔIL =  
1−  
⎜
f •L  
VOUT  
⎝
⎠
A 6.8μH inductor will produce a 31% ripple current. The  
peak inductor current will be the maximum DC value plus  
one half the ripple current, or 9.25A.  
The gain of the loop will be increased by increasing R  
C
and the bandwidth of the loop will be increased by de-  
creasing C . If R is increased by the same factor that C  
C
C
C
is decreased, the zero frequency will be kept the same,  
thereby keeping the phase shift the same in the most  
critical frequency range of the feedback loop. The output  
voltage settling behavior is related to the stability of the  
closed-loopsystemandwilldemonstratetheactualoverall  
supply performance.  
The R  
resistor value can be calculated by using the  
SENSE  
maximum current sense voltage specification with some  
accommodation for tolerances:  
75mV  
RSENSE  
≤
= 0.008Ω  
9.25A  
Choosing 1% resistors: R = 5k and R = 95.3k yields an  
A second, more severe transient is caused by switching  
in loads with large (>1μF) supply bypass capacitors. The  
dischargedbypasscapacitorsareeffectivelyputinparallel  
A
B
output voltage of 24.072V.  
The power dissipation on the top side MOSFET can  
be easily estimated. Choosing a Vishay Si7848BDP  
with C , causing a rapid drop in V . No regulator can  
OUT  
OUT  
alter its delivery of current quickly enough to prevent this  
sudden step change in output voltage if the load switch  
resistance is low and it is driven quickly. If the ratio of  
MOSFET results in: R  
= 0.012Ω, C  
= 150pF.  
DS(ON)  
MILLER  
At maximum input voltage with T(estimated) = 50°C:  
(24V − 12V) 24V  
•(4A)2  
C
to C  
is greater than 1:50, the switch rise time  
PMAIN  
=
LOAD  
OUT  
(12V)2  
should be controlled so that the load rise time is limited to  
approximately 25 • C . Thus, a 10μF capacitor would  
⎡
⎤
• 1+ (0.005)(50°C − 25°C) • 0.008Ω  
LOAD  
⎣
⎦
require a 250μs rise time, limiting the charging current  
to about 200mA.  
4A  
12V  
+ (1.7)(24V)3  
(150pF)(350kHz) = 0.7W  
C
is chosen to filter the square current in the output.  
OUT  
Design Example  
The maximum output current peak is:  
As a design example for one channel, assume V  
=
IN  
⎛
⎞
⎟
24  
12  
31%  
12V(nominal), V = 22V (max), V  
= 24V, I  
= 4A,  
IN  
OUT  
MAX  
IOUT(PEAK)  
=
• 4 1+  
= 9.3A  
⎜
⎝
V
= 75mV, and f = 350kHz.  
2 ⎠  
SENSE(MAX)  
Theinductancevalueischosenfirstbasedona30%ripple  
current assumption. The highest value of ripple current  
occurs at the maximum input voltage. Tie the PLLLPF  
A low ESR (5mꢁ) capacitor is suggested. This capacitor  
will limit output voltage ripple to 46.5mV (assuming ESR  
dominate ripple).  
3788f  
25  
LTC3788  
APPLICATIONS INFORMATION  
PC Board Layout Checklist  
6. Keep the switching nodes (SW1, SW2), top gate nodes  
(TG1, TG2) and boost nodes (BOOST1, BOOST2) away  
from sensitive small-signal nodes, especially from  
the opposites channel’s voltage and current sensing  
feedback pins. All of these nodes have very large and  
fast moving signals and, therefore, should be kept on  
the output side of the LTC3788 and occupy a minimal  
PC trace area.  
When laying out the printed circuit board, the following  
checklist should be used to ensure proper operation of  
the IC. These items are also illustrated graphically in the  
layout diagram of Figure 7. Figure 8 illustrates the current  
waveforms present in the various branches of the 2-phase  
synchronousregulatorsoperatinginthecontinuousmode.  
Check the following in your layout:  
7. Use a modified “star ground” technique: a low imped-  
ance, large copper area central grounding point on  
the same side of the PC board as the input and output  
1.PutthebottomN-channelMOSFETsMBOT1andMBOT2  
and the top N-channel MOSFETs MTOP1 and MTOP2  
in one compact area with C  
.
OUT  
capacitors with tie-ins for the bottom of the INTV  
CC  
2. Are the signal and power grounds kept separate? The  
combinedICsignalgroundpinandthegroundreturnof  
decouplingcapacitor,thebottomofthevoltagefeedback  
resistive divider and the SGND pin of the IC.  
C
mustreturntothecombinedC (–)terminals.  
INTVCC  
OUT  
The path formed by the bottom N-channel MOSFET and  
PC Board Layout Debugging  
the C capacitor should have short leads and PC trace  
IN  
Start with one controller on at a time. It is helpful to use  
a DC-50MHz current probe to monitor the current in the  
inductor while testing the circuit. Monitor the output  
switching node (SW pin) to synchronize the oscilloscope  
to the internal oscillator and probe the actual output volt-  
age. Check for proper performance over the operating  
voltage and current range expected in the application. The  
frequencyofoperationshouldbemaintainedovertheinput  
voltage range down to dropout and until the output load  
drops below the low current operation threshold— typi-  
cally 10% of the maximum designed current level in Burst  
Mode operation.  
lengths. The output capacitor (–) terminals should be  
connected as close as possible to the (–) terminals of  
the input capacitor by placing the capacitors next to  
each other.  
3. Do the LTC3788 VFB pins’ resistive dividers connect to  
the (+) terminals of C ? The resistive divider must be  
OUT  
connected between the (+) terminal of C  
and signal  
OUT  
ground and placed close to the VFB pin. The feedback  
resistor connections should not be along the high cur-  
rent input feeds from the input capacitor(s).  
–
+
4. Are the SENSE and SENSE leads routed together with  
minimumPCtracespacing?Thefiltercapacitorbetween  
Thedutycyclepercentageshouldbemaintainedfromcycle  
tocycleinawelldesigned, lownoisePCBimplementation.  
Variation in the duty cycle at a subharmonic rate can sug-  
gest noise pickup at the current or voltage sensing inputs  
or inadequate loop compensation. Overcompensation of  
the loop can be used to tame a poor PC layout if regulator  
bandwidth optimization is not required. Only after each  
controllerischeckedforitsindividualperformanceshould  
both controllers be turned on at the same time. A particu-  
larly difficult region of operation is when one controller  
channel is nearing its current comparator trip point while  
the other channel is turning on its bottom MOSFET. This  
occurs around the 50% duty cycle on either channel due  
to the phasing of the internal clocks and may cause minor  
duty cycle jitter.  
+
–
SENSE and SENSE should be as close as possible  
to the IC. Ensure accurate current sensing with Kelvin  
connections at the sense resistor.  
5. Is the INTV decoupling capacitor connected close  
CC  
to the IC, between the INTV and the power ground  
CC  
pins? This capacitor carries the MOSFET drivers’ cur-  
rent peaks. An additional 1μF ceramic capacitor placed  
immediatelynexttotheINTV andPGNDpinscanhelp  
CC  
improve noise performance substantially.  
3788f  
26  
LTC3788  
APPLICATIONS INFORMATION  
Reduce V from its nominal level to verify operation with  
effects of differential noise injection due to high frequency  
capacitive coupling.  
IN  
high duty cycle. Check the operation of the undervoltage  
lockout circuit by further lowering V while monitoring  
IN  
An embarrassing problem, which can be missed in an  
otherwise properly working switching regulator results  
when the current sensing leads are hooked up backwards.  
The output voltage under this improper hook-up will still  
bemaintained,buttheadvantagesofcurrentmodecontrol  
will not be realized. Compensation of the voltage loop will  
be much more sensitive to component selection. This  
behavior can be investigated by temporarily shorting out  
the current sensing resistor—don’t worry, the regulator  
will still maintain control of the output voltage.  
the outputs to verify operation.  
Investigate whether any problems exist only at higher out-  
put currents or only at higher input voltages. If problems  
coincide with high input voltages and low output currents,  
look for capacitive coupling between the BOOST, SW, TG,  
and possibly BG connections and the sensitive voltage  
and current pins. The capacitor placed across the current  
sensing pins needs to be placed immediately adjacent to  
the pins of the IC. This capacitor helps to minimize the  
–
SENSE1  
SENSE1  
SS1  
ILIM  
PGOOD1  
SW1  
+
V
PULL-UP  
R
L1  
SENSE1  
TG1  
LTC3788  
C
B1  
BOOST1  
BG1  
V
V
OUT1  
M1  
+
ITH1  
M2  
VBIAS  
PGND  
EXTV  
CC  
INTV  
CC  
VFB1  
FREQ  
PHSMD  
CLKOUT  
PLLIN/MODE  
SGND  
GND  
IN  
f
IN  
RUN1  
RUN2  
BG2  
M3  
+
C
B2  
M4  
VFB2  
V
BOOST2  
OUT2  
R
L2  
SENSE2  
ITH2  
TG2  
SW2  
SS2  
SENSE2  
SENSE2  
PGOOD2  
V
PULL-UP  
+
–
3788 F07  
Figure 7. Recommended Printed Circuit Layout Diagram  
3788f  
27  
LTC3788  
APPLICATIONS INFORMATION  
L1  
R
SENSE1  
V
OUT1  
C
OUT1  
R
L1  
SW1  
V
IN  
R
IN  
C
IN  
L2  
R
SENSE2  
V
OUT2  
C
OUT2  
R
L2  
SW2  
BOLD LINES INDICATE  
HIGH SWITCHING  
CURRENT. KEEP LINES  
TO A MINIMUM LENGTH.  
3788 F08  
Figure 8. Branch Current Waveforms  
3788f  
28  
LTC3788  
TYPICAL APPLICATIONS  
INTV  
CC  
100k  
100k  
–
+
SENSE1  
SENSE1  
PGOOD2  
PGOOD1  
V
OUT1  
R
B1  
24V, 5A  
C
OUTB1  
232k  
+
+
C
OUTA1  
22μF  
220μF  
R
A1  
LTC3788  
s 4  
12.1k  
L1  
R
SENSE1  
4mΩ  
MTOP1  
MBOT1  
VFB1  
ITH1  
TG1  
3.3μH  
C
, 220pF  
ITH1  
SW1  
BOOST1  
R
ITH1  
8.66k  
C
, 15nF  
ITH1  
C
, 0.1μF  
B1  
BG1  
D1  
C
, 0.1μF  
SS1  
V
IN  
VBIAS  
SS1  
ILIM  
5V TO 24V  
C
INB  
INTV  
CC  
C
INA  
C
INT  
PHSMD  
CLKOUT  
PLLIN/MODE  
SGND  
22μF  
220μF  
4.7μF  
s 4  
PGND  
D2  
, 0.1μF  
MBOT2  
MTOP2  
EXTV  
BG2  
CC  
C
B1  
RUN1  
RUN2  
FREQ  
BOOST2  
L2  
1.25μH  
R
SENSE2  
3mΩ  
C
, 0.1μF  
SS2  
SW2  
TG2  
SS2  
R
C
, 15nF  
ITH2  
ITH2  
2.7k  
ITH2  
C
, 100pF  
ITHA2  
V
OUT  
R
A2  
12V, 10A  
C
OUTB2  
12.1k  
+
C
VFB2  
SENSE2  
SENSE2  
OUTA2  
+
–
22μF  
220μF  
R
s 4  
B2  
110k  
3788 F09  
C
C
, C  
, C  
: SANYO, 50CE220AX  
INA OUTA1 OUTA2  
, C  
, C  
: TDK C4532X5R1E226M  
INB OUTB1 OUTB2  
L1: PULSE PA1494.362NL  
L2: PULSE PA1294.132NL  
MBOT1, MBOT2, MTOP1, MTOP2: RENESAS HAT2169H  
Figure 9. High Efficiency Dual ±2V/24V Boost Converter  
3788f  
29  
LTC3788  
APPLICATIONS INFORMATION  
R
53.6k, 1%  
S1  
R
S2  
INTV  
CC  
26.1k, 1%  
100k  
100k  
–
SENSE1  
SENSE1  
PGOOD2  
PGOOD1  
V
R
232k  
1%  
OUT1  
B1  
C1  
0.1μF  
24V, 4A  
C
OUTB1  
+
+
C
OUTA1  
C3  
0.1μF  
6.8μF  
220μF  
R
A1  
LTC3788  
s 4  
D3  
12.1k, 1%  
L1  
10.2μH  
MTOP1  
MBOT1  
VFB1  
ITH1  
TG1  
C
, 220pF  
ITH1  
SW1  
BOOST1  
R
ITH1  
C
, 15nF  
ITH1  
C
, 0.1μF  
8.87k, 1%  
B1  
BG1  
D1  
C
, 0.01μF  
SS1  
V
IN  
VBIAS  
SS1  
ILIM  
PHSMD  
CLKOUT  
PLLIN/MODE  
SGND  
5V TO 24V  
C
INB  
+
INTV  
CC  
C
INA  
C
INT  
22μF  
220μF  
4.7μF  
s 4  
PGND  
INTV  
CC  
D2  
, 0.1μF  
MBOT2B  
MBOT2A  
EXTV  
BG2  
CC  
C
B1  
RUN1  
RUN2  
FREQ  
R
FREQ  
BOOST2  
41.2k  
L2  
16μH  
C
, 0.1μF  
SS2  
SW2  
TG2  
SS2  
R
C
, 4.7nF  
ITH2  
ITH2  
D4  
23.7k, 1%  
MTOP2  
ITH2  
C
ITH2A  
220pF  
V
OUT2  
R
A2  
48V, 2A  
C
OUTB2  
12.1k, 1%  
+
C
VFB2  
OUTA2  
22μF  
220μF  
R
475k  
1%  
B2  
C4  
s 4  
0.1μF  
+
–
SENSE2  
C2  
0.1μF  
R
S4  
30.1k, 1%  
SENSE2  
R
42.2k, 1%  
S3  
3788 F10  
C
C
C
C
: C4532x7R1H685K  
: SANYO 63CE220KX  
MBOT1, MTOP1: RENESAS RJK0305  
OUTA1  
OUTB1  
MBOT2A, MBOT2B, MTOP2: RENESAS RJK0652  
D3: DIODES INC B340B  
, C  
: TDK C4532X5R1E226M  
: SANYO 50CE220AX  
INA OUTA2  
INB OUTB2  
, C  
D4: DIODES INC B360A  
L1: PULSE PA2050.103NL  
L2: PULSE PA2050.163NL  
Figure ±0. High Efficiency Dual 24V/48V Boost Converter with Inductor DCR Current Sensing  
3788f  
30  
LTC3788  
PACKAGE DESCRIPTION  
UH Package  
32-Lead Plastic QFN (5mm × 5mm)  
(Reference LTC DWG # 05-08-1693 Rev D)  
0.70 p0.05  
5.50 p0.05  
4.10 p0.05  
3.45 p 0.05  
3.50 REF  
(4 SIDES)  
3.45 p 0.05  
PACKAGE OUTLINE  
0.25 p 0.05  
0.50 BSC  
RECOMMENDED SOLDER PAD LAYOUT  
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED  
BOTTOM VIEW—EXPOSED PAD  
PIN 1 NOTCH R = 0.30 TYP  
OR 0.35 s 45° CHAMFER  
R = 0.05  
TYP  
0.00 – 0.05  
R = 0.115  
TYP  
0.75 p 0.05  
5.00 p 0.10  
(4 SIDES)  
31 32  
0.40 p 0.10  
PIN 1  
TOP MARK  
(NOTE 6)  
1
2
3.45 p 0.10  
3.50 REF  
(4-SIDES)  
3.45 p 0.10  
(UH32) QFN 0406 REV D  
0.200 REF  
0.25 p 0.05  
0.50 BSC  
NOTE:  
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE  
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)  
2. DRAWING NOT TO SCALE  
3. ALL DIMENSIONS ARE IN MILLIMETERS  
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE  
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE  
5. EXPOSED PAD SHALL BE SOLDER PLATED  
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION  
ON THE TOP AND BOTTOM OF PACKAGE  
3788f  
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.  
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-  
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.  
31  
LTC3788  
RELATED PARTS  
PART NUMBER  
DESCRIPTION  
COMMENTS  
4.5V ≤ V ≤ 38V, V  
LTC3788-1  
2-Phase, Dual Output Synchronous Step-Up  
Controller  
Up to 60V, 50kHz to 900kHz, SSOP-28 Package  
OUT  
IN  
LTC3862/LTC3862-1  
LTC3813  
Multiphase Current Mode Step-Up DC/DC  
Controller  
4V ≤ V ≤ 36V, 5V or 10V Gate Drive, 75kHz to 500kHz  
IN  
100V Maximum V  
Current Mode Synchronous No R  
, Large 1ꢁ Gate Driver, Adjustable Off-Time, SSOP-28 Package  
, Large 1ꢁ Gate Driver, Adjustable Off-Time, TSSOP-16 Package  
OUT  
SENSE  
Step-Up DC/DC Controller  
LTC3814-5  
60V Maximum V Current Mode Synchronous  
No R  
OUT  
SENSE  
Step-Up DC/DC Controller  
LTC1871/LTC1871-1/ Wide Input Range, No R  
Low Quiescent  
Adjustable Switching Frequency, 2.5V ≤ V ≤ 36V, Burst Mode Operation  
SENSE  
IN  
LTC1871-7  
Current Flyback, Boost and SEPIC Controller  
at Light Load, MSOP-10 Package  
LT3757  
Boost, Flyback, SEPIC and Inverting Controller  
2.9V ≤ V ≤ 40V, 100kHz to 1MHz Programmable Operation Frequency,  
IN  
3mm × 3mm DFN-10 and MSOP-10E Packages  
LT3758  
Boost, Flyback, SEPIC and Inverting Controller  
2-Phase Step-Up DC/DC Controller  
5.5V ≤ V ≤ 100V, 100kHz to 1MHz Programmable Operation Frequency,  
IN  
3mm × 3mm DFN-10 and MSOP-10E Packages  
LT3782A  
LT3580  
6V≤ V ≤ 40V, Optional Synchronous Operation  
IN  
Boost/Inverting DC/DC Converter with 2A Switch,  
Soft-Start and Synchronization  
2.5V ≤ V ≤ 32V, 200kHz to 2.5MHz, 3mm × 3mm DFN-8 and MSOP-8E  
IN  
Packages  
LTC3872  
No R  
Current Mode Boost DC/DC Controller 550kHz Fixed Frequency, 2.75V ≤ V ≤ 9.8V, ThinSOT Package  
SENSE  
IN  
LTC3857/LTC3857-1  
Low I , Dual 2-Phase Synchronous Step-Down  
4V ≤ V ≤ 38V, 0.8V ≤ V  
≤ 24V, 50μA I  
Q
Q
IN  
OUT  
DC/DC Controller  
LTC3780  
High Efficiency Synchronous 4-Switch  
Buck-Boost DC/DC Controller  
4V ≤ V ≤ 36V, 0.8V ≤ V  
≤ 30V, SSOP-24 and 5mm × 5mm QFN-32  
IN  
OUT  
Packages  
3788f  
LT 1209 • PRINTED IN USA  
LinearTechnology Corporation  
1630 McCarthy Blvd., Milpitas, CA 95035-7417  
32  
●
●
© LINEAR TECHNOLOGY CORPORATION 2009  
(408) 432-1900 FAX: (408) 434-0507 www.linear.com  

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