LTC3875IUH#PBF_技术文档

LTC3875

Dual, 2-Phase, Synchronous

Controller with Low Value DCR Sensing

and Temperature Compensation

FEATURES

DESCRIPTION

The LTC^®3875 is a dual output current mode synchronous

n

Low Value DCR Current Sensing

Programmable DCR Temperature Compensation

0.ꢀ5 0.6V Output Voltage Accuracy

Dual True Remote Sensing Differential Amplifiers

Optional Fast Transient Operation

n

step-down DC/DC controller that drives all N-channel

synchronous power MOSFET stages. It employs a unique

architecture which enhances the signal-to-noise ratio of

the current sense signal, allowing the use of very low DC

resistance power inductors to maximize the efficiency in

high current applications. This feature also reduces the

switching jitter commonly found in low DCR applications.

n

Phase-Lockable Fixed Frequency 2ꢀ0kHz to 720kHz

Dual, 180° Phased Controllers Reduce Required

Input Capacitance and Power Supply Induced Noise

Dual N-Channel MOSFET Synchronous Drive

n

TheLTC3875featurestwohighspeedremotesensediffer-

ential amplifiers, programmable current sense limits from

10mVto30mVandDCRtemperaturecompensationtolimit

the maximum output current precisely over temperature.

Wide V Range: 4.5V to 38V Operation

IN

Output Voltage Range with Low DCR: 0.6V to 3.5V,

without Low DCR: 0.6V to 5V

n

Adjustable Soft-Start Current Ramping or Tracking

Foldback Output Current Limiting

Clock Input and Output for Up to 12-Phase Operation

Short-Circuit Soft Recovery

Output Overvoltage Protection

Power Good Output Voltage Monitor

40-Lead QFN Packages

Auniquethermalbalancingfunctionadjustsperphasecur-

rent in order to minimize the thermal stress for multichip

single output applications. The LTC3875 also features a

precise0.6Vreferencewithguaranteedaccuracyof 0.5ꢀ

thatprovidesanaccurateoutputvoltagefrom0.6Vto3.5V.

A 4.5V to 38V input voltage range allows it to support a

wide variety of bus voltages. The LTC3875 is available

in a low profile 40-lead 6mm × 6mm (0.5mm pitch) and

40-lead 5mm × 5mm (0.4mm pitch) QFN packages.

L, LT, LTC, LTM, Linear Technology, the Linear logo OPTI-LOOP, Burst Mode and PolyPhase

APPLICATIONS

n

Servers and Instruments

n

are registered trademarks and No R

is a trademark of Linear Technology Corporation.

Telecom Systems

SENSE

All other trademarks are the property of their respective owners. Protected by U.S. Patents

including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066, 6580258.

n

DC Power Distribution Systems

TYPICAL APPLICATION

High Efficiency Dual Phase 1.2V/60A Step-Down Converter

V

IN

6V TO 14V

22µF

Efficiency and Power Loss

vs Load Current

INTV

CC

16V ×4

4.7µF

V

INTV

CC

PHASMD

CLKOUT

PGOOD

IFAST

IN

(OPTIONAL)

RUN1,2

ILIM

ENTMPB

TG1

100

95

90

85

80

75

70

14

12

10

8

12V

IN

1.8V

O

~400kHz

CCM

THERMAL

SENSOR

THERMAL

SENSOR

MODE/PLLIN

TG2

0.3µH

(0.32mΩ DCR)

BOOST1

BOOST2

SW2

(0.32mΩ DCR)

LTC3875

CC

SW1

EXTV

BG1

BG2

TAVG

PGND

6

TRSET1

TRSET2

+

SNSA1

SNS1

SNSD1

+

SNSA2

–

4

–

SNS2

0.32mΩ

1.5mΩ

0.32mΩ PLOSS

1.5mΩ PLOSS

+

SNSD2

2

TCOMP1

TCOMP2

+

–

V

OUT

OSNS1

TH1

V

1.2V

60A

FREQ

20k

OUT

+

V

0

V

OSNS2

I

0

20

30

40

50

60

10

–

I

+

470µF

2.5V ×2

SP

LOAD CURRENT (A)

1500pF

122k 15k

TK/SS1 TK/SS2

TH2

+

470µF

2.5V ×2

20k

3875 TA01b

0.1µF

SP

3875 TA01a

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For more information www.linear.com/LTC3875

LTC3875

ABSOLUTE MAXIMUM RATINGS

(Note 1)

Input Supply Voltage (V )......................... 40V to –0.3V

MODE/PLLIN, ILIM, FREQ, IFAST, ENTMPB

IN

+

–

Topside Driver Voltages

V

, V

Voltages ...............INTV to –0.3V

OSNS(s)

OSNS(s) CC

(BOOST1, BOOST2).................................... 46V to –0.3V

Switch Voltage (SW1, SW2).......................... 40V to –5V

I

, I , PHASMD, TRSET1, TRSET2,

TH1 TH2

TCOMP1, TCOMP2, TAVG Voltages.......INTV to –0.3V

CC

INTV , RUN(s), PGOOD, EXTV

INTV Peak Output Current................................100mA

CC

(BOOST-SW1), (BOOST2-SW2).................... 6V to –0.3V

Operating Junction Temperature Range

+

SNSA (s), SNSD (s),

(Notes 2, 3)............................................ –40°C to 125°C

Storage Temperature Range .................. –65°C to 125°C

–

SNS (s) Voltages ..................................INTV to –0.3V

CC

PIN CONFIGURATION

TOP VIEW

40 39 38 37 36 35 34 33 32 31

TK/SS1

+

1

2

3

4

5

6

7

8

9

30

29

28

TK/SS1

+

1

2

3

4

5

6

7

8

9

30

29

28

SW1

V

OSNS1

TG1

OSNS1

–

V

BOOST1

OSNS1

I

OSNS1

I

27 BG1

TH1

I

26

25

V

IN

26

25

V

IN

TH2

+

TH2

+

41

SGND/PGND

V

INTV

CC

OSNS2

CC

–

24 EXTV

CC

OSNS2

CC

TK/SS2

23

TK/SS2

23

BG2

22 BOOST2

21

BG2

22 BOOST2

21

+

SNSA2

–

SNS2 10

TG2

11 12 13 14 15 16 17 18 19 20

UJ PACKAGE

40-LEAD (6mm × 6mm) PLASTIC QFN

UH PACKAGE

40-LEAD (5mm × 5mm) PLASTIC QFN

T

= 125°C, θ = 33°C/W, θ = 2.0°C/W

T

= 125°C, θ = 44°C/W, θ = 7.3°C/W

JMAX

JA

JC

JMAX JA JC

EXPOSED PAD (PIN 41) IS SGND/PGND, MUST BE SOLDERED TO PCB

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For more information www.linear.com/LTC3875

LTC3875

ORDER INFORMATION

LEAD FREE FINISH

LTC3875EUH#PBF

LTC3875IUH#PBF

LTC3875EUJ#PBF

LTC3875IUJ#PBF

TAPE AND REEL

PART MARKING

3875

PACKAGE DESCRIPTION

TEMPERATURE RANGE

–40°C to 125°C

LTC3875EUH#TRPBF

LTC3875IUH#TRPBF

LTC3875EUJ#TRPBF

LTC3875IUJ#TRPBF

40-Lead (5mm × 5mm) Plastic QFN

40-Lead (6mm × 6mm) Plastic QFN

3875

LTC3875

Consult LTC Marketing for parts specified with wider operating temperature ranges.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPBF suffix.

The l denotes the specifications which apply over the specified operating

ELECTRICAL CHARACTERISTICS

junction temperature range, otherwise specifications are at T_A= 2ꢀ°C (Note 2). V_IN= 1ꢀV, V_RUN1,2= ꢀV unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Main Control Loops

V

Input Voltage Range

Output Voltage Range

4.5

38

V

IN

+

SNSD Pin to V

0.6

3.5

5

V

OUT

SNSD Pin to GND

+

V

Regulated V

Feedback Voltage

(Note 4); I

Voltage = 1.2V, –40°C to 85°C

Voltage = 1.2V,–40°C to 125°C

0.597 0.600 0.603

0.5965 0.600 0.6045

V

OSNS1,2

OUT

TH1,2

l

Including Diffamp Error

+

I

Feedback Current

(Note 4)

–30

–100

nA

OSNS1,2

V

Reference Voltage Line Regulation

Output Voltage Load Regulation

V

= 4.5V to 38V (Note 4)

0.002 0.005

ꢀ/V

REFLNREG

IN

(Note 4)

Measured in Servo Loop; ∆I Voltage = 1.2V to 0.7V

LOADREG

l

0.01

0.1

ꢀ

TH

Measured in Servo Loop; ∆I Voltage = 1.2V to 1.6V

–0.01 –0.1

2.2

g

m1,2

Transconductance Amplifier g

I = 1.2V; Sink/Source 5µA (Note 4)

TH1,2

mmho

m

Thermal Functions

I

Thermal Sensor Current

Internal Thermal Shutdown

Internal TS Hysteresis

29

9

30

160

10

31

µA

°C

TCOMP1,2

T

(Note 8)

SHDN

HYS

Fast Transient Functions

Fast Transient Program Current

Current Sensing Functions

l

I

10

11

2

µA

FAST

+

I

AC Sense Pins Bias Current

DC Sense Pins Bias Current

Total Sense Gain to Current Comp

Each Channel; V

= 3.3V

0.5

30

5

µA

nA

SENSE(AC)

SENSE(DC)

SNSA (S)

+

50

SNSD (S)

A

V/V

VT(SNS)

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For more information www.linear.com/LTC3875

LTC3875

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 2ꢀ°C (Note 2). V_IN= 1ꢀV, V_RUN1,2= ꢀV unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Maximum Current Sense Threshold 0°C to 85°C

SENSE(MAX)(DC)

+

–

SNS (s)

–

with SNSD Pin to V

V

= 1.2V, ILIM = 0V

9

10

15

20

25

30

11

16

mV

OUT

= 1.2V, ILIM = 1/4 INTV

14

SNS (s)

–

CC

V

= 1.2V, ILIM = 1/2 INTV

= 1.2V, ILIM = 3/4 INTV

19

23.5

28.5

21

SNS (s)

–

26.5

31.5

SNS (s)

–

= 1.2V, ILIM = INTV

SNS (s)

CC

–40°C to 125°C

–

l

V

= 1.2V, ILIM = 0V

8.5

13.5

17.5

22

10

15

20

25

30

11.5

16.5

22.5

28

mV

SNS (s)

–

SNS (s)

–

= 1.2V, ILIM = 1/4 INTV

CC

V

= 1.2V, ILIM = 1/2 INTV

= 1.2V, ILIM = 3/4 INTV

SNS (s)

–

SNS (s)

–

= 1.2V, ILIM = INTV

26.5

33.5

SNS (s)

CC

–

l

V

Maximum Current Sense Threshold

V

= 1.2V, ILIM = 0V

45

70

95

117.5

142.5

50

75

100

125

150

55

80

105

132.5

157.5

mV

SENSE(MAX)(NODE)

SNS (s)

+

–

SNS (s)

–

with SNSD Pin to GND

= 1.2V, ILIM = 1/4 INTV

= 1.2V, ILIM = 1/2 INTV

= 1.2V, ILIM = 3/4 INTV

CC

SNS (s)

–

SNS (s)

–

= 1.2V, ILIM = INTV

SNS (s)

CC

I

Channel-to-Channel Current

Mismatch

ILIM = Float, ENTMPB = Float

(Thermal Balance Disabled)

5

ꢀ

MISMATCH

Input DC Supply Current

Normal Mode

Shutdown

(Note 5)

Q

V

= 15V (without EXTV Enabled)

RUN1,2

7

40

10

60

mA

µA

IN

CC

= 0V

UVLO

Undervoltage Lockout

UVLO Hysteresis

V

Ramping Down

3.5

3.7

0.5

4.0

V

INTVCC

UVLO Hyst

+

l

V

OVL

Feedback Overvoltage Lockout

Soft-Start Charge Current

RUN Pin On Threshold

RUN Pin On Hysteresis

Measured at V

0.625 0.645 0.665

V

OSNS1,2

I

V = 0V

TK/SS1,2

1.0

1.1

1.25

1.22

80

1.5

µA

V

TK/SS1,2

V

V , V Rising

RUN1 RUN2

1.35

RUN1,2

mV

RUN1,2HYS

Driver Functions

TG Transition Time

Rise Time

Fall Time

(Note 6)

TG1,2 t

C

= 3300pF

25

ns

r

f

LOAD

BG Transition Time

Rise Time

Fall Time

(Note 6)

BG1,2 t

C

= 3300pF

25

ns

r

f

LOAD

TG/BG t

Top Gate Off to Bottom Gate On

Delay Synchronous Switch-On

Delay Time

C

= 3300pF Each Driver

30

90

ns

1D

LOAD

BG/TG t

Bottom Gate Off to Top Gate On

Delay Synchronous Switch-On

Delay Time

= 3300pF Each Driver

2D

LOAD

t

Minimum On-Time

(Note 7)

ON(MIN)

3875fb

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For more information www.linear.com/LTC3875

LTC3875

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 2ꢀ°C (Note 2). V_IN= 1ꢀV, V_RUN1,2= ꢀV unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

INTV Linear Regulator

CC

INTVCC

V

Internal V Voltage

6V < V < 38V

5.3

5.5

0.5

4.7

50

5.7

2.0

V

ꢀ

CC

IN

INT

INTV Load Regulation

I

= 0mA to 20mA

CC

LDO

CC

l

EXTV Switchover Voltage

EXTV Ramping Positive

4.5

V

EXTVCC

CC

EXT

EXTV Voltage Drop

I

= 20mA, V = 5.5V

EXTVCC

100

mV

LDO

CC

EXTV Hysteresis

200

LDOHYS

CC

Oscillator and Phase-Locked Loop

f

Nominal Frequency

V

= 1.2V

= 0V

450

220

650

500

250

720

250

10

550

270

790

kHz

kΩ

µA

NOM

LOW

HIGH

FREQ

Lowest Frequency

Highest Frequency

≥ 2.4V

R

MODE/PLLIN Input Resistance

Frequency Setting Current

Phase (Relative to Controller 1)

MODE/PLLIN

FREQ

I

9.5

10.5

CLKOUT

PHASMD = GND

60

90

120

Deg

PHASMD = FLOAT

PHASMD = INTV

CC

CLK High

CLK Low

Clock Output High Voltage

Clock Output Low Voltage

PGOOD Voltage Low

V

= 5.5V

4.5

5.5

V

INTVCC

0.2

0.3

2

V

PGL

I

= 2mA

= 5.5V

0.1

V

PGOOD

I

PGOOD Leakage Current

PGOOD Trip Level, Either Controller

V

µA

PGOOD

+

V

PG

with Respect to Set Output Voltage

OSNS

+

V

OSNS

V

OSNS

Ramping Negative

Ramping Positive

–7.5

7.5

ꢀ

On-Chip Driver

TG R

BG R

TG Pull-Up R

TG High

TG Low

BG High

BG Low

2.6

1.5

2.4

1.1

Ω

UP

DS(ON)

TG Pull-Down R

DOWN

UP

DS(ON)

BG Pull-Up R

DS(ON)

BG Pull-Down R

DOWN

DS(ON)

Note 3: T is calculated from the ambient temperature, T , and power

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

J

A

dissipation, P , according to the formula:

D

T = T + (P • θ °C/W)

J

A

D

JA

where θ = 44°C/W for the 5mm × 5mm QFN and θ = 33°C/W for

JA

Note 2: The LTC3875 is tested under pulsed load conditions such that

the 6mm × 6mm QFN.

T ≈ T . The LTC3875E is guaranteed to meet specifications from

J

A

Note 4: The LTC3875 is tested in a feedback loop that servos V

to a

ITH1,2

+

0°C to 85°C junction temperature. Specifications over the –40°C to

125°C operating junction temperature range are assured by design,

characterization and correlation with statistical process controls. The

LTC3875I is guaranteed over the full –40° to 125° operating junction

temperature range. Note that the maximum ambient temperature

consistent with these specifications is determined by specific operating

conditions in conjunction with board layout, the rated package thermal

impedance and other environmental factors.

specified voltage and measures the resultant V

.

OSNS1,2

Note ꢀ: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency. See Applications Information.

Note 6: Rise and fall times are measured using 10ꢀ and 90ꢀ levels. Delay

times are measured using 50ꢀ levels.

Note 7: The minimum on-time condition is specified for an inductor

peak-to-peak ripple current ≥40ꢀ of I

(see Minimum On-Time

MAX

Considerations in the Applications Information section).

Note 8: Guaranteed by design.

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For more information www.linear.com/LTC3875

LTC3875

TYPICAL PERFORMANCE CHARACTERISTICS

Load Step

(Figure 16 Application Circuit)

(Burst Mode Operation)

Efficiency vs Output Current and

Mode (Figure 16 Application Circuit)

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

Burst Mode

OPERATION

I

LOAD

40A/DIV

5A TO 30A

Burst Mode

OPERATION

I

L1, L2

10A/DIV

CCM

PULSE-SKIPPING

PULSE-

SKIPPING

V

OUT

100mV/DIV

AC-COUPLED

3875 G03

V

= 12V

10µs/DIV

IN

OUT

V

= 12V

V

= 12V

OUT

IN

OUT

IN

= 1.5V

= 1V

0.01

0.1

1

10

100

0.01

0.1

1

10

100

LOAD CURRENT (A)

3875 G01

3875 G02

Load Step

(Figure 16 Application Circuit)

(Forced Continuous Mode)

Load Step

(Figure 16 Application Circuit)

(Pulse-Skipping Mode)

Prebiased Output at 1V

I

LOAD

V

40A/DIV

OUT

1V/DIV

5A TO 30A

I

L1, L2

10A/DIV

+

V

OSNS

500mV/DIV

V

OUT

TK/SS

500mV/DIV

100mV/DIV

AC-COUPLED

3875 G06

3875 G04

3875 G05

V

= 12V

2.5ms/DIV

V

= 12V

10µs/DIV

V

= 12V

10µs/DIV

IN

OUT

IN

OUT

IN

OUT

= 1.5V

CCM: NO LOAD

Tracking Up and Down

with External Ramp

Quiescent Current

Coincident Tracking

vs Temperature without EXTV_CC

10.0

9.5

9.0

8.5

8.0

7.5

7.0

6.5

6.0

5.5

5.0

TK/SS1

TK/SS2

2V/DIV

RUN

2V/DIV

V

OUT2

V

OUT1

OUT2

V

OUT1

V

OUT1

OUT2

OUT1

OUT2

1V/DIV

500mV/DIV

3875 G07

3875 G08

V

= 12V

2.5ms/DIV

= 12Ω, CCM

LOAD

V

= 12V

10ms/DIV

= 1V, 1Ω LOAD

IN

= 1.5V, R

OUT1

OUT2

LOAD

OUT1

OUT2

= 1V, R

= 6Ω, CCM

= 1.5V, 1.5Ω LOAD

–50 –30 –10 10 30 50 70 90 110 130

TEMPERATURE (°C)

3875 G09

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For more information www.linear.com/LTC3875

LTC3875

TYPICAL PERFORMANCE CHARACTERISTICS

Current Sense Threshold

vs I_THVoltage

Maximum Current Sense Threshold

vs Common Mode Voltage

INTV_CCLine Regulation

40

35

30

25

20

15

10

5

35

30

25

6

5

4

3

2

1

0

ILIM = 0

ILIM = INTV

CC

ILIM = 1/4 INTV

CC

ILIM = 1/2 INTV

ILIM = 3/4 INTV

ILIM = INTV

ILIM = 3/4 INTV

CC

ILIM = 1/2 INTV

ILIM = 1/4 INTV

ILIM = GND

CC

20

15

10

5

CC

0

–5

–10

0

25 30

10 15 20

INPUT VOLTAGE (V)

0

5

35 40

0

1

2

3

4

0

0.5

1

1.5

2

I

TH

VOLTAGE (V)

V

COMMON MODE VOLTAGE (V)

SENSE

3875 G10

3875 G12

3875 G11

Maximum Current Sense

Threshold vs Feedback Voltage

(Current Foldback)

TK/SS Pull-Up Current

vs Temperature

Shutdown (RUN) Threshold

vs Temperature

35

30

25

20

15

10

5

1.30

1.25

1.40

1.35

1.30

1.25

1.20

1.15

1.10

1.05

1.00

ILIM = INTV

CC

ILIM = 3/4 INTV

CC

ON

1.20

1.15

ILIM = 1/2 INTV

ILIM = 1/4 INTV

ILIM = GND

CC

OFF

1.10

1.05

1.00

0

0.4

FEEDBACK VOLTAGE (V)

0.6

–50 –30

30 50

110 130

–50

0

50

100

150

0

0.1

0.2

0.3

0.5

–10 10

70 90

TEMPERATURE (°C)

3875 G13

3875 G14

4320 G01

Regulated Feedback Voltage

vs Temperature

Oscillator Frequency

vs Temperature

0.6045

0.6035

0.6025

0.6015

0.6005

0.5995

0.5985

0.5975

0.5965

900

800

700

600

500

400

300

200

100

0

V

= INTV

CC

FREQ

V

= 1.22V

= GND

FREQ

V

FREQ

0.5955

50

TEMPERATURE (°C)

–50

0

100

150

–50 –30 –10 10 30 50

TEMPERATURE (°C)

130

70 90 110

3875 G17

3875 G16

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For more information www.linear.com/LTC3875

LTC3875

TYPICAL PERFORMANCE CHARACTERISTICS

Oscillator Frequency

vs Input Voltage

Shutdown Current

vs Input Voltage

Undervoltage Lockout Threshold

(INTV_CC) vs Temperature

50

45

40

35

30

25

20

15

10

5

5.0

4.8

4.6

4.4

4.2

4.0

3.8

3.6

3.4

3.2

3.0

900

800

700

600

500

400

300

200

100

0

V

= INTV

CC

FREQ

RISING

V

= 1.22V

= GND

FREQ

FALLING

V

FREQ

0

30 35

20

INPUT VOLTAGE (V)

5

10 15

20

INPUT VOLTAGE (V)

25

40

0

10

30

40

–50

0

50

100

150

TEMPERATURE (°C)

3875 G20

3875 G19

3875 G18

Quiescent Current vs Input

Voltage without EXTV_CC

Shutdown Current vs Temperature

Very Low Output Voltage Ripple

50

45

40

35

30

25

20

15

10

8

7

6

5

4

3

2

1

0

V

OUT

TYPICAL

FRONT PAGE

10mV/DIV

AC-COUPLED

V

OUT

LOW RIPPLE

FIGURE 20

10mV/DIV

AC-COUPLED

3875 G23

2µs/DIV

V

= 12V

IN

OUT

= 2.5V

30 50

TEMPERATURE (°C)

–50 –30 –10 10

70 90 110 130

20 25

INPUT VOLTAGE (V)

0

5

10 15

30 35 40

3875 G21

3875 G22

3875fb

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For more information www.linear.com/LTC3875

LTC3875

PIN FUNCTIONS

ENTMPB (Pin 18): Enable Pin for Temperature Balanc-

ing Function. Ground this pin to enable the temperature

balancing function. Float this pin for normal operation.

TK/SS1, TK/SS2 (Pin 1, Pin 8): Output Voltage Tracking

and Soft-Start Inputs. When one channel is configured to

be the master, a capacitor to ground at this pin sets the

ramp rate for the master channel’s output voltage. When

the channel is configured to be the slave, the feedback

voltage of the master channel is reproduced by a resistor

divider and applied to this pin. Internal soft-start currents

of 1.25µA charge these pins.

PGOOD(Pin19):PowerGoodIndicatorOutput.Open-drain

logic that is pulled to ground when either channel’s output

exceeds 7.5ꢀ regulation window, after the internal 20µs

power bad mask timer expires.

EXTV (Pin24):ExternalPowerInputtoanInternalSwitch

CC

+

V

,V

(Pin2,Pin6):PositiveInputsofRemote

OSNS1

OSNS2

Connected to INTV . This switch closes and supplies the

CC

Sensing Differential Amplifiers. These pins receive the

remotely sensed feedback voltage from external resistive

divider across the output. The differential amplifier out-

puts are connected directly to the error amplifiers’ inputs

internally inside the IC.

IC power, bypassing the internal low dropout regulator,

whenever EXTV is higher than 4.7V. Do not exceed 6V

CC

on this pin and make sure that EXTV < V at all times.

CC

IN

INTV (Pin 2ꢀ): Internal 5.5V Regulator Output. The con-

CC

trol circuits are powered from this voltage. Decouple this

pin to PGND with a minimum of 4.7µF low ESR tantalum

or ceramic capacitor.

–

V

, V

(Pin 3, Pin 7): Negative Inputs of Re-

OSNS1

OSNS2

mote Sensing Differential Amplifiers. Connect these pins

to the negative terminal of the output capacitors when

remote sensing is desired. Connect these pins to local

signal ground if remote sensing is not used.

V

(Pin 26): Main Input Supply. Decouple this pin to

IN

PGND with a capacitor (0.1µF to 1µF).

BG1, BG2 (Pin 27, Pin 23): Bottom Gate Driver Outputs.

I

, I

(Pin 4, Pin ꢀ): Current Control Threshold and

TH1 TH2

These pins drive the gates of the bottom N-channel

Error Amplifier Compensation Points. The current com-

parators’ tripping thresholds increase with these control

voltages.

MOSFETs between INTV and PGND.

CC

BOOST1, BOOST2 (Pin 28, Pin 22): Boosted Floating

DriverSupplies. The (+)terminal ofthe booststrapcapaci-

tors connect to these pins. These pins swing from a diode

voltage drop below INTV up to V + INTV .

TAVG (Pin13):AverageTemperatureSummingPoint.Con-

nect a resistor to ground to sum all currents together for

multi-channels or multi-IC operations when temperature

balancing function is enabled. The value of the resistor

should be the TRSET resistor value divided by the number

of channels in the system. Float this pin if thermal balanc-

ing is not used.

CC

IN

CC

TG1,TG2(Pin29,Pin21):Top GateDriverOutputs.These

are the outputs of floating drivers with a voltage swing

equaltoINTV superimposedontheswitchnodevoltage.

CC

SW1, SW2 (Pin 30, Pin 20): Switch Node Connections to

FREQ (Pin 1ꢀ): There is a precision 10µA current flowing

out of this pin. A resistor to ground sets a voltage which

in turn programs the frequency. Alternatively, this pin can

be driven with a DC voltage to vary the frequency of the

internal oscillator.

Inductors. Voltage swing at these pins is from a Schottky

diode (external) voltage drop below ground to V .

IN

CLKOUT (Pin 31): Clock Output Pin. Clock output with

phasechangeablebyPHASMDtoenableusageofmultiple

LTC3875s in multiphase systems signal swing is from

IFAST (Pin 17): Programmable Pin for Fast Transient Op-

eration for Channel 2 Only. A resistor to ground programs

the threshold of the output load transient excursion. Float

this pin to disable this function. See the Applications

Information section for more details.

INTV to ground.

CC

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LTC3875

PIN FUNCTIONS

PHASMD(Pin32):PhaseProgrammablePin. Thispincan

TCOMP1/ITEMP1, TCOMP2/ITEMP2 (Pin 37, Pin 12):

Input of the Temperature Balancing Circuitries. Connect

thesepinstoexternalNTCresistorsortemperaturesensing

ICs placed near inductors. These pins are used to sense

temperature of each channel and balance the temperature

of the whole system accordingly. When thermal balancing

function is disabled, these pins can be programmed to

compensate the temperature coefficient of the DCR. Con-

nect to an NTC (negative tempco) resistor placed near the

output inductor to compensate for its DCR change over

temperature.FloatingthispindisablestheDCRtemperature

compensation function.

be tied to SGND, INTV or left floating. It determines the

CC

relative phases between the internal controllers as well

as the phasing of the CLKOUT signal. See Table 1 in the

Operation section for details.

MODE/PLLIN (Pin 33): Forced Continuous Mode, Burst

Mode or Pulse-Skipping Mode Selection Pin and External

Synchronization Input to Phase Detector Pin. Connect

this pin to SGND to force the IC into continuous mode of

operation. Connect to INTV to enable pulse-skipping

CC

mode of operation. Leave the pin floating to enable Burst

Mode operation. A clock on the pin will force the IC into

continuousmodeofoperationandsynchronizetheinternal

oscillatorwiththeclockonthispin.ThePLLcompensation

network is integrated into the IC.

+

SNSD1 ,SNSD2 (Pin38,Pin11):DCCurrentSenseCom-

parator Inputs. The (+) input to the DC current comparator

is normally connected to a DC current sensing network.

Ground these pins to disable the novel DCR sensing and

enable normal DCR sensing with five times current limit.

RUN1, RUN2 (Pin 34, Pin 16): Run Control Inputs. A volt-

age above 1.22V on either pin turns on the IC. However,

forcing both pins below 1.14V causes the IC to shut down.

There is a 1.0µA pull-up current for both pins. Once the

RUN pin rises above 1.22V, an additional 4.5µA pull-up

current is added to the pin.

–

SNS1 , SNS2 (Pin 39, Pin 10): AC and DC Current

Sense Comparator Inputs. The (–) inputs to the current

comparators are connected to the output.

+

SNSA1 , SNSA2 (Pin 40, Pin 9): AC Current Sense

Comparator Inputs. The (+) input to the AC current com-

parator is normally connected to a DCR sensing network.

ILIM(Pin3ꢀ):CurrentComparators’SenseVoltageRange

Input. A resistor divider sets the maximum current sense

thresholdtofivedifferentlevelsforthecurrentcomparators.

+

When combined with the SNSD pin, the DCR sensing

network can be skewed to increase the AC ripple voltage

by a factor of 5.

TRSET1, TRSET2 (Pin 36, Pin 14): Input of the Tempera-

ture Balancing Circuitries. Connect these pins through

resistors to ground to convert the TCOMP pin voltages

to currents. These currents are then mirrored to pin TAVG

and are added together for all channels. Float this pin if

thermal balancing is not used.

SGND/PGND(ExposedPadPin41):Signal/PowerGround

Pin. Connect this pin closely to the sources of the bot-

tom N-channel MOSFETs, the (–) terminal of C

and

VCC

the (–) terminal of C . All small-signal components and

IN

compensationcomponentsshouldconnecttothisground.

3875fb

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For more information www.linear.com/LTC3875

LTC3875

BLOCK DIAGRAM ^{(Functional diagram shows one channel only)}

EXTV

CC

TCOMP/ITEMP

MODE/PLLIN PHASMD

4.7V

FREQ

+

–

TEMPSNS

F

V

IN

0.6V

MODE/SYNC

DETECT

V

IN

+

5.5V

REG

C

+

IN

–

INTV

CC

F

PLL-SYNC

BOOST

TG

BURST EN

C

B

CLKOUT

FCNT

ON

OSC

M1

SW

S

R

IFAST

(CHANNEL 2

ONLY)

Q

V

OUT

+

SNSA

D

B

SWITCH

LOGIC

AND

ANTISHOOT-

THROUGH

5k

–

+

–

SNS

I

REV

CMP

+

–

R2

+

BG

RUN

OV

C

OUT

M2

R1

SGND

C

PGND

PGOOD

VCC

ILIM

SLOPE

COMPENSATION

+

–

0.555V

INTV

UVLO

CC

UV

OV

1

+

SNSD

50k

ACTIVE CLAMP

I

+

–

THB

AMP

–

SNS

+

–

SLEEP

+

–

20k

+

0.66V

V

OSNS

+

–

V

IN

– ^SS

– ^RUN

+

20k

DIFFAMP

1.25µA

EA

0.6V

REF

–

+ +

+

0.5V

1.22V

–

V

OSNS

20k

V

FB

0.55V

1µA/5.5µA

C

C1

C

TK/SS

ITH

RUN

SS

R

C

30µA

MIRROR

TCOMP/ITEMP

ENTMPB

+

AMP

*n EQUALS THE NUMBER

OF CHANNELS IN PARALLEL

–

TAVG

TRSET

+

R

g

m

TCOMP

n*

R

TCOMP

–

3875 BD

REPEAT FOR

MULTICHIP OPERATIONS

3875fb

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For more information www.linear.com/LTC3875

LTC3875

OPERATION

Main Control Loop

every third cycle to allow C to recharge. However, it is

B

recommended that a load be present or the IC operates

The LTC3875 is a constant frequency, current mode step-

downcontroller with two channels operating 180°or240°

out of phase. During normal operation, each top MOSFET

is turned on when the clock for that channel sets the R

latch, and turned off when the main current comparator,

at low frequency during the drop-out transition to ensure

that C is recharged.

B

S

Shutdown and Start-Up

(RUN1, RUN2 and TK/SS1, TK/SS2 Pins)

I

, resets the R latch. The peak inductor current at

CMP

which I

S

The two channels of the LTC3875 can be independently

shut down using the RUN1 and RUN2 pins. Pulling either

of these pins below 1.14V shuts down the main control

loop for that channel. Pulling both pins low disables both

resets the R latch is controlled by the voltage

CMP

TH

S

on the I pin, which is the output of each error amplifier

EA. The remote sense amplifier (DIFFAMP) converts the

sensed differential voltage across the output feedback

channels and most internal circuits, including the INTV

resistor divider to an internal voltage (V ) referred to

CC

FB

regulator. Releasing either RUN pin allows an internal

1µA current to pull up the pin and enable the controller.

Alternatively, the RUN pins may be externally pulled up

or driven directly by logic. Be careful not to exceed the

absolute maximum rating of 6V on these pins.

SGND. The V signal is then compared to the internal

FB

0.6V reference voltage by the EA. When the load current

increases, it causes a slight decrease in V relative to

FB

the 0.6V reference, which in turn causes the I voltage

TH

to increase until the average inductor current matches the

new load current. After the top MOSFET has turned off,

the bottom MOSFET is turned on until either the inductor

current starts to reverse, as indicated by the reverse cur-

The start-up of each channel’s output voltage, V , is

OUT

controlled by the voltage on its TK/SS pin. When the

voltage on the TK/SS pin is less than the 0.6V internal

rent comparator, I , or the beginning of the next cycle.

REV

reference, the LTC3875 regulates the V voltage to the

FB

TK/SS pin voltage instead of the 0.6V reference. This al-

lows the TK/SS pin to be used to program the soft-start

periodbyconnectinganexternalcapacitorfromtheTK/SS

pin to SGND. An internal 1.25µA pull-up current charges

this capacitor, creating a voltage ramp on the TK/SS pin.

As the TK/SS voltage rises linearly from 0V to 0.6V (and

INTV /EXTV Power

CC

Power for the top and bottom MOSFET drivers and most

other internal circuitry is derived from the INTV pin.

CC

When the EXTV pin is left open or tied to a voltage less

CC

than4.5V,aninternal5.5VlinearregulatorsuppliesINTV

CC

power from V . If EXTV is taken above 4.7V, the 5.5V

beyond),theoutputvoltageV

risessmoothlyfromzero

IN

CC

OUT

regulator is turned off and an internal switch is turned on

connectingEXTV toINTV .WhenusingEXTV ,theV

to its final value. Alternatively the TK/SS pin can be used

to cause the start-up of V to “track” that of another

CC

IN

OUT

voltagehastobehigherthanEXTV voltageatalltimeand

supply. Typically, this requires connecting to the TK/SS

pin an external resistor divider from the other supply to

ground (see the Applications Information section). When

the corresponding RUN pin is pulled low to disable a

CC

has to come before EXTV is applied. Otherwise, EXTV

CC

current will flow back to V through the internal switch’s

IN

body diode and potentially damage the device. Using the

EXTV pin allows the INTV power to be derived from

controller, or when INTV drops below its undervoltage

CC

a high efficiency external source.

lockout threshold of 3.7V, the TK/SS pin is pulled low

by an internal MOSFET. When in undervoltage lockout,

both controllers are disabled and the external MOSFETs

are held off.

Each top MOSFET driver is biased from the floating

bootstrap capacitor, C , which normally recharges dur-

B

ing each off cycle through an external diode when the top

MOSFET turns off. If the input voltage, V , decreases to

IN

Internal Soft-Start

a voltage close to V , the loop may enter dropout and

OUT

By default, the start-up of the output voltage is normally

controlled by an internal soft-start ramp. The internal

attempt to turn on the top MOSFET continuously. The

dropout detector detects this and forces the top MOSFET

off for about one-twelfth of the clock period plus 100ns

soft-start ramp represents one of the noninverting inputs

3875fb

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For more information www.linear.com/LTC3875

LTC3875

OPERATION

to the error amplifier. The V signal is regulated to the

In forced continuous operation, the inductor current is

allowed to reverse at light loads or under large transient

conditions. The peak inductor current is determined by

FB

lower of the error amplifier’s three noninverting inputs

(the internal soft-start ramp, the TK/SS pin or the internal

600mV reference). As the ramp voltage rises from 0V to

0.6V, over approximately 600µs, the output voltage rises

smoothly from its pre-biased value to its final set value.

Certain applications can require the start-up of the con-

verter into a non-zero load voltage, where residual charge

is stored on the output capacitor at the onset of converter

switching. Inordertopreventtheoutputfromdischarging

under these conditions, the top and bottom MOSFETs are

the voltage on the I pin. In this mode, the efficiency at

TH

lightloadsislowerthaninBurstModeoperation.However,

continuousmodehastheadvantagesofloweroutputripple

and less interference with audio circuitry.

When the MODE/PLLIN pin is connected to INTV , the

CC

LTC3875 operates in PWM pulse-skipping mode at light

loads. At very light loads, the current comparator, I

,

CMP

mayremaintrippedforseveralcyclesandforcetheexternal

topMOSFETtostayoffforthesamenumberofcycles(i.e.,

skipping pulses). The inductor current is not allowed to

reverse (discontinuous operation). This mode, like forced

continuousoperation, exhibitslowoutputrippleaswellas

low audio noise and reduced RF interference as compared

to Burst Mode operation. It provides higher low current

efficiency than forced continuous mode, but not nearly as

high as Burst Mode operation.

disabled until soft-start is greater than V .

FB

Light Load Current Operation (Burst Mode Operation,

Pulse-Skipping, or Continuous Conduction)

The LTC3875 can be enabled to enter high efficiency Burst

Modeoperation,constantfrequencypulse-skippingmode,

or forced continuous conduction mode. To select forced

continuous operation, tie the MODE/PLLIN pin to a DC

voltage below 0.6V (e.g., SGND). To select pulse-skipping

mode of operation, tie the MODE/PLLIN pin to INTV . To

Multichip Operations (PHASMD and CLKOUT Pins)

CC

select Burst Mode operation, float the MODE/PLLIN pin.

When a controller is enabled for Burst Mode operation,

the peak current in the inductor is set to approximately

one-third of the maximum sense voltage even though the

The PHASMD pin determines the relative phases between

theinternalchannelsaswellastheCLKOUTsignalasshown

in Table 1. The phases tabulated are relative to zero phase

being defined as the rising edge of the clock of phase 1.

voltage on the I pin indicates a lower value. If the aver-

TH

Table 1

age inductor current is higher than the load current, the

error amplifier, EA, will decrease the voltage on the I

PHASMD

Phase 1

Phase 2

CLKOUT

GND

0°

FLOAT

0°

INTV

CC

TH

pin. When the I voltage drops below 0.5V, the internal

0°

TH

sleep signal goes high (enabling sleep mode) and both

external MOSFETs are turned off.

180°

60°

180°

90°

240°

120°

In sleep mode, the load current is supplied by the output

capacitor.Astheoutputvoltagedecreases,theEA’soutput

begins to rise. When the output voltage drops enough, the

sleep signal goes low, and the controller resumes normal

operation by turning on the top external MOSFET on the

next cycle of the internal oscillator. When a controller is

enabled for Burst Mode operation, the inductor current is

not allowed to reverse. The reverse current comparator

The CLKOUT signal can be used to synchronize additional

powerstagesinamultiphasepowersupplysolutionfeeding

a single, high current output or separate outputs. Input

capacitance ESR requirements and efficiency losses are

substantiallyreducedbecausethepeakcurrentdrawnfrom

the input capacitor is effectively divided by the number of

phases used and power loss is proportional to the RMS

current squared. A 2-stage, single output voltage imple-

mentation can reduce input path power loss by 75ꢀ and

radically reduce the required RMS current rating of the

input capacitor(s).

(I ) turns off the bottom external MOSFET just before

REV

the inductor current reaches zero, preventing it from re-

versing and going negative. Thus, the controller operates

in discontinuous operation.

3875fb

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For more information www.linear.com/LTC3875

LTC3875

OPERATION

Single Output Multiphase Operation

translated to its output, relative to SGND. Care should be

+

–

taken to route the V

and V

PCB traces parallel

OSNS

The LTC3875 can be used for single output multiphase

converters by making these connections

to each other all the way to the remote sensing points on

the board. In addition, avoid routing these sensitive traces

near any high speed switching nodes in the circuit. Ideally,

• Tie all of the I pins together;

TH

+

–

+

the V

and V

traces should be shielded by a

OSNS

• Tie all of the V

pins together;

OSNS

low impedance ground plane to maintain signal integrity.

• Tie all of the TK/SS pins together;

• Tie all of the RUN pins together.

Current Sensing with Very Low Inductor DCR

For low output voltage, high current applications, it’s

common to use low winding resistance (DCR) inductors

tominimizethewindingconductionlossandmaximizethe

supplyefficiency.InductorDCRcurrentsensingisalsoused

toeliminatethecurrentsensingresistoranditsconduction

loss. Unfortunately, with a very low inductor DCR value,

1mΩ or less, the AC current sensing signal ripple can be

Examplesofsingleoutputmultiphaseconvertersareshown

in the Typical Applications section.

Sensing the Output Voltage

The LTC3875 includes two low offset, high input imped-

ance, unity gain, high bandwidth differential amplifier for

applicationsthatrequiretrueremotesensing.Differentially

sensing the load greatly improves regulation in high cur-

rent, low voltage applications, where board interconnec-

tion losses can be a significant portion of the total error

less than 10mV . This makes the current loop sensitive

P-P

to PCB switching noise and causes switching jitter.

The LTC3875 employs a unique and proprietary current

sensing architecture to enhance its signal-to-noise ratio

in these situations. This enables it to operate with a small

sense signal of a very low value inductor DCR, 1mΩ or

less. The result is improved power efficiency, and reduced

jitterduetoswitchingnoisewhichcouldcorruptthesignal.

TheLTC3875cansenseaDCRvalueaslowas0.2mΩwith

careful PCB layout. The LTC3875 uses two positive sense

budget. The LTC3875 differential amplifier’s positive

+

terminal V

senses the divided output through a re-

OSNS

–

sistor divider and its negative terminal V

senses the

OSNS

remotegroundoftheload.Thedifferentialamplifieroutput

is connected to the negative terminal of the internal error

amplifier inside the controller. Therefore, its differential

outputsignal(V )isnotaccessiblefromoutsidetheIC.In

FB

+

pins, SNSD and SNSA to acquire signals. It processes

theminternallytoprovidetheresponseaswithaDCRsense

signal that has a 14dB (5×) signal-to-noise ratio improve-

ment without affecting output voltage feedback loop. In

the meantime, the current limit threshold is still a function

of the inductor peak current times its DCR value and its

accuracyisalsoimprovedfivetimesandcanbeaccurately

set from 10mV to 30mV in a 5mV steps with the ILIM pin

a typical application where differential sensing is desired,

+

connect the V

pin to the center tap of the feedback

OSNS

–

divider across the output load, and the V

pin to the

OSNS

load ground. When differential sensing is not used, the

–

V

OSNS

pincanbeconnectedtolocalground.SeeFigure1.

TheLTC3875differentialamplifierhasatypicaloutputslew

rate of 2V/µs. The amplifier is configured for unity gain,

+

–

meaningthatthedifferencebetweenV

andV

is

OSNS

V

OUT

10Ω

C

LTC3875

R

C

FF

D1

D2

+

–

V

OSNS

C

OUT2

OUT1

+

–

+

DIFFAMP

10Ω

I

0.6V

INTSS

TH

OSNS

+

–

EA

TK/SS

3875 F01

Figure 1. Differential Amplifier Connection

3875fb

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For more information www.linear.com/LTC3875

LTC3875

OPERATION

The thermal balancing can be enabled by setting the

ENTMPBpintoground.EachchannelhasaTCOMP/ITEMP

pinwhichsourcesa30µAprecisioncurrent.Byconnecting

a linearized NTC network or a temperature sensing IC

placed near the hot spot of the converter from this pin to

SGND, the temperature of each channel can be sensed.

The sensed voltage from each channel is converted to a

(seeFigure4bforinductorDCRsensingconnections).The

+

filtertimeconstant,R1•C1,oftheSNSD shouldmatchthe

+

L/DCRoftheoutputinductor,whilethefilteratSNSA should

+

have a bandwidth of five times larger than that of SNSD ,

i.e, R2 • C2 equals one-fifth of R1 • C1.

Thermal Balancing For Multiphase Operation

current, which is programmable with resistor, R

,

TCOMP

When LTC3875 is used as a single output multiphase

converter, the temperature of the whole system can be

balanced by enabling the thermal balancing function. This

prevents hot spots due to imperfection of current match-

ing and component mismatch. Therefore, it improves the

overall reliability of the power supply system.

at the TRSET pin. The current from each channel is then

summed together at the TAVG pin. The resistor value at

the TAVG is R

/n, where n is the number of phases.

TCOMP

ThevoltageatTAVG isthenarepresentationoftheaverage

temperature of the whole system. By comparing the

phase temperature and average temperature, an internal

transconductanceamplifierthenadjuststhephasecurrent

accordinglytomatchthephasetemperaturetotheaverage

temperature of the system.

Refer to Figure 2 for the following discussion of thermal

balancing for the LTC3875.

30µA

MIRROR

1:1

TCOMP1

+

THERMAL

SENSOR

OR NTC

–

TRSET1

R

CHANNEL 1

TCOMP

+

–

ADJUST

CHANNEL

CURRENT

g

m

TAVG

AMP

R

AVG

30µA

+

MIRROR

1:1

TCOMP2

THERMAL

SENSOR

OR NTC

–

REPEAT FOR

MULTICHIP

OPERATIONS

TRSET2

CHANNEL 2

R

TCOMP

+

–

ADJUST

CHANNEL

CURRENT

g

m

AMP

3875 F02

Figure 2. Thermal Balancing Technique for Multichip Operations

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For more information www.linear.com/LTC3875

LTC3875

OPERATION

Inductor DCR Sensing Temperature Compensation

resistors. Consult the NTC manufacturer’s data sheets for

detailed information.

Inductor DCR current sensing provides a lossless method

of sensing the instantaneous current. Therefore, it can

provide higher efficiency for applications of high output

currents. However the DCR of a copper inductor typically

has a positive temperature coefficient. As the temperature

of the inductor rises, its DCR value increases. The current

limit of the controller is therefore reduced.

Another use for the TCOMP/ITEMP pins, in addition to

NTC compensated DCR sensing, is adjusting V

SENSE(MAX)

to values between the nominal values of 10mV,15mV,

20mV, 25mV and 30mV for a more precise current limit

setting. This is done by applying a voltage less than 0.7V

to the TCOMP/ITEMP pin. V

will be varied per

SENSE(MAX)

the above equation. The current limit can be adjusted

using this method either with a sense resistor or DCR

sensing. The ENTMPB pin also needs to be floating to

use this function.

LTC3875 offers a method to counter this inaccuracy by

allowing the user to place an NTC temperature sensing

resistor near the inductor. The ENTMPB pin has to be

floating to enable the inductor DCR sensing temperature

compensation function. The TCOMP/ITEMP pin, when left

floating, is at a voltage around 5.5V and DCR temperature

compensation is also disabled. A constant 30µA precision

current flows out the TCOMP/ITEMP pin. By connecting a

linearized NTC resistor network from the TCOMP/ITEMP

pintoSGND,themaximumcurrentsensethresholdcanbe

variedovertemperatureaccordingthefollowingequation:

For more information see the NTC Compensated DCR

SensingparagraphintheApplicationsInformationsection.

Frequency Selection and Phase-Locked Loop

(FREQ and MODE/PLLIN Pins)

Theselectionofswitchingfrequencyisatrade-offbetween

efficiency and component size. Low frequency opera-

tion increases efficiency by reducing MOSFET switching

losses, but requires larger inductance and/or capacitance

to maintain low output ripple voltage. The switching

frequency of the LTC3875’s controllers can be selected

using the FREQ pin. If the MODE/PLLIN pin is not being

driven by an external clock source, the FREQ pin can be

used to program the controller’s operating frequency

from 250kHz to 720kHz. There is a precision 10µA current

flowing out of the FREQ pin, so the user can program the

controller’s switching frequency with a single resistor to

SGND. A curve is provided later in the application section

showing the relationship between the voltage on the FREQ

pin and switching frequency. A phase-locked loop (PLL)

is integrated on the LTC3875 to synchronize the internal

oscillator to an external clock source that is connected to

the MODE/PLLIN pin. The controller is operating in forced

continuous mode when it is synchronized. The PLL loop

filter network is also integrated inside the LTC3875. The

phase-locked loop is capable of locking any frequency

withintherangeof250kHzto720kHz.Thefrequencysetting

resistor should always be present to set the controller’s

initial switching frequency before locking to the external

clock to minimize the transient.

2.2– V

ITEMP

V_{SENSEMAX(ADJ)}= V_SENSE(MAX)

•

1.5

where:

V

isthemaximumadjustedcurrentsense

SENSEMAX(ADJ)

threshold.

V

is the maximum current sense threshold

SENSE(MAX)

specified in the electrical characteristics table. It is typi-

cally 10mV, 15mV, 20mV, 25mV or 30mV depending on

the setting ILIM pins. V

ITEMP pin.

is the voltage of the TCOMP/

ITEMP

The valid voltage range for DCR temperature compensa-

tion on the TCOMP/ITEMP pin is between 0.7V to SGND

with 0.7V or above being no DCR temperature correction.

An NTC resistor has a negative temperature coefficient,

meaning that its value decreases as temperature rises.

The V

voltage, therefore, decreases as temperature

ITEMP

increases and in turn V

will increase to

SENSEMAX(ADJ)

compensate the DCR temperature coefficient. The NTC

resistor, however, is nonlinear, but the user can linear-

ize its value by building a resistor network with regular

3875fb

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For more information www.linear.com/LTC3875

LTC3875

OPERATION

Power Good (PGOOD Pin)

The plots in Figure 3 show the improvement with and

without the transient improvement circuit for a typical

+

When both V

pins’ voltages are not within 7.5ꢀ of

OSNS

12V (V ) to 1.5V (V

) high current application. The

IN

OUT

the 0.6V reference voltage, the PGOOD pin is pulled low.

The PGOOD pin is also pulled low when the RUN pins are

below 1.14V or when the LTC3875 is in the soft-start,

circuit with fast transient shows a near 30ꢀ improvement

for the worst case transient steps. For this application,

IFAST pin voltage is programmed to be around 0.62V and

the circuit is not very sensitive to this programmed volt-

age. During the double frequency operation, care has to

be taken not to violate the minimum on-time requirement

of the LTC3875. The fast transient mode is only enabled

in forced continuous mode for channel 2 and is disabled

automatically during start-up, or when output is out of

regulation window.

UVLO or tracking phase. The PGOOD pin will flag power

+

good immediately when both the V

pins are within

OSNS

the 7.5ꢀ of the reference window. However, there is an

+

internal 20µs power bad mask when V

voltages go

OSNS

out of the 7.5ꢀ window. The PGOOD pin is allowed to be

pulled up by an external resistor to sources of up to 6V.

Output Overvoltage Protection

In order to properly take advantage of the fast transient

circuit, the following equation needs to be satisfied:

An overvoltage comparator, OV, guards against transient

overshoots (>7.5ꢀ) as well as other more serious condi-

tions that may overvoltage the output. In such cases, the

topMOSFETisturnedoffandthebottomMOSFETisturned

on until the overvoltage condition is cleared.

V_SENSE(MAX)

30mV

















0.7– V

0.9375

f_OSC

V_OUT

IFAST

•

+

1–





25k

V





IN

• 5k ≥5•∆I_L•DCR

where,

Fast Transient Operation

The LTC3875 also has a transient improvement function

implemented on channel 2. In normal operation, IFAST

pin is floated. This will disable the transient improvement

circuit. To enable the transient improvement function,

connect a resistor from IFAST pin to ground. The voltage

difference between 0.7V and IFAST pin voltage programs

the window of sensitivity of when a transient condition is

detected.Duringtheloadstep-up,acomparatormonitoring

the ripple voltage will compare with the scaled version of

the programmed window voltage and trip. This indicates

that a load step is detected. The LTC3875 will immedi-

ately turn on the top gate and also double the switching

frequency for about 20 cycles.

V

is the maximum sense threshold voltage

SENSE(MAX)

is the programmed voltage on the IFAST pin

IFAST

f

is the programmed switching frequency

is the converter’s output voltage

OSC

V

OUT

V is the converter’s input voltage

IN

ΔI is the inductor ripple current

L

DCR is the winding resistance of the inductor

As a rule of thumb, the value of the left side of the equa-

tion should be 20ꢀ larger than the value of the right side

of the equation.

3875fb

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For more information www.linear.com/LTC3875

LTC3875

OPERATION

Fast Transient Disabled

Fast Transient Enabled

V

O

50mV/DIV

67.5mV

95mV

SW NODE

10V/DIV

I

O

0A TO 15A

10A/DIV

3875 F03

Figure 3. Worst-Case Transient Comparison Between Normal Mode Operation and

Fast Transient Mode of Operation for 12V/1.ꢀV Application with 1ꢀA Load Step

APPLICATIONS INFORMATION

The Typical Application on the first page of this data sheet

is a basic LTC3875 application circuit configured as a

dual phase single output power supply. The LTC3875

has an optional thermal balancing function that balances

the thermal stress between phases, thus increasing the

reliability of the whole system. In addition, the LTC3875 is

designed and optimized for use with a very low value DCR

inductor by utilizing a novel approach to reduce the noise

sensitivity of the sensing signal by a factor of 14dB. DCR

sensing is becoming popular because it saves expensive

current sensing resistors and is more power efficient,

especially in high current applications. However, as the

DCR value drops below 1mΩ, the signal-to-noise ratio is

low and current sensing is difficult. The LTC3875 uses an

LTC proprietary technique to solve this issue with mini-

mum additional external components. In general, external

component selection is driven by the load requirement,

and begins with the DCR and inductor value. Next, power

MOSFETsareselected.Finally,inputandoutputcapacitors

are selected.

provides maximum current sense thresholds of 15mV or

25mV. The user should select the proper ILIM level based

on the inductor DCR value and targeted current limit level.

+

–

SNSD , SNSA and SNS Pins

+

–

The SNSA and SNS pins are the direct inputs to the cur-

+

rent comparators, while the SNSD pin is the input of an

internal DC amplifier. The operating input voltage range

+

–

of 0V to 3.5V is for SNSA , SNSD and SNS in a typical

application. All the positive sense pins that are connected

to the current comparator or the DC amplifier are high

impedance with input bias currents of less than 1µA, but

–

there is a resistance of about 300k from the SNS pin

–

to ground. The SNS pin should be connected directly

+

to V . The SNSD pin connects to the filter that has a

OUT

R1 • C1 time constant equals L/DCR of the inductor. The

+

SNSA pin is connected to the second filter, R2 • C2,

with the time constant equals (R1 • C1)/5. Care must be

taken not to float these pins. Filter components, especially

capacitors, must be placed close to the LTC3875, and the

sense lines should run close together to a Kelvin connec-

tion underneath the current sense element (Figure 4a).

Because the LTC3875 is designed to be used with a very

low DCR value to sense inductor current, without proper

care, the parasitic resistance, capacitance and inductance

will degrade the current sense signal integrity, making

the programmed current limit unpredictable. As shown

in Figure 4b, resistors R1 and R2 are placed close to the

3875fb

Current Limit Programming

TheILIMpinisa5-levellogicinputwhichsetsthemaximum

current limit of the controller. The input impedance of the

ILIMpinis250kΩ. WhenILIMisgrounded, floated, ortied

toINTV ,thetypicalvalueforthemaximumcurrentsense

CC

thresholdwillbe10mV,20mV,or30mV,respectively.Set-

ting ILIM to one-fourth INTV and three-fourths INTV

CC

18

For more information www.linear.com/LTC3875

LTC3875

APPLICATIONS INFORMATION

TO SENSE FILTER,

NEXT TO THE CONTROLLER

C

OUT

3875 F04a

INDUCTOR

Figure 4a. Sense Lines Placement with Inductor DCR

V

IN

INTV

CC

INDUCTOR

BOOST

TG

LTC3875

L

DCR

V

OUT

SW

R

ITEMP

R

TCOMP/ITEMP

BG

PGND

R1 R2

S

22.6k

+

SNSD

C1

C2

–

SNS

R

+

NTC

P

SNSA

100k

90.9k

SGND

PLACE C1, C2 NEXT TO IC

3875 F04b

PLACE R1, R2 NEXT TO INDUCTOR

R1C1 = 5 • R2C2

Figure 4b. Inductor DCR Current Sensing

output inductor and capacitors C1 and C2 are close to

the IC pins to prevent noise coupling to the sense signal.

winding resistance, which is often less than 1mΩ for high

current inductors. In high current and low output voltage

applications, conduction loss of a high DCR inductor or a

sense resistor will cause a significant reduction in power

efficiency. For a specific output requirement and induc-

tor, choose the current limit sensing level that provides

proper margin for maximum load current, and uses the

relationship of the sense pin filters to output inductor

characteristics as depicted below.

For applications where the inductor DCR is large, the

LTC3875 could also be used like any typical current

mode controller with conventional DCR sensing by

+

disabling the SNSD pin, shorting it to ground. An

R

resistor or a DCR sensing RC filter can be used

SENSE

to sense the output inductor signal and connects to the

+

SNSA pin. If the RC filter is used, its time constant,

R • C, equals L/DCR of the output inductor. In these ap-

plications, thecurrentlimit, V

the value of V

operating voltage range of SNSA and SNS is from 0V to

5V. An output voltage of 5V can be generated.

V_SENSE(MAX)

DCR=

, willbefivetimes

SENSE(MAX)

∆I_L

I_MAX

+

with DC loop enabled, and the

SENSE(MAX)

2

+

–

L/DCR=R1•C1= 5•R2•C2

where:

Low Inductor DCR Sensing and Current Limit

Estimation

V

is the maximum sense voltage for a given

SENSE(MAX)

ILIM threshold.

The LTC3875 is specifically designed for high load current

applications requiring the highest possible efficiency; it is

capableofsensingthesignalofaninductorDCRinthesub

milliohm range (Figure 4b). The DCR is the inductor DC

I

is the maximum load current.

MAX

ΔI is the inductor ripple current.

L

L/DCR is the output inductor characteristics.

3875fb

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For more information www.linear.com/LTC3875

LTC3875

APPLICATIONS INFORMATION

+

There will be some power loss in R1 and R2 that relates to

the duty cycle, and will be the most in continuous mode

at the maximum input voltage:

R1 • C1 is the filter time constant of the SNSD pin.

+

R2 • C2 is the filter time constant of the SNSA pin.

For example, for a 12V , 1.2V/30A step-down buck con-

IN

verter running at 400kHz frequency, a 0.15µH, 0.4mΩ

inductor is chosen. This inductor provides 15A peak-to-

peak ripple current, which is 50ꢀ of the 30A full load

current. At full load, the inductor peak current is 30A +

15A/2 = 37.5A.

V

_IN(MAX)– V_OUT•V

(

)

OUT

P

R =

_LOSS( )

R

EnsurethatR1andR2haveapowerratinghigherthanthis

value. However, DCR sensing eliminates the conduction

loss of a sense resistor; it will provide a better efficiency

at heavy loads. To maintain a good signal-to-noise ratio

for the current sense signal, using ∆V

tween SNSA and SNS pins or an equivalent 3mV ripple

on the current sense signal. The actual ripple voltage

IL(PK) • DCR = 37.5A • 0.4mΩ = 15mV.

of 15mV be-

In this case, choose the 20mV ILIM setting which is the

closest but higher than 15mV to provide margin for cur-

rent limit.

SENSE

+

–

+

–

across SNSA and SNS pins will be determined by the

following equation:

Select the two R/C sensing network:

+

Filter on SNSD pin: R1 • C1 = L/DCR,

V_OUTV – V

IN

OUT

∆V_SENSE

=

•

+

Filter on SNSA pin: R2 • C2 = (L/DCR)/5.

V

R2•C2•f_OSC

IN

+

In this case, the ripple sense signal across SNSA and

Inductor DCR Sensing Temperature Compensation

with NTC Thermistor

–

SNS pins is ΔIL • DCR • 5 = 15A • 0.4mΩ • 5 = 30mV.

P-P

This signal should be more than 15mV for good signal-to-

noise ratio. In this case, it is certainly sufficient.

For DCR sensing applications, the temperature coefficient

of the inductor winding resistance should be taken into

account when the accuracy of the current limit is criti-

cal over a wide range of temperature. The main element

used in inductors is copper; that has a positive tempco

of approximately 4000ppm/°C. The LTC3875 provides

a feature to correct for this variation through the use of

the TCOMP/ITEMP pin. There is a 30µA precision current

source flowing out of the TCOMP/ITEMP pin. A thermistor

with a NTC (negative temperature coefficient) resistance

The peak inductor current at current limit is:

ILIM(PK) = 20mV/DCR = 20mV/0.4mΩ = 50A.

The average inductor current, which is also the output

current, at current limit is :

ILIM(AVG) = ILIM(PK) – ΔIL /2 = 50A – 15A/2 = 42.5A.

P-P

To ensurethattheloadcurrentwillbedeliveredoverthefull

operatingtemperaturerange,thetemperaturecoefficientof

DCR resistance, approximately 0.4ꢀ/°C, should be taken

into account. The LTC3875 features a DCR temperature

compensationcircuitthatusesanNTCtemperaturesensing

resistor for this purpose. See the Inductor DCR Sensing

Temperature Compensation section for details.

can be used in a network, R

(Figure 4b) connected to

ITEMP

maintain the current limit threshold constant over a wide

operating temperature. The TCOMP/ITEMP voltage range

that activates the correction is from 0.7V or less. If this

pin is floating, its voltage will be at INTV potential, about

CC

5.5V.WhentheTCOMP/ITEMPvoltageishigherthan0.7V,

the temperature compensation is inactive. Floating the

ENTMPB pin enables the temperature compensation

function.

Typically, C1 and C2 are selected in the range of 0.047µF

to 0.47µF. If C1 and C2 are chosen to be 100nF, and an

inductorof150nHwith0.4mΩDCRisselected, R1andR2

will be 4.64k and 931Ω respectively. The bias current at

SNSD and SNSA is about 30nA and 500nA respectively,

and it causes some small error to the sense signal.

+

The following guidelines will help to choose components

for temperature correction. The initial compensation is for

25°C ambient temperature:

3875fb

20

For more information www.linear.com/LTC3875

LTC3875

APPLICATIONS INFORMATION

1. SettheTCOMP/ITEMPpinresistanceto23.33kat25°C.

With 30µA flowing out of the TCOMP/ITEMP pin, the

voltage on the TCOMP/ITEMP pin will be 0.7V at room

temperature. Current limit correction will occur for

inductor temperatures greater than 25°C.

from the following equation:









1

R=R_O•exp B•

–









T+273 T +273









O

where:

R = Resistance at temperature T, which is in degrees C.

2. Calculate the TCOMP/ITEMP pin resistance and the

maximuminductortemperaturewhichistypically100°C.

Use the following equations:

R = Resistance at temperature T , typically 25°C.

O

V

=

B = B-constant of the thermistor.

ITEMP100C





Figure5showsatypicalresistancecurvefora100kthermis-

tor and the TCOMP/ITEMP pin network over temperature.

100°C–25°C •0.4

(

)

I_MAX•DCR (Max)•





100

0.7–1.5





V_SENSE(MAX)

Starting values for the NTC compensation network are:









• NTC R = 100k

O

= 0.25V

= I

• R = 3.92k

S

Since V

• DCR (Max):

SENSE(MAX)

MAX

• R = 24.3k

P

V

R_ITEMP100C

=

^ITEMP100C= 8.33k

But, the final values should be calculated using the above

equationsandcheckedat25°Cand100°C.Afterdetermin-

ing the components for the temperature compensation

30µA

where:

network,checktheresultsbyplottingI

versusinductor

MAX

R

= TCOMP/ITEMP pin resistance at 100°C.

= TCOMP/ITEMP pin voltage at 100°C.

ITEMP100C

SENSE(MAX)

temperature using the following equations:

V

I_DC(MAX)

=

V

= Maximum current sense threshold at

∆V_SENSE

room temperature.

V_{SENSEMAX(ADJ)}

–

2

I

= Maximum inductor peak current.

MAX

0.4

100





DCR(MAX) at 25°C• 1+ T

–25°C •

(

)







L(MAX)

DCR (Max) = Maximum DCR value.



Calculate the values for the NTC network’s parallel and

where:

10000

1000

100

10

series resistors, R and R . A simple method is to graph

P

S

thefollowingR versusR equationswithR onthey-axis

S

P

S

THERMISTOR RESISTANCE

R

= 100k, T = 25°C

O

and R on the x-axis.

P

B = 4334 for 25°C/100°C

R = R

S

– R

||R

ITEMP25C

NTC25C P

R = R

S

– R

||R

ITEMP100C

NTC100C P

RITMP

R

= 20kΩ

Next, find the value of R that satisfies both equations

S

P

= 43.2kΩ

which will be the point where the curves intersect. Once

100k NTC

R is known, solve for R .

P

S

1

The resistance of the NTC thermistor can be obtained

from the vendor’s data sheet either in the form of graphs,

tabulated data, or formulas. The approximate value for the

NTC thermistor for a given temperature can be calculated

–40 –20

0

20 40 60 80 100 120

INDUCTOR TEMPERATURE (°C)

3875 F05

Figure ꢀ. Resistance Versus Temperature for

I_TEMPPin Network and the 100k NTC

3875fb

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For more information www.linear.com/LTC3875

LTC3875

APPLICATIONS INFORMATION

CONNECT TO

ITEMP1

CONNECT TO

ITEMP2

2.2– V

ITEMP

V_{SENSEMAX(ADJ)}= V_SENSE(MAX)

•

NETWORK

V

OUT1

L1

OUT2

L2

1.5

R

NTC1

R

NTC2

V

= 30µA • (R + R ||R

S P NTC

)

ITEMP

GND

I

= Maximum average inductor current.

DC(MAX)

SW1

SW2

TC is the inductor temperature.

3875 F07a

(7a) Dual Output Dual Phase DCR Sensing Application

The resulting current limit should be greater than or equal

toI

forinductortemperaturesbetween25°Cand100°C.

MAX

V

OUT

Typical values for the NTC compensation network are:

• NTC R = 100k, B-constant = 3000 to 4000

R

NTC

L1

L2

O

• R ≈ 3.92k

S

SW1

SW2

3875 F07b

• R ≈ 24.3k

P

(7b) Single Output Dual Phase DCR Sensing Application

GeneratingtheI

versusinductortemperaturecurveplot

MAX

Figure 7. Thermistor Locations. Place Thermistor Next to

Inductor(s) for Accurate Sensing of the Inductor Temperature,

but Keep the ITEMP Pins away from the Switch Nodes and

Gate Traces

first using the above values as a starting point, and then

adjusting the R and R values as necessary, is another

S

P

approach. Figure 6 shows a curve of I

versus inductor

MAX

temperature. ForPolyPhase^®applications, tietheTCOMP/

ITEMP pins together and calculate for an TCOMP/ITEMP

pin current of 30µA • #phases.

Slope compensation provides stability in constant fre-

quency architectures by preventing sub-harmonic oscil-

lations at high duty cycles. It is accomplished internally

by adding a compensating ramp to the inductor current

signal at duty cycles in excess of 40ꢀ. Normally, this re-

sults in a reduction of maximum inductor peak current for

duty cycles > 40ꢀ. However, the LTC3875 uses a scheme

that counteracts this compensating ramp, which allows

the maximum inductor peak current to remain unaffected

throughout all duty cycles.

For the most accurate temperature detection, place the

thermistors next to the inductors as shown in Figure 7.

Take care to keep the TCOMP/ITEMP pins away from the

switch nodes.

Slope Compensation and Inductor Peak Current

70

Inductor Value Calculation

60

Given the desired input and output voltages, the inductor

value and operating frequency, f , directly determine

OSC

NOMINAL

50

the inductor’s peak-to-peak ripple current:

CORRECTED I

MAX

I

MAX

R

= 3.92k

= 24.3k



_OUT



S

P

V_OUTV – V

IN

I_RIPPLE

=

40



NTC THERMISTOR:

V

f_OSC•L





IN

R

T

= 100k

= 25°C

UNCORRECTED

O

I

MAX

B = 4334

30

Lower ripple current reduces core losses in the inductor,

ESR losses in the output capacitors, and output voltage

ripple. Thus, highest efficiency operation is obtained at

low frequency with a small ripple current. Achieving this,

however, requires a large inductor.

–40 –20

0

20 40 60 80 100 120

INDUCTOR TEMPERATURE (°C)

3875 F06

Figure 6. Worst-Case I_MAXvs Inductor Temperature Curve with

and without NTC Temperature Compensation

3875fb

22

For more information www.linear.com/LTC3875

LTC3875

APPLICATIONS INFORMATION

A reasonable starting point is to choose a ripple current

The peak-to-peak MOSFET gate drive levels are set by the

that is about 40ꢀ of I

. Note that the largest ripple

OUT(MAX)

internal regulator voltage, V

, requiring the use of

INTVCC

current occurs at the highest input voltage. To guarantee

that ripple current does not exceed a specified maximum,

the inductor should be chosen according to:

logic-level threshold MOSFETs in most applications. Pay

closeattentiontotheBVDSSspecificationfortheMOSFETs

as well; many of the logic-level MOSFETs are limited to

30V or less. Selection criteria for the power MOSFETs

V – V

V_OUT

IN

OUT

L ≥

•

include the on-resistance, R

, input capacitance,

DS(ON)

f_OSC•I_RIPPLE

V

IN

inputvoltageandmaximumoutputcurrent.MOSFETinput

capacitance is a combination of several components but

can be taken from the typical gate charge curve included

on most data sheets (Figure 8). The curve is generated by

forcing a constant input current into the gate of a common

source, current source loaded stage and then plotting the

gatevoltageversustime.Theinitialslopeistheeffectofthe

gate-to-source and the gate-to-drain capacitance. The flat

portionofthecurveistheresultoftheMillermultiplication

effectofthedrain-to-gatecapacitanceasthedraindropsthe

voltage across the current source load. The upper sloping

line is due to the drain-to-gate accumulation capacitance

andthegate-to-sourcecapacitance.TheMillercharge(the

increase in coulombs on the horizontal axis from a to b

Inductor Core Selection

Once the inductance value is determined, the type of in-

ductor must be selected. Core loss is independent of core

size for a fixed inductor value, but it is very dependent on

inductanceselected. Asinductanceincreases, corelosses

go down. Unfortunately, increased inductance requires

more turns of wire and therefore copper losses will in-

crease. Ferrite designs have very low core loss and are

preferred at high switching frequencies, so design goals

can concentrate on copper loss and preventing satura-

tion. Ferrite core material saturates “hard,” which means

that inductance collapses abruptly when the peak design

current is exceeded. This results in an abrupt increase in

inductor ripple current and consequent output voltage

ripple. Do not allow the core to saturate!

while the curve is flat) is specified for a given V drain

DS

voltage, but can be adjusted for different V voltages by

DS

multiplying the ratio of the application V to the curve

DS

specified V values. A way to estimate the C

term

DS

MILLER

Power MOSFET and Schottky Diode

(Optional) Selection

is to take the change in gate charge from points a and b

on a manufacturer’s data sheet and divide by the stated

V

DS

voltage specified. C

is the most important

MILLER

At least two external power MOSFETs need to be selected:

One N-channel MOSFET for the top (main) switch and one

or more N-channel MOSFET(s) for the bottom (synchro-

nous) switch. The number, type and on-resistance of all

MOSFETsselectedtakeintoaccountthevoltagestep-down

ratio as well as the actual position (main or synchronous)

in which the MOSFET will be used. A much smaller and

much lower input capacitance MOSFET should be used

for the top MOSFET in applications that have an output

voltage that is less than one-third of the input voltage. In

selection criteria for determining the transition loss term

in the top MOSFET but is not directly specified onMOSFET

data sheets. C

and C are specified sometimes but

RSS

OS

definitionsoftheseparametersarenotincluded.Whenthe

controller is operating in continuous mode the duty cycles

for the top and bottom MOSFETs are given by:

V

IN

MILLER EFFECT

applications where V >> V

, the top MOSFETs’ on-

V

IN

OUT

V

GS

resistance is normally less important for overall efficiency

than its input capacitance at operating frequencies above

300kHz. MOSFET manufacturers have designed special

purposedevicesthatprovidereasonablylowon-resistance

with significantly reduced input capacitance for the main

switch application in switching regulators.

a

b

+

–

V

DS

+

Q

IN

V

GS

–

C

= (Q – Q )/V

B A DS

MILLER

3875 F08

Figure 8. Gate Charge Characteristic

3875fb

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For more information www.linear.com/LTC3875

LTC3875

APPLICATIONS INFORMATION

An optional Schottky diode across the synchronous

MOSFET conducts during the dead time between the

conduction of the two large power MOSFETs. This pre-

vents the body diode of the bottom MOSFET from turning

on, storing charge during the dead time and requiring a

reverse-recoveryperiodwhichcouldcostasmuchassev-

eral percent in efficiency. A 2A to 8A Schottky is generally

a good compromise for both regions of operation due to

the relatively small average current. Larger diodes result

in additional transition loss due to their larger junction

capacitance.

V_OUT

Main Switch Duty Cycle=

V

IN



_OUT

V – V

IN

Synchronous Switch Duty Cycle=





V





IN

The power dissipation for the main and synchronous

MOSFETs at maximum output current are given by:

V_OUT

2

P_MAIN

=

I

(

1+δ R

+

(

)

MAX

DS(ON)

V

IN

I

2



_MAX

V

R

C

•

(

)

(

_DR)(

)

Soft-Start and Tracking







IN

MILLER



2

The LTC3875 has the ability to either soft-start by itself

with a capacitor or track the output of another channel or

externalsupply.Whenoneparticularchannelisconfigured

to soft-start by itself, a capacitor should be connected to

its TK/SS pin. This channel is in the shutdown state if its

RUN pin voltage is below 1.14V. Its TK/SS pin is actively

pulled to ground in this shutdown state.





1

+

•f





V

_INTVCC– V_MILLERV_MILLER





V – V

2

IN

OUT

P_SYNC

=

I

(

1+δ R

DS(ON)

(

)

MAX

V

IN

where δ is the temperature dependency of R

, R

DS(ON) DR

is the effective top driver resistance (approximately 2Ω at

= V ), V is the drain potential and the change

OncetheRUNpinvoltageisabove1.22V,thechannelpow-

ersup. A soft-start current of 1.25µA then starts to charge

its soft-start capacitor. Note that soft-start or tracking is

achieved not by limiting the maximum output current of

the controller but by controlling the output ramp voltage

according to the ramp rate on the TK/SS pin. Current

fold-back is disabled during this phase to ensure smooth

soft-start or tracking. The soft-start or tracking range is

defined to be the voltage range from 0V to 0.6V on the

TK/SS pin. The total soft-start time can be calculated as:

V

GS

MILLER

IN

in drain potential in the particular application. V

MILLER

is the data sheet specified typical gate threshold voltage

specified in the power MOSFET data sheet at the speci-

fied drain current. C

is the calculated capacitance

MILLER

using the gate charge curve from the MOSFET data sheet

and the technique described above. Both MOSFETs have

2

I R losses while the topside N-channel equation includes

an additional term for transition losses, which peak at

the highest input voltage. For V < 20V, the high cur-

IN

C_SS

1.25µA

rent efficiency generally improves with larger MOSFETs,

t

_SOFTSTART= 0.6•

while for V > 20V, the transition losses rapidly increase

IN

to the point that the use of a higher R

device with

DS(ON)

Regardless of the mode selected by the MODE/PLLIN pin,

the regulator will always start in pulse-skipping mode

up to TK/SS = 0.5V. Between TK/SS = 0.5V and 0.56V, it

will operate in forced continuous mode and revert to the

selected mode once TK/SS > 0.56V. The output ripple

is minimized during the 60mV forced continuous mode

window ensuring a clean PGOOD signal.

lower C

actually provides higher efficiency. The

MILLER

synchronous MOSFET losses are greatest at high input

voltage when the top switch duty factor is low or during

a short-circuit when the synchronous switch is on close

to 100ꢀ of the period.

The term (1 + δ ) is generally given for a MOSFET in the

form of a normalized R

vs temperature curve, but

DS(ON)

When the channel is configured to track another supply,

the feedback voltage of the other supply is duplicated by

δ = 0.005/°C can be used as an approximation for low

voltage MOSFETs.

3875fb

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For more information www.linear.com/LTC3875

LTC3875

APPLICATIONS INFORMATION

a resistor divider and applied to the TK/SS pin. Therefore,

the voltage ramp rate on this pin is determined by the

ramprateoftheothersupply’svoltage. Notethatthesmall

soft-start capacitor charging current is always flowing,

producingasmalloffseterror.To minimizethiserror,select

the tracking resistive divider value to be small enough to

make this error negligible. In order to track down another

channel or supply after the soft-start phase expires, the

LTC3875 is forced into continuous mode of operation

the LTC3875’s output 1 as a master channel and V

OUT2

refers to the LTC3875’s output 2 as a slave channel. In

practice, though, either phase can be used as the master.

To implement the coincident tracking in Figure 9a, con-

nect an additional resistive divider to V

and connect

OUT1

its midpoint to the TK/SS pin of the slave channel. The

ratio of this divider should be the same as that of the

slave channel’s feedback divider shown in Figure 10a. In

this tracking mode, V

must be set higher than V

.

OUT1

OUT2

as soon as V is below the undervoltage threshold of

To implement the ratiometric tracking in Figure 10b, the

ratio of the V divider should be exactly the same as

FB

0.55V regardless of the setting on the MODE/PLLIN pin.

However, the LTC3875 should always be set in forced

continuous mode tracking down when there is no load.

After TK/SS drops below 0.1V, its channel will operate in

discontinuous mode.

OUT2

the master channel’s feedback divider shown in Figure 9b.

By selecting different resistors, the LTC3875 can achieve

different modes of tracking including the two in Figure 9.

So which mode should be programmed? While either

mode in Figure 9 satisfies most practical applications,

some trade-offs exist. The ratiometric mode saves a pair

of resistors, but the coincident mode offers better output

regulation.Whenthemasterchannel’soutputexperiences

dynamic excursion (under load transient, for example),

The LTC3875 allows the user to program how its output

ramps up and down by means of the TK/SS pins. Through

thesepins, theoutputcanbesetuptoeithercoincidentally

or ratiometrically track another supply’s output, as shown

in Figure 9. In the following discussions, V

refers to

OUT1

V

OUT1

V

OUT2

3875 F09

TIME

(9a) Coincident Tracking

(9b) Ratiometric Tracking

Figure 9. Two Different Modes of Output Voltage Tracking

V

OUT1

V

OUT2

V

OUT2

OUT1

R3

R4

R1

R2

R3

R4

R1

R2

R3

R4

TO

OSNS2

TO

TK/SS2

TO

TK/SS2

TO

V

+

TO

V

OSNS2

+

OSNS1

3875 F10

(10a) Coincident Tracking Setup

(10b) Ratiometric Tracking Setup

Figure 10. Setup for Coincident and Ratiometric Tracking

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For more information www.linear.com/LTC3875

LTC3875

APPLICATIONS INFORMATION

the slave channel output will be affected as well. For bet-

ter output regulation, use the coincident tracking mode

instead of ratiometric.

mum junction temperature rating for the LTC3875 to be

exceeded. The INTV current, which is dominated by

CC

the gate charge current, may be supplied by either the

5.5V linear regulator or EXTV . When the voltage on

CC

Pre-Biased Output Start-Up

the EXTV pin is less than 4.7V, the linear regulator is

CC

enabled. Power dissipation for the IC in this case is high-

There may be situations that require the power supply to

start up with a pre-bias on the output capacitors. In this

case, it is desirable to start up without discharging that

output pre-bias. The LTC3875 can safely power up into

a pre-biased output without discharging it. The LTC3875

accomplishes this by disabling both TG and BG until the

TK/SS pin voltage and the internal soft-start voltage are

est and is equal to V • I

. The gate charge current

IN INTVCC

is dependent on operating frequency as discussed in the

EfficiencyConsiderationssection.Thejunctiontemperature

can be estimated by using the equations given in Note 3 of

the Electrical Characteristics. For example, the LTC3875

INTV current is limited to less than 44mA from a 38V

CC

+

supplyintheUJpackageandnotusingtheEXTV supply:

CC

above the V

pin voltage. When V

is higher than

OSNS

TK/SSortheinternalsoft-startvoltage,theerrorampoutput

is low. The control loop would like to turn BG on, which

woulddischargetheoutput.DisablingBGandTGprevents

the pre-biased output voltage from being discharged.

T = 70°C + (44mA)(38V)(33°C/W) = 125°C

J

To prevent the maximum junction temperature from being

exceeded, the input supply current must be checked while

operating in continuous conduction mode (MODE/PLLIN

When TK/SS and the internal soft-start both cross 500mV

= SGND) at maximum V . When the voltage applied to

+

IN

or V

, whichever is lower, TG and BG are enabled. If

OSNS

EXTV rises above 4.7V, the INTV linear regulator is

CC

the pre-bias is higher than the OV threshold, the bottom

gate is turned on immediately to pull the output back into

the regulation window.

turned off and the EXTV is connected to the INTV .

CC

The EXTV remains on as long as the voltage applied

CC

to EXTV remains above 4.5V. Using the EXTV allows

CC

the MOSFET driver and control power to be derived from

INTV Regulators and EXTV

CC

one of the LTC3875’s switching regulator outputs during

The LTC3875 features a PMOS LDO that supplies power

to INTV from the V supply. INTV powers the gate

normal operation and from the INTV when the output

CC

IN

CC

is out of regulation (e.g., start-up, short-circuit). If more

drivers and much of the LTC3875’s internal circuitry. The

linear regulator regulates the voltage at the INTV pin to

current is required through the EXTV than is specified,

CC

an external Schottky diode can be added between the

5.5V when V is greater than 6V. EXTV connects to

IN

CC

EXTV and INTV pins. Do not apply more than 6V to

CC

INTV through a P-channel MOSFET and can supply the

CC

the EXTV pin and make sure that EXTV < V .

CC

IN

needed power when its voltage is higher than 4.7V. Each

of these can supply a peak current of 100mA and must be

bypassed to ground with a minimum of a 4.7µF ceramic

capacitor or a low ESR electrolytic capacitor. No matter

what type of bulk capacitor is used, an additional 0.1µF

Significant efficiency and thermal gains can be realized

by powering INTV from the output, since the V cur-

CC

IN

rent resulting from the driver and control currents will be

scaled by a factor of (Duty Cycle)/(Switcher Efficiency).

Tying the EXTV pin to a 5V supply reduces the junction

CC

ceramic capacitor placed directly adjacent to the INTV

CC

temperature in the previous example from 125°C to:

and PGND pins is highly recommended. Good bypassing

is needed to supply the high transient currents required

by the MOSFET gate drivers and to prevent interaction

between the channels.

T = 70°C + (44mA)(5V)(33°C/W) = 77°C

J

However,for3.3Vandotherlowvoltageoutputs,additional

circuitryisrequiredtoderiveINTV powerfromtheoutput.

CC

High input voltage applications in which large MOSFETs

are being driven at high frequencies may cause the maxi-

3875fb

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For more information www.linear.com/LTC3875

LTC3875

APPLICATIONS INFORMATION

The following list summarizes the four possible connec-

MOSFET. This enhances the MOSFET and turns on the

tions for EXTV :

topside switch. The switch node voltage, SW, rises to V

CC

IN

and the BOOST pin follows. With the topside MOSFET on,

the boost voltage is above the input supply:

1. EXTV left open (or grounded). This will cause INTV

CC

tobepoweredfromtheinternal5.5Vregulatorresulting

in an efficiency penalty at high input voltages.

V

= V + V

– V

INTVCC D

B

BOOST

IN

2. EXTV connected directly to V . This is the normal

where V is the diode forward voltage drop.

D

B

CC

OUT

connection for a 5V regulator and provides the highest

Thevalueoftheboostcapacitor, C , needstobe100times

B

efficiency.

thatofthetotalinputcapacitanceofthetopsideMOSFET(s).

3. EXTV connectedtoanexternalsupply.Ifa5Vexternal

The reverse breakdown of the external Schottky diode

CC

supply is available, it may be used to power EXTV

must be greater than V . When adjusting the gate

IN(MAX)

CC

providing it is compatible with the MOSFET gate drive

drive level, the final arbiter is the total input current for

the regulator. If a change is made and the input current

decreases, then the efficiency has improved. If there is

no change in input current, then there is no change in

efficiency.

requirements.

4. EXTV connected to an output-derived boost network.

CC

For 3.3V and other low voltage regulators, efficiency

gains can still be realized by connecting EXTV to an

CC

output-derivedvoltagethathasbeenboostedtogreater

Undervoltage Lockout

than 4.7V.

The LTC3875 has two functions that help protect the

controller in case of undervoltage conditions. A precision

For applications where the main input power is below 5V,

tie the V and INTV pins together and tie the combined

IN

CC

UVLOcomparatorconstantlymonitorstheINTV voltage

CC

pins to the 5V input with a 1Ω or 2.2Ω resistor as shown

to ensure that an adequate gate-drive voltage is present.

in Figure 11 to minimize the voltage drop caused by the

It locks out the switching action when INTV is below

CC

gate charge current. This will override the INTV linear

CC

3.7V. To prevent oscillation when there is a disturbance

regulator and will prevent INTV from dropping too low

CC

on the INTV , the UVLO comparator has 500mV of preci-

CC

due to the dropout voltage. Make sure the INTV voltage

CC

sion hysteresis.

is at or exceeds the R

test voltage for the MOSFET

DS(ON)

Another way to detect an undervoltage condition is to

which is typically 4.5V for logic level devices.

monitor the V supply. Because the RUN pins have a

IN

precisionturn-onreferenceof1.22V,onecanusearesistor

V

IN

divider to V to turn on the IC when V is high enough.

IN

R

LTC3875

INTV

VIN

An extra 4.5µA of current flows out of the RUN pin once

the RUN pin voltage passes 1.22V. One can program the

hysteresis of the run comparator by adjusting the values

1Ω

5V

CC

+

C

INTVCC

C

IN

4.7µF

of the resistive divider. For accurate V undervoltage

3875 F11

IN

detection, V needs to be higher than 4.5V.

IN

Figure 11. Setup for a ꢀV Input

C and C

Selection

IN

OUT

Topside MOSFET Driver Supply (C , D )

B

The selection of C is simplified by the 2-phase architec-

IN

External bootstrap capacitor, C , connected to the BOOST

B

ture and its impact on the worst-case RMS current drawn

through the input network (battery/fuse/capacitor). It can

be shown that the worst-case capacitor RMS current oc-

curs when only one controller is operating. The controller

pinsuppliesthegatedrivevoltagesforthetopsideMOSFET.

Capacitor C in the Functional Diagram is charged though

B

external diode D from INTV when the SW pin is low.

B

CC

When the topside MOSFET is to be turned on, the driver

places the C voltage across the gate source of the

with the highest (V )(I ) product needs to be used

OUT OUT

B

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For more information www.linear.com/LTC3875

LTC3875

APPLICATIONS INFORMATION

in the formula below to determine the maximum RMS

capacitor current requirement. Increasing the output cur-

rent drawn from the other controller will actually decrease

the input RMS ripple current from its maximum value.

The out-of-phase technique typically reduces the input

capacitor’s RMS ripple current by a factor of 30ꢀ to 70ꢀ

when compared to a single phase power supply solution.

should be placed within 1cm of each other and share a

common C (s). Separating the sources and C may pro-

IN

duce undesirable voltage and current resonances at V .

IN

A small (0.1µF to 1µF) bypass capacitor between the chip

V pin and ground, placed close to the LTC3875, is also

IN

suggested. A 2.2Ω to 10Ω resistor placed between C

IN

and the V pin provides further isolation between the

IN

Incontinuousmode,thesourcecurrentofthetopMOSFET

two channels.

is a square wave of duty cycle (V )/(V ). To prevent

OUT

IN

The selection of C

is driven by the effective series

OUT

large voltage transients, a low ESR capacitor sized for the

maximum RMS current of one channel must be used. The

maximum RMS capacitor current is given by:

resistance (ESR). Typically, once the ESR requirement

is satisfied, the capacitance is adequate for filtering. The

output ripple (∆V ) is approximated by:

OUT



^1/2

I_MAX

C_INRequired I_RMS

≈

V

_OUT)(

V – V











(

)

1

IN

OUT





V

∆V_OUT≈I_RIPPLEESR+

IN

8fC

_OUT

This formula has a maximum at V = 2V , where

IN

OUT

I

= I /2. This simple worst-case condition is com-

where f is the operating frequency, C

is the output

OUT

RMS

OUT

monlyusedfordesignbecauseevensignificantdeviations

donotoffermuchrelief.Notethatcapacitormanufacturers’

ripple current ratings are often based on only 2000 hours

of life. This makes it advisable to further derate the capaci-

tor, or to choose a capacitor rated at a higher temperature

thanrequired.Severalcapacitorsmaybeparalleledtomeet

size or height requirements in the design. Due to the high

operating frequency of the LTC3875, ceramic capacitors

capacitance and I

is the ripple current in the induc-

RIPPLE

tor. The output ripple is highest at maximum input voltage

since I increases with input voltage.

RIPPLE

Setting Output Voltage

The LTC3875 output voltages are each set by an external

feedback resistive divider carefully placed across the out-

put, as shown in Figure 1. The regulated output voltage

is determined by:

can also be used for C . Always consult the manufacturer

IN

if there is any question.





R_D1

R

V

_OUT= 0.6V • 1+

The benefit of the LTC3875 2-phase operation can be

calculated by using the equation above for the higher

power controller and then calculating the loss that would

have resulted if both controller channels switched on at

the same time. The total RMS power lost is lower when

both controllers are operating due to the reduced overlap

of current pulses required through the input capacitor’s

ESR. This is why the input capacitor’s requirement cal-

culated above for the worst-case controller is adequate

for the dual controller design. Also, the input protection

fuse resistance, battery resistance, and PC board trace

resistance losses are also reduced due to the reduced

peak currents in a 2-phase system. The overall benefit of

a multiphase design will only be fully realized when the

source impedance of the power supply/battery is included

in the efficiency testing. The sources of the top MOSFETs







_D2

To improve the frequency response, a feed-forward ca-

pacitor, C , may be used. Great care should be taken to

FF

route the V line away from noise sources, such as the

FB

inductor or the SW line.

Fault Conditions: Current Limit and Current Foldback

The LTC3875 includes current foldback to help limit load

current when the output is shorted to ground. If the out-

put falls below 50ꢀ of its nominal output level, then the

maximum sense voltage is progressively lowered from its

maximumprogrammedvaluetoone-thirdofthemaximum

value. Foldback current limiting is disabled during the

soft-start or tracking up. Under short-circuit conditions

3875fb

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For more information www.linear.com/LTC3875

LTC3875

APPLICATIONS INFORMATION

with very low duty cycles, the LTC3875 will begin cycle

skipping in order to limit the short-circuit current. In this

situation the bottom MOSFET will be dissipating most of

the power but less than in normal operation. The short-

circuit ripple current is determined by the minimum

The internal thermal shutdown is set for approximately

160°C with 10°C of hysteresis. When the chip reaches

160°C, both TG and BG are disabled until the chip cools

down below 150°C.

Phase-Locked Loop and Frequency Synchronization

on-time, t

, of the LTC3875 (≈90ns), the input volt-

ON(MIN)

age and inductor value:

TheLTC3875hasaphase-lockedloop(PLL)comprisedof

an internal voltage-controlled oscillator (V ) and a phase

V

L

CO

IN

∆I_L(SC)= t_ON(MIN)

•

detector. This allows the turn-on of the top MOSFET of

controller 1 to be locked to the rising edge of an external

clock signal applied to the MODE/PLLIN pin. The turn-on

of controller 2’s top MOSFET is thus 180° out-of-phase

with the external clock. The phase detector is an edge

sensitivedigitaltypethatprovideszerodegreesphaseshift

between the external and internal oscillators. This type of

phase detector does not exhibit false lock to harmonics

of the external clock.

The resulting short-circuit current is:

1/3V

1

2

I_SC=

^SENSE(MAX)– ∆I_L(SC)

R_SENSE

Overcurrent Fault Recovery

When the output of the power supply is loaded beyond its

preset current limit, the regulated output voltage will col-

lapse depending on the load. The output may be shorted

to ground through a very low impedance path or it may

be a resistive short, in which case the output will collapse

partially, until the load current equals the preset current

limit. The controller will continue to source current into

the short. The amount of current sourced depends on

Theoutputofthephasedetectorisapairofcomplementary

current sources that charge or discharge the internal filter

network. There is a precision 10µA of current flowing out

of FREQ pin. This allows the user to use a single resistor

to SGND to set the switching frequency when no external

clockisappliedtotheMODE/PLLINpin.Theinternalswitch

between FREQ pin and the integrated PLL filter network

is on, allowing the filter network to be precharged to the

same voltage potential as the FREQ pin. The relationship

between the voltage on the FREQ pin and the operating

frequencyisshowninFigure12andspecifiedintheElectri-

cal Characteristic table. If an external clock is detected on

theMODE/PLLINpin, theinternalswitchmentionedabove

will turn off and isolate the influence of FREQ pin. Note

that the LTC3875 can only be synchronized to an external

clock whose frequency is within range of the LTC3875’s

the ILIM pin setting and the V voltage as shown in the

FB

Current Foldback graph in the Typical Performance Char-

acteristics section. Upon removal of the short, the output

soft starts using the internal soft-start, thus reducing

outputovershoot.Intheabsenceofthisfeature,theoutput

capacitors would have been charged at current limit, and

in applications with minimal output capacitance this may

have resulted in output overshoot. Current limit foldback

is not disabled during an overcurrent recovery. The load

must step below the folded back current limit threshold

in order to restart from a hard short.

internalV . Thisisguaranteedtobebetween250kHzand

CO

720kHz. A simplified block diagram is shown in Figure 13.

If the external clock frequency is greater than the inter-

Thermal Protection

nal oscillator’s frequency, f , then current is sourced

OSC

Excessive ambient temperatures, loads and inadequate

airflow or heat sinking can subject the chip, inductor,

FETs etc. to high temperatures. This thermal stress re-

duces component life and if severe enough, can result

in immediate catastrophic failure (Note 1). To protect the

power supply from undue thermal stress, the LTC3875

has a fixed chip temperature-based thermal shutdown.

continuously from the phase detector output, pulling up

the filter network. When the external clock frequency is

less than f , current is sunk continuously, pulling down

OSC

the filter network. If the external and internal frequencies

are the same but exhibit a phase difference, the current

sources turn on for an amount of time corresponding to

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For more information www.linear.com/LTC3875

LTC3875

APPLICATIONS INFORMATION

900

800

700

600

500

400

300

200

100

cycle applications may approach this minimum on-time

limit and care should be taken to ensure that:

V_OUT

t_ON(MIN)

<

V •f

(

)

IN

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles.Theoutputvoltagewillcontinuetoberegulated,but

the ripple voltage and current will increase. The minimum

on-time for the LTC3875 is approximately 90ns, with rea-

sonablygoodPCBlayout, minimum30ꢀinductorcurrent

ripple and at least 2mV ripple on the current sense signal

0

2

2.5

0.5

1

1.5

FREQ PIN VOLTAGE (V)

3875 F12

+

–

Figure 12. Relationship Between Oscillator Frequency

and Voltage at the FREQ Pin

or equivalent 10mV between SNSA and SNS pins. The

minimum on-time can be affected by PCB switching noise

in the voltage and current loop. As the peak sense voltage

decreases the minimum on-time gradually increases to

110ns. This is of particular concern in forced continuous

applications with low ripple current at light loads. If the

duty cycle drops below the minimum on-time limit in this

situation, a significant amount of cycle skipping can occur

with correspondingly larger current and voltage ripple.

2.4V 5V

R

SET

10µA

FREQ

MODE/

PLLIN

DIGITAL

PHASE/

FREQUENCY

DETECTOR

SYNC

EXTERNAL

OSCILLATOR

VCO

Efficiency Considerations

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100ꢀ.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can

be expressed as:

3875 F13

Figure 13. Phase-Locked Loop Block Diagram

the phase difference. The voltage on the filter network is

adjusted until the phase and frequency of the internal and

external oscillators are identical. At the stable operating

point, the phase detector output is high impedance and

the filter capacitor holds the voltage.

ꢀEfficiency = 100ꢀ – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percent-

age of input power.

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the

Typically, the external clock (on MODE/PLLIN pin) input

high threshold is 1.6V, while the input low threshold is 1V.

It is not recommended to apply the external clock when

IC is in shutdown.

losses in LTC3875 circuits: 1) IC V current, 2) INTV

IN

CC

2

regulator current, 3) I R losses, 4) Topside MOSFET

transition losses.

Minimum On-Time Considerations

1. The V current is the DC supply current given in the

IN

ElectricalCharacteristicstable,whichexcludesMOSFET

Minimum on-time, t

, is the smallest time duration

ON(MIN)

driverandcontrolcurrents. V currenttypicallyresults

IN

thattheLTC3875iscapableofturningonthetopMOSFET.

It is determined by internal timing delays and the gate

charge required to turn on the top MOSFET. Low duty

in a small (<0.1ꢀ) loss.

3875fb

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LTC3875

APPLICATIONS INFORMATION

2. INTV current is the sum of the MOSFET driver and

phase. The internal battery and fuse resistance losses can

CC

control currents. The MOSFET driver current results

from switching the gate capacitance of the power

MOSFETs. Each time a MOSFET gate is switched from

low to high to low again, a packet of charge dQ moves

beminimizedbymakingsurethatC hasadequatecharge

IN

storage and very low ESR at the switching frequency. The

LTC3875 2-phase architecture typically halves this input

capacitance requirement over competing solutions. Other

losses including Schottky conduction losses during dead

time and inductor core losses generally account for less

than 2ꢀ total additional loss.

from INTV to ground. The resulting dQ/dt is a cur-

CC

rent out of INTV that is typically much larger than the

CC

control circuit current. In continuous mode, I

=

GATECHG

f(QT + QB), where QT and QB are the gate charges of

the topside and bottom side MOSFETs.

Checking Transient Response

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

Supplying INTV power through EXTV from an

CC

output-derivedsourcewillscaletheV currentrequired

IN

for the driver and control circuits by a factor of (Duty

load current. When a load step occurs, V

shifts by an

Cycle)/(Efficiency). Forexample, ina20Vto5Vapplica-

OUT

amount equal to ∆I

, where ESR is the effective

also begins to charge or

LOAD

tion, 10mA of INTV current results in approximately

LOAD (ESR)

CC

series resistance of C . ∆I

2.5mA of V current. This reduces the midcurrent loss

OUT

IN

discharge C

generating the feedback error signal that

from 10ꢀ or more (if the driver was powered directly

OUT

forces the regulator to adapt to the current change and

return V to its steady-state value. During this recovery

from V ) to only a few percent.

IN

OUT

2

3. I R losses are predicted from the DC resistances of the

time V

can be monitored for excessive overshoot or

OUT

fuse (if used), MOSFET, inductor, current sense resis-

tor (if used). In continuous mode, the average output

current flows through L, but is “chopped” between the

topside MOSFET and the synchronous MOSFET. If the

ringing, which would indicate a stability problem. The

availability of the I pin not only allows optimization of

TH

control loop behavior but also provides a DC-coupled and

AC-filtered closed-loop response test point. The DC step,

rise time and settling at this test point truly reflects the

closed loop response. Assuming a predominantly second

ordersystem, phase margin and/ordampingfactorcanbe

estimated using the percentage of overshoot seen at this

pin.Thebandwidthcanalsobeestimatedbyexaminingthe

two MOSFETs have approximately the same R

,

DS(ON)

then the resistance of one MOSFET can simply be

2

summed with the resistances of L to obtain I R losses.

Efficiency varies as the inverse square of V

for the

OUT

sameexternalcomponentsandoutputpowerlevel. The

combined effects of increasingly lower output voltages

andhighercurrentsrequiredbyhighperformancedigital

systemsisnotdoublingbutquadruplingtheimportance

of loss terms in the switching regulator system!

rise time at the pin. The I external components shown

TH

in the Typical Application circuit will provide an adequate

starting point for most applications. The I series R -C

TH

C

filter sets the dominant pole-zero loop compensation.

The values can be modified slightly (from 0.5 to 2 times

their suggested values) to optimize transient response

once the final PC layout is done and the particular output

capacitortypeandvaluehavebeendetermined.Theoutput

capacitors need to be selected because the various types

and values determine the loop gain and phase. An output

current pulse of 20ꢀ to 80ꢀ of full-load current having a

rise time of 1µs to 10µs will produce output voltage and

4. Transition losses apply only to the topside MOSFET(s),

and become significant only when operating at high

input voltages (typically 15V or greater). Transition

losses can be estimated from:

2

Transition Loss = (1.7) V

I

C

f

IN O(MAX) RSS

Other “hidden” losses such as copper trace and internal

batteryresistancescanaccountforanadditionalefficiency

degradation in portable systems. It is very important to

include these “system” level losses during the design

I

pin waveforms that will give a sense of the overall

TH

loop stability without breaking the feedback loop. Placing

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LTC3875

APPLICATIONS INFORMATION

2. Are the signal and power grounds kept separate? The

combined IC signal ground pin and the ground return

a power MOSFET directly across the output capacitor and

driving the gate with an appropriate signal generator is a

practicalwaytoproducearealisticload-stepcondition.The

initial output voltage step resulting from the step change

in output current may not be within the bandwidth of the

feedback loop, so this signal cannot be used to determine

of C

must return to the combined C

(–)

INTVCC

OUT

terminals. The V and I traces should be as short

FB

TH

as possible. The path formed by the top N-channel

MOSFET, Schottky diode and the C capacitor should

IN

have short leads and PC trace lengths. The output

capacitor (–) terminals should be connected as close

as possible to the (–) terminals of the input capacitor

by placing the capacitors next to each other and away

from the Schottky loop described above.

phase margin. This is why it is better to look at the I pin

TH

signal which is in the feedback loop and is the filtered and

compensated control loop response. The gain of the loop

willbeincreasedbyincreasingR andthebandwidthofthe

C

loop will be increased by decreasing C . If R is increased

C

bythesamefactorthatC isdecreased,thezerofrequency

+

–

C

3. Are the SNSD , SNSA and SNS printed circuit traces

routed together with minimum PC trace spacing? The

will be kept the same, thereby keeping the phase shift the

same in the most critical frequency range of the feedback

loop. The output voltage settling behavior is related to the

stability of the closed-loop system and will demonstrate

the actual overall supply performance.

+

–

filter capacitors between SNSD , SNSA and SNS

should be as close as possible to the pins of the IC.

ConnecttheSNSD andSNSA pinstothefilterresistors

as illustrated in Figure 4.

+

A second, more severe transient is caused by switching

in loads with large (>1µF) supply bypass capacitors. The

dischargedbypasscapacitorsareeffectivelyputinparallel

4. Do the (+) plates of C connect to the drain of the

IN

topside MOSFET as closely as possible? This capacitor

provides the pulsed current to the MOSFET.

with C , causing a rapid drop in V . No regulator can

OUT

5. Keep the switching nodes, SW, BOOST and TG away

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. If the ratio of

+

from sensitive small-signal nodes (SNSD , SNSA ,

–

+

–

SNS , V

, V

). Ideally the SW, BOOST and

OSNS

TG printed circuit traces should be routed away and

separated from the IC and especially the quiet side of

the IC. Separate the high dv/dt traces from sensitive

small-signalnodeswithgroundtracesorgroundplanes.

C

to C

is greater than 1:50, the switch rise time

LOAD

OUT

should be controlled so that the load rise time is limited

to approximately 25 • C . Thus a 10µF capacitor would

LOAD

require a 250µs rise time, limiting the charging current

to about 200mA.

6. The INTV decoupling capacitor should be placed im-

CC

mediately adjacent to the IC between the INTV pin

CC

PC Board Layout Checklist

and PGND plane. A 1µF ceramic capacitor of the X7R

or X5R type is small enough to fit very close to the IC

to minimize the ill effects of the large current pulses

drawn to drive the bottom MOSFETs. An additional

4.7µF to 10µF of ceramic, tantalum or other very low

ESR capacitance is recommended in order to keep the

internal IC supply quiet.

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the IC. These items are also illustrated graphically in the

layoutdiagramofFigure14.Figure15illustratesthecurrent

waveforms present in the various branches ofthe 2-phase

synchronousregulatorsoperatinginthecontinuousmode.

Check the following in your layout:

7. Use a modified “star ground” technique: a low imped-

ance, large copper area central grounding point on

the same side of the PC board as the input and output

capacitors with tie-ins for the bottom of the INTVCC

decouplingcapacitor,thebottomofthevoltagefeedback

resistive divider and the SGND pin of the IC.

1. ArethetopN-channelMOSFETsM1andM3locatedwithin

1cm of each other with a common drain connection at

C ? Do not attempt to split the input decoupling for the

IN

two channels as it can cause a large resonant loop.

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LTC3875

APPLICATIONS INFORMATION

R

PU2

TK/SS1

CLKOUT

V

PULL-UP

PGOOD

I

PGOOD

PHASMD

IFAST

TH1

LTC3875

+

V

OSNS1

–

L1

V

OSNS

+

V

OUT1

SNSA1

TG1

–

SNS1

SW1

C

+

B1

M1

M2

D1

SNSD1

FREQ

BOOST1

BG1

(OPT)

I

LIM

10µF ×2

CERAMIC

R

IN

f

MODE/PLLIN

RUN1

IN

2.2Ω

C

OUT1

V

IN

C

1µF

VIN

RUN2

SGND

PGND

V

GND

IN

1µF

–

C

INTVCC

EXTV

SNSA2

CC

C

IN

4.7µF

–

SNS2

INTV

CC

OUT2

10µF ×2

CERAMIC

+

SNSD2

BG2

–

V

OSNS2

M4

M3

+

D2

(OPT)

V

BOOST2

C

B2

I

SW2

TG2

TH2

V

OUT2

TK/SS2

L2

3875 F14

Figure 14. Recommended Printed Circuit Layout Diagram

SW1

L1

V

OUT1

D1

C

OUT1

R

L1

V

IN

R

IN

C

IN

SW2

L2

V

OUT2

D2

C

OUT2

R

L2

BOLD LINES INDICATE

HIGH SWITCHING

CURRENT. KEEP LINES

TO A MINIMUM LENGTH.

3875 F15

Figure 1ꢀ. Branch Current Waveforms

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LTC3875

APPLICATIONS INFORMATION

8. Use a low impedance source such as a logic gate to

drive the MODE/PLLIN pin and keep the lead as short

as possible.

not required. Only after each controller is checked for

its individual performance should both controllers be

turned on at the same time. A particularly difficult region

of operation is when one controller channel is nearing its

current comparator trip point when the other channel is

turning on its top MOSFET. This occurs around 50ꢀ duty

cycle on either channel due to the phasing of the internal

clocks and may cause minor duty cycle jitter.

9. The 47pF to 330pF ceramic capacitor between the ITH

pin and signal ground should be placed as close as

possible to the IC. Figure 15 illustrates all branch cur-

rents in a switching regulator. It becomes very clear

afterstudyingthecurrentwaveformswhyitiscriticalto

keepthehighswitchingcurrentpathstoasmallphysical

size. High electric and magnetic fields will radiate from

these loops just as radio stations transmit signals. The

output capacitor ground should return to the negative

terminal of the input capacitor and not share a com-

mon ground path with any switched current paths. The

left half of the circuit gives rise to the noise generated

by a switching regulator. The ground terminations of

the synchronous MOSFET and Schottky diode should

return to the bottom plate(s) of the input capacitor(s)

with a short isolated PC trace since very high switched

currents are present. External OPTI-LOOP^®compensa-

tion allows overcompensation for PC layouts which are

not optimized but this is not the recommended design

procedure.

Reduce V from its nominal level to verify operation of

IN

the regulator in dropout. Check the operation of the un-

dervoltage lockout circuit by further lowering V while

IN

monitoring the outputs to verify operation.

Investigate whether any problems exist only at higher out-

put currents or only at higher input voltages. If problems

coincide with high input voltages and low output currents,

look for capacitive coupling between the BOOST, SW, TG,

and possibly BG connections and the sensitive voltage

and current pins. The capacitor placed across the current

sensing pins needs to be placed immediately adjacent to

the pins of the IC. This capacitor helps to minimize the

effects of differential noise injection due to high frequency

capacitive coupling. If problems are encountered with

high current output loading at lower input voltages, look

for inductive coupling between C , Schottky and the top

IN

PC Board Layout Debugging

MOSFET components to the sensitive current and voltage

sensing traces. In addition, investigate common ground

path voltage pickup between these components and the

SGND pin of the IC.

Start with one controller at a time. It is helpful to use a

DC-50MHz current probe to monitor the current in the

inductor while testing the circuit. Monitor the output

switching node (SW pin) to synchronize the oscilloscope

totheinternaloscillatorandprobetheactualoutputvoltage

as well. Check for proper performance over the operating

voltage and current range expected in the application. The

frequency of operation should be maintained over the

input voltage range down to dropout and until the output

load drops below the low current operation threshold—

typically 10ꢀ of the maximum designed current level in

Burst Mode^®operation. The duty cycle percentage should

be maintained from cycle to cycle in a well-designed, low

noise PCB implementation. Variation in the duty cycle at a

sub-harmonicratecansuggestnoisepickupatthecurrent

or voltage sensing inputs or inadequate loop compensa-

tion. Overcompensation of the loop can be used to tame

a poor PC layout if regulator bandwidth optimization is

Design Example

As a design example for a single output dual phase high

current regulator, assume V = 12V(nominal), V = 20V

IN

MAX1,2

IN

(maximum), V

= 1.5V, I

= 30A, and f = 400kHz

OUT

(see Figure 16).

The regulated output voltages are determined by:





R_B

R

V

_OUT= 0.6• 1+







_A

+

Shorting the V

pins and V

pins together. Us-

OSNS1

OSNS2

+

ing 20k, 1ꢀ resistor from V

the top feedback resistor is (to the nearest 1ꢀ standard

node to remote ground,

OSNS

value) 30.1k.

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LTC3875

APPLICATIONS INFORMATION

INTV

CC

60k

V

IN

20k

4.5V TO 20V

10µF

270µF

50V

INTV

CC

×4

4.7µF

V

INTV

CC

IN

PHASMD

CLKOUT

PGOOD

IFAST

D1

CMDSH-3

M1

BSC050NE2LS

D2

CMDSH-3

RUN1,2

ILIM

ENTMPB

TG1

THERMAL

SENSOR

THERMAL

SENSOR

M3

MODE/PLLIN

TG2

LTC3875

BSC050NE2LS

C

B1

0.1µF

C

0.1µF

B2

L1

L2

0.33µH

(0.32mΩ DCR)

0.33µH

(0.32mΩ DCR)

BOOST1

BOOST2

SW2

SW1

EXTV

BG1

M4

M2

BSC010NE2LSI

CC

BSC010NE2LSI

R1

R2

931Ω

R2

931Ω

R1

4.64k

BG2

4.64k

TAVG

PGND

R

10k

TRSET1

R

10k

TRSET2

TRSET1

SNSA1

TRSET2

+

SNSA2

220nF

–

SNS1

SNS2

+

SNSD1

SNSD2

TCOMP1

TCOMP2

+

–

V

OSNS1

OUT

R

30.1k

V

1.5V

60A

FREQ

B

OUT

+

V

I

OSNS1

TH1

V

OSNS2

I

–

+

C

OUT4

OUT3

470µF

C

OUT1

+

TH2

100µF

1.5nF

100k 10k

C

OUT2

470µF

A

TK/SS1 TK/SS2

100µF

×2

20k

R

TAVG

×2

5k

0.1µF

3875 F16

Figure 16. High Efficiency Dual Phase 400kHz, 1.ꢀV/60A Step-Down Converter with Optional Thermal Balancing

The frequency is set by biasing the FREQ pin to 1V (see

Figure 12).

It will have 10A (33ꢀ) ripple. The peak inductor current

will be the maximum DC value plus one-half the ripple

current, or 35A.

The inductance values are based on a 35ꢀ maximum

ripple current assumption (10.5A for each channel). The

highest value of ripple current occurs at the maximum

input voltage:

The minimum on-time occurs at the maximum V , and

IN

should not be less than 90ns:

V_OUT

_IN(MAX)( )

1.5V

t_ON(MIN)

=

=187ns









V

f

20V 400kHz

(

)

V_OUT

f•∆I

V_OUT

L =

1–

V

_L(MAX)

_IN(MAX)

DCRsensingisusedinthiscircuit. IfC1andC2arechosen

to be 220nF, based on the chosen 0.33µH inductor with

0.32mΩ DCR, R1 and R2 can be calculated as:

This design will require 0.33µH. The Würth 744301033,

0.32µH inductor is chosen. At the nominal input voltage

(12V), the ripple current will be:

L

R1=

R2=

= 4.69k

DCR•C1

L

DCR•C2•5







V_OUT

f•L

V_OUT

∆I_L(NOM)

=

1–



= 937Ω

V



_IN(NOM)

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LTC3875

APPLICATIONS INFORMATION

Choose R1 = 4.64k and R2 = 931Ω.

An Infineon BSC010NE2LS, R

= 1.1mΩ, is chosen

DS(ON)

for the bottom FET. The resulting power loss is:

The maximum DCR of the inductor is 0.34mΩ. The

20V –1.5V

V

is calculated as:

2

SENSE(MAX)

P_SYNC

=

30A •

(

)

20V

1+ 0.005 • 75°C–25°C •0.001Ω

V

= I

• DCR (Max) = 12mV

PEAK

SENSE(MAX)

(

)

(

)





The current limit is chosen to be 15mV. If temperature

variation is considered, please refer to Inductor DCR

SensingTemperatureCompensationwithNTCThermistor.

P_SYNC=1.14W

C is chosen for an equivalent RMS current rating of at

IN

The power dissipation on the topside MOSFET can be

easily estimated. Choosing an Infineon BSC050NE2LS

least 13.7A. C

is chosen with an equivalent ESR of

OUT

4.5mΩ for low output ripple. The output ripple in continu-

MOSFET results in: R

MILLER

(estimated) = 75°C:

= 7.1mΩ (max), V

=

J

DS(ON)

MILLER

ous mode will be highest at the maximum input voltage.

2.8V, C

≅ 35pF. At maximum input voltage with T

The output voltage ripple due to ESR is approximately:

V

= R

(∆I ) = 0.0045Ω • 10A = 45mV

1.5V

20V

ORIPPLE

ESR L P-P

2

P_MAIN

=

30A 1+ 0.005 75°C–25°C •

(

)

(

)

(

)





Further reductions in output voltage ripple can be made

by placing a 100µF ceramic capacitor across C

.

30A

2

₂



OUT

0.0071Ω + 20V

) (

2Ω 35pF •

)(

(

)

(

)









Thermal Balancing Converter Example

1





+

400kHz

(



)

If thermal balancing function is desired, connecting

ENTMPBpintogroundenablesthetemperaturebalancing

function,butdisablestheinductorDCRsensingtemperature

compensation function. For a 4-phase design select



5.5V –2.8V 2.8V





= 599mW+122mW

= 721mW

TRSET1,2,3,4 = 10k, then R

= 2.5k. The resistance

TAVG

For a 0.32mΩ DCR, a short-circuit to near ground will

result in a folded back current of:

vs temperature slope of NTC connected to the TCOMP

pin need to be modified according to the inductor current

correction range. Please refer to temperature balancing

with NTC thermistor example shown in Figure 17.

1/3 15mV

 90ns 20V 

1

(

)

(

)

I_SC=

–

=12.9A





0.0032Ω 2 0.33µH 

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LTC3875

TYPICAL APPLICATIONS

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TYPICAL APPLICATIONS

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LTC3875

TYPICAL APPLICATIONS

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TYPICAL APPLICATIONS

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TYPICAL APPLICATIONS

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TYPICAL APPLICATIONS

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LTC3875

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LTC387ꢀ#packaging for the most recent package drawings.

UH Package

40-Lead Plastic QFN (5mm × 5mm)

(Reference LTC DWG # 05-08-1746 Rev B)

0.70 ±0.05

5.50 ±0.05

4.10 ±0.05

3.50 ±0.05

3.60 REF

(4 SIDES)

3.50 ±0.05

PACKAGE OUTLINE

0.20 ±0.05

0.40 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.75 ±0.05

R = 0.100

TYP

5.00 ±0.10

(4 SIDES)

R = 0.05

TYP

39 40

0.40 ±0.10

PIN 1 TOP MARK

(SEE NOTE 5)

1

2

PIN 1 NOTCH

R = 0.30 TYP

OR 0.35 × 45°

CHAMFER

3.50 ±0.10

3.60 REF

(4-SIDES)

3.50 ±0.10

(UH40) QFN REV B 0415

0.200 REF

0.20 ± 0.05

0.00 – 0.05

0.40 BSC

NOTE:

BOTTOM VIEW—EXPOSED PAD

1. DRAWING CONFIRMS TO JEDEC PACKAGE OUTLINE MO-220

2. ALL DIMENSIONS ARE IN MILLIMETERS

3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

4. EXPOSED PAD SHALL BE SOLDER PLATED

5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

6. DRAWING NOT TO SCALE

3875fb

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LTC3875

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LTC387ꢀ#packaging for the most recent package drawings.

UJ Package

40-Lead Plastic QFN (6mm × 6mm)

(Reference LTC DWG # 05-08-ꢀ728 Rev Ø)

0.70 0.05

6.50 0.05

5.ꢀ0 0.05

4.42 0.05

4.50 0.05

(4 SIDES)

4.42 0.05

PACKAGE OUTLINE

0.25 0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.75 0.05

R = 0.ꢀꢀ5

TYP

6.00 0.ꢀ0

(4 SIDES)

R = 0.ꢀ0

TYP

39 40

0.40 0.ꢀ0

PIN ꢀ TOP MARK

(SEE NOTE 6)

ꢀ

2

PIN ꢀ NOTCH

R = 0.45 OR

0.35 × 45°

CHAMFER

4.42 0.ꢀ0

4.50 REF

(4-SIDES)

4.42 0.ꢀ0

(UJ40) QFN REV Ø 0406

0.200 REF

0.25 0.05

0.50 BSC

0.00 – 0.05

NOTE:

BOTTOM VIEW—EXPOSED PAD

ꢀ. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION ON THE TOP AND BOTTOM OF PACKAGE

3875fb

44

For more information www.linear.com/LTC3875

LTC3875

REVISION HISTORY

REV

DATE

DESCRIPTION

PAGE NUMBER

1 to 30

A

4/15

Corrected typographical errors

Modifications to figures

Simplified schematics

28 to 35

36 to 44

1, 2, 3, 5, 43

3

B

11/15 Added UH Package

Removed Temp Dot from I

SENSE(AC)

3875fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

45

For more information www.linear.com/LTC3875

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC3875

TYPICAL APPLICATION

High Efficiency Dual Phase 1V/60A Step-Down Converter

V

IN

6V TO 14V

22µF

16V ×4

INTV

CC

4.7µF

V

INTV

PHASMD

CLKOUT

PGOOD

IFAST

IN

CC

(OPTIONAL)

RUN1,2

ILIM

ENTMPB

TG1

BSC050NE2LS

0.1µF

BSC050NE2LS

THERMAL

SENSOR

THERMAL

SENSOR

MODE/PLLIN

TG2

0.1µF

0.25µH

(0.32mΩ DCR)

0.25µH

(0.32mΩ DCR)

BOOST1

BOOST2

SW2

LTC3875

CC

SW1

EXTV

BG1

BSC010NE2LSI

3.57k

715

715 3.57k

BG2

220nF

TAVG

PGND

TRSET1

220nF

TRSET2

+

SNSA1

+

SNSA2

–

SNS1

SNSD1

TCOMP1

–

SNS2

+

220nF

13.3k

+

SNSD2

TCOMP2

+

–

V

OUT

OSNS1

V

1.2V

60A

FREQ

OUT

+

V

OSNS1

TH1

V

OSNS2

I

–

I

+

470µF

2.5V ×2

SP

1500pF

100k 10k

TK/SS1 TK/SS2

TH2

+

470µF

2.5V ×2

20k

0.1µF

SP

3875 TA02

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

Operates with DrMOS, Power Blocks or External

Drives/MOSFETs, 4.5V ≤ V ≤ 38V,

LTC3774

Dual, Multiphase Current Mode Synchronous Step-Down DC/DC

Controller for Sub-Milliohm DCR Sensing

IN

0.6V ≤ V

≤ 3.5V

OUT

LTC3866

LTC3855

Single Output Current Mode Synchronous Controller with Sub-Milliohm Synchronous Fixed Frequency 250kHz to 770kHz,

DCR Sensing

4.5V ≤ V ≤ 38V, 0.6V ≤ V

≤ 3.5V

IN

OUT

Dual, Multiphase, Synchronous Step-Down DC/DC Controller with

Differential Output Sensing and DCR Temperature Compensation

PLL Fixed Frequency 250kHz to 770kHz,

4.5V ≤ V ≤ 38V, 0.8V ≤ V ≤ 12V

IN

OUT

LTC3838/LTC3838-1/ Dual, Fast, Accurate Step-Down Controlled On-Time DC/DC Controller

LTC3838-2 with Differential Output Sensing

Synchronizable Fixed Frequency 200kHz to 2MHz,

4.5V ≤ V ≤ 38V, 0.8V ≤ V ≤ 5.5V

IN

OUT

LTC3890/LTC3890-1/ Dual, High V , Low I 2-Phase Synchronous Step-Down DC/DC

PLL Capable Fixed Frequency 50kHz to 900kHz,

4V ≤ V ≤ 60V, 0.8V ≤ V ≤ 24V, I = 50µA

IN

Q

LTC3890-2/LTC3890-3 Controller

IN

OUT

Q

LTC3861/LTC3861-1

Dual, Multiphase, Synchronous Step-Down Voltage Mode DC/DC

Controller with Diff Amp and Accurate Current Sharing

Operates with DrMOS, Power Blocks or External

Drivers/MOSFETs, 3V ≤ V ≤ 24V

IN

LTC3856

Single Output, Dual Channel Synchronous Step-Down DC/DC Controller Phase-Lockable Fixed 250kHz to 770kHz Frequency,

with Differential Output Sensing and DCR Temperature Compensation

4.5V ≤ V ≤ 38V, 0.8V ≤ V

≤ 5V

IN

OUT

LTC3869

Dual 2-Phase, Synchronous Step-Down DC/DC Controller

Synchronous Fixed Frequency 250kHz to 780kHz, 4.5V

≤ V ≤ 38V, 0.6V ≤ V ≤ 12.5V

IN

OUT

LTC3857/LTC3857-1

LTC3858/LTC3858-1

38V Low I , Dual Output 2-Phase Synchronous Step-Down DC/DC

PLL Fixed Operating Frequency 50kHz to 900kHz,

4V ≤ V ≤ 38V, 0.8V ≤ V ≤ 24V, I = 50µA/170µA

Q

Controller with 99ꢀ Duty Cycle

IN

OUT

Q

3875fb

LT 1115 REV B • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

46

For more information www.linear.com/LTC3875

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC3875

●

 LINEAR TECHNOLOGY CORPORATION 2013


型号：	LTC3875IUH#PBF
厂家：	Linear
描述：	LTC3875 - Dual, 2-Phase, Synchronous Controller with Low Value DCR Sensing and Temperature Compensation; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C
文件：	总46页 (文件大小：761K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3875IUH#PBF [Linear]

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