LTM4623IY#PBF [Linear]
LTM4623 - Ultrathin 20VIN, 3A Step-Down DC/DC µModule (Power Module) Regulator; Package: BGA; Pins: 25; Temperature Range: -40°C to 85°C;
| 型号： | LTM4623IY#PBF |
| 厂家： | 
Linear |
| 描述： | LTM4623 - Ultrathin 20VIN, 3A Step-Down DC/DC µModule (Power Module) Regulator; Package: BGA; Pins: 25; Temperature Range: -40°C to 85°C |
| 文件： | 总28页 (文件大小：389K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTM4623
Ultrathin 20VIN, 3A Step-Down
DC/DC µModule Regulator
FeaTures
DescripTion
2
n
<2mm Height, Complete Solution in <1cm
The LTM®4623 is a complete 3A step-down switching
mode µModule (micromodule) regulator in a tiny ultrathin
6.25mm×6.25mm×1.82mmLGAand6.25mm×6.25mm
× 2.42mm BGA packages. Included in the package are the
switching controller, power FETs, inductor and support
components. Operating over an input voltage range of
4V to 20V or 2.375V to 20V with an external bias supply,
the LTM4623 supports an output voltage range of 0.6V to
5.5V, set by a single external resistor. Its high efficiency
designdelivers3Acontinuousoutputcurrent.Onlyceramic
input and output capacitors are needed.
2
(Single-Sided PCB) or 0.5cm (Dual-Sided PCB)
Wide Input Voltage Range: 4V to 20V
Input Voltage Down to 2.375V with External Bias
0.6V to 5.5V Output Voltage
n
n
n
n
n
n
n
n
n
n
n
n
n
3A DC Output Current
1.5% Maximum TotalDC OutputVoltageError
Current Mode Control, Fast Transient Response
Low EMI EN55022 Class B Compliant
External Frequency Synchronization
Multiphase Operation with Current Sharing
Output Voltage Tracking
Selectable Discontinuous Mode
Power Good Indicator
Overvoltage, Overcurrent and Overtemperature Pro-
tection
The LTM4623 supports selectable discontinuous mode
operation and output voltage tracking for supply rail se-
quencing. Its high switching frequency and current mode
control enable a very fast transient response to line and
load changes without sacrificing stability.
n
Ultrathin (6.25mm × 6.25mm × 1.82mm) LGA Package
and (6.25mm × 6.25mm × 2.42mm) BGA Package
Fault protection features include overvoltage, overcurrent
and overtemperature protection.
applicaTions
The LTM4623 is available with SnPb (BGA) or RoHS
compliant terminal finish.
L, LT, LTC, LTM, µModule, Linear Technology and the Linear logo are registered trademarks
and LTpowerCAD is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
n
PCIe and Backside PCB Mounting
n
Telecom, Datacom, Networking and Industrial
Equipment
n
Data Storage Rack Units and Cards
Typical applicaTion
1.5V Output Efficiency vs Load Current
3A, 1.5V Output DC/DC µModule® Step-Down Regulator
95
90
85
80
75
70
65
V
1.5V
3A
CLKIN
CLKOUT
OUT
V
IN
V
SV
V
OUT
IN
4V TO 20V
10µF
25V
47µF
6.3V
IN
RUN
INTV
LTM4623
PGOOD
COMP
FB
CC
MODE
PHMODE
TRACK/SS
FREQ
0.1µF
40.2k
V
V
= 5V
IN
IN
GND SGND
= 12V
60
1
2
0
0.5
1.5
2.5
3
4623 TA01a
LOAD CURRENT (A)
4623 TA01b
4623fc
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For more information www.linear.com/LTM4623
LTM4623
absoluTe MaxiMuM raTings
pin conFiguraTion
(Note 1)
(See Pin Functions, Pin Configuration Table)
V , SV .................................................... –0.3V to 22V
IN
IN
TOP VIEW
CLKOUT
V
.................................................–0.3V to SV or 6V
OUT
IN
CLKIN
SV
IN
RUN ........................................................... –0.3V to 22V
V
5
4
3
2
1
IN
INTV ...................................................... –0.3V to 3.6V
CC
SGND
FREQ
MODE
INTV
PGOOD, MODE, TRACK/SS, FREQ,
CC
RUN
PHMODE, CLKIN.................................. –0.3V to INTV
GND
PGOOD
CC
PHMODE
TRACK/SS
FB
Internal Operating Junction Temperature Range
V
OUT
(Notes 2, 5)............................................ –40°C to 125°C
Storage Temperature Range .................. –55°C to 125°C
Peak Solder Reflow Body Temperature.................260°C
COMP
A
B
C
D
E
LGA PACKAGE 25-LEAD (6.25mm × 6.25mm × 1.82mm)
BGA PACKAGE 25-LEAD (6.25mm × 6.25mm × 2.42mm)
T
= 125°C, θ
= 17°C/W, θ
= 11°C/W,
JMAX
JCtop
JCbottom
θ
+ θ = 22°C/W, θ = 22°C/W,
JB
BA JA
θ
DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS
JA
θ VALUES DETERMINED PER JESD51-12, WEIGHT = 0.5g
http://www.linear.com/product/LTM4623#orderinfo
orDer inForMaTion
PART MARKING*
PACKAGE
TYPE
MSL
RATING
TEMPERATURE RANGE
(Note 2)
PART NUMBER
LTM4623EV#PBF
LTM4623IV#PBF
LTM4623EY#PBF
LTM4623IY#PBF
LTM4623IY
PAD OR BALL FINISH
Au (RoHS)
DEVICE
FINISH CODE
LTM4623V
LTM4623V
LTM4623Y
LTM4623Y
LTM4623Y
e4
e4
e1
e1
e0
LGA
LGA
BGA
BGA
BGA
3
3
3
3
3
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
Au (RoHS)
SAC305 (RoHS)
SAC305 (RoHS)
SnPb (63/37)
Consult Marketing for parts specified with wider operating temperature
ranges. *Device temperature grade is indicated by a label on the shipping
container. Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures:
www.linear.com/umodule/pcbassembly
• Pb-free and Non-Pb-free Part Markings:
www.linear.com/leadfree
• LGA and BGA Package and Tray Drawings:
www.linear.com/packaging
4623fc
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For more information www.linear.com/LTM4623
LTM4623
elecTrical characTerisTics The l denotes the specifications which apply over the full internal
operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = SVIN = 12V per the typical application shown on
the front page.
SYMBOL
PARAMETER
CONDITIONS
SV = V
MIN
4
TYP
MAX
20
UNITS
l
l
V
V
V
Input DC Voltage
Output Voltage Range
Output Voltage, Total
V
V
IN
IN
IN
0.6
5.5
OUT(RANGE)
OUT(DC)
C
= 22µF, C
= 100µF Ceramic, R = 40.2k,
CC OUT
IN
OUT FB
Variation with Line and Load MODE = INTV , I
= 0A to 3A (Note 3)
l
–40°C to 125°C
Rising
RUN
1.477
1.1
1.50
1.2
1.523
1.3
V
V
V
RUN Pin On Threshold
V
RUN
I
Input Supply Bias Current
V
V
= 12V, V
= 12V, V
= 1.5V, MODE = INTV
= 1.5V, MODE = GND
6
2
11
mA
mA
µA
Q(SVIN)
IN
IN
OUT
OUT
CC
Shutdown, RUN = 0, V = 12V
IN
I
I
Input Supply Current
V
V
= 12V, V
= 12V, V
= 1.5V, I
= 1.5V
= 3A
OUT
0.5
A
A
S(VIN)
IN
IN
OUT
OUT
Output Continuous Current
Range
0
3
OUT(DC)
l
l
ΔV
ΔV
(Line)/V
Line Regulation Accuracy
Load Regulation Accuracy
Output Ripple Voltage
V
V
= 1.5V, V = 4V to 20V, I = 0A
OUT
0.04
0.5
5
0.15
1.5
%/V
%
OUT
OUT
OUT
OUT
OUT
OUT
IN
(Load)/V
= 1.5V, I
= 0A to 3A
OUT
OUT
V
I
V
= 0A, C
= 1.5V
= 100µF Ceramic, V = 12V,
mV
OUT(AC)
OUT
IN
OUT
ΔV
Turn-On Overshoot
Turn-On Time
I
= 0A, C
= 100µF Ceramic, TRACK/SS = 0.01µF,
= 1.5V
30
2.5
80
40
mV
ms
mV
µs
OUT(START)
OUT
IN
OUT
V
= 12V, V
OUT
t
C
V
= 100µF Ceramic, No Load, TRACK/SS = 0.01µF,
OUT
= 12V, V
START
= 1.5V
IN
OUT
ΔV
Peak Deviation for Dynamic
Load
Load: 0% to 50% to 0% of Full Load, C
Ceramic, V = 12V, V
= 47µF
= 47µF
OUTLS
OUT
OUT
= 1.5V
IN
OUT
t
Settling Time for Dynamic
Load Step
Load: 0% to 50% to 0% of Full Load, C
Ceramic, V = 12V, V = 1.5V
SETTLE
IN
OUT
I
Output Current Limit
Voltage at FB Pin
Current at FB Pin
V
= 12V, V
= 1.5V
3.5
5
A
V
OUTPK
IN
OUT
OUT
l
V
I
= 0A, V
= 1.5V, –40°C to 125°C
0.592
0.60
0.606
30
FB
OUT
I
(Note 4)
nA
kΩ
FB
R
Resistor Between V
and
OUT
60.05
2.4
60.40
2
60.75
FBHI
FB Pins
I
Track Pin Soft-Start Pull-Up
Current
TRACK/SS = 0V
4
µA
TRACK/SS
V
V
Undervoltage Lockout
V
V
Falling, SV = V
IN
Hysteresis, SV = V
2.6
350
2.8
V
mV
IN(UVLO)
IN
IN
IN
IN
IN
IN
t
t
Minimum On-Time
Minimum Off-Time
PGOOD Trip Level
(Note 4)
(Note 4)
40
70
ns
ns
ON(MIN)
OFF(MIN)
V
V
With Respect to Set Output
Ramping Negative
Ramping Positive
PGOOD
FB
V
V
–15
7
–10
10
–7
15
%
%
FB
FB
4623fc
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For more information www.linear.com/LTM4623
LTM4623
elecTrical characTerisTics The l denotes the specifications which apply over the full internal
operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = SVIN = 12V per the typical application shown on
the front page.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
2
UNITS
µA
I
PGOOD Leakage
PGOOD Voltage Low
PGOOD
V
V
V
I
= 1mA
PGOOD
0.02
3.3
0.5
1
0.1
3.4
V
PGL
Internal V Voltage
SV = 4V to 20V
IN
3.1
V
INTVCC
INTVCC
OSC
CC
Load Reg INTV Load Regulation
I
CC
= 0mA to 20mA
%
CC
f
Oscillator Frequency
FREQ = OPEN
MHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: See output current derating curves for different V , V
Note 4: 100% tested at wafer level.
Note 5: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
and T .
IN OUT A
Note 2: The LTM4623 is tested under pulsed load conditions such that
T ≈ T . The LTM4623E is guaranteed to meet performance specifications
J
A
over the 0°C to 125°C internal operating temperature range. Specifications
over the –40°C to 125°C internal operating temperature range are assured
by design, characterization and correlation with statistical process
controls. The LTM4623I is guaranteed to meet specifications over the
full –40°C to 125°C internal operating temperature range. Note that the
maximum ambient temperature consistent with these specifications is
determined by specific operating conditions in conjunction with board
layout, the rated package thermal resistance and other environmental
factors.
4623fc
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For more information www.linear.com/LTM4623
LTM4623
Typical perForMance characTerisTics
Efficiency vs Load Current
with 5VIN
Efficiency vs Load Current
with 12VIN
Efficiency vs Load Current
with 16VIN
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
95
90
85
80
75
70
65
60
V
V
V
V
V
V
= 5V, 2MHz
= 3.3V, 2MHz
= 2.5V
V
V
V
V
V
V
= 5V, 2MHz
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
V
V
V
V
V
= 3.3V, 2MHz
= 2.5V
= 3.3V, 2MHz
= 2.5V
OUT
OUT
OUT
OUT
OUT
= 1.5V
= 1.5V
= 1.5V
= 1.2V
= 1.0V
= 1.2V
= 1.0V
= 1.2V
= 1.0V
60
1
0
2
3
4623 G03
1
0
1
2
3
0
2
3
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
4623 G01
4623 G02
DCM Mode Efficiency with 12VIN,
1.5VOUT
1.2V Output Transient Response
1.0V Output Transient Response
100
90
80
70
60
50
40
30
20
10
0
V
V
OUT
OUT
50mV/DIV
50mV/DIV
DCM
AC-COUPLED
AC-COUPLED
CCM
LOAD STEP
1A/DIV
LOAD STEP
1A/DIV
4623 G06
4623 G05
V
V
= 12V
20µs/DIV
V
V
= 12V
20µs/DIV
IN
OUT
IN
OUT
= 1.2V
= 1.0V
FREQ = 1MHz
FREQ = 1MHz
OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP
LOAD STEP = 2A TO 3A WITH 1A/µS SLEW RATE
FEED FORWARD CAP = 100pF
OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP
LOAD STEP = 2A TO 3A WITH 1A/µS SLEW RATE
FEED FORWARD CAP = 100pF
0.01
0.1
1
LOAD CURRENT (A)
4623 G03
1.5V Output Transient Response
2.5V Output Transient Response
1.8V Output Transient Response
V
V
V
OUT
OUT
OUT
50mV/DIV
50mV/DIV
50mV/DIV
AC-COUPLED
AC-COUPLED
AC-COUPLED
LOAD STEP
1A/DIV
LOAD STEP
1A/DIV
LOAD STEP
1A/DIV
4623 G07
4623 G09
4623 G08
V
V
= 12V
20µs/DIV
V
V
= 12V
20µs/DIV
V
V
= 12V
20µs/DIV
IN
OUT
IN
OUT
IN
OUT
= 1.5V
= 2.5V
= 1.8V
FREQ = 1MHz
FREQ = 1MHz
FREQ = 1MHz
OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP
LOAD STEP = 2A TO 3A WITH 1A/µS SLEW RATE
FEED FORWARD CAP = 100pF
OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP
LOAD STEP = 2A TO 3A WITH 1A/µS SLEW RATE
FEED FORWARD CAP = 100pF
OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP
LOAD STEP = 2A TO 3A WITH 1A/µS SLEW RATE
FEED FORWARD CAP = 100pF
4623fc
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For more information www.linear.com/LTM4623
LTM4623
Typical perForMance characTerisTics
3.3V Output Transient Response
5V Output Transient Response
Start-Up with No Load Applied
V
V
OUT
OUT
I
IN
50mV/DIV
50mV/DIV
0.5A/DIV
AC-COUPLED
AC-COUPLED
V
OUT
LOAD STEP
1A/DIV
LOAD STEP
1A/DIV
0.5V/DIV
4623 G10
4623 G11
4623 G12
V
V
= 12V
20µs/DIV
V
V
= 12V
OUT
FREQ = 1MHz
20µs/DIV
IN
OUT
IN
V
V
= 12V
5ms/DIV
IN
OUT
= 3.3V
= 5V
= 1.5V
FREQ = 1MHz
FREQ = 1MHz
OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP
LOAD STEP = 2A TO 3A WITH 1A/µS SLEW RATE
FEED FORWARD CAP = 100pF
OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP
LOAD STEP = 2A TO 3A WITH 1A/µS SLEW RATE
FEED FORWARD CAP = 100pF
INPUT CAPACITOR = 1 × 22µF CERAMIC CAP
OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP
SOFT START = 0.1µF
Short Circuit with No Load
Applied
Short Circuit with 3A Load
Applied
Start-Up with 3A Load Applied
I
IN
I
I
IN
0.5A/DIV
IN
0.5A/DIV
0.5A/DIV
V
OUT
0.5V/DIV
V
OUT
0.5V/DIV
V
OUT
0.5V/DIV
4623 G14
4623 G15
4623 G13
V
V
= 12V
5ms/DIV
V
V
= 12V
20µs/DIV
V
V
= 12V
5ms/DIV
IN
OUT
IN
OUT
IN
OUT
= 1.5V
= 1.5V
= 1.5V
FREQ = 1MHz
FREQ = 1MHz
FREQ = 1MHz
INPUT CAPACITOR = 1 × 22µF CERAMIC CAP
OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP
INPUT CAPACITOR = 1 × 22µF CERAMIC CAP
OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP
INPUT CAPACITOR = 1 × 22µF CERAMIC CAP
OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP
SOFT START = 0.1µF
Short Circuit with 3A Load
Applied
Start into Pre-Biased Output
Output Ripple
V
IN
2V/DIV
I
IN
0.5A/DIV
V
OUT
V
OUT
5mV/DIV
V
OUT
0.5V/DIV
AC-COUPLED
1V/DIV
PRE-BIASED V
= 2.5V
OUT
4623 G16
4623 G18
4623 G17
V
V
= 12V
20µs/DIV
V
V
= 12V
= 5V
500ns/DIV
= 2.5V
V
V
= 12V
= 5V
500ns/DIV
IN
OUT
IN
OUT
IN
OUT
FREQ = 1MHz
= 1.5V
FREQ = 1MHz
FREQ = 1MHz
PRE-BIASED V
INPUT CAPACITOR = 1 × 22µF CERAMIC CAP
OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP
INPUT CAPACITOR = 1 × 22µF CERAMIC CAP
OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP
OUT
INPUT CAPACITOR = 1 × 22µF CERAMIC CAP
OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP
4623fc
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For more information www.linear.com/LTM4623
LTM4623
pin FuncTions
PACKAGE ROW AND COLUMN LABELING MAY VARY
SGND (B4): Signal Ground Connection. Tie to GND with
minimum distance. Connect FREQ resistor, COMP com-
ponent, MODE, TRACK/SS component, FB resistor to this
pin as needed.
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
COMP(A1):CurrentControlThresholdandErrorAmplifier
CompensationPoint.Thecurrentcomparator’stripthresh-
old is linearly proportional to this voltage, whose normal
range is from 0.3V to 1.8V. Tie the COMP pins together for
parallel operation. The device is internally compensated.
This is an output pin. Do not force a voltage on this pin.
V
(C1, D1-D2, E1-E2): Power Output Pins. Apply out-
OUT
put load between these pins and GND pins. Recommend
placing output decoupling capacitance directly between
these pins and GND pins.
PGOOD (C2): Output Power Good with Open-Drain Logic.
PGOOD is pulled to ground when the voltage on the FB pin
is not within 10% of the internal 0.6V reference.
TRACK/SS (A2): Output Tracking and Soft-Start Input.
Allows the user to control the rise time of the output volt-
age. Putting a voltage below 0.6V on this pin bypasses the
internal reference input to the error amplifier, and servos
the FB pin to match the TRACK/SS voltage. Above 0.6V,
the tracking function stops and the internal reference
resumes control of the error amplifier. There’s an internal
MODE (C4): Operation Mode Select. Tie this pin to INTV
CC
to force continuous synchronous operation at all output
loads. Tying it to SGND enables discontinuous mode
operation at light loads. Do not leave floating.
2µA pull-up current from INTV on this pin, so putting a
capacitor here provides a soft-start function.
CC
SV (C5): Signal V . Input voltage to the on-chip 3.3V
IN
IN
regulator. Tie this pin to the V pin in most applications.
IN
Otherwise connect SV to an external voltage supply of
RUN (A3): Run Control Input of the Switching Mode
Regulator. Enables chip operation by tying RUN above
1.2V. Pulling it below 1.1V shuts down the part. Do not
leave floating.
IN
at least 4V which must also be greater than V
.
OUT
V
(D5, E5): Power Input Pins. Apply input voltage be-
IN
tween these pins and GND pins. Recommend placing
input decoupling capacitance directly between V pins
and GND pins.
FREQ (A4): Frequency is set internally to 1MHz. An ex-
IN
ternal resistor can be placed from this pin to SGND to
increase frequency, or from this pin to INTV to reduce
CC
INTV (E4): Internal 3.3V Regulator Output. The internal
CC
frequency. See the Applications Information section for
power drivers and control circuits are powered from this
voltage. This pin is internally decoupled to GND with a
1µF low ESR ceramic capacitor.
frequency adjustment.
FB(B1):TheNegativeInputoftheErrorAmplifier.Internally,
this pin is connected to V
with a 60.4k precision resis-
OUT
CLKIN (A5): External Synchronization Input to Phase
Detector of the Switching Mode Regulator. This pin is
internally terminated to SGND with 20k. The phase-locked
loop will force the top power NMOS’s turn-on signal to
be synchronized with the rising edge of the CLKIN signal.
tor. Different output voltages can be programmed with an
additional resistor between the FB and SGND pins. Tying
the FB pins together allows for parallel operation. See the
Applications Information section for details.
PHMODE (B2): Control Input to Phase Selector of the
Switching Mode Regulator Channel. This pin determines
the phase relationship between internal oscillator and
CLKOUT (B5): Output Clock Signal for PolyPhase Op-
eration of the Switching Mode Regulator. The phase of
CLKOUT with respect to CLKIN is determined by the state
of the PHMODE pin. CLKOUT’s peak-to-peak amplitude
CLKOUT signal. Tie it to INTV for 2-phase operation, tie
CC
it to SGND for 3-phase operation, and tie it to INTV /2
CC
is INTV to GND. This is an output pin. Do not force a
CC
for 4-phase operation.
voltage on this pin.
GND (B3, C3, D3-D4, E3): Power Ground Pins for Both
Input and Output Returns.
4623fc
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For more information www.linear.com/LTM4623
LTM4623
block DiagraM
V
OUT
60.4k
10k
PGOOD
FB
INTV
CC
R
FB
SV
IN
IN
40.2k
INTV
CC
V
V
IN
1µF
4V TO 20V
C
IN
0.1µF
10µF
CLKIN
CLKOUT
PHMODE
MODE
1µH
V
1.5V
3A
V
OUT
OUT
POWER CONTROL
C
OUT
1µF
GND
47µF
TRACK/SS
RUN
0.1µF
COMP
INTERNAL
COMP
INTERNAL
FILTER
162k
FREQ
SGND
4623 BD
Figure 1. Simplified LTM4623 Block Diagram
Decoupling requireMenTs
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
C
C
External Input Capacitor Requirement
I
= 3A
4.7
10
µF
IN
OUT
(V = 4V to 20V, V
= 1.5V)
IN
OUT
External Output Capacitor Requirement
(V = 4V to 20V, V = 1.5V)
I
= 3A
22
47
µF
OUT
OUT
IN
OUT
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LTM4623
operaTion
TheLTM4623isastandalonenonisolatedswitchmodeDC/
DC power supply. It can deliver up to 3A DC output current
withfewexternalinputandoutputcapacitors.Thismodule
provides precisely regulated output voltage adjustable
between 0.6V to 5.5V via one external resistor over a 4V
to 20V input voltage range. With an external bias supply
comparators pull the open-drain PGOOD output low if the
output feedback voltage exits a 10% window around the
regulationpoint.ContinuousoperationisforcedduringOV
and UV condition except during start-up when the TRACK
pin is ramping up to 0.6V.
Furthermore,inordertoprotecttheinternalpowerMOSFET
devices against transient voltage spikes, the LTM4623
above 4V connected to SV , this module operates with
IN
an input voltage down to 2.375V. The typical application
constantly monitors the V pin for an overvoltage condi-
IN
schematic is shown in Figure 24.
tion. When V rises above 23.5V, the regulator suspends
IN
The LTM4623 contains an integrated constant on-time
valley current mode regulator, power MOSFETs, inductor,
and other supporting discrete components. The default
switchingfrequencyis1MHz.Foroutputvoltagesbetween
3.3Vand5.5V,anexternal162kresistorisrequiredbetween
FREQ and SGND pins to set the operating frequency to
2MHz to optimize inductor current ripple. For switching
noise-sensitive applications, the switching frequency can
beadjustedbyexternalresistorsandtheμModuleregulator
can be externally synchronized to a clock within 30% of
thesetfrequency.SeetheApplicationsInformationsection.
operation by shutting off both power MOSFETs. Once V
IN
drops below 21.5V, the regulator immediately resumes
normal operation. The regulator does not execute its
soft-start function when exiting an overvoltage condition.
Multiphase operation can be easily employed with the
synchronizationandphasemodecontrols.Upto12phases
can be cascaded to run simultaneously with respect to
each other by programming the PHMODE pin to different
levels. The LTM4623 has CLKIN and CLKOUT pins for
PolyPhase operation of multiple devices or frequency
synchronization.
With current mode control and internal feedback loop
compensation, the LTM4623 module has sufficient stabil-
ity margins and good transient performance with a wide
range of output capacitors, even with all ceramic output
capacitors.
Pulling the RUN pin below 1.1V forces the controller into
its shutdown state, turning off both power MOSFETs
and most of the internal control circuitry. At light load
currents, discontinuous mode (DCM) operation can be
enabled to achieve higher efficiency compared to continu-
ous mode (CCM) by pulling the MODE pin to SGND. The
TRACK/SS pin is used for power supply tracking and
soft-start programming. See the Applications Informa-
tion section.
Current mode control provides cycle-by-cycle fast cur-
rent limiting. Foldback current limiting is provided in an
overcurrent condition indicated by a drop in V reducing
FB
inductor valley current to approximately 40% of the origi-
nal value. Internal output overvoltage and undervoltage
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LTM4623
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The typical LTM4623 application circuit is shown in
Figure 24. External component selection is primarily
determined by the input voltage, the output voltage and
the maximum load current. Refer to Table 7 for specific
externalcapacitorrequirementsforaparticularapplication.
For parallel operation of N-channels LTM4623, tie all the
FB pins together and use the following equation to solve
for R :
FB
0.6V
VOUT –0.6V
60.4k
N
RFB =
•
V to V
Step-Down Ratios
IN
OUT
There are restrictions in the maximum V and V
step-
Input Decoupling Capacitors
IN
OUT
down ratios that can be achieved for a given input voltage
due to the minimum off-time and minimum on-time limits
of the regulator. The minimum off-time limit imposes a
maximum duty cycle which can be calculated as:
The LTM4623 module should be connected to a low AC
impedance DC source. For the regulator, a 10µF input
ceramic capacitor is required for RMS ripple current de-
coupling. Bulk input capacitance is only needed when the
inputsourceimpedanceiscompromisedbylonginductive
leads, traces or not enough source capacitance. The bulk
capacitor can be an aluminum electrolytic capacitor or
polymer capacitor.
D
= 1 – (t
• f
)
MAX
OFF(MIN) SW
where t
is the minimum off-time, typically 70ns
OFF(MIN)
for LTM4623, and f (Hz) is the switching frequency.
SW
Converselytheminimumon-timelimitimposesaminimum
duty cycle of the converter which can be calculated as:
Without considering the inductor ripple current, the RMS
current of the input capacitor can be estimated as:
D
MIN
= t
• f
ON(MIN) SW
IOUT(MAX)
where t
is the minimum on-time, typically 40ns
ON(MIN)
ICIN(RMS)
=
• D•(1−D)
for LTM4623. In the rare cases where the minimum duty
cycle is surpassed, the output voltage will still remain
in regulation, but the switching frequency will decrease
from its programmed value. Note that additional thermal
derating may be applied. See the Thermal Considerations
and Output Current Derating section in this data sheet.
η%
whereη%istheestimatedefficiencyofthepowermodule.
Output Decoupling Capacitors
Withanoptimizedhighfrequency, highbandwidthdesign,
only a single low ESR output ceramic capacitor is required
for the LTM4623 to achieve low output ripple voltage and
very good transient response. Additional output filtering
mayberequiredbythesystemdesigneriffurtherreduction
of output ripple or dynamic transient spikes is required.
Table 7 shows a matrix of different output voltages and
output capacitors to minimize the voltage droop and
overshoot during a 1A load-step transient. The Linear
Technology LTpowerCAD™ design tool is available to
download online for output ripple, stability and transient
response analysis for further optimization.
Output Voltage Programming
ThePWMcontrollerhasaninternal0.6Vreferencevoltage.
As shown in the Block Diagram, a 60.4k internal feedback
resistor connects the V
and FB pins together. Adding a
OUT
resistor, R , from FB pin to SGND programs the output
FB
voltage:
0.6V
OUT −0.6V
RFB =
• 60.4k
V
Table 1. RFB Resistor Table vs Various Output Voltages
Discontinuous Current Mode (DCM)
V
(V)
0.6
1.0
1.2
1.5
1.8
2.5
3.3
5.0
OUT
R
(kΩ) OPEN 90.9 60.4 40.2 30.1 19.1 13.3 8.25
FB
Inapplicationswherelowoutputrippleandhighefficiency
at intermediate current are desired, discontinuous current
mode (DCM) should be used by connecting the MODE pin
Pease note that for 3.3V and 5V output, a higher operating frequency
(2MHz) is required to optimize inductor current ripple. See Operating
Frequency section.
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to SGND. At light loads the internal current comparator
may remain tripped for several cycles and force the top
MOSFETtostayoffforseveralcycles,thusskippingcycles.
The inductor current does not reverse in this mode.
The programmable operating frequency range is from
800kHz to 4MHz.
Please note a minimum switching frequency is required
for given V , V
operating conditions to keep a maxi-
IN OUT
mum peak-to-peak inductor ripple current below 2A for
Forced Continuous Current Mode (CCM)
the LTM4623.
In applications where fixed frequency operation is more
critical than low current efficiency, and where the lowest
outputrippleisdesired,forcedcontinuousoperationshould
be used. Forced continuous operation can be enabled by
Thepeak-to-peakinductorripplecurrentcanbecalculated
as:
⎛
⎞
⎟
⎠
VOUT
1
ΔIP-P = VOUT 1−
•
⎜
tyingtheMODEpintoINTV .Inthismode,inductorcurrent
CC
V
fSW(MHz)
⎝
IN
is allowed to reverse during low output loads, the COMP
voltage is in control of the current comparator threshold
throughout,andthetopMOSFETalwaysturnsonwitheach
oscillator pulse. During start-up, forced continuous mode
is disabled and inductor current is prevented from revers-
ing until the LTM4623’s output voltage is in regulation.
The maximum 2A peak-to-peak inductor ripple current
is enforced due to the nature of the valley current mode
control to maintain output voltage regulation at no load.
Frequency Synchronization and Clock In
The power module has a phase-locked loop comprised
of an internal voltage controlled oscillator and a phase
detector.ThisallowstheinternaltopMOSFETturn-ontobe
lockedtotherisingedgeoftheexternalclock. Theexternal
clock frequency range must be within 30% around the
set operating frequency. A pulse detection circuit is used
to detect a clock on the CLKIN pin to turn on the phase-
locked loop. The pulse width of the clock has to be at least
100ns. The clock high level must be above 2V and clock
low level below 0.3V. During the start-up of the regulator,
the phase-locked loop function is disabled.
Operating Frequency
The operating frequency of the LTM4623 is optimized to
achieve the compact package size and the minimum out-
put ripple voltage while still keeping high efficiency. The
default operating frequency is internally set to 1MHz. In
most applications, no additional frequency adjusting is
required.
If any operating frequency other than 1MHz is required
by application, the operating frequency can be increased
by adding a resistor, RFSET, between the FREQ pin and
SGND, as shown in Figure 28. The operating frequency
can be calculated as:
Multiphase Operation
For output loads that demand more than 3A of current,
multiple LTM4623s can be paralleled to run out of phase
to provide more output current without increasing input
and output voltage ripples.
1.6e11
162k ||RFSET(Ω)
f(Hz)=
To reduce switching current ripple, 2MHz operating fre-
quencyisrequiredfor3.3Vto5.5VoutputwithR
to SGND.
=162k
The CLKOUT signal can be connected to the CLKIN pin of
thefollowingLTM4623stagetolineupboththefrequency
and the phase of the entire system. Tying the PHMODE pin
FSET
The operating frequency can also be decreased by adding
aresistorbetweentheFREQpinandINTV ,calculatedas:
to INTVCC, SGND or INTV /2 generates a phase differ-
CC
CC
ence (between CLKIN and CLKOUT) of 180°, 120°, or 90°
respectively, which corresponds to 2-phase, 3-phase or
4-phase operation. A total of 12 phases can be cascaded
2.8e11
RFSET(Ω)
f(Hz)= 1MHz −
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LTM4623
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0
90
180
270
+90
+90
+90
CLKIN CLKOUT
CLKIN CLKOUT
CLKIN CLKOUT
CLKIN CLKOUT
INTV /2
INTV /2
CC
INTV /2
CC
INTV /2
CC
PHMODE
PHASE 1
PHMODE
PHASE 2
PHMODE
PHASE 3
PHMODE
PHASE 4
CC
(420)
60
0
120
240
180
300
+120
+120
+180
+120
+120
CLKIN CLKOUT
CLKIN CLKOUT
CLKIN CLKOUT
CLKIN CLKOUT
CLKIN CLKOUT
CLKIN CLKOUT
PHMODE
PHASE 1
PHMODE
PHASE 3
INTV
PHMODE
PHASE 5
PHMODE
PHASE 2
PHMODE
PHASE 4
INTV
PHMODE
PHASE 6
CC
CC
4623 F02
Figure 2. 4-Phase, 6-Phase Operation
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
1 PHASE
2 PHASE
3 PHASE
4 PHASE
6 PHASE
0
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY FACTOR (V /V
)
OUT IN
4623 F03
Figure 3. RMS Input Ripple Current to DC Load Current Ratio as a Function of Duty Cycle
to run simultaneously out-of-phase with respect to each
other by programming the PHMODE pin of each LTM4623
to different levels. Figure 2 shows a 4-phase design and
a 6-phase design example for clock phasing.
A multiphase power supply significantly reduces the
amount of ripple current in both the input and output ca-
pacitors. The RMS input ripple current is reduced by, and
the effective ripple frequency is multiplied by, the number
of phases used (assuming that the input voltage is greater
thanthenumberofphasesusedtimestheoutputvoltage).
Theoutputrippleamplitudeisalsoreducedbythenumber
of phases used when all of the outputs are tied together
to achieve a single high output current design.
Table 2. PHMODE Pin Status and Corresponding Phase
Relationship (Relate to CLKIN)
PHASMD
INTV
SGND
INTV /2
CC
CC
CLKOUT
180°
120°
90°
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The LTM4623 device is an inherently current mode con-
trolled device, so parallel modules will have very good
current sharing. This will balance the thermals on the
design. Please tie the RUN, TRACK/SS, FB and COMP pins
of each paralleling module together. Figure 26 shows an
example of parallel operation and pin connection.
rate of the output voltage. An internal 2µA current source
will charge up the external soft-start capacitor towards
INTV voltage. When the TRACK/SS voltage is below
CC
0.6V, it will take over the internal 0.6V reference voltage
to control the output voltage. The total soft-start time can
be calculated as:
CSS
2µA
Input RMS Ripple Current Cancellation
t
SS = 0.6 •
Application Note 77 provides a detailed explanation of
multiphase operation. The input RMS ripple current can-
cellation mathematical derivations are presented, and a
graph is displayed representing the RMS ripple current
reductionasafunctionofthenumberofinterleavedphases.
Figure 3 shows this graph.
where C is the capacitance on the TRACK/SS pin. Cur-
rent foldback and forced continuous mode are disabled
during the soft-start process.
SS
Outputvoltagetrackingcanalsobeprogrammedexternally
using the TRACK/SS pin. The output can be tracked up
and down with another regulator. Figure 4 and Figure 5
show an example waveform and schematic of ratiometric
tracking where the slave regulator’s output slew rate is
proportional to the master’s.
Soft-Start And Output Voltage Tracking
The TRACK/SS pin provides a means to either soft start
the regulator or track it to a different power supply. A
capacitor on the TRACK/SS pin will program the ramp
MASTER OUTPUT
SLAVE OUTPUT
TIME
4623 F04
Figure 4. Output Ratiometric Tracking Waveform
V
IN
4V TO 15V
CLKIN FREQ CLKOUT
CLKIN FREQ CLKOUT
V
1.5V
3A
V
1.2V
3A
OUT(MA)
OUT(SL)
V
V
V
IN
V
IN
OUT
OUT
10µF
16V
47µF
6.3V
10µF
16V
47µF
6.3V
SV
SV
IN
IN
RUN LTM4623
INTV
RUN LTM4623
INTV
CC
CC
R
TR(TOP)
60.4k
MODE
MODE
TRACK/SS
PGOOD
FB
COMP
SGND
TRACK/SS
PGOOD
FB
COMP
SGND
R
TR(BOT)
C
SS
R
R
FB(SL)
60.4k
FB(MA)
40.2k
GND
GND
40.2k
4623 F05
Figure 5. Example Schematic of Ratiometric Output Voltage Tracking
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Since the slave regulator’s TRACK/SS is connected to
The TRACK/SS pin will have the 2µA current source on
when a resistive divider is used to implement tracking
on the slave regulator. This will impose an offset on the
TRACK/SSpininput.Smallervalueresistorswiththesame
ratios as the resistor values calculated from the above
equation can be used. For example, where the 60.4k is
used then a 6.04k can be used to reduce the TRACK/SS
pin offset to a negligible value.
the master’s output through a R
/R
resistor
TR(TOP) TR(BOT)
divider and its voltage used to regulate the slave output
voltage when TRACK/SS voltage is below 0.6V, the slave
outputvoltageandthemasteroutputvoltageshouldsatisfy
the following equation during start-up:
RFB(SL)
VOUT(SL)
•
=
R
FB(SL) +60.4k
RTR(BOT)
TR(TOP) +RTR(BOT)
The coincident output tracking can be recognized as a
special ratiometric output tracking in which the master’s
output slew rate (MR) is the same as the slave’s output
slew rate (SR), waveform as shown in Figure 6.
VOUT(MA)
•
R
The R
TR(BOT)
is the feedback resistor and the R
/
TR(TOP)
From the equation, we could easily find that, in coincident
tracking,theslaveregulator’sTRACK/SSpinresistordivider
is always the same as its feedback divider:
FB(SL)
R
is the resistor divider on the TRACK/SS pin of
the slave regulator, as shown in Figure 5.
Following the previous equation, the ratio of the master’s
output slew rate (MR) to the slave’s output slew rate (SR)
is determined by:
RFB(SL)
FB(SL) +60.4k
RTR(BOT)
=
R
R
TR(TOP) +RTR(BOT)
For example, R
= 60.4k and R
= 60.4k is a
TR(TOP)
TR(BOT)
RFB(SL)
good combination for coincident tracking for a V
OUT(MA)
R
FB(SL) +60.4k
= 1.5V and V
= 1.2V application.
MR
SR
OUT(SL)
=
RTR(BOT)
Power Good
R
TR(TOP) +RTR(BOT)
The PGOOD pin is an open-drain pin that can be used to
monitor valid output voltage regulation. This pin is pulled
low when the output voltage exceeds a 10% window
around the regulation point. To prevent unwanted PGOOD
Forexample,V
=1.5V,MR=1.5V/1msandV
OUT(SL)
OUT(MA)
= 1.2V, SR = 1.2V/1ms. From the equation, we could solve
that R = 60.4k and R = 40.2k are a good
TR(TOP)
TR(BOT)
glitches during transients or dynamic V
changes, the
combination for the ratiometric tracking.
OUT
LTM4623’s PGOOD falling edge includes a blanking delay
of approximately 52 switching cycles.
MASTER OUTPUT
Stability Compensation
TheLTM4623’sinternalcompensationloopisdesignedand
optimizedforusewithlowESRceramicoutputcapacitors.
Table 7 is provided for most application requirements. In
case more phase margin is required for the application,
SLAVE OUTPUT
an additional 100pF feedforward capacitor (C ) can be
FF
placed between the V
and FB pins. The LTpowerCAD
OUT
design tool is available for control loop optimization.
TIME
4623 F06
Figure 6. Output Coincident Tracking Waveform
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RUN Enable
Overtemperature Protection
Pulling the RUN pin to ground forces the LTM4623 into
its shutdown state, turning off both power MOSFETs and
most of its internal control circuitry. Bringing the RUN pin
above 0.7V turns on the internal reference only, while still
keeping the power MOSFETs off. Increasing the RUN pin
voltage above 1.2V will turn on the entire chip.
The internal overtemperature protection monitors the
junction temperature of the module. If the junction
temperature reaches approximately 160°C, both power
switches will be turned off until the temperature drops
about 15°C cooler.
Radiated EMI Noise
Low Input Application
High radiated EMI noise is a disadvantage for switching
regulators by nature. Fast switching turn-on and turn-off
make the large di/dt change in the converters, which act
as the radiation sources in most systems. LTM4623 in-
tegrates the feature to minimize the radiated EMI noise to
meet the most applications with low noise requirements.
It is fully compliant with the EN55022 Class B Standard.
TheLTM4623modulehasaseparateSVIN pinwhichmakes
itsuitableforlowinputvoltageapplicationsdownto2.375V.
TheSVIN pinisthesingleinputofthewholecontrolcircuitry
while the VIN pin is the power input which directly connects
to the drain of the top MOSFET. In most applications where
VIN is greater than 4V, connect SVIN directly to VIN with a
short trace. An optional filter, consisting of a resistor (1Ω
to 10Ω) between SVIN and VIN along with a 0.1µF bypass
capacitor between SVIN and ground, can be placed for
additional noise immunity. This filter is not necessary in
most cases if good PCB layout practices are followed (see
Figure 23). In a low input voltage application (2.375V to
4V), connect SVIN to an external voltage higher than 4V
with 1µF local bypass capacitor. See Operating Frequency
section. Figure 25 shows an example of a low input voltage
application. Please note the SVIN voltage cannot go below
the VOUT voltage.
Thermal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those param-
eters defined by JESD 51-12 and are intended for use with
finite element analysis (FEA) software modeling tools that
leverage the outcome of thermal modeling, simulation,
and correlation to hardware evaluation performed on a
µModule package mounted to a hardware test board.
The motivation for providing these thermal coefficients is
found in JESD 51-12 (Guidelines for Reporting and Using
Electronic Package Thermal Information).
Pre-Biased Output Start-Up
Many designers may opt to use laboratory equipment
and a test vehicle such as the demo board to anticipate
the µModule regulator’s thermal performance in their ap-
plicationatvariouselectricalandenvironmentaloperating
conditions to compliment any FEA activities. Without FEA
software, the thermal resistances reported in the Pin Con-
figurationsectionare,inandofthemselves,notrelevantto
providing guidance of thermal performance; instead, the
derating curves provided in this data sheet can be used
in a manner that yields insight and guidance pertaining to
one’s application usage, and can be adapted to correlate
thermal performance to one’s own application.
There may be situations that require the power supply to
start up with a pre-bias on the output capacitors. In this
case, it is desirable to start up without discharging that
output pre-bias. The LTM4623 can safely power up into
a pre-biased output without discharging it.
TheLTM4623accomplishesthisbyforcingdiscontinuous
mode (DCM) operation until the TRACK/SS pin voltage
reaches 0.6V reference voltage. This will prevent the BG
from turning on during the pre-biased output start-up
which would discharge the output.
Please do not pre-bias LTM4623 with a voltage higher
than INTVCC (3.3V) voltage or a voltage higher than the
output voltage set by the feedback resistor (RFB).
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The Pin Configuration section gives four thermal coeffi-
cients explicitly defined in JESD 51-12; these coefficients
are quoted or paraphrased next:
4. θ , the thermal resistance from junction to the printed
JB
circuitboard,isthejunction-to-boardthermalresistance
where almost all of the heat flows through the bottom
oftheµModulepackageandintotheboard, andisreally
1. θ , the thermal resistance from junction to ambient, is
JA
the sum of the θ
and the thermal resistance of
JCbottom
the natural convection junction-to-ambient air thermal
resistance measured in a one cubic foot sealed enclo-
sure. This environment is sometimes referred to as
“still air” although natural convection causes the air to
move. This value is determined with the part mounted
to a 95mm × 76mm PCB with four layers.
the bottom of the part through the solder joints and
through a portion of the board. The board temperature
is measured a specified distance from the package.
A graphical representation of the aforementioned ther-
mal resistances is given in Figure 7; blue resistances are
contained within the μModule regulator, whereas green
resistances are external to the µModule package.
2. θ
, the thermal resistance from junction to the
JCbottom
bottom of the product case, is determined with all of
the component power dissipation flowing through the
bottomofthepackage.InthetypicalµModuleregulator,
the bulk of the heat flows out the bottom of the pack-
age, but there is always heat flow out into the ambient
environment. As a result, this thermal resistance value
may be useful for comparing packages, but the test
conditionsdon’tgenerallymatchtheuser’sapplication.
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD 51-12 or provided in the
Pin Configuration section replicates or conveys normal
operating conditions of a μModule regulator. For example,
in normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bot-
tom of the µModule package—as the standard defines
3. θ
, the thermal resistance from junction to top of
JCtop
the product case, is determined with nearly all of the
componentpowerdissipationflowingthroughthetopof
the package. As the electrical connections of the typical
µModule regulator are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
for θ
and θ , respectively. In practice, power
JCbottom
JCtop
loss is thermally dissipated in both directions away from
the package—granted, in the absence of a heat sink and
airflow, a majority of the heat flow is into the board.
Within the LTM4623 be aware there are multiple power
devices and components dissipating power, with a con-
sequence that the thermal resistances relative to different
junctions of components or die are not exactly linear with
As in the case of θ
, this value may be useful
JCbottom
for comparing packages but the test conditions don’t
generally match the user’s application.
JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS
JUNCTION-TO-CASE (TOP)
RESISTANCE
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION
AMBIENT
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
CASE (BOTTOM)-TO-BOARD
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
4623 F07
µMODULE DEVICE
Figure 7. Graphical Representation of JESD 51-12 Thermal Coefficients
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respect to total package power loss. To reconcile this
complicationwithoutsacrificingmodelingsimplicity—but
also,notignoringpracticalrealities—anapproachhasbeen
taken using FEA software modeling along with laboratory
testing in a controlled environment chamber to reason-
ably define and correlate the thermal resistance values
supplied in this data sheet: (1) Initially, FEA software is
used to accurately build the mechanical geometry of the
LTM4623 and the specified PCB with all of the correct
materialcoefficientsalongwithaccuratepowerlosssource
definitions; (2) this model simulates a software-defined
JEDECenvironmentconsistentwithJESD51-12topredict
powerlossheatflowandtemperaturereadingsatdifferent
interfacesthatenablethecalculationoftheJEDEC-defined
thermalresistance values; (3)themodeland FEA software
isusedtoevaluatetheLTM4623withheatsinkandairflow;
(4)havingsolvedforandanalyzedthesethermalresistance
values and simulated various operating conditions in the
softwaremodel,athoroughlaboratoryevaluationreplicates
the simulated conditions with thermocouples within a
controlledenvironmentchamberwhileoperatingthedevice
at the same power loss as that which was simulated. An
outcome of this process and due diligence yields the set
of derating curves shown in this data sheet. After these
laboratory tests have been performed and correlated to
then the load current is lowered to maintain the junction at
120°C while increasing ambient temperature up to 120°C.
The derating curves are plotted with the output current
starting at 3A and the ambient temperature at 30°C. The
output voltages are 1.0V, 1.5V, 3.3V and 5V. These are
chosen to include the lower and higher output voltage
ranges for correlating the thermal resistance. Thermal
models are derived from several temperature measure-
ments in a controlled temperature chamber along with
thermal modeling analysis. The junction temperatures are
monitored while ambient temperature is increased with
and without airflow. The power loss increase with ambient
temperature change is factored into the derating curves.
The junctions are maintained at 120°C maximum while
lowering output current or power with increasing ambient
temperature.Thedecreasedoutputcurrentwilldecreasethe
internal module loss as ambient temperature is increased.
The monitored junction temperature of 120°C minus the
ambientoperatingtemperaturespecifieshowmuchmodule
temperature rise can be allowed. As an example, in Figure
16 the load current is derated to 2.5A at ~95°C with no air
flow or heat sink and the power loss for the 12V to 1.5V
at 2.5A output is about 1.0W. The 1.0W loss is calculated
with the ~0.8W room temperature loss from the 12V to
1.5V power loss curve at 2.5A in Figure 9, and the 1.3
multiplying factor at 120°C junction temperature. If the
95°C ambient temperature is subtracted from the 120°C
junction temperature, then the difference of 25°C divided
the LTM4623 model, then the θ and θ are summed
JB
BA
together to provide a value that should closely equal the
θ
value because approximately 100% of power loss
JA
flows from the junction through the board into ambient
with no airflow or top mounted heat sink.
by 1.0W equals a 25°C/W θ thermal resistance. Table 4
JA
specifies a 25°C/W value which is very close. Table 3 to
Table 6 provide equivalent thermal resistances for 1.0V to
5V outputs with and without airflow. The derived thermal
resistances in Table 3 to Table 6 for the various condi-
tions can be multiplied by the calculated power loss as
a function of ambient temperature to derive temperature
rise above ambient, thus maximum junction temperature.
Room temperature power loss can be derived from the ef-
ficiencycurvesintheTypicalPerformanceCharacteristics
section and adjusted with the above ambient temperature
multiplicativefactors.Theprintedcircuitboardisa1.6mm
thick4-layerboardwithtwoouncecopperforthetwoouter
layers and one ounce copper for the two inner layers. The
PCB dimensions are 95mm × 76mm.
The 1.0V, 1.5V, 3.3V and 5V loss curves in Figures 8 to 11
can be used in coordination with the load current derating
curves in Figures 12 to 22 for calculating an approximate
θ
thermal resistance for the LTM4623 with various air-
JA
flow conditions. The power loss curves are taken at room
temperature, andareincreasedwithamultiplicativefactor
according to the ambient temperature. This approximate
factor is: 1.3 for 120°C at junction temperature. Maximum
load current is achievable while increasing ambient tem-
perature as long as the junction temperature is less than
120°C, whichisa5°Cguardbandfrommaximumjunction
temperature of 125°C. When the ambient temperature
reaches a point where the junction temperature is 120°C,
4623fc
17
For more information www.linear.com/LTM4623
LTM4623
applicaTions inForMaTion
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
IN
V
IN
V
IN
= 16V
= 12V
= 5V
V
IN
V
IN
V
IN
= 16V
= 12V
= 5V
V
IN
V
IN
V
IN
= 16V
= 12V
= 5V
2
3
0
1
2
3
0
1
2
3
0
1
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
4623 F08
4623 F09
4623 F10
Figure 8. 1.0V Output Power Loss
Figure 9. 1.5V Output Power Loss
Figure 10. 3.3V Output Power Loss
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
3.5
3
3.5
3
V
IN
V
IN
= 16V
= 12V
2.5
2
2.5
2
1.5
1
1.5
1
0LFM
200LFM
400LFM
0LFM
200LFM
400LFM
0.5
0
0.5
0
2
3
100 110
130
100 110
130
120
0
1
30 40 50 60 70 80 90
120
30 40 50 60 70 80 90
LOAD CURRENT (A)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4623 F11
4623 F12
4623 F13
Figure 11. 5V Output Power Loss
Figure 12. 5V to 1V Derating Curve,
No Heat Sink
Figure 13. 12V to 1V Derating Curve,
No Heat Sink
3.5
3
3.5
3
3.5
3
2.5
2
2.5
2
2.5
2
1.5
1
1.5
1
1.5
1
0LFM
0LFM
0LFM
200LFM
400LFM
200LFM
400LFM
200LFM
400LFM
0.5
0
0.5
0
0.5
0
100 110
130
100 110
130
100 110
130
120
30 40 50 60 70 80 90
120
30 40 50 60 70 80 90
120
30 40 50 60 70 80 90
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4623 F14
4623 F15
4623 F16
Figure 14. 16V to 1V Derating Curve,
No Heat Sink
Figure 15. 5V to 1.5V Derating Curve,
No Heat Sink
Figure 16. 12V to 1.5V Derating Curve,
No Heat Sink
4623fc
18
For more information www.linear.com/LTM4623
LTM4623
applicaTions inForMaTion
3.5
3.5
3.5
3
3
3
2.5
2
2.5
2
2.5
2
1.5
1
1.5
1
1.5
1
0LFM
0LFM
0LFM
200LFM
400LFM
200LFM
400LFM
200LFM
400LFM
0.5
0
0.5
0
0.5
0
100 110
130
120
30 40 50 60 70 80 90
100 110
130
120
30 40 50 60 70 80 90
100 110 120
30 40 50 60 70 80 90
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4623 F17
4623 F18
4623 F25
Figure 17. 16V to 1.5V Derating Curve,
No Heat Sink
Figure 18. 5V to 3.3V Derating Curve,
No Heat Sink
Figure 19. 12V to 3.3V Derating Curve,
No Heat Sink
3.5
3
3.5
3
3.5
3
2.5
2
2.5
2
2.5
2
1.5
1
1.5
1
1.5
1
0LFM
0LFM
0LFM
200LFM
400LFM
200LFM
400LFM
200LFM
400LFM
0.5
0
0.5
0
0.5
0
100 110 120
100 110 120
100 110 120
30 40 50 60 70 80 90
30 40 50 60 70 80 90
30 40 50 60 70 80 90
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4623 F26
4623 F27
4623 F28
Figure 20. 16V to 3.3V Derating Curve,
No Heat Sink
Figure 21. 12V to 5V Derating Curve,
No Heat Sink
Figure 22. 16V to 5V Derating Curve,
No Heat Sink
Table 3. 1.0V Output, No Heat Sink
DERATING CURVE
Figures 12, 13, 14
Figures 12, 13, 14
Figures 12, 13, 14
V
(V)
POWER LOSS CURVE
Figure 8
AIR FLOW (LFM)
HEAT SINK
None
θ
IN
JA(°C/W)
5, 12, 16
5, 12, 16
5, 12, 16
0
25
Figure 8
200
400
None
22
22
Figure 8
None
Table 4. 1.5V Output, No Heat Sink
DERATING CURVE
Figures 15, 16, 17
Figures 15, 16, 17
Figures 15, 16, 17
V
(V)
POWER LOSS CURVE
Figure 9
AIR FLOW (LFM)
HEAT SINK
None
θ
IN
JA(°C/W)
5, 12, 16
5, 12, 16
5, 12, 16
0
25
Figure 9
200
400
None
22
22
Figure 9
None
4623fc
19
For more information www.linear.com/LTM4623
LTM4623
applicaTions inForMaTion
Table 5. 3.3V Output, No Heat Sink
DERATING CURVE
Figures 18, 19, 20
Figures 18, 19, 20
Figures 18, 19, 20
V
(V)
POWER LOSS CURVE
Figure 10
AIR FLOW (LFM)
HEAT SINK
None
θ
θ
IN
JA(°C/W)
5, 12, 16
5, 12, 16
5, 12, 16
0
25
Figure 10
200
400
None
22
22
Figure 10
None
Table 6. 5V Output, No Heat Sink
DERATING CURVE
Figures 21, 22
Figures 21, 22
Figures 21, 22
V
IN
(V)
POWER LOSS CURVE
Figure 11
AIR FLOW (LFM)
HEAT SINK
None
JA(°C/W)
12, 16
12, 16
12, 16
0
25
Figure 11
200
400
None
22
22
Figure 11
None
Table 7. Output Voltage Response vs Component Matrix (Refer to Figure 24)
C
PART NUMBER
VALUE
C
PART NUMBER
VALUE
IN
OUT1
Murata
GRM21BR61E106KA73L
TMK212BBJ106KG-T
GRM31CR61C226ME15L
TMK316BBJ226ML-T
10µF, 25V, 0805, X5R
10µF, 25V, 0805, X5R
22µF, 25V, 1206, X5R
22µF, 25V, 1206, X5R
Murata
GRM21BR60J476ME15
JMK212BJ476MG-T
47µF, 6.3V, 0805, X5R
47µF, 6.3V, 0805, X5R
Taiyo Yuden
Murata
Taiyo Yuden
Taiyo Yuden
C
C
LOAD STEP
IN
OUT1
V
(CERAMIC) (CERAMIC)
C
V
DROOP P-P DERIVATION RECOVERY
LOAD
SLEW RATE
(A/µs)
R
FB
FREQ
(MHz)
OUT
FF
IN
(V)
(µF)
10
10
10
10
10
10
10
(µF)
47
47
47
47
47
47
47
(pF)
100
100
100
100
100
100
100
(V)
(mV)
(mV)
59
TIME (µs) STEP (A)
(kΩ)
90.9
60.4
40.2
30.1
19.1
13.3
8.25k
1
5, 12
5, 12
5, 12
5, 12
5, 12
5, 12
12
1
1
1
1
2
3
5
40
40
40
40
50
60
60
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1.2
1.5
1.8
2.5
3.3
5
59
66
75
108
111
156
Safety Considerations
The LTM4623 modules do not provide galvanic isolation
from V to V . There is no internal fuse. If required,
a slow blow fuse with a rating twice the maximum input
current needs to be provided to protect each unit from
catastrophic failure. The device does support thermal
shutdown and overcurrent protection.
• Use large PCB copper areas for high current paths,
including V , GND and V . It helps to minimize the
IN
OUT
PCB conduction loss and thermal stress.
IN
OUT
• Place high frequency ceramic input and output capaci-
tors next to the V , PGND and V
pins to minimize
IN
OUT
high frequency noise.
• Placeadedicatedpowergroundlayerunderneaththeunit.
Layout Checklist/Example
• Tominimizetheviaconductionlossandreducemodule
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
The high integration of LTM4623 makes the PCB board
layoutverysimpleandeasy.However,tooptimizeitselectri-
cal and thermal performance, some layout considerations
are still necessary.
• Do not put via directly on the pad, unless they are
capped or plated over.
4623fc
20
For more information www.linear.com/LTM4623
LTM4623
applicaTions inForMaTion
• Use a separated SGND ground copper area for com-
ponents connected to signal pins. Connect the SGND
to GND underneath the unit.
• Bring out test points on the signal pins for monitoring.
Figure23givesagoodexampleoftherecommendedlayout.
GND
V
IN
V
OUT
C
GND
C
OUT
IN
4623 F19
Figure 23. Recommended PCB Layout
1.31MΩ
FREQ CLKIN CLKOUT
V
FREQ CLKIN CLKOUT
V
1.5V
3A
V
1V
3A
OUT
OUT
V
IN
V
IN
V
OUT
V
OUT
IN
V
IN
4V TO 20V
2.375V TO 4V
10µF
25V
47µF
4V
47µF
4V
SV
IN
5V
SV
IN
10µF
6.3V
1µF
6.3V
RUN
INTV
RUN
INTV
LTM4623
LTM4623
CC
CC
MODE
MODE
PHMODE
TRACK/SS
PGOOD
GND
PHMODE
TRACK/SS
PGOOD
FB
COMP
FB
90.9k
0.1µF
0.1µF
COMP
40.2k
SGND
GND
SGND
4623 F20
4623 F21
Figure 24. 4VIN to 20VIN, 1.5V Output at 3A Design
Figure 25. 2.375VIN to 4VIN, 1V Output at 3A Design
with 800kHz Reduced Frequency
4623fc
21
For more information www.linear.com/LTM4623
LTM4623
applicaTions inForMaTion
FREQ CLKIN CLKOUT
V
V
1.5V
6A
OUT
V
IN
V
OUT
IN
4V TO 20V
10µF
25V
×2
SV
IN
47µF
RUN
INTV
LTM4623
4V
×2
CC
MODE
PHMODE
FB
TRACK/SS
COMP
0.1µF
PGOOD
GND
SGND
FREQ CLKIN CLKOUT
V
V
OUT
IN
SV
IN
RUN
INTV
LTM4623
CC
MODE
PHMODE
FB
TRACK/SS
COMP
PGOOD
GND
20.1k
SGND
4623 F22
Figure 26. 4VIN to 20VIN, Two Phases, 1.5V at 6A Design
4623fc
22
For more information www.linear.com/LTM4623
LTM4623
applicaTions inForMaTion
FREQ CLKIN CLKOUT
V
V
1.5V
3A
OUT
V
IN
V
OUT
IN
4V TO 20V
10µF
25V
×2
47µF
4V
SV
IN
RUN
INTV
LTM4623
CC
MODE
PHMODE
TRACK/SS
PGOOD
FB
40.2k
COMP
0.1µF
GND
SGND
FREQ CLKIN CLKOUT
V
V
1.2V
3A
OUT2
V
OUT
IN
47µF
4V
SV
IN
RUN
INTV
LTM4623
CC
MODE
60.4k
PHMODE
TRACK/SS
PGOOD
GND
FB
60.4k
COMP
60.4k
SGND
4623 F23
Figure 27. 4VIN to 20VIN, 1.2V and 1.5V with Coincident Tracking
2MHz
CLOCK
162k
FREQ CLKIN CLKOUT
V
V
3.3V
3A
OUT
V
IN
V
OUT
IN
5V TO 20V
10µF
25V
47µF
6.3V
SV
IN
RUN
INTV
LTM4623
CC
MODE
PHMODE
TRACK/SS
PGOOD
GND
FB
0.1µF
COMP
13.3k
SGND
4623 F24
Figure 28. 5VIN to 20VIN, 3.3V Output with 2MHz External Clock
4623fc
23
For more information www.linear.com/LTM4623
LTM4623
package DescripTion
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
LTM4623 Component LGA and BGA Pinout
PIN ID
A1
FUNCTION
COMP
FB
PIN ID
A2
FUNCTION
TRACK/SS
PHMODE
PGOOD
PIN ID
A3
FUNCTION
RUN
PIN ID
A4
FUNCTION
FREQ
PIN ID
A5
FUNCTION
CLKIN
B1
B2
B3
GND
B4
SGND
B5
CLKOUT
C1
V
OUT
V
OUT
V
OUT
C2
C3
GND
C4
MODE
GND
C5
SV
IN
D1
D2
V
OUT
V
OUT
D3
GND
D4
D5
V
IN
V
IN
E1
E2
E3
GND
E4
INTV
E5
CC
4623fc
24
For more information www.linear.com/LTM4623
LTM4623
package DescripTion
Please refer to http://www.linear.com/product/LTM4623#packaging for the most recent package drawings.
Z
/ / b b b Z
2 . 5 4 0
1 . 2 7 0
0 . 3 1 7 5
0 . 0 0 0
0 . 3 1 7
1 . 2 7 0
2 . 5 4 0
4623fc
25
For more information www.linear.com/LTM4623
LTM4623
package DescripTion
Please refer to http://www.linear.com/product/LTM4623#packaging for the most recent package drawings.
Z
/ / b b b Z
2 . 5 4 0
1 . 2 7 0
0 . 3 1 7 5
0 . 0 0 0
0 . 3 1 7
1 . 2 7 0
2 . 5 4 0
4623fc
26
For more information www.linear.com/LTM4623
LTM4623
revision hisTory
REV
DATE
DESCRIPTION
PAGE NUMBER
10, 22
A
7/15
Corrected R
in the Operating Frequency section from 161k to 162k
FSET
B
10/15 Added BGA package
1, 2, 26
C
06/16 Updated Absolute Maximum Rating section. Peak body temperature from 245°C to 260°C
Added the description about minimum switching frequency in the Operating Frequency section
2
11
23
Changed minimum V voltage in Figure 28 from 4V to 5V
IN
4623fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTM4623
package phoTos
Design resources
SUBJECT
DESCRIPTION
µModule Design and Manufacturing Resources
Design:
Manufacturing:
• Selector Guides
• Quick Start Guide
• Demo Boards and Gerber Files
• Free Simulation Tools
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
2. Search using the Quick Power Search parametric table.
TechClip Videos
Quick videos detailing how to bench test electrical and thermal performance of µModule products.
Digital Power System Management
Linear Technology’s family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
relaTeD parTs
PART NUMBER DESCRIPTION
COMMENTS
LTM4625
Higher Current than LTM4623, BGA Package, Taller 5A, 4V < V < 20V
IN MAX
but Same Footprint
Dual 4A
LTM4619
LTM4644
LTM4649
LTM8020
4.5V < V < 28V
, 15mm × 15mm × 2.82mm LGA
IN
MAX
Quad 4A
Configurable up to 16A, 4V < V < 16V
, 9mm × 15mm × 5.01mm BGA
IN
MAX
10A
4.5V < V < 18V
, 9mm × 15mm × 4.92mm
IN
MAX
200mA, Higher V than LTM4625, Same Package 4V < V < 40V , 6.25mm × 6.25mm × 2.32mm LGA
MAX
IN
IN
Footprint
4623fc
LT 0616 REV C • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTM4623
●
●
LINEAR TECHNOLOGY CORPORATION 2014
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