LTP5902IPC-IPMA#PBF_技术文档

LTP5901-IPM/LTP5902-IPM

SmartMesh IP Node 2.4GHz

802.15.4e Wireless Mote Module

neTwork FeaTures

DescripTion

n

Complete Radio Transceiver, Embedded Processor,

and Networking Software for Forming a Self-Healing

Mesh Network

SmartMesh IP™ wireless sensor networks are self man-

aging, low power Internet Protocol (IP) networks built

from wireless nodes called motes. The LTP™5901-IPM/

LTP5902-IPMistheIPmoteproductintheEterna^®*family

ofIEEE802.15.4eprintedcircuitboardassemblysolutions,

featuring a highly-integrated, low power radio design by

Dust Networks^®as well as an ARM Cortex-M3 32-bit

microprocessor running Dust’s embedded SmartMesh IP

networking software. Both the LTP5901-IPM (with chip

antenna), at 24mm × 42mm, and the LTP5902-IPM (with

MMCX connector), at 24mm × 37mm, are designed for

surface mount assembly.

SmartMesh^®Networks Incorporate:

n

Time Synchronized Network-Wide Scheduling

n

Per Transmission Frequency Hopping

n

Redundant Spatially Diverse Topologies

n

Network-Wide Reliability and Power Optimization

n

NIST Certified Security

n

SmartMesh Networks Deliver:

n

>99.999% Network Reliability Achieved in the

Most Challenging RF Environments

Sub 50µA Routing Nodes

n

With Dust’s time-synchronized SmartMesh IP networks,

all motes in the network may route, source or terminate

data, while providing many years of battery powered

operation. The SmartMesh IP software provided with the

LTP5901-IPM/LTP5902-IPM is fully tested and validated,

and is readily configured via a software Application Pro-

gramming Interface.

n

Compliant to 6LoWPAN Internet Protocol (IP) and

IEEE 802.15.4e Standards

lTp5901-ipM/lTp5902-ipM

FeaTures

n

Industry-Leading Low Power Radio Technology with

SmartMesh IP motes deliver a highly flexible network

with proven reliability and low power performance in an

easy-to-integrate platform.

4.5mA to Receive and 9.7mA to Transmit at 8dBm

n

RF Modular Certification Include USA, Canada, EU,

Japan, Taiwan, Korea, India, Australia and New Zealand

n

L, LT, LTC, LTM, Linear Technology, the Linear logo, Dust, Dust Networks, SmartMesh and

Eterna are registered trademarks and LTP, the Dust Networks logo and SmartMesh IP are

trademarks of Linear Technology Corporation. All other trademarks are the property of their

respective owners. Protected by U.S. Patents, including 7375594, 7420980, 7529217, 7791419,

7881239, 7898322, 8222965.

PCB Assembly with Chip Antenna (LTP5901-IPM) or

with MMCX Antenna Connector (LTP5902-IPM). QFN

Version (LTC^®5800-IPM) Available

* Eterna is Dust Networks’ low power radio SoC architecture.

n

Micrium µCOS-II Real Time Operating System Based

On-Chip Software Development Kit

Typical applicaTion

LTP5901-IPM

LTP5901-IPR/

LTP5902-IPR

ANTENNA

IN+

UART

LTC2379-18 SPI

UART

SENSOR

µCONTROLLER

IN–

HOST

APPLICATION

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LTP5901-IPM/LTP5902-IPM

Table oF conTenTs

Network Features .......................................... 1

LTP5901-IPM/LTP5902-IPM Features ................... 1

Typical Application ........................................ 1

Description.................................................. 1

Table of Contents .......................................... 2

SmartMesh Network Overview........................... 3

Absolute Maximum Ratings.............................. 4

Pin Configuration .......................................... 4

Order Information.......................................... 5

Recommended Operating Conditions................... 5

DC Characteristics......................................... 5

Radio Specifications ...................................... 6

Radio Receiver Characteristics.......................... 6

Radio Transmitter Characteristics....................... 7

Digital I/O Characteristics ................................ 7

Temperature Sensor Characteristics.................... 8

Analog Input Chain Characteristics ..................... 8

System Characteristics ................................... 8

UART AC Characteristics.................................. 9

TIMEn AC Characteristics................................10

Radio_Inhibit AC Characteristics.......................10

Flash AC Characteristics.................................11

Flash SPI Slave AC Characteristics ....................11

SPI Master AC Characteristics..........................12

Operation...................................................24

Power Supply..........................................................24

Supply Monitoring and Reset .................................25

Precision Timing.....................................................25

Application Time Synchronization ..........................25

Time References.....................................................25

Radio ......................................................................26

UARTs.....................................................................26

Autonomous MAC...................................................27

Security ..................................................................27

Temperature Sensor ...............................................27

RADIO INHIBIT .......................................................27

Software Installation...............................................27

Flash Data Retention...............................................28

State Diagram.........................................................28

2

I C Master ..............................................................30

SPI Master..............................................................30

1-Wire Master.........................................................30

Applications Information ................................31

Modes of Operation ................................................31

Regulatory and Standards Compliance...................31

Soldering Information.............................................32

Related Documentation..................................32

Package Description .....................................33

Revision History ..........................................35

Typical Application .......................................36

Related Parts..............................................36

2

I C AC Characteristics....................................13

1-Wire Master.............................................13

Flash SPI Slave AC Characteristics ....................14

Typical Performance Characteristics ..................15

Pin Functions..............................................20

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LTP5901-IPM/LTP5902-IPM

sMarTMesh neTwork overview

ASmartMeshnetworkconsistsofaself-formingmulti-hop

mesh of nodes, known as motes, which collect and relay

data, and a network manager that monitors and manages

network performance and security, and exchanges data

with a host application.

The Network Manager uses health reports to continually

optimizethenetworktomaintain>99.999%datareliability

even in the most challenging RF environments.

The use of TSCH allows SmartMesh devices to sleep in

between scheduled communications and draw very little

power in this state. Motes are only active in time slots

where they are scheduled to transmit or receive, typically

resulting in a duty cycle of < 1%. The optimization soft-

ware in the Network Manager coordinates this schedule

automatically. When combined with the Eterna low power

radio, every mote in a SmartMesh network—even busy

routing ones—can run on batteries for years. By default,

all motes in a network are capable of routing traffic from

other motes, which simplifies installation by avoiding the

complexity of having distinct routers vs non-routing end

nodes. Motesmaybeconfiguredasnon-routingtofurther

reduce that particular mote’s power consumption and to

support a wide variety of network topologies.

SmartMesh networks communicate using a time slotted

channel hopping (TSCH) link layer, pioneered by Dust

Networks. In a TSCH network, all motes in the network

are synchronized to within less than a millisecond. Time

in the network is organized into time slots, which enables

collision-free packet exchange and per-transmission

channel-hopping. In a SmartMesh network, every device

has one or more parents (e.g. mote 3 has motes 1 and

2 as parents) that provide redundant paths to overcome

communicationsinterruptionduetointerference,physical

obstruction or multi-path fading. If a packet transmission

fails on one path, the next retransmission may try on a

different path and different RF channel.

A network begins to form when the network manager

instructs its on-board Access Point (AP) radio to begin

sendingadvertisements—packetsthatcontaininformation

that enables a device to synchronize to the network and

request to join. This message exchange is part of the secu-

rityhandshakethatestablishesencryptedcommunications

betweenthemanagerorapplication,andmote.Oncemotes

have joined the network, they maintain synchronization

through time corrections when a packet is acknowledged.

ALL NODES ARE ROUTERS.

THEY CAN TRANSMIT AND RECEIVE.

THIS NEW NODE CAN JOIN

ANYWHERE BECAUSE ALL

NODES CAN ROUTE.

HOST

APPLICATION

SNO 02

At the heart of SmartMesh motes and network manag-

ers is the Eterna IEEE 802.15.4e System-on-Chip (SoC),

featuring Dust Networks’ highly integrated, low power

radio design, plus an ARM Cortex-M3 32-bit micropro-

cessor running SmartMesh networking software. The

SmartMesh networking software comes fully compiled

yet is configurable via a rich set of Application Program-

ming Interfaces (APIs) which allows a host application

to interact with the network, e.g. to transfer information

to a device, to configure data publishing rates on one or

more motes, or to monitor network state or performance

metrics. Data publishing can be uniform or different for

each device, with motes being able to publish infrequently

NETWORK MANAGER

AP

Mote

1

Mote

2

Mote

3

SNO 01

An ongoing discovery process ensures that the network

continually discovers new paths as the RF conditions

change. In addition, each mote in the network tracks per-

formance statistics (e.g. quality of used paths, and lists of

potential paths) and periodically sends that information

to the network manager in packets called health reports.

or faster than once per second as needed.

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LTP5901-IPM/LTP5902-IPM

absoluTe MaxiMuM raTings

pin conFiguraTion

(Note 1)

Pin functions shown in italics are currently not supported in software.

Supply Voltage on VSUPPLY..................................4.20V

Input Voltage on AI_0/1/2/3 Inputs........................1.98V

Voltage on Any Digital

GND

RESERVED

NC

GPIO17

GPIO18

GPIO19

AI_2

1

2

3

4

5

6

7

8

9

66 GND

65 NC

64 RADIO_INHIBIT / GPIO15

63 TIMEn / GPIO1

62 UART_TX

61 UART_TX_CTSn

60 UART_TX_RTSn

59 UART_RX

58 UART_RX_CTSn

57 UART_RX_RTSn

56 GND

I/O pin.................................... –0.3V to VSUPPLY + 0.3V

Input RF Level.................................................... +10dBm

Storage Temperature Range (Note 3)..... –55°C to 105°C

Operating Temperature Range

AI_1

AI_3

AI_0 10

GND 11

RESERVED 12

NC 13

LTP5901I/LPT5902I.............................–40°C to 85°C

55 VSUPPLY

54 RESERVED

NC 14

53 NC

RESETn 15

52 NC

CAUTION: This part is sensitive to electrostatic discharge

(ESD). It is very important that proper ESD precautions be

observedwhenhandlingtheLTP5901-IPM/LTP5902-IPM.

TDI 16

TDO 17

TMS 18

TCK 19

51 FLASH_P_ENn / GPIO2

50 SPIS_SSn / SDA

49

48 SPIS_MOSI / GPIO26 / UARTC1_RX

47 SPIS_MISO / 1_WIRE / UARTC1_TX

46 PWM0 / GPIO16

45 DP1 (GPIO20) / TIMER16_IN

44 SPIM_SS_0n / GPIO12

43 SPIM_SS_1n / GPIO13

42 GND

41 SPIM_SCK / GPIO9

40 SPIM_MOSI / GPIO10

39 IPCS_SSn / GPIO3

38 SPIM_MISO / GPIO11

37 GND

SPIS_SCK / SCL

GND 20

DP4 (GPIO23) 21

RESERVED 22

RESERVED 23

RESERVED 24

DP3 (GPIO22) / TIMER8_IN 25

DP2 (GPIO21) / LPTIMER_IN 26

SLEEPn / GPIO14 27

DP0 (GPIO0) / SPIM_SS_2n 28

NC 29

GND 30

PC PACKAGE

66-LEAD PCB

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LTP5901-IPM/LTP5902-IPM

orDer inForMaTion

LEAD FREE FINISH†

PART MARKING*

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTP5901IPC-IPMA#PBF

LTP5902IPC-IPMA#PBF

LTP5901IPC-IPMA#PBF

LTP5902IPC-IPMA#PBF

–40°C to 85°C

66-Lead (42mm × 24mm × 5.5mm) PCB with Chip Antenna

66-Lead (37.5mm × 24mm × 5.5mm) PCB with MMCX Connector –40°C to 85°C

†This product ships with the flash erased at the time of order. OEMs will need to program devices during development and manufacturing.

For legacy part numbers and ordering information go to: http://www.linear.com/product/LTP5901-IPM#orderinfo or

http://www.linear.com/product/LTP5902-IPM#orderinfo

*The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

recoMMenDeD operaTing conDiTions ^Thel denotes the specifications which apply over

the full operating temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

3.76

250

90

UNITS

V

l

VSUPPLY

Supply Voltage

Including Noise and Load Regulation

50Hz to 2MHz

2.1

Supply Noise

mV

Operating Relative Humidity

Temperature Ramp Rate

Non-Condensing

10

–8

% RH

°C/min

While Operating in Network

+8

Dc characTerisTics ^Thel denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted.

OPERATION/STATE

CONDITIONS

MIN

TYP

MAX

UNITS

Power-on Reset

During Power-On Reset, Maximum 750µs + VSUPPLY Rise Time

from 1V to 1.9V

12

mA

Doze

RAM on, ARM Cortex-M3, Flash, Radio, and Peripherals Off, All

Data and State Retained, 32.768kHz Reference Active

1.2

0.8

20

µA

Deep Sleep

RAM on, ARM Cortex-M3, Flash, Radio, and Peripherals Off, All

Data and State Retained, 32.768kHz Reference Inactive

In-Circuit Programming

RESETn and FLASH_P_ENn Asserted, IPCS_SCK at 8MHz

mA

Peak Operating Current

+8dBm

System Operating at 14.7MHz, Radio Transmitting, During Flash

Write. Maximum Duration 4.33 ms.

30

26

mA

+0dBm

Active

ARM Cortex M3, RAM and Flash Operating, Radio and All Other

Peripherals Off. Clock Frequency of CPU and Peripherals Set to

7.3728MHz, VCORE = 1.2V

1.3

mA

Flash Write

Flash Erase

Single Bank Flash Write

3.7

2.5

mA

Single Bank Page or Mass Erase

Radio Tx

+0dBm

+8dBm

Current with Autonomous MAC Managing Radio Operation,

CPU Inactive. Clock Frequency of CPU and Peripherals Set to

7.3728MHz.

5.4

9.7

mA

Radio Rx

Current with Autonomous MAC Managing Radio Operation,

CPU Inactive. Clock Frequency of CPU and Peripherals Set to

7.3728MHz.

4.5

mA

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LTP5901-IPM/LTP5902-IPM

raDio speciFicaTions ^Thel denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

Frequency Band

2.4000

2.4835

GHz

Number of Channels

Channel Separation

Channel Center Frequency

Modulation

15

5

MHz

Where k = 11 to 25, as Defined by IEEE 802.15.4

2405 + 5•(k-11)

IEEE 802.15.4 Direct Sequence Spread Spectrum (DSSS)

l

Raw Data Rate

250

kbps

V

Antenna Pin ESD Protection

HBM per JEDEC JESD22-A114F (Note 2)

6000

Range (Note 4)

Indoor

25°C, 50% RH, +2dBi Omni-Directional Antenna, Antenna 2m

Above Ground

100

300

1200

m

Outdoor

Free Space

raDio receiver characTerisTics ^Thel denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted.

PARAMETER

CONDITIONS

MIN

TYP

–93

–95

0

MAX

UNITS

dBm

Receiver Sensitivity

Saturation

Packet Error Rate (PER) = 1% (Note 5)

PER = 50%

Maximum Input Level the Receiver Will

Properly Receive Packets

Adjacent Channel Rejection (High Side) Desired Signal at –82dBm, Adjacent Modulated Channel 5MHz

Above the Desired Signal, PER = 1% (Note 5)

22

19

40

36

42

–6

dBc

Adjacent Channel Rejection (Low Side) Desired Signal at –82dBm, Adjacent Modulated Channel 5MHz

Below the Desired Signal, PER = 1% (Note 5)

Alternate Channel Rejection

(High Side)

Desired Signal at –82dBm, Alternate Modulated Channel 10MHz

Above the Desired Signal, PER = 1% (Note 5)

Alternate Channel Rejection (Low Side) Desired Signal at –82dBm, Alternate Modulated Channel 10MHz

Below the Desired Signal, PER = 1% (Note 5)

Second Alternate Channel Rejection

Desired Signal at –82dBm, Second Alternate Modulated Channel

Either 15MHz Above or Below, PER = 1% (Note 5)

Co-Channel Rejection

Desired Signal at –82dBm, Undesired Signal is an 802.15.4

Modulated Signal at the Same Frequency, PER = 1%

LO Feed Through

–55

50

dBm

ppm

dBm

Frequency Error Tolerance (Note 6)

Symbol Error Tolerance

50

Received Signal Strength Indicator

(RSSI) Input Range

–90 to –10

RSSI Accuracy

6

1

dB

RSSI Resolution

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LTP5901-IPM/LTP5902-IPM

raDio TransMiTTer characTerisTics ^Thel denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Output Power

Delivered to a 50Ω load

High Calibrated Setting

8

0

dBm

Low Calibrated Setting

Spurious Emissions

Conducted Measurement with a 50Ω Single-Ended Load,

+8dBm Output Power. All Measurements Made with Max

Hold.

30MHz to 1000MHz

R

BW

R

BW

R

BW

R

BW

R

BW

= 120kHz, V = 100Hz

<–70

–45

–37

–49

–45

dBm

dBc

BW

1GHz to 12.75GHz

= 1MHz, V = 3MHz

BW

2.4GHz ISM Upper Band Edge (Peak)

2.4GHz ISM Upper Band Edge (Average)

2.4GHz ISM Lower Band Edge

= 1MHz, V = 3MHz

BW

= 1MHz, V = 10Hz

BW

= 100kHz, V = 100kHz

BW

Harmonic Emissions

2nd Harmonic

Conducted Measurement Delivered to a 50Ω Load,

Resolution Bandwidth = 1MHz, Video Bandwidth = 1MHz

–50

–45

dBm

3rd Harmonic

DigiTal i/o characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS (Note 7)

MIN

TYP

MAX

UNITS

l

V

Low Level Input Voltage

High Level Input Voltage

–0.3

0.6

V

IL

(Note 8)

VSUPPLY

– 0.3

VSUPPLY

+ 0.3

IH

l

V

Low Level Output Voltage

Type 1, I

= 1.2mA

0.4

V

OL

OH

OL(MAX)

Type 2, Low Drive, I

= 2.2mA

= 4.5mA

OL(MAX)

Type 2, High Drive, I

OL(MAX)

V

High Level Output Voltage

Type 1, I

= –0.8mA

VSUPPLY

– 0.3

VSUPPLY

+ 0.3

OH(MAX)

l

Type 2, Low Drive, I

= –1.6mA

= –3.2mA

VSUPPLY

– 0.3

VSUPPLY

+ 0.3

V

OH(MAX)

Type 2, High Drive, I

VSUPPLY

– 0.3

VSUPPLY

+ 0.3

OH(MAX)

Input Leakage Current

Input Driven to VSUPPLY or GND

50

nA

Pull-Up/Pull-Down Resistance

kΩ

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LTP5901-IPM/LTP5902-IPM

TeMperaTure sensor characTerisTics ^Thel denotes the specifications which apply over

the full operating temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted.

PARAMETER

Offset

CONDITIONS

MIN

TYP

MAX

UNITS

°C

Temperature Offset Error at 25°C

0.25

0.033

Slope Error

°C/°C

analog inpuT chain characTerisTics ^Thel denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Variable Gain Amplifier

Gain

1

8

2

Gain Error

%

Offset-Digital to Analog Converter (DAC)

Full-Scale

1.80

4

V

Bits

mV

Resolution

DNL

Differential Non-Linearity

2.7

Analog to Digital Converter (ADC)

Full-Scale, Signal

Resolution

1.80

1.8

V

mV

LSB

µs

Offset

Mid-Scale

1.4

12

1

DNL

INL

Differential Non-Linearity

Integral Non-Linearity

Settling Time

Conversion Time

Current Consumption

1

10kΩ Source Impedance

10

20

µs

40

µA

Analog Inputs (Note 9)

Load

20

1

pF

kΩ

Series Input Resistance

sysTeM characTerisTics ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

5

MAX

UNITS

µs

Doze to Active State Transition

Doze to Radio Tx or Rx

1.2

4

ms

Q

Charge to Sample RF Channel RSSI

Charge Consumed Starting from Doze State

and Completing an RSSI Measurement

µC

CCA

l

Largest Atomic Charge Operation

RESETn Pulse Width

Total Capacitance

Flash Erase, 21ms Max Duration

200

µC

µs

µF

µH

MAX

125

Note 13

6

3

Total Inductance

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LTP5901-IPM/LTP5902-IPM

uarT ac characTerisTics ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)

SYMBOL

PARAMETER

Permitted R Baud Rate Error

CONDITIONS

MIN

TYP

MAX

UNITS

l

Both Application Programming

Interface (API) and Command Line

Interface (CLI) UARTs

–2

2

%

X

l

Generated T Baud Rate Error

Both API and CLI UARTs

–1

0

1

2

%

X

t

Assertion of UART_RX_RTSn to Assertion

of UART_RX_CTSn, or Negation of UART_

RX_RTSn to Negation of UART_RX_CTSn

ms

RX_RTS to RX_CTS

l

t

Assertion of UART_RX_CTSn to Start of

Byte

0

2

0

20

22

ms

RX_CTS to RX

End of Packet (End of the Last Stop Bit) to

Negation of UART_RX_RTSn

EOP to RX_RTS

Assertion of UART_TX_RTSn to Assertion

of UART_TX_CTSn

ms

BEG_TX_RTS to TX_CTS

END_TX_CTS to TX_RTS

TX_CTS to TX

Negation of UART_TX_CTSn to Negation

of UART_TX_RTSn

Bit Period

l

Assertion of UART_TX_CTSn to Start of

Byte

2

1

End of Packet (End of the Last Stop Bit) to

Negation of UART_TX_RTSn

EOP to TX_RTS

l

t

Receive Inter-Byte Delay

Receive Inter-Packet Delay

Transmit Inter-Packet Delay

100

ms

RX_INTERBYTE

RX_INTERPACKET

TX_INTERPACKET

TX to TX_CTS

20

1

Bit Period

ns

Start of Byte to Negation of

UART_TX_CTSn

0

t

EOP TO RX_RTS

UART_RX_RTSn

t

RX_RTS TO RX_CTS

t

RX_RTS TO RX_CTS

UART_RX_CTSn

UART_RX

t

RX_INTERBYTE

BYTE 1

t

RX_CTS TO RX

BYTE 0

t

EOP TO TX_RTS

UART_TX_RTSn

UART_TX_CTSn

UART_TX

t

END_TX_CTS TO TX_RTS

BEG_TX_RTS TO TX_CTS

t

END_TX_RTS TO TX_CTS

t

TX TO TX_CTS

t

TX_CTS TO TX

BYTE 0

BYTE 1

59012ipm F01

Figure 1. API UART Timing

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LTP5901-IPM/LTP5902-IPM

TiMeꢀ ac characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)

SYMBOL

PARAMETER

CONDITIONS

MIN

125

0

TYP

MAX

UNITS

µs

l

t

TIMEn Signal Strobe Width

STROBE

Delay from Rising Edge of TIMEn to the Start

of Time Packet on API UART

100

ms

RESPONSE

l

t

Delay from End of Time Packet on API UART

to Falling Edge of Subsequent TIMEn

0

ns

TIME_HOLD

l

Timestamp Resolution (Note 10)

1

5

µs

Network-Wide Time Accuracy (Note 11)

t

STROBE

t

TIME_HOLD

TIMEn

t

RESPONSE

UART_TX

TIME INDICATION PAYLOAD

59012ipm F02

Figure 2. Timestamp Timing

raDio_inhibiT ac characTerisTics ^Thel denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

t

Delay from Rising Edge of

20

ms

RADIO_OFF

RADIO_INHIBIT to Radio Disabled

t

Maximum RADIO_INHIBIT Strobe Width

2

s

RADIO_INHIBIT_STROBE

t

RADIO_INHIBIT_STROBE

RADIO_INHIBIT

t

RADIO_OFF

RADIO STATE

ACTIVE/OFF

OFF

ACTIVE/OFF

59012ipm F03

Figure 3. RADIO_INHIBIT Timing

59012ipmfa

10

For more information www.linear.com/LTP5901-IPM or www.linear.com/LTP5902-IPM

LTP5901-IPM/LTP5902-IPM

Flash ac characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

21

UNITS

µs

l

t

Time to Write a 32-Bit Word (Note 12)

Time to Erase a 2kB Page (Note 12)

Time to Erase 256kB Flash Bank (Note 12)

Data Retention

WRITE

21

ms

PAGE_ERASE

MASS_ERASE

21

ms

25°C

85°C

105°C

100

20

8

Years

Flash spi slave ac characTerisTics ^Thel denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

t

Setup from Assertion of FLASH_P_ENn to

Assertion of RESETn

0

ns

FP_EN_to_RESET

Delay from the Assertion RESETn to the

First Falling Edge of IPCS_SSn

125

10

µs

FP_ENTER

Delay from the Completion of the Last

Flash SPI Slave Transaction to the

Negation of RESETn and FLASH_P_ENn

FP_EXIT

l

t

IPCS_SSn Setup to the Leading Edge of

IPCS_SCK

15

ns

SSS

IPCS_SSn Hold from Trailing Edge of

IPCS_SCK

SSH

l

t

IPCS_SCK Period

300

15

5

ns

CK

IPCS_MOSI Data Setup

IPCS_MOSI Data Hold

IPCS_MISO Data Valid

DIS

DIH

DOV

OFF

–5

0

30

IPCS_MISO Data Tri-State from Trailing

Edge of IPCS_SSn

t

FP_EN_TO_RESET

FLASH_P_ENn

RESETn

t

FP_EXIT

FP_ENTER

t

SSH

SSS

IPCS_SSn

IPCS_SCK

t

CK

t

DIS

t

DIH

IPCS_MOSI

59012ipm F04

Figure 4. Flash Programming Interface Timing

59012ipmfa

11

For more information www.linear.com/LTP5901-IPM or www.linear.com/LTP5902-IPM

LTP5901-IPM/LTP5902-IPM

spi MasTer ac characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

t

SPIM_SSXn Setup to the Leading Edge of

SPIM_SCK

t

ns

SSS

CK-30

t

SPIM_SSXn Hold from Trailing Edge of

SPIM_SCK

ns

SSH

CK-30

l

t

SPIM_SCK Period

268

30

5

ns

CK

SPIM_MOSI Data Setup

SPIM_MOSI Data Hold

SPIM_MISO Data Valid

DIS

DIH

DOV

OFF

–5

0

30

SPIM_MISO Data Tri-State from Trailing

Edge of SPIM_SSXn

t

SSS

SSH

SPIM_SSXn

SPIM_SCK

t

CK

CPOL = 0

CPOL = 1

t

DIS

t

DIH

SPIM_MISO

SPIM_MOSI

t

OFF

DOV

59012ipm F05

Figure 5. SPI Master Timing - CPHA = 0

t

SSS

SSH

SPIM_SSXn

SPIM_SCK

t

CK

CPOL = 0

CPOL = 1

t

DIS

t

DIH

SPIM_MISO

SPIM_MOSI

t

OFF

DOV

59012ipm F06

Figure 6. SPI Master Timing - CPHA = 1

59012ipmfa

12

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LTP5901-IPM/LTP5902-IPM

i²c ac characTerisTics ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

f

t

SCL Frequency

184kHz Operation

92kHz Operation

184.3

92.2

188

94

kHz

SCL

Start Hold Time (SCL from SDA)

Setup Time for a Repeated Start

Data Hold Time

184kHz Operation

92kHz Operation

1

2

µs

HD_STA

SU_STA

HD_DAT

SU_DAT

SU_STO

184kHz Operation, 750ns SCL Rise Time

92kHz Operation, 1.5µs SCL Rise Time

300

600

ns

184kHz Operation

92kHz Operation

1

2

µs

Data Setup Time

184kHz Operation

92kHz Operation

1

2

µs

Setup Time for Stop Condition

184kHz Operation

92kHz Operation

1

2

µs

t

SU_STA

t

HD_STA

SDA

SCL

t

HD_DAT

SU_DAT

HD_DAT

t

59012ipm F07

Figure 7. I²C Master Timing

1-wire MasTer ^Thel denotes the specifications which apply over the full operating temperature range, otherwise

specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)

SYMBOL

PARAMETER

CONDITIONS

MIN

527

60.1

82

TYP

556

69.4

86.8

69

MAX

584

79

UNITS

µs

l

t

Reset Low

RSTL

Presence Sample

µs

PS

1_WIRE Data Bit Period

1_WIRE Write Data 0 Low Width

1_WIRE Write Data 1 Low Width

1_WIRE Read Data Low Width

Read Sample from 1_WIRE Low

92

µs

BIT_PERIOD

LOW0

LOW1

LOWR

RS

65

82

µs

8.2

8.7

9.2

15.0

µs

8.2

8.7

µs

13.2

14.6

µs

59012ipmfa

13

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Flash spi slave ac characTerisTics

t

PS

RSTL

1-WIRE

t

BIT_PERIOD

t

LOW1

t

LOW0

t

RS

1-WIRE

t

59012ipm F08

LOWR

Figure 8. 1-Wire Master Timing

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 6: IEEE Std. 802.15.4-2006 requires transmitters to maintain a

frequency tolerance of better than 40 ppm.

Note 7: Per-pin I/O types are provided in the Pin Functions section.

Note 8: VIH maximum voltage input must respect the VSUPPLY maximum

Note 2: ESD (electrostatic discharge) sensitive device. ESD protection

devices are used extensively internal to Eterna. However, high electrostatic

discharge can damage or degrade the device. Use proper ESD handling

precautions.

Note 3: Extended storage at high temperature is discouraged, as this

negatively affects the data retention of Eterna’s calibration data. See the

FLASH Data Retention section for details.

voltage specification.

Note 9: The analog inputs to the ADC can be modeled as a series resistor

to a capacitor. At a minimum the entire circuit, including the source

impedance for the signal driving the analog input should be designed

to settle to within ¼ LSB within the sampling window to match the

performance of the ADC.

Note 10: See the SmartMesh IP Mote API Guide for the time indication

Note 4: Actual RF range is subject to a number of installation-specific

variables including, but not restricted to ambient temperature, relative

humidity, presence of active interference sources, line-of-sight obstacles,

and near-presence of objects (for example, trees, walls, signage, and so

on) that may induce multipath fading. As a result, range varies.

notification definition.

Note 11: Network time accuracy is a statistical measure and varies over

the temperature range, reporting rate and the location of the device

relative to the manager in the network. See the Typical Performance

Characteristics section for a more detailed description.

Note 5: As Specified by IEEE Std. 802.15.4-2006: Wireless Medium

Access Control (MAC) and Physical Layer (PHY) Specifications for Low-

Rate Wireless Personal Area Networks (LR-WPANs) http://standards.ieee.

org/findstds/standard/802.15.4-2011.html.

Note 12: Code execution from flash banks being written or erased is

suspended until completion of the flash operation.

Note 13: Guaranteed by design. Not production tested.

59012ipmfa

14

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LTP5901-IPM/LTP5902-IPM

Typical perForMance characTerisTics

Networkmotestypicallyroutethroughatleasttwoparents

the traffic destined for the manager. The supply current

graphs shown in Figure 9 include a parameter called de-

scendants. In these graphs the term descendants is short

for traffic-weighted descendants and refers to an amount

of activity equivalent to the number of descendants if all

of the network traffic directed to the mote in question.

Generally the number of descendants of a parent is more,

typically 2x or more, than the number of traffic-weighted

descendants. For example, with reference to Figure 10.

Network Graph mote P1 has 0.75 traffic-weighted de-

scendants. To obtain this value notice that mote D1 routes

half its packets through mote P1 adding 0.5 to the traffic-

weighted descendant value; the other half of D1’s traffic is

routed through its other parent, P2. Mote D2 routes half

its packets through mote D1 (the other half going through

parent P3), which we know routes half its packets to mote

P1,addinganother0.25tothetraffic-weighteddescendant

value for a total traffic-weighted descendant value of 0.75.

was performed with the 1-hop mote inside a temperature

chamber. Timing errors due to temperature changes and

temperature differences both between the manager and

this mote and between this mote and its descendents

thereforepropagateddownthroughthenetwork. Thesyn-

chronizationofthe3-hopand5-hopmotestothemanager

was then affected by the temperature ramps even though

they were at room temperature. For 2°C/minute testing

the temperature chamber was cycled between –40°C and

85°C at this rate for 24 hours. For 8°C/minute testing, the

temperaturechamberwasrapidlycycledbetween85°Cand

45°C for 8 hours, followed by rapid cycling between –5°C

and 45°C for 8 hours, and lastly, rapid cycling between

–40°C and 15°C for 8 hours.

MANAGER

P1

As described in the Application Time Synchronization

section, Eternaprovidestwomechanismsforapplications

to maintain a time base across a network. The synchro-

nization performance plots that follow were generated

using the more precise TIMEn input. Publishing rate is

the rate a mote application sends upstream data. Syn-

chronization improves as the publishing rate increases.

Baseline synchronization performance is provided for a

network operating with a publishing rate of zero. Actual

performance for applications in network will improve

as publishing rates increase. All synchronization testing

P2

1 HOP

P3

2 HOP

D1

3 HOP

D2

58012ipm F10

Figure 10. Example Network Graph

4.0

2 DESCENDANTS 5sec REPORTING

5 DESCENDANTS 30sec REPORTING

2 DESCENDANTS 30sec REPORTING

0 DESCENDANTS 5sec REPORTING

0 DESCENDANTS 30sec REPORTING

5 HOPS

4 HOPS

3 HOPS

2 HOPS

1 HOP

140

120

100

80

5 DESCENDANTS

2 DESCENDANTS

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

1 DESCENDANTS

200

0 DESCENDANTS

60

100

40

20

0

90

0

30

–60

–10

40

10

20

0

30

10

20

TEMPERATURE (°C)

REPORTING INTERVAL (sec)

58012ipm F09a

58012ipm F09b

58012ipm F09c

Figure 9

59012ipmfa

15

For more information www.linear.com/LTP5901-IPM or www.linear.com/LTP5902-IPM

LTP5901-IPM/LTP5902-IPM

Typical perForMance characTerisTics

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

1 Hop, Room Temperature

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

3 Hops, Room Temperature

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

5 Hops, Room Temperature

60

50

40

30

20

10

0

30

25

20

15

10

5

14

12

10

8

µ = 0.0

µ = –0.2

σ = 1.7

µ = –0.2

σ = 3.6

σ = 0.9

N = 89700

N = 89699

N = 89698

6

4

2

0

–40

–10

40

–40

–10

40

–40

–10

40

–30 –20

0

10 20 30

–30 –20

SYNCHRONIZATION ERROR (µs)

0

10 20 30

–30 –20

SYNCHRONIZATION ERROR (µs)

0

10 20 30

SYNCHRONIZATION ERROR (µs)

58012ipm G01

58012ipm G02

58012ipm G03

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

1 Hop, 2°C/Min

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

3 Hops, 2°C/Min

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

5 Hops, 2°C/Min

7

6

5

4

3

2

1

0

20

15

10

5

14

12

10

8

µ = 1.0

µ = 1.5

µ = 0.9

σ = 7.7

σ = 3.3

σ = 3.9

N = 93845

N = 93812

N = 93846

6

4

2

0

–40

–10

–40

–10

–40

–10

–30 –20

SYNCHRONIZATION ERROR (µs)

0

10 20 30

–30 –20

SYNCHRONIZATION ERROR (µs)

0

10 20 30

–30 –20

SYNCHRONIZATION ERROR (µs)

0

10 20 30

58012ipm G06

58012ipm G04

58012ipm G05

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

1 Hop, 8°C/Min

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

3 Hops, 8°C/Min

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

5 Hops, 8°C/Min

12

10

8

14

12

10

8

7

6

5

4

3

2

1

0

µ = 3.6

µ = 1.1

µ = 1.0

σ = 5.0

σ = 3.8

σ = 7.4

N = 88144

N = 88179

N = 88178

6

4

2

0

–40

–10

–40

–10

–30 –20

0

10 20 30

–30 –20

0

10 20 30

–40

–10

–30 –20

0

10 20 30

SYNCHRONIZATION ERROR (µs)

58012ipm G07

58012ipm G08

58012ipm G09

59012ipmfa

16

For more information www.linear.com/LTP5901-IPM or www.linear.com/LTP5902-IPM

LTP5901-IPM/LTP5902-IPM

Typical perForMance characTerisTics

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

1 Hop, Room Temperature

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

3 Hops, Room Temperature

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

5 Hops, Room Temperature

60

50

40

30

20

10

0

60

50

40

30

20

10

0

50

40

30

20

10

0

µ = 0.0

µ = –0.2

σ = 1.2

µ = –0.2

σ = 1.2

N = 22753

N = 17008

N = 17007

–40

–10

40

–40

–10

40

–40

–10

40

–30 –20

0

10 20 30

–30 –20

0

10 20 30

–30 –20

0

10 20 30

SYNCHRONIZATION ERROR (µs)

58012ipm G10

58012ipm G11

58012ipm G12

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

1 Hop, 2°C/Min

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

3 Hops, 2°C/Min

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

5 Hops, 2°C/Min

35

30

25

20

15

10

5

45

40

35

30

25

20

15

10

5

35

30

25

20

15

10

5

µ = 0.5

µ = 0.1

σ = 1.9

σ = 1.5

N = 85860

N = 85858

N = 85855

0

–40

–10

–40

–10

–40

–10

–30 –20

SYNCHRONIZATION ERROR (µs)

0

10 20 30

–30 –20

SYNCHRONIZATION ERROR (µs)

0

10 20 30

–30 –20

SYNCHRONIZATION ERROR (µs)

0

10 20 30

58012ipm G13

58012ipm G14

58012ipm G15

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

1 Hop, 8°C/Min

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

3 Hops, 8°C/Min

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

5 Hops, 8°C/Min

60

50

40

30

20

10

0

60

50

40

30

20

10

0

50

40

30

20

10

0

µ = 0.2

µ = 0.0

µ = –1.0

σ = 1.3

N = 33929

σ = 1.4

σ = 1.3

N = 33932

N = 33930

–40

–10

–40

–10

–40

–10

–30 –20

0

10 20 30

–30 –20

0

10 20 30

–30 –20

0

10 20 30

SYNCHRONIZATION ERROR (µs)

58012ipm G16

58012ipm G17

58012ipm G18

59012ipmfa

17

For more information www.linear.com/LTP5901-IPM or www.linear.com/LTP5902-IPM

LTP5901-IPM/LTP5902-IPM

Typical perForMance characTerisTics

As described in the SmartMesh Network Overview sec-

tion, devices in network spend the vast majority of their

time inactive in their lowest power state (doze). On a

synchronous schedule a mote will wake to communicate

with another mote. Regularly occurring sequences which

wake, perform a significant function and return to sleep

are considered atomic. These operations are considered

atomic as the sequence of events can not be separated

into smaller events while performing a useful function.

For example, transmission of a packet over the radio is an

atomicoperation.Atomicoperationsmaybecharacterized

in either charge or energy. In a time slot where a mote

successfully sends a packet, an atomic transmit includes

setuppriortosendingthemessage, sendingthemessage,

receiving the acknowledgment and the post processing

needed as a result of the message being sent. Similarly in

a time slot when a mote successfully receives a packet, an

atomic receive includes setup prior to listening, listening

untilthestartofthepackettransition, receivingthepacket,

sendingtheacknowledgeandthepostprocessingrequired

due to the arrival of the packet.

To ensure reliability each mote in the network is provided

multiple time slots for each packet it nominally will send

and forward. The time slots are assigned to communicate

upstreamwithatleasttwodifferentmotes.Whencombined

with frequency hopping this provides temporal, spacial

and spectral redundancy. Given this approach a mote will

often listen for a message that it will never receive, since

the time slot is not being used by the transmitting mote.

It has already successfully transmitted the packet. Since

typically 3 time slots are scheduled for every 1 packet to

be sent or forwarded, motes will perform more of these

atomic“idlelistens”thanatomictransmitoratomicreceive

sequences. Examples of transmit, receive and idle listen

atomic operations are shown in Figure 11.

59012ipmfa

18

For more information www.linear.com/LTP5901-IPM or www.linear.com/LTP5902-IPM

LTP5901-IPM/LTP5902-IPM

Typical perForMance characTerisTics

Figure 11

59012ipmfa

19

For more information www.linear.com/LTP5901-IPM or www.linear.com/LTP5902-IPM

LTP5901-IPM/LTP5902-IPM

pin FuncTions

Pin functions shown in italics are currently not supported in software.

The following table organizes the pins by functional

groups. For those I/O with multiple functions the alternate

functions are shown on the second and third line in their

respective row. The No column provides the pin number.

The second column lists the function. The Type column

lists the I/O type. The I/O column lists the direction of the

signal relative to Eterna. The Pull column shows which

signals have a fixed passive pull-up or pull-down. The

Description column provides a brief signal description.

NO POWER SUPPLY

GND

TYPE

Power

I/O

-

PULL DESCRIPTION

1

-

Ground Connection

Power Supply Input to Eterna

11 GND

20 GND

30 GND

34 GND

37 GND

42 GND

56 GND

66 GND

55 VSUPPLY

-

NO RADIO

TYPE

I/O

I

PULL DESCRIPTION

64 RADIO_INHIBIT

1 (Note 14)

-

Radio Inhibit

4

5

6

-

GPIO17

GPIO18

GPIO19

ANTENNA

1

I/O

N/A

General Purpose Digital I/O

1

General Purpose Digital I/O

N/A

Chip Antenna (LTP5901) or MMCX Connector (LPT5902)

NO ANALOG

TYPE

I/O

PULL DESCRIPTION

7

8

9

AI_2

AI_1

AI_3

Analog

I

-

Analog Input 2

Analog Input 1

Analog Input 3

Analog Input 0

10 AI_0

NO RESET

TYPE

I/O

PULL DESCRIPTION

15 RESETn

1

I

UP

Reset Input, Active Low

NO JTAG

16 TDI

TYPE

I/O

PULL DESCRIPTION

1

I

O

I

UP

-

JTAG Test Data In

17 TDO

18 TMS

19 TCK

JTAG Test Data Out

JTAG Test Mode Select

UP

I

DOWN JTAG Test Clock

59012ipmfa

20

For more information www.linear.com/LTP5901-IPM or www.linear.com/LTP5902-IPM

LTP5901-IPM/LTP5902-IPM

pin FuncTions

Pin functions shown in italics are currently not supported in software.

NO GPIOs

TYPE

I/O

PULL DESCRIPTION

21 DP4 (GPIO23)

1

I/O

-

General Purpose Digital I/O

25 DP3 (GPIO22)

I/O

I

-

General Purpose Digital I/O

External Input to 8-Bit Timer/Counter

TIMER8_EXT

26 DP2 (GPIO21)

1

I/O

-

General Purpose Digital I/O

LPTIMER_EXT

I

External Input to Low Power Timer/Counter

28 DP0 (GPIO0)

SPIM_SS_2n

I/O

O

-

General Purpose Digital I/O

SPI Master Slave Select 2, Active Low

45 DP1 (GPIO20)

I/O

I

-

General Purpose Digital I/O

External Input to 16-Bit Timer/Counter

TIMER16_EXT

NO SPECIAL PURPOSE

TYPE

1 (Note 14)

2

I/O

PULL DESCRIPTION

27 SLEEPn

I

-

Deep Sleep, Active Low

46 PWM0

TIMER16_OUT

GPIO16

O

I/O

-

Pulse Width Modulator 0

16-Bit Timer/Counter Match Output/PWM Output

General Purpose Digital I/O

63 TIMEn

1 (Note 14)

I

-

Time Capture Request, Active Low

NO CLI

TYPE

I/O

O

PULL DESCRIPTION

31 UARTC0_TX

32 UARTC0_RX

2

1

-

CLI UART 0 Transmit

CLI UART 0 Receive

I

UP

NO SPI MASTER

TYPE

I/O

PULL DESCRIPTION

38 SPIM_MISO

GPIO11

1

I

-

SPI Master (MISO) Master In Slave Out Port

General Purpose Digital I/O

I/O

40 SPIM_MOSI

GPIO10

2

1

O

-

SPI Master (MOSI) Master Out Slave In Port

General Purpose Digital I/O

I/O

41 SPIM_SCK

GPIO9

O

I/O

-

SPI Master (SCK) Serial Clock Port

General Purpose Digital I/O

43 SPIM_SS_1n

GPIO13

O

I/O

-

SPI Master Slave Select 1, Active Low

General Purpose Digital I/O

44 SPIM_SS_0n

GPIO12

O

I/O

-

SPI Master Slave Select 0, Active Low

General Purpose Digital I/O

59012ipmfa

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pin FuncTions

Pin functions shown in italics are currently not supported in software.

NO IPCS SPI/FLASH PROGRAMMING (NOTE 15) TYPE

I/O

PULL DESCRIPTION

33 IPCS_MISO

TIMER16_OUT

GPIO6

2

1

I

-

SPI Flash Emulation (MISO) Master In Slave Out Port

O

16-Bit Timer/Counter Match Output/PWM Output

I/O

General Purpose Digital I/O

35 IPCS_MOSI

TIMER16_EXT

GPIO5

I

-

SPI Flash Emulation (MOSI) Master Out Slave In Port

External Input to 16-Bit Timer/Counter

General Purpose Digital I/O

I/O

36 IPCS_SCK

TIMER8_EXT

GPIO4

I

-

SPI Flash Emulation (SCK) Serial Clock Port

External Input to 8-Bit Timer/Counter

General Purpose Digital I/O

I/O

39 IPCS_SSn

LPTIMER_EXT

GPIO3

I

-

SPI Flash Emulation Slave Select, Active Low

External Input to Low Power Timer/Counter

General Purpose Digital I/O

I/O

51 FLASH_P_ENn

I

UP

Flash Program Enable, Active Low

2

NO I C/1-WIRE/SPI SLAVE

TYPE

I/O

PULL DESCRIPTION

47 SPIS_MISO

UARTC1_TX

1_WIRE

2

O

I/O

-

SPI Slave (MISO) Master In Slave Out Port

CLI UART 1 Transmit

1 Wire Master

48 SPIS_MOSI

UARTC1_RX

GPIO26

1

I

-

SPI Slave (MOSI) Master Out Slave In Port

CLI UART 1 Receive

General Purpose Digital I/O

I/O

49 SPIS_SCK

SCL

2

I

-

SPI Slave (SCK) Serial Clock Port

2

I/O

I C Serial Clock

50 SPIS_SSn

SDA

I

-

SPI Slave Select, Active Low

2

I/O

I C Serial Data

NO API UART

TYPE

I/O

I

PULL DESCRIPTION

57 UART_RX_RTSn

58 UART_RX_CTSn

59 UART_RX

1 (Note 14)

-

UART Receive (RTS) Request to Send, Active Low

1

O

I

UART Receive (CTS) Clear to Send, Active Low

UART Receive

1 (Note 14)

60 UART_TX_RTSn

61 UART_TX_CTSn

62 UART_TX

1

O

I

UART Transmit (RTS) Request to Send, Active Low

UART Transmit (CTS) Clear to Send, Active Low

UART Transmit

1 (Note 14)

2

O

Note 14: These inputs are always enabled and must be driven or pulled to

a valid state to avoid leakage.

Note 15: Embedded programming over the IPCS SPI bus is only avaliable

when RESETn is asserted.

59012ipmfa

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pin FuncTions

VSUPPLY: System and I/O Power Supply. Provides power

to the module. The digital-interface I/O voltages are also

set by this voltage.

UART_RX,UART_RX_RTSn,UART_RX_CTSn,UART_TX,

UART_TX_RTSn,UART_TX_CTSn:TheAPIUARTinterface

includes bidirectional wake up and flow control. Unused

inputsignalsmustbedrivenorpulledtotheirinactivestate.

ANTENNA: Multiplexed Receiver Input and Transmitter

Output Pin. The impedance presented to the MMCX con-

nectorshouldbe50Ω,single-endedwithrespecttoground.

TIMEn: Strobing the TIMEn input is the most accurate

method to acquire the network time maintained by Eterna.

Eterna latches the network time stamp with sub-micro-

second resolution on the rising edge of the TIMEn signal

and produces a packet on the API serial port containing

the timing information.

AI_0, AI_1, AI_2, AI_3: Analog Inputs. These pins are

multiplexed to the analog input chain. The analog input

chain, as shown in Figure 12, is software-configurable

and includes a variable-gain amplifier, an offset-DAC for

adjusting input range, and a 10-bit ADC. Valid input range

is between 0V to 1.8V. Analog inputs can be sampled as

described in section Signal/Data Acquisition and Control.

UARTC0_RX, UARTC0_TX: The CLI UART provides a

mechanism for monitoring, configuration and control of

Eterna during operation. For a complete description of

the supported commands see the SmartMesh IP Mote

CLI Guide.

ANALOG INPUT

GPIO0, GPIO3 to GPIO6, GPIO9 to GPIO13, GPIO16,

GPIO20 to GPIO23, GPIO26: General purpose I/Os that

can be sampled or driven as described in the On-Chip

Software Development Kit (On-Chip SDK).

10-BIT ADC

3-BIT

VGA

+

4-BIT DAC

59012ipm F12

FLASH_P_ENn, IPCS_SSn, IPCS_SCK, IPCS_MISO,

IPCS_SSn: The In-Circuit Programming Control System

(IPCS)busenablesin-circuitprogrammingofEterna’sflash

memory. IPCS_SCK is a clock and should be terminated

appropriately for the driving source to prevent overshoot

and ringing.

Figure 12. Analog Input Chain

RESETn:Theasynchronousresetsignalisinternallypulled

up. Resetting Eterna will result in the ARM Cortex M3

rebooting and loss of network connectivity. Use of this

signal for resetting Eterna is not recommended, except

during power-on and in-circuit programming.

SPIM_CLK, SPIM_MISO, SPIM_MOSI, SPIM_SS_0n,

SPIM_SS_1n, SPIM_SS_4n: The SPI Master bus with

support for up to three SPI slave devices, via the On-Chip

Software Development Kit (On-Chip SDK) provides an

interfacetoSPIperipheralslavedevices. TheSPIinterface

is synchronous to SPIM_CLK, which should be treated as

a clock signal and terminated appropriately .

RADIO_INHIBIT: RADIO_INHIBIT provides a mechanism

foranexternaldevicetotemporarilydisable radiooperation.

Failure to observe the timing requirements defined in the

RADIO_INHIBIT AC Characteristics section, may result

in unreliable network operation. In designs where the

RADIO_INHIBIT function is not needed the input must

either be tied, pulled or actively driven low to avoid excess

leakage.

1-WIRE: The 1-Wire master clock/data/power signal. See

the On-Chip Software Development Kit (On-Chip SDK) for

details on operating the 1-Wire Master controller.

TMS, TCK, TDI, TDO: JTAG Port Supporting Software

Debug and Boundary Scan.

2

SCL, SDA: The I C bus SCL and SDA should be externally

pulled to V

with a 10k resistor. See the On-Chip

SLEEPn: The SLEEPn function is not currently supported

in software. The SLEEPn input must either be tied, pulled

or actively driven high to avoid excess leakage.

SUPPLY

Software Development Kit (On-Chip SDK) for details on

operating the 1-Wire Master controller.

59012ipmfa

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LTP5901-IPM/LTP5902-IPM

operaTion

TheLTP5901-IPM/LTP5902-IPMistheworld’smostenergy

efficient IEEE 802.15.4 compliant platform, enabling bat-

tery and energy harvested applications. With a powerful

32-bit ARM Cortex-M3, best-in-class radio, flash, RAM

and purpose-built peripherals, Eterna provides a flexible,

scalable and robust networking solution for applications

demandingminimalenergyconsumptionanddatareliability

in even the most challenging RF environments.

POWER SUPPLY

Eterna is powered from a single pin, VSUPPLY, which

powers the I/O cells and is also used to generate internal

supplies.Eterna’stwoon-chipDC/DCconvertersminimize

Eterna’senergyconsumptionwhilethedeviceisawake.To

conserve power the DC/DC converters are disabled when

the device is in low power state. Eterna’s power supply

conditioningarchitecture,includingthetwointegratedDC/

DC converters and three integrated low dropout regula-

tors, provides excellent rejection of supply noise. Eterna’s

operating supply voltage range is high enough to support

Shown in Figure 13, Eterna integrates purpose-built

peripherals that excel in both low operating-energy con-

sumption and the ability to rapidly and precisely cycle

between operating and low-power states. Items in the

gray shaded region labeled Analog Core correspond to

the analog/RF components.

direct connection to lithium-thionyl chloride (Li-SOCl )

2

sources and wide enough to support battery operation

over a broad temperature range.

32kHz

DIGITAL CORE

ANALOG CORE

32kHz, 20MHz

TIMERS

SCHED

VOLTAGE REFERENCE

PRIMARY

CORE REGULATOR

CLOCK REGULATOR

ANALOG REGULATOR

DC/DC

SRAM

72kB

CONVERTER

PMU/

RELAXATION

OSCILLATOR

FLASH

512kB

CLOCK

CONTROL

PA

DC/DC

CONVERTER

PoR

20MHz

FLASH

CONTROLLER

802.15.4

MOD

LPF

DAC

AES

PA

CODE

802.15.4

FRAMING

DMA

PLL

AUTO

MAC

802.15.4

DEMOD

BPF

PPF

LNA

ADC

LIMITER

AGC

SYSTEM

RSSI

BAT

LOAD

IPCS

SPI

SLAVE

CLI

UART

(2-PIN)

API

ADC

CTRL

10-BIT

ADC

UART

(6-PIN)

VGA

PTAT

4-BIT

DAC

59012ipm F13

Figure 13. Eterna Block Diagram

59012ipmfa

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SUPPLY MONITORING AND RESET

The use of TIMEn has the advantage of being more accu-

rate. The value of the timestamp is captured in hardware

relative to the rising edge of TIMEn. If an API request is

used,duetopacketprocessing,thevalueofthetimestamp

may be captured several milliseconds after receipt of

the packet due to packet processing. See the TIMEn AC

Characteristics section for the time function’s definition

and specifications.

Eterna integrates a Power-on Reset (PoR) circuit. As the

RESETn input pin is nominally configured with an internal

pull-up resistor, no connection is required. For a graceful

shutdown, the software and the networking layers should

be cleanly halted via API commands prior to assertion of

the RESETn pin. See the SmartMesh IP Mote API Guide

for details on the disconnect and reset commands. Eterna

includes a soft brown-out monitor that fully protects the

flash from corruption in the event that power is removed

while writing to flash. Integrated flash supervisory func-

tionality, in conjunction with a fault tolerant file system,

yields a robust nonvolatile storage solution.

TIME REFERENCES

Eterna includes three clock sources: an internal relaxation

oscillator,alowpoweroscillatordesignedfora32.768kHz

crystal, and the radio reference oscillator designed for a

20MHz crystal.

PRECISION TIMING

Relaxation Oscillator

A major feature of Eterna over competing 802.15.4 prod-

uct offerings is its low-power dedicated timing hardware

and timing algorithms. This functionality provides timing

precision two to three orders of magnitude better than

any other low-power solution available at the time of

publication. Improved timing accuracy allows motes to

minimize the amount of radio listening time required to

ensure packet reception thereby lowering even further

the power consumed by SmartMesh networks. Eterna’s

patented timing hardware and timing algorithms provide

superior performance over rapid temperature changes,

further differentiating Eterna’s reliability when compared

with other wireless products. In addition, precise timing

enablesnetworkstoreducespectraldeadtime, increasing

total network throughput.

The relaxation oscillator is the primary clock source

for Eterna, providing the clock for the CPU, memory

subsystems, and all peripherals. The internal relaxation

oscillator is dynamically calibrated to 7.3728 MHz. The

internal relaxation oscillator typically starts up in a few

μs, providing an expedient, low energy method for duty

cyclingbetweenactiveandlowpowerstates.Quickstart-up

from the doze state, defined in the State Diagram section,

allows Eterna to wake up and receive data over the UART

and SPI interfaces by simply detecting activity on the

appropriate signals.

32.768kHz Crystal

Once Eterna is powered up and the 32.768kHz crystal

source has begun oscillating, the 32.768kHz crystal re-

mains operational while in the active state, and is used as

the timing basis when in doze state. See the State Diagram

section for a description of Eterna’s operational states.

APPLICATION TIME SYNCHRONIꢀATION

In addition to coordinating time slots across the network,

which is transparent to the user, Eterna’s timing manage-

mentisusedtosupporttwomechanismstosharenetwork

time. Having an accurate, shared, network-wide time base

enables events to be accurately time stamped or tasks to

be performed in a synchronized fashion across a network.

Eterna will send a time packet through its serial interface

when one of the following occurs:

20MHz Crystal

The 20 MHz crystal source provides a frequency reference

for the radio, and is automatically enabled and disabled

by Eterna as needed.

n

Eterna receives an API request to read time

n

The TIMEn signal is asserted

59012ipmfa

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operaTion

RADIO

UART Mode 4

Eterna includes the lowest power commercially available

2.4GHz IEEE 802.15.4e radio by a substantial margin.

(Please refer to the Radio Specifications section for

powerconsumptionnumbers.).Eterna’sintegratedpower

amplifier is calibrated and temperature compensated to

consistentlyprovidepoweratalimitsuitableforworldwide

radio certifications. Additionally, Eterna uniquely includes

a hardware-based autonomous MAC that handles precise

sequencing of peripherals, including the transmitter, the

receiver, and Advanced Encryption Standard (AES) pe-

ripherals.Thehardware-basedautonomousMediaAccess

Controller (MAC) minimizes CPU activity, thereby further

decreasing power consumption.

UART Mode 4 incorporates level sensitive flow control

on the TX channel and requires no flow control on the

RX channel, supporting 115200 baud. The use of level-

sensitive flow control signals enables data rates above

9600 baud with the option of using a reduced set of

the flow control signals; however, Mode 4 has specific

limitations. First, the use of the RX flow control signals

(UART_RX_RTSn and UART_RX_CTSn) for Mode 4

are optional provided the use is limited to the industrial

temperature range (–40°C to 85°C); otherwise, the flow

control is mandatory. If RX flow control signals are

not used, UART_RX_RTSn should be tied to VSUPPLY

(inactive)andUART_RX_CTSnshouldbeleftunconnected.

Second, unless the companion processor is always ready

toreceiveapacket, thecompanionprocessormustnegate

UART_TX_CTSn prior to the end of the current packet.

FailuretonegateUART_TX_CTSnpriortotheendofapacket

may result in back to back packets. Third, the companion

UARTs

The principal network interface is through the application

programming interface (API) UART. A Command-Line

Interface (CLI) is also provided for support of test and

debug functions. Both UARTs sense activity continuously,

consumingvirtuallynopoweruntildataistransferredover

the port and then automatically returning to their lowest

power state after the conclusion of a transfer. The defini-

tion for packet encoding on the API UART interface can

be found in the SmartMesh IP Mote API Guide and the

CLI command definitions can be found in the SmartMesh

IP Mote CLI Guide.

processor must wait at least t

between

RX_RTS to RX_CTS

transmmitting packets on UART_RX. See the UART AC

Characteristicssectionforcompletetimingspecifications.

Packets are HDLC encoded with one stop bit and no parity

bit. The flow control signals for the TX channel are shown

in Figure 14. Transfers are initiated by Eterna asserting

UART_TX_RTSn. The UART_TX_CTSn signal may be

activelydrivenbythecompanionprocessorwhenreadyto

receive a packet or UART_TX_CTSn may be tied low if the

companion processor is always ready to receive a packet.

Afterdetectingalogic‘0’onUART_TX_CTSnEternasends

the entire packet. Following the transmission of the final

byteinthepacketEternanegatesUART_TX_RTSnandwaits

API UART Protocol

The API UART protocol was created with the goal of

supporting a wide range of companion Multipoint Control

Units (MCUs) while reducing power consumption of the

system.ThereceivehalfoftheAPIUARTprotocolincludes

twoadditionalsignalsinadditiontoUART_RX:UART_RX_

RTSn and UART_RX_CTSn. The transmit half of the API

UART protocol includes two additional signals in addition

to UART_TX: UART_TX_RTSn and UART_TX_CTSn. The

API UART protocol is referred to as Mode 4.

fort

,definedintheUARTACCharacteristics

TX_INTERPACKET

section before asserting UART_TX_RTSn again.

UART_TX_RTSn

UART_TX_CTSn

In the Figures accompanying the protocol descriptions,

signals driven by the companion processor are drawn

in black and signals driven by Eterna are drawn in blue.

UART_TX

BYTE 0

BYTE 1

59012ipm F14

Figure 14. UART Mode 4 Transmit Flow Control

59012ipmfa

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operaTion

For details on the timing of the UART protocol, see the

UART AC Characteristics section.

devices, thereby preventing access to Eterna’s flash and

RAM memory and thus the keys and code stored therein.

CLI UART

TEMPERATURE SENSOR

The Command Line Interface (CLI) UART port is a two

wire protocol (TX and RX) that operates at a fixed 9600

baud rate with one stop bit and no parity. The CLI UART

interfaceisintendedtosupportcommandlineinstructions

and response activity.

Eterna includes a calibrated temperature sensor on chip.

The temperature readings are available locally through

Eterna’s serial API, in addition to being available via the

network manager. The performance characteristics of

the temperature sensor can be found in the Temperature

Sensor Characteristics section.

AUTONOMOUS MAC

RADIO INHIBIT

Eterna was designed as a system solution to provide a

reliable, ultralow power, and secure network. A reliable

network capable of dynamically optimizing operation

over changing environments requires solutions that are

far too complex to completely support through hardware

acceleration alone. As described in the Precision Timing

section,propertimemanagementisessentialforoptimizing

a solution that is both low power and reliable. To address

theserequirementsEternaincludestheautonomousMAC,

which incorporates a coprocessor for controlling all of

the time critical radio operations. The autonomous MAC

provides two benefits: first, preventing variable software

latency from affecting network timing and second, greatly

reducing system power consumption by allowing the CPU

to remain inactive during the majority of the radio activity.

The autonomous MAC, provides software independent

timing control of the radio and radio related functions,

resultinginsuperiorreliabilityandexceptionallylowpower.

The RADIO_INHIBIT input enables an external controller

to temporarily disable the radio software drivers (for

example, to take a sensor reading that is susceptible to

radio interference). When RADIO_INHIBIT is asserted

the software radio drivers will disallow radio operations

including clear channel assessment, packet transmits,

or packet receipts. If the radio is active in the current

timeslotwhenRADIO_INHIBITisassertedtheradiowillbe

diabled after the present operation completes. For details

on the timing associated with RADIO_INHIBIT, see the

RADIO_INHIBIT AC Characteristics section.

SOFTWARE INSTALLATION

Devices are supplied with the flash erased, requiring pro-

gramming as part of the OEMs manufacturing procedure.

The US Department of Commerce places restrictions on

export of systems and software supporting encryption.

All of Linear/Dust product software produced to date

contains encryption and is subject to export regulations

and may be provided only via MyLinear, https://www.

linear.com/mylinear. Customers purchasing SmartMesh

products will receive a certificate containing a registration

key and registration instructions with their order. After

registering with the key, customers will be able to

download SmartMesh software images from MyLinear.

Once registered, customers will receive automated e-mail

notifications as software updates are made available.

SECURITY

Network security is an often overlooked component of a

complete network solution. Proper implementation of se-

curity protocols is significant in terms of both engineering

effort and market value in an OEM product. Eterna system

solutionsprovideaFIPS-197validatedencryptionscheme

that includes authentication and encryption at the MAC

and network layers with separate keys for each mote.

This not only yields end-to-end security, but if a mote is

somehowcompromised,communicationfromothermotes

is still secure. A mechanism for secure key exchange al-

lows keys to be kept fresh. To prevent physical attacks,

Eternaincludeshardwaresupportforelectronicallylocking

Linear Technology offers the DC9010, in circuit program-

mer for the Eterna based products. While the DC9010, is

provided as a finished product, the design documents are

provided as a reference for customers.

59012ipmfa

27

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LTP5901-IPM/LTP5902-IPM

operaTion

Oncesoftwarehasbeenloaded,devicescanbeconfigured

via either the CLI or API ports. Configuration commands

and settings are defined in SmartMesh IP Mote API Guide

and SmartMesh IP Mote CLI Guide.

STATE DIAGRAM

In order to provide capabilities and flexibility in addition

to ultralow power, Eterna operates in various states, as

shown in Figure 11. Eterna State Diagram and described

in this section. State transitions shown in red are not

recommended.

FLASH DATA RETENTION

Eterna contains internal flash (nonvolatile memory) to

store calibration results, unique ID, configuration settings

and software images. Flash retention over the operating

temperature range. See Electrical Characteristics and

Absolute Maximum Ratings sections.

Start-Up

Start-upoccursasaresultofeithercrossingthepower-on

reset threshold or asserting RESETn. After the completion

of power-on reset or the falling edge of an internally

synchronized RESETn, Eterna loads its fuse table which,

as described in the previous section, includes setting

I/O direction. In this state, Eterna checks the state of

the FLASH_P_ENn and RESETn and enters the serial

flash emulation mode if both signals are asserted. If the

FLASH_P_ENnpinisnotassertedbutRESETnisasserted,

Eterna automatically reduces its energy consumption to

a minimum until RESETn is released. Once RESETn is

de-asserted, Eterna goes through a boot sequence, and

then enters the active state.

Non destructive storage above the operating temperature

range of –40°C to 85°C is possible; although, this may

result in a degradation of retention characteristics.

The degradation in flash retention for temperatures >85°C

can be approximated by calculating the dimensionless

acceleration factor using the following equation.































Ea

k

1

•

−



T

+273

T

+273





AF = e^^

USE

STRESS

Where:

AF = acceleration factor

Serial Flash Emulation

When both RESETn and FLASH_P_ENn are asserted,

Eterna disables normal operation and enters a mode to

emulate the operation of a serial flash. In this mode, its

flash can be programmed.

Ea = activation energy = 0.6eV

–5

k = 8.625 • 10 eV/°K

T

= is the specified temperature retention in °C

USE

Operation

= actual storage temperature in °C

STRESS

Once Eterna has completed start-up, Eterna transitions to

the operational group of states (active/CPU active, active/

CPU inactive, and Doze). There, Eterna cycles between the

various states, automatically selecting the lowest pos-

sible power state while fulfilling the demands of network

operation.

Example: Calculate the effect on retention when storing

at a temperature of 105°C.

T

= 105°C

STRESS

= 85°C

USE

AF = 2.8

Active State

So the overall retention of the flash would be degraded

by a factor of 2.8, reducing data retention from 20 years

at 85°C to 7.1 years at 105°C.

In the active state, Eterna’s relaxation oscillator is running

andperipheralsareenabledasneeded.TheARMCortex-M3

59012ipmfa

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Doze State

cycles between CPU-active and CPU-inactive (referred

to in the ARM Cortex-M3 literature as sleep now mode).

Eterna’s extensive use of DMA and intelligent peripherals

that independently move Eterna between active state and

doze state minimizes the time the CPU is active, signifi-

cantly reducing Eterna’s energy consumption.

The doze state consumes orders of magnitude less cur-

rent than the active state and is entered when all of the

peripherals and the CPU are inactive. In the doze state

Eterna’s full state is retained, timing is maintained, and

Eterna is configured to detect, wake, and rapidly respond

to activity on I/Os (such as UART signals and the TIMEn

pin). In the doze state the 32.768kHz oscillator and as-

sociated timers are active.

POWER-ON

RESET

VSUPPLY > PoR

RESETn LOW AND

FLASH_P_ENn LOW

LOAD FUSE

SETTINGS

SET RESETn HIGH AND

FLASH_P_ENn HIGH

FOR 125µs, THEN

SERIAL FLASH

EMULATION

SET RESETn LOW

RESETn LOW AND

FLASH_P_ENn HIGH

RESETn HIGH

AND

FLASH_P_ENn

HIGH

RESET

DEASSERT

RESETn

BOOT

START-UP

ASSERT RESETn ASSERT RESETn

ASSERT RESETn

CPU AND

PERIPHERALS

INACTIVE

CPU

ACTIVE

DEEP SLEEP

DOZE

CPU

INACTIVE

LOW POWER SLEEP

COMMAND

HW OR PMU EVENT

OPERATION

INACTIVE

59012ipm F15

Figure 15. Eterna State Diagram

59012ipmfa

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I C MASTER

2

ing output, enabling repetitive sampling of signals from a

SPI ADC or SPI sensor based upon a clock reference of

better than 50ppm. For implementation details refer to

the On-Chip Software Development Kit (On-Chip SDK).

2

The I C Master enables control of I C slave devices,

2

including support for clock stretching slaves. I C Multi-

master and bus arbitration protocols are not supported.

For implementation details refer to the On-Chip Software

Development Kit (On-Chip SDK).

1-WIRE MASTER

The Eterna 1-Wire Master controller supports the reset,

presencedetect,readandwrite1-Wireprotocoloperations,

incorporatinganactivepull-up. Theactivepull-upbecomes

active when the passive pull-up raises the voltage on the

1_WIRE pin nominally above 1.4V, driving the 1_WIRE

signal as specified in Digital I/O Characteristics. For

implementation details refer to the On-Chip Software

Development Kit (On-Chip SDK).

SPI MASTER

TheEternaSPImastercontrollersupportsallconfigurations

ofclockpolarityandphase,supportingshiftclockfrequen-

cies of 460.8kHz, 921.6kHz, 1.8432MHz, or 3.6864MHz.

In addition the SPI master controller can be configured to

repetitively issue commands and capture the correspond-

59012ipmfa

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applicaTions inForMaTion

MODES OF OPERATION

n

General Purpose Input-Output (GPIO) pins

Analog-to-Digital Converter (ADC)

The SmartMesh IP Mote software can be operated in three

distinct modes, namely, namely Slave, Master, and On-

Chip SDK. Mode selection should be considered during

thearchitecture/designphaseofthedevelopmentprocess.

Universal Asynchronous Receiver/Transmitter

(UART)

n

Serial Peripheral Interface (SPI) Master

2

Inter-Integrated Circuit (I C) Master

Slave Mode

n

1-Wire Master

In Slave mode, the Eterna is connected to an external

microprocessor through the API UART and is solely used

as a networking device. None of the built in I/Os are ac-

cessible in this mode. Refer to the SmartMesh IP User's

Guide for more detailed information.

Network connectivity and quality of service is handled by

theSmartMeshIPprotocolstack.TheSmartMeshIPstack

comes as a pre-compiled library and delivers >99.999%

data reliability while providing ultra low power operation.

Master Mode

REGULATORY AND STANDARDS COMPLIANCE

Radio Certification

In Master mode, no external µProcessor is required and a

limited set of functionality is made available with no pro-

gramming required on the device. The following features

are available

The LTP5901 and LTP5902 have been certified under a

single modular certification, with the module name of

ETERNA2. Following the regulatory requirements pro-

vided in the ETERNA2 User’s Guide enables customers

to ship products in the supported geographies, by simply

completing an unintentional radiator scan of the finished

product(s). The ETERNA2 User’s Guide also provides

the technical information needed to enable customers

to further certify either the modules or products based

upon the modules in geographies that have not or do not

support modular certification.

n

On-Chip Temperature Sensor

n

4 Analog Inputs

n

4 Digital Inputs

n

3 Digital Outputs

Refer to the SmartMesh IP User's Guide for more detailed

information.

On-Chip SDK (OCSDK)

TheSmartMeshIPOn-ChipSoftwareDevelopmentKit(On-

ChipSDK)enablesdevelopmentofC-codeapplicationsfor

executionontheLTC5800-IPM,runningMicrium’sµCOS-II

real-time operating system. With the On-Chip SDK, users

may quickly and easily develop application code without

the need for an external microprocessor.

Compliance to Restriction of Hazardous Substances

(RoHS)

Restriction of Hazardous Substances 2 (RoHS 2) is a

directive that places maximum concentration limits on

the use of certain hazardous substances in electrical and

electronic equipment. Linear Technology is committed to

meeting the requirements of the European Community

directive 2011/65/EU.

Applications written within the On-Chip SDK may send

andreceivewirelessmessagesthroughthemeshnetwork;

process data, such as statistical analysis; execute local

decision-making and control; and manage the following

peripherals:

59012ipmfa

31

For more information www.linear.com/LTP5901-IPM or www.linear.com/LTP5902-IPM

LTP5901-IPM/LTP5902-IPM

applicaTions inForMaTion

This product has been specifically designed to utilize

RoHS-compliant materials and to eliminate or reduce the

use of restricted materials to comply with 2011/65/EU.

Note: Customers may elect to use certain types of lead-

free solder alloys in accordance with the European Com-

munity directive 2011/65/EU. Depending on the type of

solder paste chosen, a corresponding process change to

optimize reflow temperatures may be required.

The RoHS-compliant design features include:

n

RoHS-compliant solder for solder joints

n

RoHS-compliant base metal alloys

SOLDERING INFORMATION

n

RoHS-compliant precious metal plating

The LTP5901 and LTP5902 are suitable for both eutectic

PbSn and RoHS-6 reflow. The maximum reflow solder-

ing temperature is 260°C. A more detailed description of

layoutrecommendations,assemblyproceduresanddesign

considerations is included in the LTP5901 and LTP5902

Hardware Integration Guide.

n

RoHS-compliant cable assemblies and connector

choices

n

RoHS-compliant and 245°C reflow compatible


型号：	LTP5902IPC-IPMA#PBF
厂家：	Linear
描述：	LTP5902-IPM - SmartMesh IP Wireless 802.15.4e PCBA Module with Antenna Connector; Package: PCA; Pins: 66; Temperature Range: -40°C to 85°C PC 无线
文件：	总36页 (文件大小：697K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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