TB62747AFNAG [MARKTECH]
16-Output Constant Current LED Driver; 16路输出恒流LED驱动器
| 型号： | TB62747AFNAG |
| 厂家： | 
MARKTECH CORPORATE |
| 描述： | 16-Output Constant Current LED Driver |
| 文件： | 总20页 (文件大小：336K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TB62747AFG/AFNG/AFNAG/BFNAG
TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic
TB62747AFG,TB62747AFNG,
TB62747AFNAG,TB62747BFNAG
16-Output Constant Current LED Driver
TB62747AFG
The TB62747 series is comprised of constant-current drivers
designed for LEDs and LED panel displays.
The regulated current sources are designed to provide a
constant current, which is adjustable through one external
resistor.
The TB62747 series incorporates 16 channels of shift registers,
latches, AND gates and constant-current outputs.
SSOP24-P-300-1.00B
Fabricated using the Bi-CMOS process, the TB62747 series
satisfies the system requirement of high-speed data transmission.
The TB62747 series is RoHS compatible
TB62747AFNG
SSOP24-P-300-0.65A
TB62747AFNAG/BFNAG
SSOP24-P-150-0.64
Weight
Features
SSOP24-P-300-1.00B : 0.29 g (typ.)
SSOP24-P-300-0.65A : 0.14 g (typ.)
SSOP24-P-150-0.64: 0.14 g (typ.)
•
•
•
Power supply voltages: V
16-output built-in
= 3.3 V to 5.0 V
DD
Output current setting range
: 1.5 to 35 mA @ V
= 3.3 V, VO = 0.4 to 1.0 V
DD
: 1.5 to 45 mA @ V
= 5.0 V, VO = 0.4 to 1.2 V
DD
•
•
Constant current output voltage: V = 26 V (max)
O
Current accuracy (@ R
EXT
= 1.2 kΩ, V = 0.4 V, V = 3.3 V, 5.0 V)
DD
O
: Between outputs: ± 1.5 % (max)
: Between devices: ± 1.5 % (max)
•
•
•
•
•
•
•
Fast response of output current : t
= 100 ns (min)
wOE(L)
Control data format: serial-in, parallel-out
Input signal voltage level: 3.3 V and 5 V CMOS interfaces (Schmitt trigger input)
Serial data transfer rate: 25 MHz (max) @cascade connection
Operation temperature range: T
Power on reset (POR)
= −40 to 85 °C
opr
Package
: AFG type
: SSOP24-P-300-1.00B
: AFNG type
: AFNAG type
: BFNAG type
: SSOP24-P-300-0.65A
: SSOP24-P-150-0.64
: SSOP24-P-150-0.64
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2009-01-21
TB62747AFG/AFNG/AFNAG/BFNAG
Pin Assignment (top view)
TB62747AFG/AFNG/AFNAG
TB62747BFNAG
OUT13
OUT14
GND
SIN
V
DD
R
OUT12
OUT11
OUT10
OUT9
OUT15
OE
EXT
SCK
SOUT
OE
SLAT
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
SOUT
R
EXT
OUT15
OUT14
OUT13
OUT12
OUT8
V
DD
OUT7
GND
SIN
OUT6
OUT5
OUT4
OUT3
OUT2
SCK
OUT11
OUT10
OUT9
SLAT
OUT0
OUT1
OUT8
Note1: Short circuiting an output pin to a power supply pin (V
DD
or V ), or short-circuiting the R
LED*
pin to
EXT
the GND pin will likely exceed the rating, which in turn may result in smoldering and/or permanent
damage. Please keep this in mind when determining the wiring layout for the power supply and GND pins.
*VLED: LED power supply
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2009-01-21
TB62747AFG/AFNG/AFNAG/BFNAG
Block Diagram
OUT0
OUT1
OUT15
V
DD
OUT0
OUT1
Constant current outputs
OUT15
POR
B.G
GND
R
EXT
OE
Q0 Q1
16-bit D-latch
D0 D1
Q15
D15
R
G
SLAT
SIN
D0
Q0 Q1
16-bit shift register
Q15
Q15
R
SOUT
SCK
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TB62747AFG/AFNG/AFNAG/BFNAG
Truth Table
SCK
SLAT
OE
SIN
OUT0 … OUT7 … OUT15 *1
SOUT
H
L
L
L
L
L
H
Dn
Dn … Dn − 7 … Dn − 15
No Change
Dn − 15
Dn − 14
Dn − 13
Dn − 13
Dn − 13
Dn + 1
Dn + 2
Dn + 3
Dn + 3
H
Dn + 2 … Dn − 5 … Dn − 13
Dn + 2 … Dn − 5 … Dn − 13
OFF
−*2
−*2
Note1: When OUT0 to OUT15 output pins are set to "H" the respective output will be ON and when set to
"L" the respective output will be OFF.
Note2: “-“ is irrelevant to the truth table.
Timing Diagram
n = 0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
H
SCK
SIN
L
H
L
H
SLAT
OE
L
H
L
ON
OFF
ON
OFF
ON
OFF
OUT0
OUT1
OUT2
ON
OFF
H
OUT15
SOUT
L
Note 1: The latch circuit is a leveled-latch circuit. Please exercise precaution as it is not triggered-latch circuit.
Note 2: Keep the SLAT pin is set to “L” to enable the latch circuit to hold data. In addition, when the SLAT pin
is set to “H” the latch circuit does not hold data. The data will instead pass onto output.
When the OE pin is set to “L” the OUT0 to OUT15 output pins will go ON and OFF in response to
the data. In addition, when the OE pin is set to “H” all the output pins will be forced OFF regardless of
the data.
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2009-01-21
TB62747AFG/AFNG/AFNAG/BFNAG
Pin Functions
Pin No
AFG
AFNG
AFNAG
Pin Name
I/O
Function
BFNAG
1
2
3
7
8
9
GND
SIN
⎯
The ground pin.
I
I
The serial data input pin.
SCK
The serial data transfer clock input pin.
The latch signal input pin.
Data is saved at L level.
4
10
SLAT
I
5
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
A sink type constant current output pin.
A sink type constant current output pin.
A sink type constant current output pin.
A sink type constant current output pin.
A sink type constant current output pin.
A sink type constant current output pin.
A sink type constant current output pin.
A sink type constant current output pin.
A sink type constant current output pin.
A sink type constant current output pin.
A sink type constant current output pin.
A sink type constant current output pin.
A sink type constant current output pin.
A sink type constant current output pin.
A sink type constant current output pin.
A sink type constant current output pin.
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
2
The constant current output enable signal input pin.
During the “H” level, the output will be forced off.
21
3
OE
I
22
23
24
4
5
6
SOUT
O
⎯
⎯
The serial data output pin.
R
EXT
The constant current value setting resistor connection pin.
The power supply input pin.
V
DD
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TB62747AFG/AFNG/AFNAG/BFNAG
Absolute Maximum Ratings (T = 25°C)
a
Characteristics
Power supply voltage
Symbol
Rating *1
Unit
V
−0.4 to 6.0
V
mA
V
DD
Output current
I
55
O
Logic input voltage
Output voltage
V
−0.3 to V
+ 0.3 *2
DD
IN
V
−0.3 to 26
V
O
Operating temperature
Storage temperature
T
−40 to 85
°C
°C
opr
T
−55 to 150
stg
94 (AFG) *3, 120 (AFNG) *3, 80.07(AFNAG/BFNAG)
When mounted PCB
Rth(j-a)
°C/W
W
Thermal resistance
Power dissipation
1.32 (AFG) *3, 1.04 (AFNG) *3, 1.56(AFNAG/BFNAG)
When mounted PCB
P *4
D
Note1: Voltage is ground referenced.
Note2: However, do not exceed 6V.
Note3: PCB condition 76.2 x 114.3 x 1.6 mm, Cu 30% (SEMI conforming)
Note4: The power dissipation decreases the reciprocal of the saturated thermal resistance (1/ Rth(j-a)) for each
degree (1°C) that the ambient temperature is exceeded (Ta = 25°C).
Operating Conditions
DC Items (Unless otherwise specified, V = 3.0 to 5.5 V, T = −40°C to 85°C)
DD
a
Characteristics
Power supply voltage
Symbol
Test Conditions
Min
Typ.
Max
Unit
V
⎯
3.0
0.4
⎯
⎯
5.5
4.0
V
V
DD
Output voltage when OFF
V
OUTn
O (ON)
0.7 ×
DD
High level logic input voltage
V
SIN,SCK, SLAT , OE
SIN,SCK, SLAT , OE
⎯
⎯
V
V
V
IH
DD
V
0.3 ×
V
Low level logic input voltage
V
GND
IL
DD
High level SOUT output current
Low level SOUT output current
I
⎯
⎯
⎯
⎯
⎯
⎯
⎯
−1
1
mA
mA
OH
I
I
I
⎯
OL
O1
O2
OUTn , V
DD
= 3.3 V, V = 0.4 to 1.0 V
1.5
1.5
35
45
O
Constant current output
mA
OUTn , V = 5.0 V, V = 0.4 to 1.2 V
DD
O
AC Items (Unless otherwise specified, V = 3.0 to 5.5 V, T = −40°C to 85°C)
DD
a
Test
Characteristics
Symbol
Test Conditions
Min
Typ.
Max
Unit
Circuits
Serial data transfer frequency
Hold time
f
6
6
6
6
6
6
6
⎯
⎯
⎯
⎯
⎯
⎯
5
⎯
⎯
⎯
⎯
⎯
⎯
⎯
25
⎯
MHz
ns
SCK
t
t
HOLD1
HOLD2
5
⎯
ns
t
5
⎯
ns
SETUP1
SETUP2
Setup time
t
5
⎯
ns
Maximum clock rise time
Maximum clock fall time
t
t
*1
*1
⎯
⎯
500
500
ns
r
ns
f
Note1: If the device is connected in a cascade and the tr/tf of the clock waveform increases due to deceleration of the clock
waveform,it may not be possible to achieve the timing required for data transfer. Please keep these timing conditions in mind
when designing your application.
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TB62747AFG/AFNG/AFNAG/BFNAG
Electrical Characteristics (Unless otherwise specified, VDD = 3.3V, T = 25°C)
a
Test
Circuits
Characteristics
Symbol
Test Conditions
Min
Typ.
Max
Unit
V
V
−
DD
High level logic output voltage
V
1
I
I
= −1 mA
⎯
⎯
OH
OH
0.4
Low level logic output voltage
High level logic input current
Low level logic input current
V
I
1
2
3
= +1 mA
⎯
⎯
⎯
⎯
⎯
⎯
0.4
1
V
OL
OL
V
V
V
= V , OE , SIN, SCK
DD
µA
µA
IH
IN
IN
O
I
= GND, SLAT , SIN, SCK
−1
IL
= 25 V, R
EXT
= OPEN,
I
4
⎯
⎯
1.0
mA
DD1
SCK = “L”, OE = “H”
Power supply current
Output current
I
I
4
4
R
= 1.2 kΩ, All output off
= 1.2 kΩ, All output on
⎯
⎯
⎯
⎯
4.0
8.0
mA
mA
DD2
DD3
EXT
EXT
R
V
= 3.3 V, V = 0.4 V,
O
DD
I
5
⎯
14
⎯
mA
O
R
= 1.2 kΩ, OUT0 to OUT15
EXT
= 3.3 V, V = 0.4 V,
V
DD
O
Constant current error(Ch to Ch)
Constant current error(IC to IC)
Output OFF leak current
∆I
5
5
5
5
⎯
⎯
⎯
⎯
±1
±1
⎯
±1
±1.5
±1.5
0.5
%
%
O
R
EXT
= 1.2 kΩ, OUT0 to OUT15
V
= 3.3 V, V = 0.4 V,
DD
O
∆I
O(IC)
R
EXT
= 1.2 kΩ, OUT0 to OUT15
V
= 3.3 V, V = 25 V,
DD
O
I
µA
%
OK
R
V
= 1.2 kΩ, OUT0 to OUT15
EXT
= 3.0 to 3.6 V, V = 0.4 V,
Constant current power supply voltage
regulation
DD
O
%V
±2
DD
R
EXT
= 1.2 kΩ, OUT0 to OUT15
V
= 3.3 V, V = 0.4 to 3.0 V,
Constant current output voltage
regulation
DD
O
%V
5
⎯
±1
⎯
%/V
O
R
= 1.2 kΩ, OUT0 to OUT15
EXT
OE
SLAT
Pull-up resistor
R
UP
3
2
250
250
500
500
800
800
kΩ
kΩ
Pull-down resistor
R
DOWN
Electrical Characteristics (Unless otherwise specified, VDD = 5.0V, T = 25°C)
a
Test
Circuits
Characteristics
Symbol
Test Conditions
Min
Typ.
Max
Unit
V
V
−
DD
High level logic output voltage
V
1
I
I
= −1 mA
⎯
⎯
OH
OH
0.4
Low level logic output voltage
High level logic input current
Low level logic input current
V
I
1
2
3
= +1 mA
⎯
⎯
⎯
⎯
⎯
⎯
0.4
1
V
OL
OL
V
V
V
= V , OE , SIN, SCK
DD
µA
µA
IH
IN
IN
O
I
= GND, SLAT , SIN, SCK
−1
IL
= 25 V, R
EXT
= OPEN,
I
4
⎯
⎯
1.0
mA
DD1
SCK = “L”, OE = “H”
Power supply current
Output current
I
I
4
4
R
= 1.2 kΩ, All output off
= 1.2 kΩ, All output on
⎯
⎯
⎯
⎯
4.5
8.0
mA
mA
DD2
DD3
EXT
EXT
R
V
= 5.0 V, V = 0.4 V,
O
DD
I
5
⎯
14
⎯
mA
O
R
EXT
= 1.2 kΩ, OUT0 to OUT15
V
= 5.0 V, V = 0.4 V,
DD
O
Constant current error(Ch to Ch)
Constant current error(IC to IC)
Output OFF leak current
∆I
5
5
5
5
⎯
⎯
⎯
⎯
±1
±1
⎯
±1
±1.5
±1.5
0.5
%
%
O
R
= 1.2 kΩ, OUT0 to OUT15
EXT
V
= 5.0 V, V = 0.4 V,
DD
O
∆I
O(IC)
R
= 1.2 kΩ, OUT0 to OUT15
EXT
V
= 5.0 V, V = 25 V,
DD
O
I
µA
%
OK
R
V
= 1.2 kΩ, OUT0 to OUT15
EXT
= 4.5 to 5.5 V, V = 0.4 V,
Constant current power supply voltage
regulation
DD
O
%V
±2
DD
R
= 1.2 kΩ, OUT0 to OUT15
EXT
V
= 5.0 V, V = 0.4 to 3.0 V,
Constant current output voltage
regulation
DD
O
%V
5
⎯
±1
⎯
%/V
O
R
= 1.2 kΩ, OUT0 to OUT15
EXT
OE
SLAT
Pull-up resistor
R
UP
3
2
250
250
500
500
800
800
kΩ
kΩ
Pull-down resistor
R
DOWN
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TB62747AFG/AFNG/AFNAG/BFNAG
Switching Characteristics (Unless otherwise specified, V = 3.3V, T = 25°C)
DD
a
Test
Characteristics
Symbol
Test Conditions
Min
Typ.
Max
Unit
Circuits
SCK- OUT0
t
t
t
6
6
6
6
6
6
6
6
6
6
SLAT = “H”, OE = “L”
OE = “L”
⎯
⎯
⎯
10
⎯
⎯
⎯
10
⎯
⎯
20
20
20
20
30
70
70
20
20
25
300
300
300
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pLH1
pLH2
pLH3
SLAT - OUT0
OE - OUT0
SLAT = “H”
SCK-SOUT
SCK- OUT0
SLAT - OUT0
OE - OUT0
t
CL=10.5 pF
pLH
Propagation delay
time
t
SLAT = “H”, OE = “L”
OE = “L”
340
340
340
35
pHL1
pHL2
pHL3
t
t
SLAT = “H”
SCK-SOUT
t
CL=10.5 pF
pHL
Output rise time
Output fall time
t
or
10 to 90% of voltage waveform
90 to 10% of voltage waveform
90
t
180
of
wOE(L)
Enable pulse width
t
6
100
⎯
⎯
ns
OE = “L” *1
SCK = “H” or “L”
SLAT = “H”
Clock pulse width
Latch pulse width
t
6
6
20
20
⎯
⎯
⎯
⎯
ns
ns
wSCK
t
wSLAT
Note1: At the condition of t
= 250ns or more
wOE(H)
Switching Characteristics (Unless otherwise specified, V = 5.0V, T = 25°C)
DD
a
Test
Characteristics
Symbol
Test Conditions
Min
Typ.
Max
Unit
Circuits
SCK- OUT0
t
t
t
6
6
6
6
6
6
6
6
6
6
SLAT = “H”, OE = “L”
OE = “L”
⎯
⎯
⎯
10
⎯
⎯
⎯
10
⎯
⎯
20
20
20
20
30
70
70
20
20
25
300
300
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pLH1
pLH2
pLH3
SLAT - OUT0
OE - OUT0
SLAT = “H”
SCK-SOUT
SCK- OUT0
SLAT - OUT0
OE - OUT0
t
CL=10.5 pF
35
pLH
Propagation delay
time
t
SLAT = “H”, OE = “L”
OE = “L”
340
340
340
35
pHL1
pHL2
pHL3
t
t
SLAT = “H”
SCK-SOUT
t
CL=10.5 pF
pHL
Output rise time
Output fall time
t
or
10 to 90% of voltage waveform
90 to 10% of voltage waveform
90
t
180
of
wOE(L)
Enable pulse width
t
6
100
⎯
⎯
ns
OE = “L” *1
Clock pulse width
Latch pulse width
t
6
6
SCK = “H” or “L”
SLAT = “H”
20
20
⎯
⎯
⎯
⎯
ns
ns
wSCK
t
wSLAT
Note1: At the condition of t
= 250ns or more
wOE(H)
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TB62747AFG/AFNG/AFNAG/BFNAG
I/O Equivalent Circuits
1. SCK, SIN
2. OE
V
V
DD
DD
(SCK)
(SIN)
OE
GND
GND
3. SLAT
4. SOUT
V
V
DD
DD
SOUT
GND
SLAT
GND
5. OUT0 to OUT15
OUT0 to OUT15
GND
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TB62747AFG/AFNG/AFNAG/BFNAG
Test Circuits
Test Circuit1: High level logic input voltage / Low level logic input voltage
V
DD
SCK
OUT0
OUT7
SIN
SLAT
F.G
OE
OUT15
V
V
= V
DD
= 0 V
IH
IL
R
EXT
GND
SOUT
t = t = 10 ns
r
f
(10 to 90%)
V
Test Circuit2: High level logic input current / Pull-down resistor
= V
V
IN
DD
V
DD
A
SCK
OUT0
OUT7
SIN
SLAT
A
A
OE
A
OUT15
R
EXT
GND
SOUT
Test Circuit3: Low level logic input current / Pull-up resistor
V
DD
A
SCK
OUT0
OUT7
SIN
SLAT
A
A
OE
A
OUT15
R
EXT
GND
SOUT
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TB62747AFG/AFNG/AFNAG/BFNAG
Test Circuit4: Power supply current
F.G
V
DD
SCK
OUT0
OUT7
SIN
SLAT
OE
OUT15
A
V
V
= V
DD
= 0 V
IH
IL
R
EXT
GND
SOUT
t = t = 10 ns
r
f
(10 to 90%)
Test Circuit5: Constant current output / Output OFF leak current / Constant current error
Test Circuit5: Constant current power supply voltage regulation / Constant current output voltage regulation
V
DD
SCK
OUT0
OUT7
A
A
SIN
SLAT
F.G
OE
OUT15
A
V
V
= V
DD
= 0 V
IH
IL
R
EXT
GND
SOUT
t = t = 10 ns
r
f
(10 to 90%)
Test Circuit6: Switching Characteristics
SCK
R
L
= 300 Ω
V
DD
OUT0
OUT7
C
L
SIN
SLAT
F.G
R
C
L
L
OE
R
L
OUT15
V
V
= V
DD
= 0 V
IH
IL
R
EXT
GND
SOUT
C = 10.5 pF
L
t = t = 10 ns
r
f
(10 to 90%)
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2009-01-21
TB62747AFG/AFNG/AFNAG/BFNAG
Timing Waveforms
1. SCK, SIN, SOUT
t
wSCK
90%
10%
90%
10%
SCK
50%
50%
50%
t
SETUP1
t
wSCK
t
t
f
r
SIN
50%
50%
50%
t
HOLD1
SOUT
t
/t
pLH pHL
2. SCK, SIN, SLAT , OE, OUT0
SCK
50%
50%
SIN
t
t
SETUP2
HOLD2
50%
SLAT
50%
t
t
wOE(L)
wSLAT
50%
50%
OE
OUT0
50%
t
/t
pHL1 pLH1
t
/t
pHL2 pLH2
3. OE, OUT0
t
wOE
50%
50%
OE
tpLH3
tpHL3
90%
OFF
ON
90%
50%
10%
50%
10%
OUT0
t
t
or
of
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TB62747AFG/AFNG/AFNAG/BFNAG
Reference data
*This data is provided for reference only. Thorough evaluation and testing should be implemented when
designing your application's mass production design.
Output Current – R
Resistor
EXT
IOUT - R
EXT
50
45
40
35
30
25
20
15
10
5
Theoretical value
IOUT (A) = 1.13 (V) ÷ REXT (Ω) × 14.9
All output on
Ta=25°C
VOUT=0.7V
0
100
1000
( )
10000
R
Ω
EXT
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TB62747AFG/AFNG/AFNAG/BFNAG
Reference data
*This data is provided for reference only. Thorough evaluation and testing should be implemented when
designing your application's mass production design.
Output Current – Duty (LED turn-on rate)
IO - Duty
AFNG AFNAG/BFNAG
IO - Duty
AFNAG/BFNAG
50
45
40
35
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
AFG
AFG
AFNG
Ta=25°C
Ta=55°C
VDD=5.0V
VO=1.0V
ON PCB
VDD=5.0V
VO=1.0V
ON PCB
0
0
0
20
40
60
80
100
0
20
40
60
80
100
Duty - Turn on rate (%)
Duty - Turn on rate (%)
IO - Duty
50
45
40
35
30
25
20
15
10
5
AFNAG/BFNAG
AFG
AFNG
Ta=85°C
VDD=5.0V
VO=1.0V
ON PCB
0
0
20
40
60
80
100
Duty - Turn on rate (%)
Power dissipation – Ta
PD - Ta
1.8
AFNAG/BFNAG
1.6
1.4
AFG
1.2
1.0
AFNG
0.8
0.6
0.4
0.2
0.0
0
10 20 30 40 50 60 70 80 90
Ta (℃)
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2009-01-21
TB62747AFG/AFNG/AFNAG/BFNAG
Package Dimensions
Weight: 0.29 g (typ.)
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2009-01-21
TB62747AFG/AFNG/AFNAG/BFNAG
Package Dimensions
Weight: 0.14 g (typ.)
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2009-01-21
TB62747AFG/AFNG/AFNAG/BFNAG
Package Dimensions
SSOP24-P-150-0.64
Unit : Inch
0.337 to 0.344
0.0325(REF)
0.025
0.008 to 0.012
0.004 to 0.098
0.010(TYP)
0.016 to 0.034
Weight: 0.14 g (typ.)
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TB62747AFG/AFNG/AFNAG/BFNAG
Notes on Contents
1. Block Diagrams
Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for
explanatory purposes.
2. Equivalent Circuits
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory
purposes.
3. Timing Charts
Timing charts may be simplified for explanatory purposes.
4. Application Circuits
The application circuits shown in this document are provided for reference purposes only. Thorough
evaluation is required, especially at the mass production design stage.
Toshiba does not grant any license to any industrial property rights by providing these examples of
application circuits.
5. Test Circuits
Components in the test circuits are used only to obtain and confirm the device characteristics. These
components and circuits are not guaranteed to prevent malfunction or failure from occurring in the
application equipment.
22
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TB62747AFG/AFNG/AFNAG/BFNAG
IC Usage Considerations
Notes on handling of ICs
[1] The absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded,
even for a moment. Do not exceed any of these ratings.
Exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury
by explosion or combustion.
[2] Use an appropriate power supply fuse to ensure that a large current does not continuously flow in case of
over current and/or IC failure. The IC will fully break down when used under conditions that exceed its
absolute maximum ratings, when the wiring is routed improperly or when an abnormal pulse noise occurs
from the wiring or load, causing a large current to continuously flow and the breakdown can lead smoke or
ignition. To minimize the effects of the flow of a large current in case of breakdown, appropriate settings,
such as fuse capacity, fusing time and insertion circuit location, are required.
[3] If your design includes an inductive load such as a motor coil, incorporate a protection circuit into the
design to prevent device malfunction or breakdown caused by the current resulting from the inrush
current at power ON or the negative current resulting from the back electromotive force at power OFF. IC
breakdown may cause injury, smoke or ignition.
Use a stable power supply with ICs with built-in protection functions. If the power supply is unstable, the
protection function may not operate, causing IC breakdown. IC breakdown may cause injury, smoke or
ignition.
[4] Do not insert devices in the wrong orientation or incorrectly.
Make sure that the positive and negative terminals of power supplies are connected properly.
Otherwise, the current or power consumption may exceed the absolute maximum rating, and exceeding
the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by
explosion or combustion.
In addition, do not use any device that is applied the current with inserting in the wrong orientation or
incorrectly even just one time.
[5] Carefully select external components (such as inputs and negative feedback capacitors) and load
components (such as speakers), for example, power amp and regulator.
If there is a large amount of leakage current such as input or negative feedback condenser, the IC output
DC voltage will increase. If this output voltage is connected to a speaker with low input withstand voltage,
overcurrent or IC failure can cause smoke or ignition. (The over current can cause smoke or ignition from
the IC itself.) In particular, please pay attention when using a Bridge Tied Load (BTL) connection type IC
that inputs output DC voltage to a speaker directly.
Points to remember on handling of ICs
(1) Heat Radiation Design
In using an IC with large current flow such as power amp, regulator or driver, please design the
device so that heat is appropriately radiated, not to exceed the specified junction temperature (TJ) at
any time and condition. These ICs generate heat even during normal use. An inadequate IC heat
radiation design can lead to decrease in IC life, deterioration of IC characteristics or IC breakdown.
In addition, please design the device taking into considerate the effect of IC heat radiation with
peripheral components.
(2) Back-EMF
When a motor rotates in the reverse direction, stops or slows down abruptly, a current flow back to the motor’s
power supply due to the effect of back-EMF. If the current sink capability of the power supply is small, the
device’s motor power supply and output pins might be exposed to conditions beyond maximum ratings. To avoid
this problem, take the effect of back-EMF into consideration in system design.
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TB62747AFG/AFNG/AFNAG/BFNAG
RESTRICTIONS ON PRODUCT USE
20070701-EN
• The information contained herein is subject to change without notice.
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety
in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such
TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc.
• The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.).These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in his
document shall be made at the customer’s own risk.
• The products described in this document shall not be used or embedded to any downstream products of which
manufacture, use and/or sale are prohibited under any applicable laws and regulations.
• The information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from
its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third
parties.
• Please use these products in this document in compliance with all applicable laws and regulations that regulate the
inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result
of noncompliance with applicable laws and regulations.
• The products described in this document are subject to foreign exchange and foreign trade control laws.
24
2009-01-21
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