DS28E38Q+T [MAXIM]
Analog Circuit,;
| 型号： | DS28E38Q+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Analog Circuit, 光电二极管 |
| 文件： | 总16页 (文件大小：380K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DS28E38
DeepCover® Secure ECDSA Authenticator
with ChipDNA PUF Protection
General Description
Benefits and Features
● Robust Countermeasures Protect Against Security
The DS28E38 is an ECDSA public key-based secure
authenticator that incorporates Maxim’s patented
ChipDNA™ PUF technology. ChipDNA technology
involves a physically unclonable function (PUF) that
enables the DS28E38 to deliver cost-effective protec-
tion against invasive physical attacks. Using the random
variation of semiconductor device characteristics that
naturally occur during wafer fabrication, the ChipDNA
circuit generates a unique output value that is repeatable
over time, temperature, and operating voltage. Attempts
to probe or observe ChipDNA operation modifies the
underlying circuit characteristics, preventing discovery
of the unique value used by the chip cryptographic func-
tions. The DS28E38 utilizes the ChipDNA output as key
content to cryptographically secure all device stored data
and optionally, under user control, as the private key for
the ECDSA signing operation. With ChipDNA capabil-
ity, the device provides a core set of cryptographic tools
derived from integrated blocks including an asymmetric
(ECC-P256) hardware engine, a FIPS/NIST-compliant
true random number generator (TRNG), 2Kb of secured
EEPROM, a decrement-only counter and a unique 64-bit
ROM identification number (ROM ID). The ECC public/
private key capabilities operate from the NIST-defined
P-256 curve to provide a FIPS 186-compliant ECDSA
signature generation function. The unique ROM ID is
used as a fundamental input parameter for cryptographic
operations and serves as an electronic serial number
within the application. The DS28E38 communicates over
the single-contact 1-Wire® bus at both standard and
overdrive speeds. The communication follows the 1-Wire
protocol with the ROM ID acting as node address in the
case of a multidevice 1-Wire network.
Attacks
• Patented Physically Unclonable Function Secures
Device Data
• Actively Monitored Die Shield Detects and Reacts
to Intrusion Attempts
• All Stored Data Cryptographically Protected from
Discovery
● Efficient Public-Key Authentication Solution to
Authenticate Peripherals
• FIPS 186-Compliant ECDSA P256 Signature for
Challenge/Response Authentication
• Options for ECDSA Public/Private Key Pair Source
Include ChipDNA Generated, Chip Computed, and
User Installed
• TRNG with NIST SP 800-90B Compliant Entropy
Source
● Supplemental Features Enable Easy Integration into
End Applications
• 17-Bit One-Time Settable, Nonvolatile Decrement-
Only Counter with Authenticated Read
• 2Kbits of EEPROM for User Data, Key, Control
Registers, and Certificate
• Unique and Unalterable Factory Programmed
64-Bit Identification Number (ROM ID)
• Single-Contact, 1-Wire Interface Communication
with Host at 11.7kbps and 62.5kbps
• Operating Range: 3.3V ±10%, -40°C to +85°C
• 6-Pin TDFN-EP Package (3mm x 3mm)
Ordering Information appears at end of data sheet.
Applications
● Authentication of Medical Sensors and Tools
● Secure Management of Limited Use Consumables
● IoT Node Authentication
DeepCover and 1-Wire are registered trademarks and
ChipDNA is a trademark of Maxim Integrated Products, Inc.
● Peripheral Authentication
● Reference Design License Management
● Printer Cartridge Identification and Authentication
19-100093; Rev 1; 9/17
DS28E38
DeepCover® Secure ECDSA Authenticator
with ChipDNA PUF Protection
Typical Application Circuit
V
CC
CC
100kΩ
R
PUP
Q1
1kΩ
V
PIOX
PIOY
*PMV65XP
BIDIRECTIONAL
OPEN DRAIN PORT
DS28E38
IO
C
EXT
C
X
GND
V
CC
µC
Rp
V
CC
2
IO
I C
PIOA
PIOB
SDA
SCL
PORT
IO
DS2476
GND
*NOTE: USE A Q1 LOW-IMPEDANCE BYPASS OR EQUALLY DRIVE LOGIC ‘1’ WITH PIOY.
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DS28E38
DeepCover® Secure ECDSA Authenticator
with ChipDNA PUF Protection
Absolute Maximum Ratings
Voltage Range on Any Pin Relative to GND..........-0.5V to 4.0V
Maximum Current into Any Pin........................... -20mA to 20mA
Operating Temperature Range........................... -40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range............................ -40°C to +125°C
Lead temperature (soldering, 10s)..................................+300°C
Soldering Temperature (reflow).......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
6 TDFN-EP
PACKAGE CODE
T633+2
Outline Number
21-0137
90-0058
Land Pattern Number
Thermal Resistance, Single-Layer Board:
Junction to Ambient (θ
)
55ºC/W
9ºC/W
JA
Junction to Case (θ
)
JC
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θ
)
42ºC/W
9ºC/W
JA
Junction to Case (θ
)
JC
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(Limits are 100% tested at T = +25°C and T = +85°C. Limits over the operating temperature range and relevant supply voltage
A
A
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to the minimum operating temperature are guaranteed by design and are not production tested. )
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
3.3
MAX
UNITS
IO PIN: GENERAL DATA
1-Wire Pullup Voltage
1-Wire Pullup Resistance
V
R
System requirement
2.97
3.63
V
PUP
(Note 1)
1000
Ω
PUP
0.1 +
Input Capacitance
C
(Notes 1, 2)
nF
IO
C
X
Capacitor External
Input Load Current
C
System requirement. IO pin at V
399.5
470
10
540.5
360
nF
µA
X
PUP
I
IO pin at V
PUP
L
High-to-Low Switching
Threshold
0.65 x
V
(Notes 3, 4)
(Note 5)
V
V
TL
V
PUP
0.10 x
Input Low Voltage
V
IL
V
PUP
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DS28E38
DeepCover® Secure ECDSA Authenticator
with ChipDNA PUF Protection
Electrical Characteristics (continued)
(Limits are 100% tested at T = +25°C and T = +85°C. Limits over the operating temperature range and relevant supply voltage
A
A
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to the minimum operating temperature are guaranteed by design and are not production tested. )
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Low-to-High Switching
Threshold
0.75 x
V
(Notes 3, 6)
(Notes 3, 7)
V
TH
V
PUP
Switching Hysteresis
V
V
0.3
V
V
HY
Output Low Voltage
I
= 4mA (Note 8)
0.4
OL
OL
IO PIN: 1-Wire INTERFACE
Standard speed, R
= 1000Ω
= 1000Ω
PUP
25
10
PUP
Recovery Time (Note 9)
t
Overdrive speed, R
μs
REC
Directly prior to reset pulse: R
= 1000Ω
100
PUP
Rising-Edge Hold-Off
(Note 10)
t
Applies to standard speed only
1
μs
μs
REH
Standard speed
Overdrive speed
85
16
Time Slot Duration
(Note 11)
t
SLOT
IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE
System requirement, standard speed
480
48
480
48
60
6
640
80
Reset Low Time
t
μs
μs
μs
RSTL
System requirement, overdrive speed
Standard speed
Reset High Time
(Note 21)
t
RSTH
Overdrive speed
Standard speed
75
10
Presence-Detect Sample
Time (Note 12)
t
MSP
Overdrive speed
IO PIN: 1-Wire WRITE
Standard speed
Overdrive speed
Standard speed
Overdrive speed
60
6
120
15.5
15
Write-Zero Low Time
(Note 13)
t
t
μs
μs
W0L
W1L
0.25
0.25
Write-One Low Time
(Note 13)
2
IO PIN: 1-Wire READ
Standard speed
Overdrive speed
Standard speed
Overdrive speed
0.25
0.25
15 - δ
2 - δ
15
Read Low Time (Note 14)
t
μs
μs
RL
t
+ δ
Read Sample Time
(Note 14)
RL
t
MSR
t
+ δ
2
RL
STRONG PULLUP OPERATION
Strong Pullup Current
I
(Note 15)
(Note 15)
10
mA
V
SPU
Strong Pullup Voltage
Read Memory
V
2.8
SPU
RM
t
30
65
ms
ms
ms
ms
Write Memory
t
WM
Write State
t
15
WS
Generate ECC Key Pair
t
200
GKP
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DS28E38
DeepCover® Secure ECDSA Authenticator
with ChipDNA PUF Protection
Electrical Characteristics (continued)
(Limits are 100% tested at T = +25°C and T = +85°C. Limits over the operating temperature range and relevant supply voltage
A
A
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to the minimum operating temperature are guaranteed by design and are not production tested. )
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Generate ECDSA
Signature
t
130
ms
GES
TRNG On-Demand
Check
t
20
ms
ODC
EEPROM
Write/Erase Cycles
(Endurance)
N
(Notes 16, 17)
= +85ºC (Notes 18, 19, 20)
100K
10
CY
Data Retention
t
T
years
DR
A
Note 1: System requirement. Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system
and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire
recovery times.
Note 2: Value represents the typical parasite capacitance when V
is first applied. Once the parasite capacitance is charged,
PUP
it does not affect normal communication. Typically, during normal communication, the parasite capacitance is effectively
~100pF.
Note 3: V , V , and V
are a function of the internal supply voltage, which is a function of V
, R
, 1-Wire timing, and
TL TH
HY
PUP PUP
capacitive loading on IO. Lower V
, higher R
, shorter t
, and heavier capacitive loading all lead to lower values of
PUP
PUP
REC
V
, V , and V
.
TL TH
HY
Note 4: Voltage below which, during a falling edge on IO, a logic-zero is detected.
Note 5: The voltage on IO must be less than or equal to V at all times the master is driving IO to a logic-zero level.
ILMAX
Note 6: Voltage above which, during a rising edge on IO, a logic-one is detected.
Note 7: After V is crossed during a rising edge on IO, the voltage on IO must drop by at least V
to be detected as logic-zero.
TH
HY
Note 8: The I-V characteristic is linear for voltages less than 1V.
Note 9: System requirement. Applies to a single device attached to a 1-Wire line.
Note 10: The earliest recognition of a negative edge is possible at t
after V has been previously reached.
REH
TH
Note 11: Defines maximum possible bit rate. Equal to 1/(t
+ t
).
W0LMIN
RECMIN
Note 12: System requirement. Interval after t
during which a bus master can read a logic 0 on IO if there is a DS28E38 present.
RSTL
The power-up presence detect pulse could be outside this interval but will be complete within 2ms after power-up.
Note 13: System requirement. ε in Figure 5 represents the time required for the pullup circuitry to pull the voltage on IO up from V to
IL
V
. The actual maximum duration for the master to pull the line low is t
+ t - ε and t
+ t - ε, respectively.
TH
W1LMAX
F
W0LMAX F
Note 14: System requirement. δ in Figure 5 represents the time required for the pullup circuitry to pull the voltage on IO up from V to
IL
the input-high threshold of the bus master. The actual maximum duration for the master to pull the line low is t
+ t .
RLMAX
F
Note 15: Current drawn from IO during a SPU operation interval. The pullup circuit on IO during the SPU operation interval should
be such that the voltage at IO is greater than or equal to V . A low-impedance bypass of R activated during the
SPUMIN
PUP
SPU operation is the recommended way to meet this requirement.
Note 16: Write-cycle endurance is tested in compliance with JESD47G.
Note 17: Not 100% production tested; guaranteed by reliability monitor sampling.
Note 18: Data retention is tested in compliance with JESD47G.
Note 19: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the
data sheet limit at operating temperature range is established by reliability testing.
Note 20: EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated
temperatures is not recommended.
Note 21: An additional reset or communication sequence cannot begin until the reset high time has expired.
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DS28E38
DeepCover® Secure ECDSA Authenticator
with ChipDNA PUF Protection
Pin Configuration
TOP VIEW
N.C. 1 +
IO 2
GND 3
6 CEXT
5 N.C.
4 N.C.
DS28E38
TDFN-EP
(3mm x 3mm)
Pin Description
DS28E38Q+
PIN
NAME
N.C.
FUNCTION
1, 4, 5
No Connection
1-Wire IO
2
3
6
IO
Ground
CEXT
Ground
Input for External Capacitor
Exposed Pad (TDFN Only). Solder evenly to the board's ground plane for proper operation. Refer to
Application Note 3273: Exposed Pads: A Brief Introduction for additional information.
–
EP
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DS28E38
DeepCover® Secure ECDSA Authenticator
with ChipDNA PUF Protection
Design Resource Overview
Detailed Description
Operation of the DS28E38 involves use of device EEPROM
and execution of device function commands. The following
provides an overview including the decrement counter.
Refer to the DS28E38 Security User Guide for details.
The DS28E38 is the first secure authenticator to integrate
the Maxim ChipDNA capability to protect all device stored
data from invasive discovery. Optionally, under user con-
trol, the ChipDNA output can also be used as the ECC-
P256 private key. In addition to the ChipDNA circuit and
ECC-P256 engines for signatures, the device integrates
a FIPS/NIST-compliant TRNG, 2Kb EEPROM for user
memory, ECC key set, control registers, and certificates.
One user page can optionally be designated as a
decrement-only counter. The device operates from a
1-Wire interface with external parasitic supply by way of
Memory
A2KbsecuredEEPROMarrayprovidesstorageoptionsfor
an ECDSA key pair and certificate, a decrement counter,
and/or general-purpose, user-programmable memory.
Depending on the memory space, there are either default
or user-programmable options to set protection modes.
an external capacitor (C ). Figure 1 shows the relation-
X
ships between the circuit elements of the DS28E38.
C
X
PARASITE
POWER
CEXT
64-BIT ROM ID
1-WIRE
INFC
&
IO
BUFFER
ECC-P256
CMD
TRNG
2kb E2 ARRAY
USER MEMORY
KEYS & CERTIFICATE
DECREMENT COUNTER
PRIVATE KEY
ChipDNA
DS28E38
Figure 1. Block Diagram
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DS28E38
DeepCover® Secure ECDSA Authenticator
with ChipDNA PUF Protection
Withinthisdiagram,thedatatransferisverifiedwhenwriting
and reading by a CRC of 16-bit type (CRC-16). The CRC-16
is computed as described in Maxim's Application Note 27:
Understanding and Using Cyclic Redundancy Checks with
Maxim 1-Wire and iButton Products.
Function Commands
After a 1-Wire reset/presence cycle and ROM function
command sequence is successful, a command start
can be accepted and then followed by a device function
command. These commands, in general, follow Figure 2.
66h
N
FROM ROM FUNCTIONS
FLOW CHART
MASTER Tx
COMMAND START
COMMAND
START?
Y
MASTER Tx INPUT
LENGTH BYTE
MASTER Tx COMMAND BYTE
MASTER Tx
PARAMETER BYTE(S)
MASTER Rx CRC-16 (INVERTED
OF COMMAND START, LENGTH,
COMMAND, AND PARAMETERS)
MASTER Tx RELEASE BYTE
N
SLAVE Rx AAh
RELEASE BYTE?
Y
DELAY WITH STRONG PULLUP
MASTER Rx FFh DUMMY BYTE
MASTER Rx OUTPUT
LENGTH BYTE
MASTER Rx RESULT BYTE
MASTER Rx DATA BYTE(S)
MASTER Rx CRC-16 (INVERTED
OF LENGTH, RESULT, AND DATA)
N
MASTER
Rx 1s
MASTER Tx
RESET?
Y
TO ROM FUNCTIONS
FLOW CHART
Figure 2. Device Function Flow Chart
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DS28E38
DeepCover® Secure ECDSA Authenticator
with ChipDNA PUF Protection
and 90.9kbps (max), respectively. The value of the pullup
resistor primarily depends on the network size and load
conditions. The DS28E38 requires a pullup resistor of
1kΩ (max) at any speed.
Decrement Counter
The optional 17-bit decrement counter can be written one
time on a dual-purpose page of memory. A dedicated
device function command is used to decrement the count
value by one with each call. Once the count value reaches
a value of 0, no additional decrements are possible.
The idle state for the 1-Wire bus is high. If for any reason
a transaction needs to be suspended, the bus must be left
in the idle state if the transaction is to resume. If this does
not occur and the bus is left low for more than 15.5μs
(overdrive speed) or more than 120μs (standard speed),
one or more devices on the bus could be reset.
1-Wire Bus System
The 1-Wire bus is a system that has a single bus master
and one or more slaves. In all instances, the DS28E38 is
a slave device. The bus master is typically a microcon-
troller. The discussion of this bus system is broken down
into three topics: hardware configuration, transaction
sequence, and 1-Wire signaling (signal types and timing).
The 1-Wire protocol defines bus transactions in terms of
the bus state during specific time slots that are initiated
on the falling edge of sync pulses from the bus master.
Transaction Sequence
The protocol for accessing the DS28E38 through the
1-Wire port is as follows:
● Initialization
● ROM Function command
● Device Function command
● Transaction/data
Hardware Configuration
The 1-Wire bus has only a single line by definition; it is
important that each device on the bus can drive it at the
appropriate time. To facilitate this, each device attached
to the 1-Wire bus must have open-drain or three-state
outputs. The 1-Wire port of the DS28E38 is open drain
with an internal circuit equivalent.
Initialization
All transactions on the 1-Wire bus begin with an initializa-
tion sequence. The initialization sequence consists of a
reset pulse transmitted by the bus master followed by
presence pulse(s) transmitted by the slave(s). The pres-
ence pulse lets the bus master know that the DS28E38 is
on the bus and is ready to operate. For more details, see
the 1-Wire Signaling and Timing section.
A multidrop bus consists of a 1-Wire bus with multiple
slaves attached. The DS28E38 supports both a standard
and overdrive communication speed of 12.5kbps (max)
V
PUP
*SEE NOTE
1-WIRE SLAVE PORT
BUS MASTER
C
X
Tx
PIOX
PIOY
CTL
Rx
R
PUP
Rx
Tx
DATA
I
L
Tx
Rx = RECEIVE
Tx = TRANSMIT
BIDIRECTIONAL
OPEN-DRAIN PORT
100Ω
MOSFET
*NOTE: USE A LOW-IMPEDANCE BYPASS OR EQUALLY DRIVE LOGIC ‘1’ WITH PIOY.
Figure 3. Hardware Configuration
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DS28E38
DeepCover® Secure ECDSA Authenticator
with ChipDNA PUF Protection
After the bus master has released the line, it goes into
1-Wire Signaling and Timing
receive mode. Now, the 1-Wire bus is pulled to V
through the pullup resistor or, in the case of a special
driver chip, through the active circuitry. Now, the 1-Wire
PUP
The DS28E38 requires strict protocols to ensure data
integrity. The protocol consists of four types of signaling
on one line: reset sequence with reset pulse and presence
pulse, write-zero, write-one, and read-data. Except for the
presence pulse, the bus master initiates all falling edges.
The DS28E38 can communicate at two speeds: standard
and overdrive. If not explicitly set into the overdrive mode,
the DS28E38 communicates at standard speed. While in
overdrive mode, the fast timing applies to all waveforms.
bus is pulled to V
through the pullup resistor. When
PUP
the threshold V
is crossed, the DS28E38 waits and
TH
then transmits a presence pulse by pulling the line low. To
detect a presence pulse, the master must test the logical
state of the 1-Wire line at t
.
MSP
Immediately after t
has expired, the DS28E38 is
RSTH
ready for data communication. In a mixed population net-
work, t should be extended to a minimum 480μs at
standard speed and a 48μs at overdrive speed to accom-
To get from idle to active, the voltage on the 1-Wire line
RSTH
needs to fall from V
below the threshold V . To get
PUP
TL
from active to idle, the voltage needs to rise from V
ILMAX
modate other 1-Wire devices.
past the threshold V . The time it takes for the voltage
TH
to make this rise is seen in Figure 4 as ε, and its dura-
Read/Write Time Slots
tion depends on the pullup resistor (R
) used and the
PUP
Data communication with the DS28E38 takes place in
time slots that carry a single bit each. Write time slots
transport data from bus master to slave. Read time slots
transfer data from slave to master. Figure 5 illustrates the
definitions of the write and read time slots.
capacitance of the 1-Wire network attached. The voltage
is relevant for the DS28E38 when determining a
logical level, not triggering any events.
V
ILMAX
Figure 4 shows the initialization sequence required to begin
any communication with the DS28E38. A reset pulse fol-
lowed by a presence pulse indicates that the DS28E38 is
ready to receive data, given the correct ROM and device
function command. If the bus master uses slew-rate control
All communication begins with the master pulling the data
line low. As the voltage on the 1-Wire line falls below
the threshold V , the DS28E38 starts its internal timing
TL
generator that determines when the data line is sampled
during a write time slot and how long data is valid during
a read time slot.
on the falling edge, it must pull down the line for t
+
RSTL
t to compensate for the edge. A t
duration of 480μs
F
RSTL
or longer exits the overdrive mode, returning the device to
standard speed. If the DS28E38 is in overdrive mode and
Master-to-Slave
t
is no longer than 80μs, the device remains in over-
RSTL
For a write-one time slot, the voltage on the data line must
drive mode. If the device is in overdrive mode and t
between 80μs and 480μs, the device resets, but the com-
munication speed is undetermined.
is
RSTL
have crossed the V
threshold before the write-one low
TH
time t
is expired. For a write-zero time slot, the
W1LMAX
voltage on the data line must stay below the V threshold
TH
MASTER Tx “RESET PULSE”
MASTER Rx “PRESENCE PULSE”
t
MSP
ε
V
PUP
V
IHMASTER
V
TH
V
TL
V
ILMAX
0V
t
t
REC
RSTL
t
F
t
RSTH
MASTER
1-WIRE SLAVE
RESISTOR (R
)
PUP
Figure 4. Initialization Procedure: Reset and Presence Pulse
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DS28E38
DeepCover® Secure ECDSA Authenticator
with ChipDNA PUF Protection
until the write-zero low time t
is expired. For the
The sum of t + δ (rise time) on one side and the internal
W0LMIN
RL
most reliable communication, the voltage on the data line
should not exceed V during the entire t or t
timing generator of the DS28E38 on the other side define
the master sampling window (t
to t
), in
ILMAX
W0L
W1L
MSRMIN
MSRMAX
window. After the V
DS28E38 needs a recovery time t
for the next time slot.
threshold has been crossed, the
which the master must perform a read from the data line.
For the most reliable communication, t should be as
TH
before it is ready
REC
RL
short as permissible, and the master should read close
to, but no later than t . After reading from the data
MSRMAX
Slave-to-Master
line, the master must wait until t
guarantees sufficient recovery time t
is expired. This
for the DS28E38
SLOT
REC
A read-data time slot begins like a write-one time slot. The
voltage on the data line must remain below V until the
TL
to get ready for the next time slot. Note that t
speci-
REC
read low time t is expired. During the t window, when
RL
RL
fied herein applies only to a single DS28E38 attached to a
1-Wire line. For multidevice configurations, t must be
responding with a 0, the DS28E38 starts pulling the data
line low; its internal timing generator determines when this
pulldown ends and the voltage starts rising again. When
responding with a 1, the DS28E38 does not hold the data
line low at all, and the voltage starts rising as soon as t
is over.
REC
extended to accommodate the additional 1-Wire device
input capacitance. Alternatively, an interface that performs
active pullup during the 1-Wire recovery time such as the
special 1-Wire line drivers can be used.
RL
WRITE-ONE TIME SLOT
t
W1L
V
PUP
V
IHMASTER
V
TH
V
TL
V
ILMAX
0V
t
F
ε
t
SLOT
MASTER
RESISTOR (R
)
PUP
WRITE-ZERO TIME SLOT
t
W0L
V
PUP
V
IHMASTER
V
TH
V
TL
V
ILMAX
0V
t
F
ε
t
REC
t
SLOT
MASTER
RESISTOR (R
)
PUP
READ-DATA TIME SLOT
t
MSR
t
RL
V
PUP
V
IHMASTER
V
TH
MASTER SAMPLING
WINDOW
V
TL
V
ILMAX
0V
t
F
δ
t
REC
t
SLOT
MASTER
1-WIRE SLAVE
RESISTOR (R
)
PUP
Figure 5. Read/Write Timing Diagrams
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DS28E38
DeepCover® Secure ECDSA Authenticator
with ChipDNA PUF Protection
long. For operational details, see Figure 6 and Figure 7.
A descriptive list of these ROM function commands fol-
lows in the subsequent sections and the commands are
summarized in Table 1.
1-Wire ROM Commands
Once the bus master has detected a presence, it can
issue one of the seven ROM function commands that the
DS28E38 supports.All ROM function commands are 8 bits
BUS MASTER Tx
RESET PULSE
FROM ROM FUNCTION FLOW PART 2
FROM DEVICE FUNCTIONS
FLOW CHART
N
OD
OD = 0
RESET PULSE?
Y
BUS MASTER Tx
SLAVE Tx
ROM FUNCTION COMMAND
PRESENCE PULSE
33h
55h
F0h
N
CCh
N
N
N
READ ROM
COMMAND?
MATCH ROM
COMMAND?
SEARCH ROM
COMMAND?
SKIP ROM
COMMAND?
TO ROM FUNCTION
FLOW PART 2
Y
Y
Y
Y
RC = 0
RC = 0
RC = 0
RC = 0
SLAVE Tx BIT 0
SLAVE Tx BIT 0
MASTER Tx BIT 0
SLAVE Tx
FAMILY CODE
(1 BYTE)
MASTER Tx BIT 0
N
N
BIT 0 MATCH?
Y
BIT 0 MATCH?
Y
SLAVE Tx BIT 1
SLAVE Tx BIT 1
MASTER Tx BIT 0
SLAVE Tx
SERIAL NUMBER
(6 BYTES)
MASTER Tx BIT 1
Y
N
N
BIT 1 MATCH?
Y
BIT 1 MATCH?
Y
SLAVE Tx BIT 63
SLAVE Tx BIT 63
MASTER Tx BIT 63
SLAVE Tx
CRC BYTE
MASTER Tx BIT 63
N
N
BIT 63 MATCH?
RC = 1
BIT 63 MATCH?
RC = 1
TO ROM FUNCTION
FLOW PART 2
FROM ROM FUNCTION FLOW PART 2
Figure 6. ROM Function Flow, Part 1
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DS28E38
DeepCover® Secure ECDSA Authenticator
with ChipDNA PUF Protection
TO ROM FUNCTION FLOW PART 1
FROM ROM
FUNCTION
FLOW PART 1
A5h
3Ch
69h
N
N
N
RESUME
COMMAND?
OVERDRIVE-
SKIP ROM?
OVERDRIVE-
MATCH ROM?
Y
Y
Y
RC = 0; OD = 1
RC = 0; OD = 1
N
RC = 1?
MASTER Tx BIT 0
Y
N
MASTER Tx
RESET?
BIT 0 MATCH?
Y
OD = 0
N
MASTER Tx BIT 1
Y
MASTER Tx
RESET?
N
N
BIT 1 MATCH?
Y
OD = 0
SLAVE Tx BIT 63
N
BIT 63 MATCH?
RC = 1
OD = 0
FROM ROM FUNCTION
FLOW PART 1
TO ROM FUNCTION FLOW PART 1
TO DEVICE FUNCTIONS
FLOW CHART
Figure 7. ROM Function Flow, Part 2
Table 1. 1-Wire ROM Commands Summary
ROM FUNCTION COMMAND
CODE
DESCRIPTION
Search ROM
F0h
33h
55h
CCh
A5h
3Ch
69h
Search for a device
Read ROM
Read ROM from device (single drop)
Select a device by ROM number
Select only device on 1-Wire
Selected device with RC bit set
Put all devices in overdrive
Match ROM
Skip ROM
Resume
Overdrive Skip ROM
Overdrive Match ROM
Put the device with the ROM in overdrive
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DS28E38
DeepCover® Secure ECDSA Authenticator
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Search ROM[F0h]
Resume [A5h]
When a system is initially brought up, the bus master
might not know the number of devices on the 1-Wire bus
or their ROM ID numbers. By taking advantage of the
wired-AND property of the bus, the master can use a pro-
cess of elimination to identify the ID of all slave devices.
For each bit in the ID number, starting with the least sig-
nificant bit, the bus master issues a triplet of time slots.
On the first slot, each slave device participating in the
search outputs the true value of its ID number bit. On the
second slot, each slave device participating in the search
outputs the complemented value of its ID number bit. On
the third slot, the master writes the true value of the bit
to be selected. All slave devices that do not match the
bit written by the master stop participating in the search.
If both of the read bits are zero, the master knows that
slave devices exist with both states of the bit. By choos-
ing which state to write, the bus master branches in the
search tree. After one complete pass, the bus master
knows the ROM ID number of a single device. Additional
passes identify the ID numbers of the remaining devices.
Refer to Application Note 187: 1-Wire Search Algorithm
for a detailed discussion, including an example.
To maximize the data throughput in a multidrop environ-
ment, the Resume command is available. This command
checks the status of the RC bit and, if it is set, directly
transfers control to the device function commands, similar
to a Skip ROM command. The only way to set the RC bit
is through successfully executing the Match ROM, Search
ROM, or Overdrive-Match ROM command. Once the RC
bit is set, the device can repeatedly be accessed through
the Resume command. Accessing another device on the
bus clears the RC bit, preventing two or more devices from
simultaneously responding to the Resume command.
Overdrive-Skip ROM [3Ch]
On a single-drop bus this command can save time by
allowing the bus master to access the device functions
without providing the 64-bit ROM ID. Unlike the normal
Skip ROM command, the Overdrive-Skip ROM command
sets the DS28E38 into the overdrive mode (OD = 1). All
communication following this command must occur at
overdrive speed until a reset pulse of minimum 480μs
duration resets all devices on the bus to standard speed
(OD = 0).
When issued on a multidrop bus, this command sets all
overdrive-supporting devices into overdrive mode. To
subsequently address a specific overdrive-supporting
device, a reset pulse at overdrive speed must be issued
followed by a Match ROM or Search ROM command
sequence. This speeds up the time for the search pro-
cess. If more than one slave supporting overdrive is pres-
ent on the bus and the Overdrive-Skip ROM command
is followed by a read command, data collision occurs on
the bus as multiple slaves transmit simultaneously (open-
drain pulldowns produce a wired-AND result).
Read ROM[33h]
The Read ROM command allows the bus master to read
the DS28E38’s 8-bit family code, unique 48-bit serial
number, and 8-bit CRC. This command can only be used
if there is a single slave on the bus. If more than one
slave is present on the bus, a data collision occurs when
all slaves try to transmit at the same time (open drain
produces a wired-AND result). The resultant family code
and 48-bit serial number result in a mismatch of the CRC.
Match ROM[55h]
The Match ROM command, followed by a 64-bit ROM
sequence, allows the bus master to address a specific
DS28E38 on a multidrop bus. Only the DS28E38 that
exactly matches the 64-bit ROM sequence responds
to the subsequent device function command. All other
slaves wait for a reset pulse. This command can be used
with a single device or multiple devices on the bus.
Overdrive-Match ROM [69h]
The Overdrive-Match ROM command followed by a 64-bit
ROM sequence transmitted at overdrive speed allows the
bus master to address a specific DS28E38 on a multi-
drop bus and to simultaneously set it in overdrive mode.
Only the DS28E38 that exactly matches the 64-bit ROM
sequence responds to the subsequent device function
command. Slaves already in overdrive mode from a previ-
ous Overdrive-Skip ROM or successful Overdrive-Match
ROM command remain in overdrive mode. All overdrive-
capable slaves return to standard speed at the next reset
pulse of minimum 480μs duration. The Overdrive-Match
ROM command can be used with a single device or mul-
tiple devices on the bus.
Skip ROM [CCh]
This command can save time in a single-drop bus system
by allowing the bus master to access the device functions
without providing the 64-bit ROM ID. If more than one
slave is present on the bus and, for example, a read com-
mand is issued following the Skip ROM command, data
collision occurs on the bus as multiple slaves transmit
simultaneously (open-drain pulldowns produce a wired-
AND result).
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DS28E38
DeepCover® Secure ECDSA Authenticator
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The DS28E38’s 1-Wire front-end has the following features:
● There is additional lowpass filtering in the circuit that
detects the falling edge at the beginning of a time
slot. This reduces the sensitivity to high-frequency
noise. This additional filtering does not apply at over-
drive speed.
Improved Network Behavior
(Switch-Point Hysteresis)
In a 1-Wire environment, line termination is possible only
during transients controlled by the bus master (1-Wire
driver). 1-Wire networks, therefore, are susceptible to
noise of various origins. Depending on the physical size
and topology of the network, reflections from end points
and branch points can add up or cancel each other to
some extent. Such reflections are visible as glitches or
ringing on the 1-Wire communication line. Noise coupled
onto the 1-Wire line from external sources can also result
in signal glitching. A glitch during the rising edge of a time
slot can cause a slave device to lose synchronization with
the master and, consequently, result in a Search ROM
command coming to a dead end or cause a device-spe-
cific function command to abort. For better performance
in network applications, the DS28E38 uses a 1-Wire front
end that is less sensitive to noise.
● There is a hysteresis at the low-to-high switching
threshold V . If a negative glitch crosses V , but
TH
TH
does not go below V - V , it is not recognized
TH
HY
(Figure 8, Case A). The hysteresis is effective at any
1-Wire speed.
● There is a time window specified by the rising edge
hold-off time t
during which glitches are ignored,
REH
even if they extend below the V - V
threshold
TH
HY
(Figure 8, Case B, t < t
). Deep voltage drops
GL
REH
or glitches that appear late after crossing the V
TH
threshold and extend beyond the t
window can-
REH
not be filtered out and are taken as the beginning of
a new time slot (Figure 8, Case C, t ≥ t ).
GL
REH
t
REH
t
REH
V
PUP
V
TH
V
HY
CASE A
CASE B
CASE C
0V
t
t
GL
GL
Figure 8. Noise Suppression Scheme
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
DS28E38Q+T
-40°C to +85°C
6 TDFN (2.5k pcs)
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
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DS28E38
DeepCover® Secure ECDSA Authenticator
with ChipDNA PUF Protection
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
6/17
Initial release
—
Updated General Description, Benefits and Features, Electrical Characteristics table,
Detailed Description, and Design Resource Overview sections
1
9/17
1, 4, 5, 7
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2017 Maxim Integrated Products, Inc.
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