MAX17509ATJ+ [MAXIM]
Dual Switching Controller, 2200kHz Switching Freq-Max, BICMOS, 5 X 5 MM, ROHS COMPLIANT, TQFN-32;
| 型号： | MAX17509ATJ+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual Switching Controller, 2200kHz Switching Freq-Max, BICMOS, 5 X 5 MM, ROHS COMPLIANT, TQFN-32 信息通信管理 开关 |
| 文件： | 总24页 (文件大小：588K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX17509
4.5V–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
General Description
Features and Benefits
● Reduces Number of DC-DC Regulators in Inventory
• Output Voltage (0.904V to 3.782V and 4.756V to
5.048V with 20mV Resolution)
The MAX17509 integrates two 3A internal switch step-down
regulators with programmable features. The device can
be configured as two single-phase independent, 3A power
supplies or as a dual-phase, single-output 6A power
supply. The device operates from 4.5V to 16V input and
generates independently adjustable output voltage in the
ranges of 0.904V to 3.782V and 4.756V to 5.048V, with
±2% system accuracy.
• Configurable Two Independent Outputs (3A/3A) or
a Dual-Phase Single Output (6A)
● Mitigate Noise Concerns and EMI
• Adjustable Switching Frequency with Selectable
0/180° Phase Shift
• External Frequency Synchronization
• Adjustable Switching Slew Rate
• Passes EN55022 (CISPR22) Class-B Radiated
and Conducted EMI Standard
This device provides maximum flexibility to the end-user
by allowing to choose multiple programmable options by
connecting resistors to the configuration pins. Two key
highlights of the device are the self-configured compen-
sation for any output voltage and the ability to program
the slew rate of LX switching nodes to mitigate noise
concerns. In noise-sensitive applications, such as high-
speed multi-gigabit transceivers in FPGAs, RF, and audio
benefit from this unique slew rate control. SYNC input is
provided for synchronized operation of multiple devices
with system clocks.
● Ease of System Design
• All Ceramic Capacitors Solution
• Auto-Configured Internal Compensation
• Selectable Hiccup or Brickwall Mode
• Adjustable Soft-Start Rise/Fall Time with Soft Stop
Modes and Prebias Startup
• -40°C to +125°C Operation
● Reliable Operation
MAX17509 offers output overvoltage (OV) and
undervoltage (UV) protection, as well as overcurrent
(OC) and undercurrent (UC) protection with a selectable
hiccup/latch option. It operates over the -40°C to +125°C
temperature range, with thermal sensing and shutdown
provided for overtemperature (OT) protection. The device
is available in a 32-pin 5mm x 5mm TQFN package.
• Robust Fault Protections (VIN_UVLO, UV/OV, UC/
OC, OT)
• Power Good
Application Circuit
MAX17509
PGOOD1, 2
AVCC
EN1, 2
SYNC
VCC
Applications
● FPGA and DSP Core Power
● Industrial Control Equipment
CVCC
V
IN
IN1
CAVCC
CIN1
AVCC
BST1
CBST1
● Multiple Point-of-Load (POL) Power Supplies
● Base Station Point-of-Load Regulator
V
OUT1
RCOARSE1
RFINE1
RSS1
L1
COARSE1
FINE1
LX1
OUT1
COUT1
Ordering Information appears at end of data sheet.
PGND1
SS1
V
IN
IN2
RCOARSE2
RFINE2
RSS2
CIN2
L2
COARSE2
FINE2
BST2
CBST2
V
OUT2
LX2
SS2
OUT2
COUT2
RMODE
PGND2
MODE
SGND
EP
19-7051; Rev 0; 2/15
MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
Absolute Maximum Ratings
IN_ to PGND_ .........................................................-0.3V to 22V
BST_ to PGND_......................................................-0.3V to 28V
BST_ to LX_..............................................................-0.3V to 6V
BST_ to VCC...........................................................-0.3V to 22V
LX_ to PGND_....... -0.3V to the lower of +22V or (VIN_ + 0.3V)
VCC to SGND ......... -0.3V to the lower of +6V or (VIN1 + 0.3V)
AVCC to SGND ....... -0.3V to the lower of +6V or (VIN1 + 0.3V)
OUT_, EN_, PGOOD_, SYNC, COARSE_, FINE_, SS_,
PGND_ to SGND....................................................-0.3V to 0.3V
EP to SGND .........................................................-0.3V to +0.3V
Operating Temperature Range..........................-40ºC to +125ºC
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65ºC to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow).......................................+260°C
MODE to SGND ....................................................-0.3V to 6V
(Note 2)
Package Thermal Characteristics
32 TQFN T3255+4
Junction-to-Ambient Thermal Resistance (θ
)
JA
Continuous Power Dissipation (T = +70°C)
32 TQFN (derate 34.5 mW/°C above +70°C)
32 TQFN......................................................................29°C/W
Junction-to-Case Thermal Resistance (θ
A
)
JC
(multilayer board) ...................................................2758.6mW
32 TQFN.....................................................................1.7°C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(V
= 10V, V
= 3.3V, CVIN_ = 1µF, CAVCC = 1µF, CVCC = 2.2µF, CBST_ = 0.1µF, T = T = -40°C to +125°C, with typical
IN_
OUT_
A
J
value at T = 25°C, unless otherwise stated) (See Typical Application Circuits) (Note 1).
A
PARAMETER
INPUT SUPPLY VIN_
IN1-2 Voltage Range
IN1 Standby Current
IN2 Standby Current
SYMBOL
CONDITIONS
MIN
4.5
TYP
MAX
UNITS
VIN_RANGE
IIN1_STBY
16
1.9
20
V
mA
µA
V
EN1-2 = SGND (shutdown)
EN1-2 = SGND (shutdown)
Rising
1
IIN2_STBY
10
4.2
3.4
VIN_UVLO_R
VIN_UVLO_F
4.0
3.2
4.4
3.6
IN1-2 Undervoltage Lockout
Falling
V
VIN_UVLO_R
5VOUT
Rising
Falling
5.8
4.1
6.0
4.3
6.2
4.5
V
V
IN1-2 Undervoltage Lockout
for V
> 4.75V
OUT
VIN_UVLO_F
5VOUT
ENABLES
EN_ Rising Threshold
EN_ Threshold Hysteresis
EN_ Input Leakage Current
LDO
EN_TH_R
EN_TH_HYS
EN_ILEAK
1242
-100
1262
250
0
1287
100
mV
mV
nA
V
= 5V, T = 25°C
A
EN
V
V
V
Output Voltage Range
Output Voltage (Dropout)
Current Capability
VCC_RANGE
VCC_DROP
I_VCC
6V < V
< 16V
4.5
V
V
CC
CC
CC
IN1
V
V
= 4.5 V, I
= 20mA
VCC
4.3
50
IN1
CC
= 4.3V, V
= 6V
mA
IN1
INTERNAL CHIP INPUT SUPPLY
AVCC_TH_R
AVCC_TH_F
Rising
Falling
3.9
V
V
AVCC UVLO
3.2
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MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
Electrical Characteristics (continued)
(VIN_ = 10V, VOUT_ = 3.3V, CVIN_ = 1µF, CAVCC = 1µF, CVCC = 2.2µF, CBST_ = 0.1µF, T = -40°C to +125°C with typical value at
A
T
= 25°C, unless otherwise stated) (See Typical Application Circuits) (Note 1).
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CONFIGURATION PINS
COARSE_, FINE_, SS_,
MODE pins Analog Resolution
#BITS_L
4
Bits
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
SYNCHRONIZATION
TW_TH
Temperature rising (Note 3)
Temperature falling (Note 3)
160
20
°C
°C
TW_HYS
SYNC Threshold Level High
SYNC Threshold Level Low
SYNC_H
SYNC_L
1.8
V
V
0.6
1.3
2.2
SYNC_FREQ1 6V < V
< 16V
0.9
0.45
30
MHz
MHz
ns
IN_
SYNC Frequency Range
SYNC_FREQ2 4.5V ≤ V
SYNC_PW
≤ 6V
IN_
Minimum SYNC Pulse Width
SYNC Pull-Down Resistance
POWER SWITCHES
High-Side RDSon
SYNC_PD
1
MΩ
HS_RON
LS_RON
For converter 1,2
For converter 1,2
50
50
90
90
mΩ
mΩ
Low-Side RDSon
V
= V – 1V, V = V
= 25°C
+ 1V,
LX
IN
LX
PGND
LX_ Leakage Current
BST_ On resistance
LX_LEAK
BST_RON
5
µA
T
A
Note: Min BST capacitance = 10nF;
= 10mA, V = 5V
4.5
Ω
I
BST
CC
OSCILLATOR
Minimum Off-Time
TOFF_MIN
Set by the internal clock. (Note 2)
< 16V
6.5
%T
SW
FREQ_RANGE1 1MHz; 6V < V
1000
kHz
IN_
Frequency Range
500kHz, 1MHz, 1.5MHz, 2MHz;
FREQ_RANGE2
500
2000
kHz
4.5V ≤ V
≤ 6V
IN_
Frequency Accuracy
FREQ_1MHZ
FREQ_ACC1
FREQ_ACC2
F
F
F
= 1MHz
969
-3.1
-4
1030
+3
kHz
%
SW
SW
SW
Frequency Accuracy Range 1
Frequency Accuracy Range 2
OUTPUT VOLTAGE
= 500kHz and 2MHz
= 1.5MHz. (Note 3)
+4
%
No load output voltage accuracy
T = 25°C; V = 0.9V;
OUT
VOUT_0.9V
VOUT_1.2V
0.8927 0.9045 0.9166
1.1750 1.1990 1.2230
V
V
4.5V < V
< 16V. COARSE_ = 0010;
IN_
FINE_ = 1101.
VOUT1-2 Output Voltage
Accuracy
No load output voltage accuracy
T = -40°C to 125°C; V
= 1.2V;
OUT
4.5V < V
< 16V COARSE_ = 0011;
IN_
Fine_ = 1100
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MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
Electrical Characteristics (continued)
(VIN_ = 10V, VOUT_ = 3.3V, CVIN_ = 1µF, CAVCC = 1µF, CVCC = 2.2µF, CBST_ = 0.1µF, T = -40°C to +125°C with typical value at
A
T
= 25°C, unless otherwise stated) (See Typical Application Circuits) (Note 1).
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
8-bit resolution over 5.048V range.
VOUT1-2 Output Voltage
Lower Range
VOUT_RANGEL LSB = ~20mV; Min_V
= 0010 1101; 0.9045
3.786
V
OUT
Max_V
= 1011 1111.
OUT
8-bit resolution over 5.048V range.
VOUT_RANGEH LSB = ~20mV; Min_V = 11xx 0000;
VOUT1-2 Output Voltage
Higher Range
4.752
30
5.048
55
V
OUT
Max_V
= 11xx 1111.
OUT
V
= 3.3V; ADDR = Disabled
= 25°C
OUT1-2
OUT_ Pull-Down Resistance
OUT_RES
42.5
kΩ
T
A
OUTPUT VOLTAGE FAULT THRESHOLDS
Overvoltage Threshold
OV_TH
UV_TH
V
V
V
V
= 0.9V
116.4
78.1
119.7
79.9
122.9 %VOUT
81.7 %VOUT
116.8 %VOUT
OUT1-2
OUT1-2
OUT1-2
OUT1-2
Undervoltage Threshold
Power Good Threshold High
Power Good Threshold Low
SOFT-START/STOP TIME
= 0.9V
= 0.9V
= 0.9V
PGOOD_H
PGOOD_L
111.8
84.0
114.6
86.1
88.1
%VOUT
SS_00
SS_01
SS_10
SS_11
0.850
3.40
1
4
1.150
4.60
ms
ms
ms
ms
Programmable Soft-Start
Time Duration
6.80
8
9.20
13.60
16
18.40
CURRENT LIMIT
Buck1,2 LS Peak Current
Limit Fault Threshold
ILIM
IRWY
#ILIM
(Note 4)
(Note 4)
3.59
4.72
4.2
5.6
7
4.7
A
A
Buck1,2 LS Runaway Current
Limit Fault Threshold
6.82
Number of Peak Current Limit
Events Before LATCHOFF
Events
Number of Runaway Current
Limit Events Before HICCUP
or LATCHOFF
#RWY
1
Event
Cycles of programmable soft-start time
before retry
Buck HICCUP Timeout
T
64
Cycles
HICCUP
Note 1: Limits are 100% tested at T = 25°C. Maximum and Minimum limits are guaranteed by design and characterization over
A
temperature
Note 2: Design Guaranteed by ATE characterization. Limits are not production tested
Note 3: Guaranteed by design; not production tested
Note 4: Current Limit and Runaway thresholds tracks in value and in temperature (see Typical Operating Characteristics section).
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MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
Typical Operating Characteristics
(CVIN_ = 10µF, CAVCC = 1µF, CVCC = 2.2µF, CBST_ = 0.1µF, f
= 1MHz, T = +25°C unless otherwise stated, default state on
A
SW
configuration setting.)
EFFICIENCY
vs. OUTPUT CURRENT
EFFICIENCY
vs. OUTPUT CURRENT
EFFICIENCY
vs. OUTPUT CURRENT
toc03
toc01
toc02
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
VOUT = 3.3V
VOUT = 3.3V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 2.5V
VOUT = 5.0V
VOUT = 5.0V
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 1.0V
VIN1 = 16V
EN2 = 0V
VIN1 = 12V
EN2 = 0V
VIN1 = 5V
EN2 = 0V
VOUT = 1.0V
VOUT = 1.0V
0
1000
2000
3000
0
1000
2000
3000
0
1000
2000
3000
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
LOAD REGULATION
LINE REGULATION
OUTPUT VOLTAGE vs. TEMPERATURE
V
OUT = 0.9V
V
OUT = 0.9V
toc04
toc06
toc05
0.9070
0.9065
0.9060
0.9055
0.9050
0.9045
0.9040
920
915
910
905
900
895
890
0.9080
0.9075
0.9070
0.9065
0.9060
0.9055
0.9050
0.9045
0.9040
VOUT MAX
IOUT = 3A
VOUT AVG
VIN = 16V
VIN = 12V
VIN = 5V
IOUT = 0A
VOUT MIN
0.0
5.0
10.0
15.0
20.0
-50
0
50
100
0.0
0.5
1.0
1.5
2.0
2.5
3.0
INPUT VOLTAGE (V)
TEMPERATURE (°C)
OUTPUT CURRENT (A)
LOAD CURRENT TRANSIENT RESPONSE
CURRENT LIMIT vs. TEMPERATURE
FREQUENCY vs. TEMPERATURE
VIN = 12V, VOUT = 1.2V, IOUT = 1.5 - 3A
toc09
toc08
toc07
6.0
5.5
5.0
4.5
4.0
3.5
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
0.95
IRWY
50mV/div
(AC
VOUT
COUPLED)
FREQ MAX
ILIM
1A/div
FREQ MIN
FREQ AVG
IOUT
VIN = 10V
VOUT = 3.3V
40µs/div
-50
0
50
100
-50
0
50
100
TEMPERATURE (°C)
TEMPERATURE (°C)
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MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
Typical Operating Characteristics (continued)
(CVIN_ = 10µF, CAVCC = 1µF, CVCC = 2.2µF, CBST_ = 0.1µF, f
= 1MHz, T = +25°C unless otherwise stated, default state on
A
SW
configuration setting.)
STARTUP/SOFTSTOP DISABLED
LOAD CURRENT TRANSIENT RESPONSE
STARTUP/SOFTSTOP DISABLED
V
IN = 12V, VOUT = 1.2V, IOUT = 0A, TSS = 4ms
V
IN = 12V, VOUT = 3.3V, IOUT = 1.5 - 3A
VIN = 12V, VOUT = 1.2V, IOUT = 3A, TSS = 4ms
toc11
toc10
toc12
EN
5V/div
EN
5V/div
200mV/div
(AC
2V/div
2V/div
PGOOD
VOUT
PGOOD
COUPLED)
500mV/div
500mV/div
VOUT
VOUT
1A/div
10V/div
LX
IOUT
10V/div
LX
2ms/div
2ms/div
40µs/div
STARTUP INTO PRE-BIAS (50% OF TARGET)
IN = 12V, VOUT = 1.2V, IOUT = 0A, TSS = 4ms
STARTUP/SOFTSTOP ENABLED
STARTUP/SOFTSTOP DISABLED
V
VIN = 12V, VOUT = 1.2V, IOUT = 0A, TSS = 4ms
V
IN = 12V, VOUT = 1.2V, IOUT = 3A, TSS = 4ms
toc15
toc14
toc13
EN
EN
5V/div
5V/div
5V/div
PGOOD
5V/div
2V/div
PGOOD
PGOOD
500mV/div
10V/div
500mV/div
500mV/div
VOUT
0V
VOUT
VOUT
LX
10V/div
10V/div
LX
LX
1ms/div
2ms/div
2ms/div
LOAD SHORT-CIRCUIT SHUTDOWN (LATCH)
STARTUP INTO PRE-BIAS (120% OF TARGET)
LOAD SHORT-CIRCUIT SHUTDOWN (HICCUP)
V
IN = 12V, VOUT = 1.2V
V
IN = 12V, VOUT = 1.2V, IOUT = 0A, TSS = 4ms
toc17
VIN = 12V, VOUT = 1.2V
toc16
toc18
PGOOD
VOUT
PGOOD
5V/div
PGOOD
VOUT
5V/div
5V/div
500mV/div
500mV/div
VOUT
500mV/div
IL
2A/div
IL
0V
LX
5A/div
10V/div
LX
10V/div
10V/div
LX
4µs/div
1ms/div
4µs/div
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MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
Typical Operating Characteristics (continued)
(CVIN_ = 10µF, CAVCC = 1µF, CVCC = 2.2µF, CBST_ = 0.1µF, f
= 1MHz, T = +25°C unless otherwise stated, default state on
A
SW
configuration setting.)
SYNCHRONIZATION vs. LX1 and LX2
LOAD SHORT-CIRCUIT RECOVERY (HICCUP)
180 OUT-OF-PHASE
V
IN = 12V, VOUT = 1.2V
toc20
toc19
CLKIN
PGOOD
5V/div
5V/div
LX1
LX2
VOUT
10V/div
10V/div
500mV/div
10V/div
LX
400ns/div
100ms/div
RADIATED EMISSIONS (EN55022 Class B)
VIN = 12V, VOUT1 = 3.3V, IOUT = 2A,
V
OUT2 = 1.2V, IOUT = 2A
toc21
Amplitude
(dBuV/m)
Frequency(MHz)
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MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
Pin Configuration
TOP VIEW
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
EN2
PGOOD2
MODE
NC
COARSE2
FINE2
SS2
SYNC
MAX17509
SS1
VCC
AVCC
SGND
PGOOD1
FINE1
COARSE1
EN1
*EP
+
1
2
3
4
5
6
7
8
TQFN
5mm x 5mm
*CONNECT EXPOSED PAD TO GND.
Pin Description
PIN
NAME
FUNCTION
Regulator 1 Feedback Regulation Point. Connect OUT1 to output of Regulator 1 to sense the
output voltage.
1
OUT1
Power Ground Connection for Regulator 1. Connect negative terminal of output capacitor and input
capacitor of Regulator 1 to PGND1. Connect PGND1 externally at a single point to SGND.
2, 3
4, 5
6, 7
8
PGND1
LX1
Inductor Connection for Regulator 1. Connect LX1 to the switched side of the inductor.
Input Supply for Regulator 1 and Internal 5V LDO. Bypass IN1 to PGND1 with a 10µF and 0.1µF
ceramic capacitor as close as possible to the device.
IN1
BST1
Regulator 1 High-Side Gate-Driver Supply. Connect a 0.1µF ceramic capacitor from BST1 to LX1.
Open-Drain Power Good Output for Regulator 1. PGOOD1 is low if OUT1 is 15% (typ) above or below
the normal regulation point. PGOOD1 asserts low during soft-start, and when the device is shut down
due to disabling or due to fault responses. PGOOD1 becomes high impedance when OUT1 is in
regulation. To obtain a logic signal, pullup PGOOD1 with an external resistor (10kΩ) connected to a
positive voltage less than 5.5V.
9
PGOOD1
Signal Ground Connection. Connect SGND to PGND_ at a single point typically near the output
capacitor ground.
10
11
12
SGND
AVCC
VCC
Input for Internal Analog Circuits. Connect a minimum of 1µF ceramic capacitor from AVCC to SGND.
Internally connected to VCC with 28Ω resistor.
Internal 5V LDO Output. it acts as low side gate driver supply. Connect a 2.2µF ceramic capacitor from
VCC to PGND_.
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MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
Pin Description (continued)
PIN
NAME
SYNC
N.C.
FUNCTION
External Clock Synchronization Input. Connect an external clock for frequency synchronization to
within 0.7 - 2.75 of the internal switching frequency with a limit of 450kHz to 2.2MHz before regulation
start for stable operation.
13
14
No Connect. Connect this pin to ground.
Mode Selection Pin. Programming input to select:
- Two Independent Outputs or Dual-phase Single Output Mode
- Phase Shift (0 or 180°)
15
MODE
- Internal Clock Frequency (500KHz/1.0MHz/1.5MHz/2MHz at 5VIN, or 1.0MHz at 12VIN)
Open-Drain Power-Good Output for Regulator 2. PGOOD2 is low if OUT2 is 15% (typ) above or below
the normal regulation point. PGOOD2 asserts low during soft-start, and when the device is shut down
due to disabling or due to fault responses. PGOOD2 becomes high impedance when OUT2 is in
regulation. To obtain a logic signal, pull up PGOOD2 with an external resistor (10kΩ) connected to a
positive voltage less than 5.5V.
16
PGOOD2
17
BST2
IN2
Regulator 2 High-Side Gate-Driver Supply. Connect a 0.1µF ceramic capacitor from BST2 to LX2.
Input Supply for Regulator 2. Bypass IN2 to PGND2 with a 10µF and 0.1µF ceramic capacitor as close
as possible to the device.
18, 19
20, 21
22, 23
LX2
Inductor Connection for Regulator 2. Connect LX2 to the switched side of the inductor.
Power Ground Connection for Regulator 2. Connect negative terminal of output capacitor and input
capacitor of Regulator 2 to PGND2. Connect PGND2 externally at a single point to SGND.
PGND2
Regulator 2 Feedback Regulation Point. Connect OUT2 to output of Regulator 2 to sense the output
voltage.
24
OUT2
Enable Pin for Regulator 2. The voltage at EN2 is compared to internal comparator reference to
determine when to enable the regulation. Pull-up to AVCC to enable Regulator 2, or optionally connect
to a resistor-divider from IN2 to EN2 to SGND to program the UVLO level. Pull EN2 to SGND to
disable the Regulator 2.
25
26
EN2
COARSE2
Regulator 2 Output Voltage Coarse Programming.
27
28
29
30
FINE2
SS2
Regulator 2 Output Voltage Fine Programming.
Regulator 2 Soft-Start/Stop Time Programming and Lx-Slew Rate Selection Pin.
Regulator 1 Soft-Start/Stop Time Programming and Overcurrent Response Selection Pin.
Regulator 1 Output Voltage Fine Programming.
SS1
FINE1
31
COARSE1
Regulator 1 Output Voltage Coarse Programming.
Enable Pin for Regulator 1. The voltage at EN1 is compared to internal comparator reference to
determine when to enable the regulation. Pull up to AVCC to enable Regulator 1, or optionally connect
to a resistor-divider from IN1 to EN1 to SGND to program the UVLO level. Pull EN1 to SGND to
disable the Regulator 1.
32
EN1
Exposed Paddle. Connect EP to a large copper plane at SGND potential to improve thermal
dissipation. Do not use EP as SGND ground connection alone.
EP
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MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
Functional Diagram
BST2
BUCK2
4.5V LDO
GENERATOR
IN2
VCC
LEVEL
SHIFT
IN_UVLO
UVLO
UVLO
AVCC
SGND
BST1
BUCK1
IN1
REF
VOLTAGE
REFERENCE
IN_UVLO
LEVEL
SHIFT
THSD
THERMAL
SHDN
LX1
LX_SLEW
VCC
CLK
OSCILLATOR
+ PLL
SYNC
PWM
CONTROL LOGIC
REGISTERS
COARSE1
COARSE1
FINE1
PGND1
OUT1
FINE1
SS1
SLOPE
CURR.
LIMIT
SS1
COMP
SS2
SS2
PWM
FINE2
ERROR
AMPLIFIER
COMPARATOR
FINE2
COARSE2
MODE
COARSE2
MODE
LOOP
COMP
g
M
REF
INTERNAL
REFIN
REF
EN1
PGOOD1
0.85
PGOOD_L
1.15
SS COMPLETE
MAX17509
PGOOD_H
REFIN
OUT1
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MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
For input voltages of less than 5.5V, connect V
and
IN1
Detailed Description
V
together to power the MAX17509 directly to increase
CC
The MAX17509 is a valley-current-mode, synchronous
pulse-width-modulated (PWM) buck regular designed to
provide either two independent 3A outputs (see Figure 1)
or a single 6A output (see Figure 2). The device operates
over an input-voltage range of 4.5V to 16V and generates
independently adjustable output voltage in the ranges of
0.904V to 3.782V and 4.756V to 5.048V in 20mV steps
with ±2% system accuracy over load, line, and tempera-
ture. The power solution can be completed using only
external resistors setting. The self-configured internal
compensation scheme allows a simple plug-and-play
solution without the need for compensation parameter
calculation.
efficiency by bypassing the internal LDO. If V
is sup-
CC
plied externally and V
< V , switching activities will
IN1
CC
be inhibited. For input voltage ranges higher than 5.5V,
use the internal regulator. Bypass V to PGND_ with
IN_
a low-ESR, 0.1µF and 10μF or greater ceramic capaci-
tor, and V with a low-ESR, ceramic 2.2μF capacitor to
CC
PGND_ placed close to the device.
Once the input bias supply rises above its UVLO rising
threshold 4.2V (typ), the regulators are allowed to regu-
late the output voltages. If the V
voltage is below the
IN_
input undervoltage lockout (VIN_UVLO) threshold 3.4V
(typ), the controller stops switching and turns off both
high-side and low-side gate drivers until the V
voltage
IN_
The MAX17509 supports a selectable switching fre-
quency of either 500kHz, 1MHz, 1.5MHz or 2MHz for
input supply rails up to 6V. For supply rails greater
than 6V, the switching frequency can be programmed
only to 1MHz. The device can be synchronized to
an external clock (see Switching Frequency/External
Synchronization/Phase Shift section for details. The
phase shift between the two regulators can be set to
either 0 or 180°. Programmable switching slew rate allows
for electromagnetic compliant optimization. For sequenc-
ing purposes, the device provides enable inputs, power
good outputs, the ability to adjust soft-start timing, and the
option to power down with soft-stop. Adjustable soft-start
reduces the inrush current by gradually ramping up the
internal reference voltage, and also powers up glitch-free
into a prebiased output. Protection features include inter-
nal input undervoltage lockout (UVLO) with hysteresis,
lossless, cycle-by-cycle current limit, hiccup-mode output
short-circuit protection, undervoltage/overvoltage protec-
tion, and thermal shutdown.
recovers. In case the 5V range output voltage is selected,
VIN_UVLO rising threshold will change in order to allow
proper start-up of the respective channel. In this case, the
VIN_UVLO_ value is 6V rising threshold and 4.3 falling
threshold. See criteria of the device to begin the regula-
tion in the Soft-Start/Soft-Stop and Prebias Condition
section.
Internal Chip Supply Input
Voltage Range (AVCC)
AVCC is the input for internal analog circuitry. The
AVCC input undervoltage lockout (AVCC_UVLO) circuitry
inhibits switching if the 4.5V AVCC supply is below its
AVCC_UVLO threshold, 3.2V (typ). Once the 5V bias sup-
ply AVCC rises above its UVLO rising threshold and EN1
and EN2 enable the buck controllers, the controllers start
switching and the output voltages begin to ramp up using
soft-start. Bypass AVCC to SGND with a low-ESR, 1μF
or greater ceramic capacitor placed close to the device.
Device Configuration from
Pin Programming
Input Supply (IN_)/Internal Linear Regulator (VCC
)
The input supply voltage (V ) is the input power supply
IN_
Power solution with MAX17509 can be configured
completely using 7 configuration pins. The configuration
pins are MODE, SS[1,2], COARSE[1,2], and FINE[1,2].
To recognize the value of resistance reliably, connect
standard 1% resistors between the configuration pins
and SGND, and keep the trace length to below 3cm to
minimize the trace capacitance. These pins are read
once when the voltage on AVCC is above AVCC_TH_R.
The pins are re-read when AVCC rises above AVCC_
TH_R after dropping below AVCC_TH_F. There is a fixed
2ms total time (typ.) required for device configuration.
EN_ signals are ignored during this time, and switching
activity is only allowed to occur subsequently.
for internal regulators, which support a voltage range from
4.5V to 16V. In addition, it has an internal linear regulator
(V ) to provide its own bias from a high-voltage input
CC
supply at V . V
bias supply provides up to 50mA
IN1
CC
typical total current directly for gate drivers for the internal
MOSFETs, and through AVCC pin for the analog control-
ler, reference, and logic blocks. The linear regulator has
an overcurrent threshold of approximately 150mA. In case
of an overcurrent event on V , the current is limited, and
CC
V
CC
voltage starts to droop.
At higher input voltages (V ) of 5.0V to 16V, V
is reg-
IN1
CC
ulated to 4.5V. At 5.0V or below, the internal linear regu-
lator operates in dropout mode, where V
follows V
.
CC
IN1
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MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
MODE pin chooses between single-phase (two outputs)
and dual-phase (one output), sets the relative phase-shift
of the PWM between two regulators, and sets the internal
switching frequency. SS1 chooses between brickwall/
latchoff and hiccup for the OCP behavior of both regula-
tors, and enables/disables soft-stop along with soft-start/
stop time for Regulator 1. SS2 chooses between maxi-
mum and minimum Lx-slew rate for both regulators, and
enables/disables soft-stop along with soft-start/stop time
for Regulator 2. MODE, SS[1,2], COARSE[1,2], and
FINE[1,2] have 16 possible selections.
Table 1. The table also shows a correspondence between
the resistor values to the index numbers. Pin strapping
takes three possible stages: V , OPEN, GND. V
CC
CC
and OPEN provide the same setting result. The resistor
value for each pin is independent from each other, and
Table 2 show examples of a few scenarios of the settings.
The details of the each functional behavior are described
in the corresponding sections subsequently.
The configuration pins can respond to both pin strapping
and resistor programming, and the settings summarized in
Table 1. Summary of Resistor Programming
INDEX 1% RES.
MODE
SS1
SS2
COARSE_
FINE_
PHASE
SHIFT
TSS1 LX-
(ms) SLEW
TSS2 COARSE
FINE
VOUT (V)
(kΩ)
MODE
FSW
OC
SSTOP1
SSTOP2
(ms)
VOUT (V)
475
0
(OPEN or
VCC)
500kHz
1
1
0.000
0.650
180°
1
2
200
115
75
1.0MHz
1.5MHz
2.0MHz
500kHz
1.0MHz
1.5MHz
2.0MHz
500kHz
1.0MHz
1.5MHz
2.0MHz
4
8
4
8
0.019
0.037
0.057
0.078
0.097
0.115
0.135
0.157
0.176
0.194
0.213
3
16
1
16
1
0.966
1.281
1.597
1.912
2.228
2.543
2.859
3.174
3.490
4
53.6
40.2
30.9
24.3
19.1
15
5
4
4
0°
6
8
8
7
16
1
16
1
8
9
4
4
10
11
11.8
9.09
8
8
16
16
4.756
(7V VIN)
12
13
14
15
6.81
4.75
3.01
GND
500kHz
1.0MHz
1.5MHz
2.0MHz
1
4
1
4
0.235
0.254
0.272
0.291
180°
4.756
(9V VIN)
4.756
(12V VIN)
8
8
4.756
(16V VIN)
16
16
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MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
Table 2. Examples of Resistor Programming
SETTINGS
MODE
SS1
SS2
COARSE1 FINE1 COARSE2 FINE2
MODE = Single-Phase (Two Outputs),
180° Phase-Shift, 1MHz
SS1 = Hiccup OCP,
Soft-Stop 1 Disabled,
Soft-Start Time 1 = 8ms
SS2 = Maximum Lx-Slew Rate,
Soft-Stop 2 Enabled,
200kΩ
11.8kΩ
24.3kΩ
3.01kΩ
4.75kΩ
75kΩ
6.81kΩ
Soft-Start Time 2 = 16ms
Note: 12VIN
VOUT1 = 5.0V (4.756V + 0.254V)
VOUT2 = 1.2V (0.966V + 0.235V)
MODE = Dual-Phase (Single Output),
180° Phase-Shift, 2.0MHz
SS1 = Brickwall and Latchoff OCP,
Soft-Stop 1 Disabled,
9.09kΩ
200kΩ
GND
40.2kΩ
11.8kΩ
40.2kΩ
11.8kΩ
Soft-Start Time 1 = 4ms
SS2 = Minimum Lx-slew Rate
VOUT = 1.8V (1.597V + 0.194V)
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MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
EN_
A regulator allows to start the regulate output voltage
when the voltage on EN_ is above EN_TH_R level of
1.262V (typ.) after device configuration from pin program-
ming is complete. EN_ below EN_TH_F results in regula-
tor disable.
IN_
IN_
RU
MAX17509
To configure the device to self-enable when input
voltage is sufficient, pull EN_ to AVCC. Optionally, to
set the voltage at which the device turns on from VIN,
connect a resistive voltage-divider from IN_ to GND
(Figure 1) with the center node of the divider to EN_.
EN_
RB
Choose R to be 10k - 100kΩ, and then calculate R as:
U
B
1.262
−1.262
R
= R ×
U
B
V
INU
Figure 1. Adjustable EN network
where V
is the voltage at which the device is required
INU
to turn on. For adjustable output voltage devices, ensure
that IN_ is higher than 0.93 x V
sinking current from the output. In the case of starting from
an initial output voltage above target, the device smoothly
discharges the output voltage by decreasing the internal
reference voltage down to 0V in 512µs, and then initiates
the soft-start sequence. During this discharge period, the
negative current limit is gradually increased to allow up to
4.2A of negative current to prevent a sudden dip in output
voltage. During the follow soft-start sequence, the device
ramps up the internal reference to the target level with
both high-side and low-side switches activated.
.
OUT
Soft-Start/Soft-Stop and Prebias Condition
Once a regulator is enabled by driving the corresponding
EN_ above EN_rising threshold, the soft-start circuitry
gradually ramps up the reference voltage during soft-start
time to reduce the input surge currents during startup.
The device controls switching activities to have only
positive inductor current, and then gradually transition to
PWM mode at the end of soft-start. Before the device can
begin the soft-start, the following conditions must be met:
With soft-stop option, when the device is disabled the
soft-stop circuitry gradually ramps down the reference
voltage with the same time as soft-start timing to dis-
charge the remaining energy in the output capacitor in
a controlled manner. During a soft-stop event, faults are
masked as during start-up, and no hiccup will occur after
a fault even though hiccup is set. To ensure a proper soft-
stop sequence the device must be in PWM mode. This
requires the duration of the EN_ signal to be longer than
the soft-start time. Soft-stop should be used for two-inde-
pendent-output configuration only, and not in dual-phase,
single-output mode.
1) AVCC_ exceeds the 3.9V (max) AVCC rising thresh-
old (AVCC_TH_R).
2) Reading of pin configuration is complete.
3) IN_ exceeds the 4.4V (max) IN undervoltage lockout
threshold (VIN_UVLO_R).
4) EN_ exceeds the 1.3V (max) EN rising threshold
(EN_TH_R).
5) The device temperature is below 160°C thermal
shutdown threshold.
SS_ pins are used to select the soft-start timing among 1,
4, 8, and 16ms, as well as to enable the soft-stop option.
The default setting will be 8ms soft-start timing, and soft-
Switching Frequency/External
Synchronization/Phase Shift
The MAX17509 supports a selectable switching frequen-
cy of either 500kHz, 1MHz, 1.5MHz, or 2MHz for input
supply rails up to 6V. For supply rails greater than 6V, the
switching frequency can be programmed only to 1MHz.
High-frequency operation optimizes the application for
the smallest component size, lower output ripple, and
improve transient response, but trading off efficiency to
higher switching losses. Low-frequency operation offers
stop disabled. For V
soft-start time.
≥ 2.5V, use a minimum of 4ms
OUT
There are two scenarios for startup sequence depending
on the initial output voltage. During both scenarios, UV
and OV are disabled, and overcurrent protection oper-
ates in brickwall mode (±4.2A). In the case that the device
starts from an initial output voltage below the target, the
device will not cause the output voltage to dip down by not
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MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
the best overall efficiency at the expense of component
size and board space. The device also offers the option to
set the relative PWM phase-shift between the regulators
to be in-phase (0°) or interleave (180° out-of-phase). With
in-phase setting, Regulator 2’s low-side MOSFET turn
on at the same time as Regulator 1. With out-of-phase
setting, the Regulator 2’s low-side MOSFET turns on with
a time delay corresponding to half of the switching period.
The instantaneous input current peaks of both regulators
do not overlap, resulting in reduced RMS ripple current
and input voltage ripple. This reduces the required input
capacitor ripple current rating, allows for fewer or less
expensive capacitors, and reduces shielding requirements
for electromagnetic interference (EMI). A resistor on the
MODE pin allows the user to set the desired switching
frequency, phase shift, and independent output/dual-
phase operation.
pull-down to GND for minimum. The OCP behavior is
recommended to be set to brickwall and latchoff option.
The operation and functional behavior (startup/shutdown,
regulation, fault responses) will be uniform between the
two phases.
Output Voltage Setting (COARSE_ and FINE_)
and Sensing (VOUT_)
COARSE_ and FINE_ pins set the output range of each
regulator in MAX17509 in 20mV steps from 0.904V to
3.782V and 4.756V to 5.048V provided that the input
voltage is higher than the desired output voltage by an
amount sufficient to prevent the device from exceeding
its maximum duty cycle specification. VOUT_ senses the
output voltage feedback used for output voltage monitor-
ing and fault detection. Connect VOUT_ directly to the
point of regulation
The target output voltage is achieved by the sum of
coarse voltage (COARSE_) and an offset (FINE_). The
resistor value can be found from cross-referencing the
index number to the resistor value on Table 1. For a
target output voltage between 0.904V to 3.782V, the index
of the two resistors can be found from (Equations 2 and
The device can be synchronized to an external clock
by connecting the external clock signal to SYNC with
frequency within 900kHz to 1.3MHz before regulation start
forastableoperationfor1.0MHzinternalswitchingfrequency
at 12V range, and within 0.7 - 2.75 of the internal switching
IN
frequency with a limit of 450kHz to 2.2MHz for 5V range.
IN
3) with a minimum V
of 0.904V. For 4.756V to
COARSE
With lower switching frequency, the pre-set peak current
limit tends to make the effective DC current limit lower
due to higher inductor peak current, but this can be com-
pensated by choosing higher inductance value. Regulator
1’s high-side MOSFET turning off with a time delay
corresponding to 58% of the switching period (210°) with
respect to the rising edge of SYNC signal, and Regulator
2’s high-side MOSFET turning on depends on the
relative phase-shift setting. The minimum external clock
pulse-width high should be greater than 30ns.
5.048V, COARSE_ resistor is selected based on input
voltage with index from 12 to 15, and FINE_ resistor can
be found from (Eq.3), where V
is 4.756V.
OUTCOARSE
Table 3 shows resistor setting for typical output voltages.
5.048
256
V
=
16×Index
+1+ Index
COARSE FINE
OUT
(Equation 1) for 0.904V ≤ V
≤ 3.782V, min.
OUT
Index
= 2
COARSE
Single and Dual-Phase mode
256× V
1
MODE pin is used to configure MAX17509 to produce two
single-phase independent outputs or a dual-phase single-
output regulator. In single-phase mode, the component
selection and operation of each phase is independent
from each other.
OUT
Index
= Integer
−1
COARSE
16
5.048
(Equation 2) for 0.904V < V
< 3.782V
OUT
256
In dual-phase mode, the two phases operate to supply a
shared output current up to 6A with 180° relative phase
shift of PWM. The inductor selection must be the same,
and EN_ should be connected together. The configura-
tion of both phases is determined by that of Regulator 1
(OC, SSTOP, TSS, COARSE1, FINE1). SS2 is still needed
to set Lx-slew of both phases with the option to use only
Index
= Integer
V
− V
FINE
OUT
OUTCOARSE
5.048
(Equation 3)
pin strapping: pull-up to
V
CC
for maximum Lx-slew and
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MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
three types current fault events. Peak positive current
Table 3. V
Voltages
Setting for Common Output
OUT
limit can occur when the load demand is greater than the
regulator capability (overloading). Valley negative current
limit can occur when the regulator sinks current, where
the device draws the energy back from the output, such
as during soft-start from above target output voltage level
or soft-stop. OCR can occur when the output is short to
ground, and the cycle-by-cycle switching results in a rapid
increase in current without sufficient voltage across induc-
tor to properly discharge. OCR current limit is declared
when the current level reached 5.6A (typ), and the
regulator shuts immediately similar to fault response due to
output undervoltage (UV) or output overvoltage (OV)
events.
COARSE FINE
COARSE
FINE
V
(V)
OUT
INDEX
INDEX RESISTOR RESISTOR
0.9
1.0
1.2
1.5
2.0
2.5
3.0
3.3
2
3
13
2
115k
75k
4.75k
115k
3
12
11
5
75k
6.81k
9.09k
40.2k
3.01k
24.3k
24.3k
4
53.6k
30.9k
24.3k
15.0k
11.8k
6
7
14
7
9
10
7
SS1 pin sets options to attempt regulation following those
fault event(s), in addition to fault response due to UC/
OC protection. The two options for fault response due to
UC/OC protection are (1) Hiccup and (2) Brickwall and
Latchoff.
5.0 (7V V
5.0 (9V V
)
)
12
13
14
15
6.81k
4.75k
3.01k
GND
IN
IN
13
4.75k
5.0 (12V V
5.0 (16V V
)
)
IN
IN
With Hiccup setting, the UC/OC current fault protection
is set to shut down immediately, which implies that the
regulators shut down immediately after UC/OC/OCR/UV
or OV occurs. An UC or OC event is declared after the
device sensed seven consecutives peak positive current
limit above 4.2A (typ), or consecutives valley negative
undercurrent limit below -4.2A (typ). Subsequently, the
regulator attempts a soft-start sequence after the Hiccup
timeout period expired, which corresponds to the 64
times period set for soft-start time. This allows the over-
load current to decay due to power loss in the converter
resistances, load, and the inductor before soft-start is
attempted again.
High-Side Gate-Driver Supply (BST_)
The high-side MOSFET is turned on by closing an inter-
nal switch between BST_ and DH_ and transferring the
bootstrap capacitor’s (at BST_) charge to the gate of the
internal high-side MOSFET. This charge refreshes when
the high-side MOSFET turns off and the LX_ voltage
drops down to ground potential, taking the negative ter-
minal of the capacitor to the same potential. At this time,
the bootstrap diode recharges the positive terminal of the
bootstrap capacitor. The boost capacitor should be a low-
ESR ceramic capacitor with a minimum value of 100nF.
Adjustable Switching Slew Rate
With Brickwall and Latchoff setting, the current fault
protection is set to constant current mode. The device
attempts to provide continuous output current limited by
peak positive current-limit (4.2A typ) in current-sourcing
event, while in a current-sinking event it attempts to con-
tinuously sink current limited by valley negative undercur-
rent limit (-4.2A typ). With this setting UC/OC status is
latched, and the switching activities continue until OCR/
UV/OV/OT or disable event(s) occur. If a shutdown due
to an OCR/UV or OV event occurs, the regulator remains
shutdown until the EN_ input is toggled.
Reducing the LX switching transition time has the ben-
efit of improved efficiency; however, the fast slewing
of the LX slew nodes results in relatively high radiated
EMI. MAX17509 has the ability to program the slew rate
of LX switching nodes to address noise requirements
in sensitive applications such as multi-GB transceiver
supplies in FPGA applications. SS2 pin can set Lx-slew
rate of both regulators to be either the maximum (5V/ns)
or minimum value (0.25V/ns).
Current Protections (UC/OCP/OCR) and Retry
Setting (Hiccup vs. Brickwall and Latchoff)
During current-sinking, the input voltage can increase
since the energy is delivered back to the input. It is rec-
ommended to monitor the input voltage to ensure that it
is below the device’s limit. In an application where the
load is inductive, the output could swing negatively below
ground when it is suddenly shorted to ground. In order
to withstand such a stress it is recommended to place
The current protection circuit monitors the output cur-
rent levels through both internal high-side and low-side
MOSFETs during all switching activities to protect them
during overload and short-circuit conditions. Peak posi-
tive current limit (OC), valley negative undercurrent limit
(UC), and positive runway overcurrent (OCR) limit are
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MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
a 50Ω series resistor close to the IC from OUT_ to the
regulation point.
Design Procedure
Input Voltage Range
The maximum value (V
Output Overvoltage Protection (OVP)
) and minimum value
IN (MAX)
The MAX17509 includes an output overvoltage protection
(OVP) circuit that begins to monitor the output through
VOUT_ pin once the soft-start is complete. If the output
voltage rises above 120% (typ) of its nominal regula-
tion voltage, the regulator shuts down. The subsequent
response depends on retry setting.
(V
) must accommodate the worst-case conditions
IN (MIN)
accounting for the input voltage soars and drops. If there
is a choice at all, lower input voltages result in better
efficiency. With a maximum duty cycle of 93%, V
is
OUT
limited to 0.93 x V .
IN
Input Capacitor Selection
The input capacitor must meet the ripple current require-
ment (I ) imposed by the switching currents. The
Output Undervoltage Protection (UVP)
The MAX17509 includes an output undervoltage pro-
tection (UVP) circuit that begins to monitor the output
through VOUT_ pin once the soft-start is complete. If the
output voltage drops below 80% (typ) of its nominal regu-
lation voltage, the regulator shuts down. The subsequent
response depends on retry setting.
RMS
I
requirements of the regulator can be determined by
RMS
the following equation:
IRMS = IOUT
/V is the duty ratio of the controller.
×
D ×(1− D)
where D = V
OUT IN
Over Thermal Protection
The worst-case RMS current requirement occurs when
operating with D = 0.5. At this point, the above equation
simplifies to I
The MAX17509 features a thermal-fault protection circuit.
When the junction temperature rises above +160°C (typ),
a thermal sensor activates, pulls down the PGOOD out-
puts, and shuts down both regulators. The regulators are
allowed to restart after the junction temperature cools by
20°C (typ).
= 0.5 x I
.
RMS
OUT
The minimum input capacitor required can be calculated
by the following equation,
I
(
×(1− D)
)
IN_AVG
C
=
Power Good Output (PGOOD_)
IN
∆V ×F
(
)
IN
SW
PGOOD_ is an open-drain output of the window compara-
tor that continuously monitors output voltage. Effectively,
it indicates fault conditions, including UV/OV of output
voltage, OCR of regulators’ current, and OT. PGOOD_
can be used to enable circuits that are supplied by the
corresponding voltage rail, or to turn on subsequent supplies.
Where,
I
is the average input current given by,
IN_AVG
P
OUT
I
=
IN_AVG
η× V
IN
Each PGOOD_ goes high (high impedance) when the
corresponding channel has completed soft-start, regulator
output voltage is in regulation. Each PGOOD_ goes low
when the corresponding regulator output voltage drops
below 15% (typ) or rises above 15% (typ) of its nominal
regulated voltage. PGOOD_ asserts low during soft-start,
soft-stop, fault conditions, and when the corresponding
regulator is disabled. Connect a 1k – 100kΩ (10kΩ, typ)
pullup resistor from PGOOD_ to the relevant logic rail to
level-shift the signal. PGOOD pins cannot sink more than
10mA of current.
D is the operating duty cycle, which is approximately
equal to V /V
OUT IN
∆V is the required input voltage ripple
IN
f
is the operating switching frequency
SW
P
is the out power, which is equal to V
x I
OUT
OUT OUT
η is the efficiency.
For the MAX17509 system (IN_) supply, ceramic capaci-
tors are preferred due to their resilience to inrush surge
currents typical of systems, and due to their low parasitic
inductance, which helps reduce the high-frequency ring-
ing on the IN supply when the internal MOSFETs are
turned off. Choose an input capacitor that exhibits less
than +10°C temperature rise at the RMS input current
for optimal circuit longevity. A 10µF works well in general
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MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
application. Place an additional 0.1µF between IN_ and
PGND_ as close to the device as possible.
V
V
− V
(
)
OUT SUP OUT
∆I
=
INDUCTOR
V
× f
×L
SUP SW
Inductor Selection
Three key inductor parameters must be specified for
operation with the MAX17509: inductance value (L),
where ΔI
is in mA, L is in μH, and f
is in kHz
INDUCTOR
SW
The inductor specification must be large enough not
to saturate at the peak inductor current (I ), or at
inductor saturation current (I
), and DC resistance
SAT
PEAK
(R
). To select inductance value, the ratio of induc-
least in a range where the inductance does not degrade
significantly. The maximum inductor current equals the
maximum load current in addition to half of the peak-
to-peak ripple current. The runaway peak current limit
(5.6A) can be used directly for the inductor saturation
current specification of a conservative system design.
DCR
tor peak-to-peak AC current to DC average current (LIR)
must be selected first. MAX17509 is optimally designed
to work with 30% peak-to-peak ripple current to average-
current ratio (LIR = 0.3). The switching frequency, input
voltage, output voltage, and selected LIR then determine
the inductor value as follows:
∆I
INDUCTOR
2
I
= I
+
LOAD(MAX)
PEAK
V
V
− V
(
)
OUT SUP(MIN)
OUT
L =
V
× f
×I
×LIR
SUP(MIN) SW OUT(MAX)
Table 4 summarizes the optimal inductor and output
capacitor value selection for typical 5V and 12V
range. The requirement is to select an inductor greater
than or equal to the value shown, and output capacitor
the same actual value (not nominal value) or higher. The
components listed optimize the transient response time
IN
IN
where V
is the minimum supply voltage, V
is
SUP(MIN)
the typical output voltage, and I
OUT
is the maximum
OUT(MAX)
is the switching frequency. However, if it
load current.
f
SW
is necessary, higher inductor values can be selected.
For the selected inductance value, the actual peak-to-
and set bandwidth to be f /8.
SW
peak inductor ripple current (ΔI
) is defined by:
INDUCTOR
Table 4. Optimal Inductor and Output Capacitor Selection
6 ≤ V ≤ 16V
IN
4.5V ≤ V ≤ 6V
IN
(TYPICAL 12V
IN
(TYPICAL 5V RANGE)
IN
RANGE DOWN TO 6V
)
IN
V
(V)
OUT
F
= 500KHZ
F
= 1MHZ
F
= 1.5MHZ
F
= 2MHZ
F
= 1MHZ
SW
SW
SW
SW
SW
L
(µH)
C
L
(µH)
C
L
(µH)
C
L
(µH)
C
L
MIN
(µH)
MIN
OUTMIN
(µF)
MIN
OUTMIN
(µF)
MIN
OUTMIN
(µF)
MIN
OUTMIN
(µF)
C
(µF)
OUTMIN
0.9
1
2.2
2.2
2.7
3.3
3.9
3.9
4.7
4.7
3.3
2.7
139
107
89
71
59
54
43
36
36
36
1
100
82
68
55
46
41
33
18
18
18
0.82
0.82
1
78
55
46
36
30
27
22
12
12
12
0.56
0.56
0.68
0.82
0.82
1
50
41
34
27
23
21
16
9
1
100
82
68
55
46
41
33
18
18
18
1.2
1.2
1.5
1.8
2.2
2.2
2.2
1.5
1.5
1.2
1.2
1.5
1.8
2.2
2.2
2.2
2.2
2.7
1.2
1.5
1.8
2
1
1.2
1.2
1.5
1.5
1.2
1.2
2.5
3
1.2
1.2
3.3
3.6
0.82
0.82
9
9
5.0 (7V
5.0 (9V
)
)
1.8
2.7
18
18
IN
IN
(NOT APPLICABLE)
5.0 (12V
5.0 (16V
)
3.9
4.7
18
18
IN
)
IN
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MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
With ceramic capacitors, the ripple voltage due to capaci-
tance dominates the output ripple voltage. Therefore
the minimum capacitance needed with ceramic output
capacitors is,
Output Capacitor Selection
The output capacitor selection requires careful evaluation
of several different design requirements – DC voltage
rating, stability, transient response, and output ripple
voltage. Based on these requirements, a combination of
low-ESR polymer capacitor (lower cost but higher output-
ripple voltage) and ceramic capacitor (higher cost but low
output-ripple voltage) should be used to achieve stability
with low output ripple.
∆I
1
L
C
=
×
OUT
8× f
V
RIPPLE
SW
Alternatively, combining ceramics (for the low ESR) and
polymers (for the bulk capacitance) helps balance the
output capacitance vs. output ripple voltage requirements.
When choosing the ceramic capacitors, it is recommended
to choose the X5R and X7R dielectric formulations,
since the dielectrics have the best temperature and
voltage characteristics of all the ceramics for a given
value and size. It is important to note that the capaci-
tance decreases as the voltage applied increases; thus
a ceramic capacitor rated at 47µF 6.3V may measure
47µF at 0V but measure 34µF with an applied voltage of
3.3V depending on the type of capacitor selected. Consult
capacitor manufacturer datasheet for the derating.
Load Transient Response
The load transient response depends on the overall out-
put impedance over frequency, and the overall amplitude
and slew rate of the load step. In applications with large,
fast load transients (load step > 80% of full load and slew
rate > 10A/μs), the output capacitor’s high-frequency
response–ESL and ESR–needs to be considered. To
prevent the output voltage from spiking too low under a
load-transient event, the ESR is limited by the following
equation (ignoring the sag due to finite capacitance):
Loop Compensation
The simplified equation for minimum capacitor is shown
V
in the table below, where f
is the switch frequency in
RIPPLESTEP
SW
R
≤
ESR
MHz, and C
is the output capacitor in (µF). It is rec-
∆IOUTSTEP
OUT
ommended to use all ceramic output capacitor solution,
so that the ESR is placed such that the zero frequency
formed by output capacitor and ESR is at or above f /2.
Table 5. Simplified Equation for
Minimum Output Capacitor Requirement
SW
Output Ripple Voltage
FREQUENCY
PROGRAMMED
(V)
With polymer capacitors, the ESR dominates and deter-
mines the output ripple voltage. The step-down regulator’s
V
OUT
500kHz 1MHz
107/ V
1.MHz
2MHz
x V
0.904 to 2.839
2.859 to 5.048
82/(f
)
OUT
output ripple voltage (V
) equals the total inductor
OUT
SW
RIPPLE
ripple current (ΔI ) multiplied by the output capacitor’s
18/f
L
SW
ESR. Therefore, the maximum ESR to meet the output
ripple voltage requirement is:
where V
is the allowed voltage drop during
RIPPLESTEP
V
load current transient, I
current step.
is the maximum load
OUTSTEP
RIPPLE
R
≤
ESR
∆I
L
The capacitance value dominates the mid frequency
output impedance and continues to dominate the load
transient response as long as the load transient’s slew
rate is fewer than two switching cycles. Under these
conditions, the sag and soar voltages depend on the
output capacitance, inductance value, and delays in the
transient response. Low inductor values allow the induc-
tor current to slew faster, replenishing charge removed
from or added to the output filter capacitors by a sudden
load step, especially with low differential voltages across
where,
where f
V
− V
L
V
OUT
1
IN
OUT
∆I
=
×
×
L
V
f
IN SW
is the switching frequency and L is the Inductor.
SW
The actual capacitance value required relates to the
physical case size needed to achieve the ESR require-
ment, as well as to the capacitor chemistry. Thus, polymer
capacitor selection is usually limited by ESR and voltage
rating rather than by capacitance value.
the inductor. The sag voltage (V
) that occurs after
SAG
applying the load current can be estimated as:
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MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
If the application has a thermal-management system that
2
ensures that the devices’ exposed pad is maintained at a
given temperature (T ) by using proper heatsinks,
L × ∆IOUT
×D
1
2
STEP
1
EP_MAX
V
− V
OUT
C
=
×
(
)
IN
MAX
OUT_SAG
then the junction temperature rise can be estimated
at any given maximum ambient temperature from the
following equation:
V
SAG
+ ∆IOUT
(
× (T
− ∆T)
)
STEP
SW
Where
T
= T
+ (θ x P
)
J_MAX
EP_MAX
JC
LOSS
D
is the maximum duty factor (93%),
where,
P
MAX
T
is the switching period (1/f
)
is the maximum allowed power losses with
SW
SW
LOSS
maximum allowed junction temperature
ΔT equals V
/V x T
OUT IN SW
T
is the maximum allowed Junction temperature
J_MAX
The amount of overshoot voltage (V ) that occurs
SOAR
after load removal (due to stored inductor energy) can be
calculated as:
T is operating ambient temperature
A
θ
JA
θ
JC
is the junction-to-ambient thermal resistance
is the junction-to-case thermal resistance
2
∆IOUT
L
(
=
)
STEP
C
OUT_SOAR
2V
V
OUT SOAR
When the MAX17509 is operating under low duty cycle
the output capacitor size is usually determined by the
C
.
OUTSOAR
Power dissipation
Ensure that the junction temperature of the device
does not exceed +125ºC under the operating conditions
specified for the power supply.
At a particular operating condition, the power losses that
lead to temperature rise of the part are estimated as
follows:
1
PLOSS = (POUT x ( -1) - (IOUT2 x RDCR
)
POUT = VOUT x IOUT
is the total output power, η is the efficiency
where P
OUT
of the converter, and R
is the DC resistances of
DCR
the inductor (see the Typical Operating Characteristics
for more information on efficiency at typical operating
conditions.)
For a multilayer board, the thermal-performance metrics
for the package are given below:
θ
= 29°C/W
= 1.7°C/W
JA
θ
JC
The junction temperature rise of the devices can be
estimated at any given ambient temperature (T ) from the
A
following equation:
T
= T + (θ x P
)
J_MAX
A
JA
LOSS
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MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
●
●
Connect EP to SGND plane, and connect to PGND_
at a single point typically at the output capacitor
ground.
PCB Layout Guidelines
Careful PCB layout is critical to achieving low switching
losses and clean, stable operation. Use the following
guidelines for good PCB layout shown in Figure 4. The
layout of Regulator 2 can be achieved by applying the
recommended layout of Regulator 1 symmetrically.
Keep the power traces and load connections short.
This practice is essential for high efficiency. Using
thick copper PCBs (2oz vs. 1oz) can enhance full
load efficiency. Correctly routing PCB traces is a
difficult task that must be approached in terms of
fractions of centimeters, where a single milliohm of
excess trace resistance causes a measurable ef-
ficiency penalty.
●
Keep the bypass capacitors as close as possible to
the pins and the return path (1) VIN_ and PGND_
pins, (2) VCC and PGND_ pins, (3) OUT side of the
inductor and PGND_ pins, (4) BST_ and LX_ pins,
and (5) AVCC and SGND pin.
●
Use multiple vias to connect internal PGND_ planes
(not shown) to the top layer PGND_ plane. Connect
PGND1 and PGND2 together to become PGND
using large copper plane.
●
●
Route high-speed switching nodes (BST_ and LX_)
away from sensitive analog areas (OUT_, AVCC).
Connect resistors between device configuration pins
and SGND, and keep the trace length to below 3cm
to minimize the trace capacitance
L1
VOUT1
LX1
LX1
PGND
COUT1
OUT2
OUT1
PGND1
PGND1
LX1
PGND2
PGND2
LX2
PGND
IN1
LX2
LX1
CIN1
IN2
IN1
IN2
IN1
CBST1
BST2
BST1
VIAS TO BOTTOM-SIDE PGND PLANE
VIAS TO BOTTOM-SIDE LX1
VIAS TO BOTTOM-SIDE SGND
PGND
TOP LAYER
BOTTOM LAYER
Figure 4: Recommended Layout
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MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
Typical Application Circuits
SGND
AVCC
AVCC
PGND1
PGND2
PGND2
32 31 30 29
27 26 25
EP
28
SGND
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
OUT2
OUT1
PGND2
PGND2
LX2
PGND1
PGND1
PGND1
LX1
L1
L2
VOUT1
VOUT2
MAX17509
COUT1
PGND1
COUT2
PGND2
LX2
LX1
IN1
IN2
IN2
VIN1
IN1
VIN2
CIN2
CIN1
BST1
BST2
CBST2
CBST1
PGND1
PGND2
9
10 11 12 13 14 15 16
PGND2
PGND1
AVCC
PGND1 SGND
SGND
PGND2
SGND
SGND PGND1
SGND
SGND
Figure 5: Two Independent Outputs
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MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
Typical Application Circuits (continued)
VOUT
COUT
PGND
SGND
AVCC
AVCC
32 31 30 29
27 26 25
EP
28
SGND
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
OUT2
OUT1
PGND2
PGND2
LX2
PGND1
PGND2
PGND1
PGND1
LX1
L1
L2
MAX17509
LX2
LX1
IN1
IN2
IN2
VIN
IN1
VIN
CIN2
CIN1
BST1
BST2
CBST2
CBST1
PGND1
PGND2
9
10 11 12 13 14 15 16
PGND2
PGND1
AVCC
PGND
PGND1 SGND
SGND
PGND2
PGND1
PGND2
SGND
SGND PGND
SGND
SGND
Figure 6: Dual-Phase Single Output
Ordering Information
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PART
TEMP RANGE
PIN-PACKAGE
MAX17509ATJ+
-40ºC to +125ºC
32 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed paddle.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
Chip Information
PROCESS: BiCMOS
32 TQFN-EP
T3255+4
21-0140
90-0012
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MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
2/15
Initial release
—
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2015 Maxim Integrated Products, Inc.
│ 24
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