MAX17510ATB+T [MAXIM]
Terminator Support Circuit, BICMOS, PDSO10, 3 X 3 MM, ROHS COMPLIANT, TDFN-10;
| 型号： | MAX17510ATB+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Terminator Support Circuit, BICMOS, PDSO10, 3 X 3 MM, ROHS COMPLIANT, TDFN-10 信息通信管理 光电二极管 接口集成电路 |
| 文件： | 总13页 (文件大小：433K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3279; Rev 5; 3/11
Low-Voltage DDR Linear Regulators
/MAX7510
General Description
Features
The MAX1510/MAX17510 DDR linear regulators source
and sink up to 3A peak (typ) using internal n-channel
MOSFETs. These linear regulators deliver an accurate
o Internal Power MOSFETs with Current Limit (3A typ)
o Fast Load-Transient Response
o External Reference Input with Reference
0.5V to 1.5V output from a low-voltage power input (V
IN
Output Buffer
= 1.1V to 3.6V). The MAX1510/MAX17510 use a sepa-
rate 3.3V bias supply to power the control circuitry and
drive the internal n-channel MOSFETs.
o 1.1V to 3.6V Power Input
o
15mV (max) Load-Regulation Error
o Thermal-Fault Protection
o Shutdown Input
The MAX1510/MAX17510 provide current and thermal
limits to prevent damage to the linear regulator.
Additionally, the MAX1510/MAX17510 generate a
power-good (PGOOD) signal to indicate that the output
is in regulation. During startup, PGOOD remains low
until the output is in regulation for 2ms (typ). The internal
soft-start limits the input surge current.
o Power-Good Window Comparator with 2ms
(typ) Delay
o Small, Low-Profile 10-Pin, 3mm x 3mm TDFN
Package
o Ceramic or Polymer Output Capacitors
The MAX1510/MAX17510 power the active-DDR termi-
nation bus that requires a tracking input reference. The
MAX1510/MAX17510 can also be used in low-power
chipsets and graphics processor cores that require
dynamically adjustable output voltages. The
MAX1510/MAX17510 are available in a 10-pin, 3mm x
3mm thin DFN package.
Ordering Information
PIN-
PACKAGE
TOP
MARK
PART
TEMP RANGE
MAX1510ETB
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +125°C
10 TDFN-EP* ARD
10 TDFN-EP* ABD
10 TDFN-EP* AWD
10 TDFN-EP* AWQ
10 TDFN-EP* AWQ
MAX1510ETB+
MAX1510ATB/V+
MAX17510ATB+
Applications
Notebook/Desktop Computers
MAX17510ATB/V+ -40°C to +125°C
DDR Memory Termination
+Denotes a lead(Pb)-free and RoHS-compliant package.
*EP = Exposed pad.
/V denotes an automotive qualified part.
Active Termination Buses
Graphics Processor Core Supplies
Chipset/RAM Supplies as Low as 0.5V
Pin Configuration
Typical Operating Circuit
V
IN
(1.1V TO 3.6V)
V
= V
TT
OUT
IN
OUT
TOP VIEW
OUTS
10
9
8
7
6
MAX1510
V
BIAS
(2.7V TO 3.6V)
MAX17510
V
PGND
MAX1510
CC
MAX17510
AGND
SHDN
+
1
2
3
4
5
PGOOD
V
DDQ
(2.5V OR 1.8V)
V
= V
TTR
REFOUT
REFIN
REFOUT
TDFN
3mm x 3mm
A "+" SIGN WILL REPLACE THE FIRST PIN INDICATOR ON LEAD-FREE PACKAGES.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Low-Voltage DDR Linear Regulators
ABSOLUTE MAXIMUM RATINGS
IN to PGND............................................................-0.3V to +4.3V
Operating Temperature Range
OUT to PGND ..............................................-0.3V to (V + 0.3V)
MAX1510ETB...................................................-40°C to +85°C
MAX17510ATB ..............................................-40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow)
IN
OUTS to AGND............................................-0.3V to (V + 0.3V)
IN
V
CC
to AGND.........................................................-0.3V to +4.3V
REFIN, REFOUT, SHDN, PGOOD to AGND..-0.3V to (V + 0.3V)
CC
PGND to AGND.....................................................-0.3V to +0.3V
REFOUT Short Circuit to AGND .................................Continuous
OUT Continuous RMS Current: 100s .................................. 1.6A
1s...................................... 2.5A
Lead(Pb)-free packages..............................................+260°C
Packages containing lead(Pb).....................................+240°C
Continuous Power Dissipation (T = +70°C)
A
10-Pin 3mm x 3mm Thin DFN
(derated 24.4mW/°C above +70°C)...........................1951mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = 1.8V, V
= 3.3V, V
= V
= 1.25V, SHDN = V , circuit of Figure 1, T = T = -40°C to +85°C for MAX1510ETB, T =
IN
CC
REFIN
OUTS
CC
J
A
J
/MAX7510
T
A
= -40°C to +125°C for MAX17510ATB, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
1.1
TYP
MAX
3.6
3.6
1.3
600
100
10
UNITS
V
V
Power input
Bias supply
Load = 0, V
IN
Input-Voltage Range
V
2.7
CC
CC
Quiescent Supply Current (V
)
I
> 0.45V
REFIN
0.7
350
50
mA
µA
CC
SHDN = GND, V
> 0.45V
REFIN
Shutdown Supply Current (V
)
I
CC(SHDN)
CC
SHDN = GND, REFIN = GND
Load = 0
Quiescent Supply Current (V
)
I
IN
0.4
0.1
0
mA
µA
IN
Shutdown Supply Current (V
)
I
SHDN = GND
10
IN
IN(SHDN)
T
T
= +25°C
-4
-6
+4
A
REFIN to OUTS
200mA
≤ +1A
Feedback-Voltage Error
V
mV
OUTS
I
=
OUT
= -40°C to +125°C
+6
A
Load-Regulation Error
Line-Regulation Error
OUTS Input-Bias Current
OUTPUT
-1A ≤ I
-15
+15
mV
mV
µA
OUT
1.4V ≤ V ≤ 3.3V, I
=
100mA
1
IN
OUT
I
-1
+1
OUTS
Output Adjust Range
0.5
1.5
V
Ω
High-side MOSFET (source) (I
= 0.1A)
0.14
0.14
3
0.25
0.25
OUT
OUT On-Resistance
Low-side MOSFET (sink) (I
= -0.1A)
OUT
Output Current Slew Rate
C
= 100µF, I
= 0.1A to 2A
A/µs
dB
kΩ
Ω
OUT
OUT
OUT Power-Supply Rejection
Ratio
10Hz < f < 10kHz, I
= 200mA,
OUT
PSRR
80
12
8
C
= 100µF
OUT
OUT-to-OUTS Resistance
R
OUTS
DISCHARGE
Discharge MOSFET
On-Resistance
R
SHDN = GND
2
_______________________________________________________________________________________
Low-Voltage DDR Linear Regulators
/MAX7510
ELECTRICAL CHARACTERISTICS (continued)
(V = 1.8V, V
IN
= 3.3V, V
= V
= 1.25V, SHDN = V , circuit of Figure 1, T = T = -40°C to +85°C for MAX1510ETB, T =
CC
REFIN
OUTS
CC
J
A
J
T
A
= -40°C to +125°C for MAX17510ATB, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
REFERENCE
REFIN Voltage Range
REFIN Input-Bias Current
V
0.5
-1
1.5
+1
V
REFIN
I
T
A
= +25°C
µA
REFIN
REFIN Undervoltage-Lockout
Voltage
Rising edge, hysteresis = 50mV
0.35
0.45
V
V
V
REFIN
+ 0.01
REFIN
REFOUT Voltage
V
V
= 3.3V, I
= 0V
V
V
REFOUT
CC
REFOUT
REFIN
- 0.01
REFOUT Load Regulation
FAULT DETECTION
ΔV
I
=
5mA
-20
+20
mV
REFOUT
REFOUT
Thermal-Shutdown Threshold
T
Rising edge, hysteresis = 15°C
Rising edge, hysteresis = 100mV
+165
2.55
°C
V
SHDN
V
Undervoltage-Lockout
CC
V
2.45
2.65
1.1
UVLO
Threshold
IN Undervoltage-Lockout
Threshold
Rising edge, hysteresis = 55mV
0.9
V
T
T
= -40°C to +85°C
= -40°C to +125°C
1.8
1.5
3
3
4.2
4.2
A
Current-Limit Threshold
I
A
LIMIT
A
Soft-Start Current-Limit Time
t
200
µs
SS
INPUTS AND OUTPUTS
With respect to feedback threshold,
hysteresis = 12mV
PGOOD Lower Trip Threshold
PGOOD Upper Trip Threshold
PGOOD Propagation Delay
-200
100
5
-150
150
10
-100
200
35
mV
mV
µs
With respect to feedback threshold,
hysteresis = 12mV
OUTS forced 25mV beyond PGOOD trip
threshold
t
I
PGOOD
Startup rising edge, OUTS within 100mV of
the feedback threshold
PGOOD Startup Delay
1
2
3.5
0.3
1
ms
V
PGOOD Output Low Voltage
PGOOD Leakage Current
I
= 4mA
SINK
OUTS = REFIN (PGOOD high impedance),
PGOOD = V + 0.3V, T = +25°C
µA
PGOOD
CC
A
Logic-high
Logic-low
2.0
V
V
SHDN Logic Input Threshold
SHDN Logic Input Current
0.8
-1
SHDN = V
or GND, T = +25°C
+1
µA
CC
A
Note 1: Limits are 100% production tested at T = +25°C. Limits over the operating temperature range are guaranteed through cor-
A
relation using statistical-quality-control (SQC) methods.
_______________________________________________________________________________________
3
Low-Voltage DDR Linear Regulators
Typical Operating Characteristics
(Circuit of Figure 1. T = +25°C, unless otherwise noted.)
A
MAXIMUM OUTPUT CURRENT
vs. INPUT VOLTAGE
OUTPUT LOAD REGULATION
OUTPUT LOAD REGULATION
3.0
2.5
0.96
0.94
1.300
1.275
1.250
1.225
1.200
V
= 0.9V
V
= 1.25V
REFIN
REFIN
V
= 0.9V
OUT
V
= 1.25V
OUT
2.0
1.5
1.0
0.92
0.90
0.88
V
= 1.8V
IN
V
= 1.5V
IN
THERMALLY LIMITED
DROPOUT VOLTAGE LIMITED
V
= 1.2V
IN
V
= 1.5V
1
IN
0.5
0
0.86
0.84
1.0
1.5
2.0
2.5
3.0
-3
-2
-1
0
1
2
3
-3
-2
-1
0
2
3
INPUT VOLTAGE (V)
I
(A)
I
(A)
OUT
OUT
/MAX7510
BIAS CURRENT (I
)
BIAS CURRENT (I
)
INPUT CURRENT (I )
CC
CC
IN
vs. INPUT VOLTAGE (V )
vs. LOAD CURRENT (I
)
vs. INPUT VOLTAGE (V )
IN
OUT
IN
1.4
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
250
200
150
100
50
V
= 1.5V
IN
1.2
1.0
0.8
0.6
0.4
0.2
0
V
V
= 1.25V
= 0.90V
OUT
OUT
V
= 1.25V
OUT
V
= 1.25V
OUT
V
= 0.90V
OUT
ENTERING
DROPOUT
DROPOUT
INPUT UVLO
0.5 1.0 1.5 2.0 2.5 3.0 3.5
(V)
0
-2
-1
0
1
2
0
0
0.5 1.0
1.5 2.0
(V)
2.5 3.0 3.5
I
(A)
V
V
OUT
IN
IN
POWER GROUND CURRENT (I
vs. SOURCE LOAD CURRENT (I
)
)
INPUT CURRENT (I )
IN
vs. SINK LOAD CURRENT (I
DROPOUT VOLTAGE
vs. OUTPUT CURRENT
PGND
OUT
)
OUT
7
6
5
4
3
2
1
0
0.25
0.20
0.15
0.10
0.05
0
0.6
V
= 1.5V
V
= 1.5V
IN
IN
0.5
0.4
0.3
0.2
V
= 1.25V
OUT
ENTERING
DROPOUT
V
= 0.90V
OUT
V
= 1.25V
OUT
V
= 1.25V
OUT
V
= 0.9V
OUT
V
= 0.90V
0.5
OUT
0.1
0
-2.0
-1.5
-1.0
(A)
-0.5
0.0
0
0.5
1.0
1.5
2.0
2.5
3.0
0
1.0
(A)
1.5
2.0
I
OUTPUT CURRENT (A)
I
OUT
OUT
4
_______________________________________________________________________________________
Low-Voltage DDR Linear Regulators
/MAX7510
Typical Operating Characteristics (continued)
(Circuit of Figure 1. T = +25°C, unless otherwise noted.)
A
REFOUT VOLTAGE ERROR
vs. REFOUT LOAD CURRENT
STARTUP WAVEFORM
SHUTDOWN WAVEFORM
MAX1510/MAX17510 toc11
MAX1510/MAX17510 toc12
5V
SHDN
0V
5V
SHDN
0V
20
15
10
5
R
= 100Ω
LOAD
2V
1V
1.25V
V
V
OUT
OUT
0V
0V
0
4V
4V
-5
-10
-15
-20
PGOOD
0V
PGOOD
0V
500μs/div
-10
-5
0
5
10
100μs/div
REFOUT LOAD CURRENT (mA)
SOURCE/SINK LOAD TRANSIENT
SOURCE LOAD TRANSIENT
MAX1510/MAX17510 toc14
MAX1510/MAX17510 toc13
V
OUT
AC-COUPLED
5mV/div
V
OUT
AC-COUPLED
1mV/div
+1.5A
I
1A
OUT
-1.5A
I
OUT
0A
4.00μs/div
20.0μs/div
LINE TRANSIENT
DYNAMIC OUTPUT-VOLTAGE TRANSIENT
MAX1510/MAX17510 toc15
MAX1510/MAX17510 toc16
V
= 1.5V
2.5V
IN
3.3V
V
DDQ
V
(1V/div)
1.8V
IN
1.5V
1.2V
V
REFOUT
V
(10mV/div)
OUT
0.9V
1.2V
AC-COUPLED
0.9V
V
OUT
0.9V
I
= 100mA
OUT
40μs/div
20.0μs/div
_______________________________________________________________________________________
5
Low-Voltage DDR Linear Regulators
Typical Operating Characteristics (continued)
(Circuit of Figure 1. T = +25°C, unless otherwise noted.)
A
SINK CURRENT-LIMIT
DISTRIBUTION
SOURCE CURRENT-LIMIT
DISTRIBUTION
DYNAMIC OUTPUT-VOLTAGE TRANSIENT
MAX1510/MAX17510 toc17
50
50
40
30
20
10
0
V
= 1.8V
SAMPLE SIZE = 200
SAMPLE SIZE = 200
2.5V
+25°C
IN
+25°C
+85°C
+85°C
V
DDQ
40
30
20
10
0
1.8V
1.2V
V
REFOUT
0.9V
1.2V
V
OUT
0.9V
20.0μs/div
-4.0
-3.5
-3.0
-2.5
-2.0
2.0
2.5
3.0
3.5
4.0
SINK CURRENT LIMIT (A)
SOURCE CURRENT LIMIT (A)
/MAX7510
SINK CURRENT-LIMIT DISTRIBUTION
T = +125°C
SOURCE CURRENT-LIMIT DISTRIBUTION
T = +125°C
A
A
50
50
40
30
20
10
0
SAMPLE SIZE = 200
SAMPLE SIZE = 200
40
30
20
10
0
SINK CURRENT LIMIT (A)
SOURCE CURRENT LIMIT (A)
SINK LOAD REGULATION DISTRIBUTION
SINK CURRENT-LIMIT DISTRIBUTION
I
= -1A, T = +125°C
T = +125°C
A
OUT
A
50
40
30
20
10
0
50
40
30
20
10
0
SAMPLE SIZE = 200
SAMPLE SIZE = 200
1
2
3
4
5
6
7
8
9
10 11
SINK LOAD REGULATION (mV)
SINK CURRENT LIMIT (A)
6
_______________________________________________________________________________________
Low-Voltage DDR Linear Regulators
/MAX7510
Pin Description
PIN
NAME
FUNCTION
Buffered Reference Output. The output of the unity-gain reference input buffer sources and sinks over
5mA. Bypass REFOUT to AGND with a 0.33µF or greater ceramic capacitor.
1
REFOUT
Analog Supply Input. Connect to the system supply voltage (+3.3V). Bypass V
greater ceramic capacitor.
to AGND with a 1µF or
CC
2
V
CC
3
4
AGND
REFIN
Analog Ground. Connect the backside pad to AGND.
External Reference Input. REFIN sets the output regulation voltage (V
= V
).
REFIN
OUTS
Open-Drain Power-Good Output. PGOOD is low when the output voltage is more than 150mV (typ) above
or below the regulation point, during soft-start, and when shut down. 2ms after the output reaches the
regulation voltage during startup, PGOOD becomes high impedance.
5
PGOOD
Output Sense Input. The OUTS regulation level is set by the voltage at REFIN. Connect OUTS to the
remote DDR termination bypass capacitors. OUTS is internally connected to OUT through a 12kΩ
resistor.
6
7
OUTS
Shutdown Control Input. Connect to V
for normal operation. Connect to analog ground to shut down the
CC
SHDN
linear regulator. The reference buffer remains active in shutdown.
Power Ground. Internally connected to the output sink MOSFET.
Output of the Linear Regulator
8
9
PGND
OUT
IN
10
Power Input. Internally connected to the output source MOSFET.
Exposed Pad. Internally connected to AGND. Connect EP to AGND PCB ground plane to maximize
thermal performance. Not intended as an electrical connection point.
—
EP
Detailed Description
The MAX1510/MAX17510 are low-voltage, low-dropout
DDR termination linear regulators with an external bias
supply input and a buffered reference output (see
V
= V = V /2
TT DDQ
OUT
V
=
IN
IN
OUT
1.1V TO 3.6V
C
C
10μF
OUT1
100μF
IN2
Figures 1 and 2). V
is powered by a 2.7V to 3.6V
CC
supply that is commonly available in laptop and desk-
top computers. The 3.3V bias supply drives the gate of
the internal pass transistor, while a lower voltage input
at the drain of the transistor (IN) is regulated to provide
MAX1510
MAX17510
3.3V BIAS
SUPPLY
V
PGND
CC
C1
1.0μF
V
. By using separate bias and power inputs, the
OUT
R3
100kΩ
AGND
MAX1510/MAX17510 can drive an n-channel high-side
MOSFET and use a lower input voltage to provide bet-
ter efficiency.
POWER-GOOD
PGOOD
SHDN
OUTS
ON
The MAX1510/MAX17510 regulate their output voltage
to the voltage at REFIN. When used in DDR applica-
tions as a termination supply, the MAX1510/MAX17510
deliver 1.25V or 0.9V at 3A peak (typ) from an input
voltage of 1.1V to 3.6V. The MAX1510/MAX17510 sink
up to 3A peak (typ) as required in a termination sup-
ply. The MAX1510/MAX17510 provide shoot-through
protection, ensuring that the source and sink
MOSFETs do not conduct at the same time, yet pro-
duce a fast source-to-sink load transient.
OFF
R1
10kΩ
V
= V
REFOUT
TTR
V
DDQ
REFIN
REFOUT
C
REFIN
1000pF
C
R2
10kΩ
REFOUT
0.33μF
Figure 1. Standard Application Circuit
_______________________________________________________________________________________
7
Low-Voltage DDR Linear Regulators
INPUT
1.1V TO 3.6V
V
CC
IN
3.3V BIAS
SUPPLY
SOFT-
START
EN
UVLO
SHDN
REFIN
OFF ON
THERMAL
SHDN
V
DDQ
OUT
V
TT
Gm
/MAX7510
PGND
12kΩ
REFOUT
AGND
V
TTR
OUTS
REFIN
+150mV
EN
8Ω
REFIN
-150mV
PGOOD
MAX1510
MAX17510
POWER-
GOOD
DELAY
LOGIC
Figure 2. Functional Diagram
8
_______________________________________________________________________________________
Low-Voltage DDR Linear Regulators
/MAX7510
The MAX1510/MAX17510 feature an open-drain
connected to ceramic bypass capacitors (0.33µF to
PGOOD output that transitions high 2ms after the out-
put initially reaches regulation. PGOOD goes low within
10µs of when the output goes out of regulation by
150mV. The MAX1510/MAX17510 feature current- and
thermal-limiting circuitry to prevent damage during fault
conditions.
1.0µF). REFOUT is active when V
> 0.45V and
REFIN
V
is above V
. REFOUT is independent of
UVLO
CC
SHDN.
Shutdown
Drive SHDN low to disable the error amplifier, gate-
drive circuitry, and pass transistor (Figure 2). In shut-
down, OUT is terminated to GND with an 8Ω MOSFET.
REFOUT is independent of SHDN. Connect SHDN to
3.3V Bias Supply (V
)
CC
The V
input powers the control circuitry and provides
CC
the gate drive to the pass transistor. This improves effi-
ciency by allowing V to be powered from a lower sup-
V
CC
for normal operation.
IN
Current Limit
ply voltage. Power V
supply. Current drawn from the V
from a well-regulated 3.3V
CC
The MAX1510/MAX17510 feature source and sink cur-
rent limits to protect the internal n-channel MOSFETs.
The source and sink MOSFETs have a typical 3A cur-
rent limit (1.8A min). This current limit prevents damage
to the internal power transistors, but the device can
enter thermal shutdown if the power dissipation
increases the die temperature above +165°C (see the
Thermal-Overload Protection section).
supply remains rel-
CC
atively constant with variations in V and load current.
IN
Bypass V
with a 1µF or greater ceramic capacitor as
CC
close to the device as possible.
V
Undervoltage Lockout (UVLO)
CC
The V
input undervoltage-lockout (UVLO) circuitry
CC
ensures that the regulator starts up with adequate volt-
age for the gate-drive circuitry to bias the internal pass
Soft-Start Current Limit
Soft-start gradually increases the internal source cur-
rent limit to reduce input surge currents at startup. Full-
source current limit is available after the 200µs soft-start
timer has expired. The soft-start current limit is
given by:
transistor. The UVLO threshold is 2.55V (typ). V
remain above this level for proper operation.
must
CC
Power-Supply Input (IN)
IN provides the source current for the linear regulator’s
output, OUT. IN connects to the drain of the internal n-
channel power MOSFET. IN can be as low as 1.1V,
minimizing power dissipation. The input UVLO prohibits
operation below 0.8V (typ). Bypass IN with a 10µF or
greater capacitor as close to the device as possible.
I
× t
LIMIT
I
=
LIMIT(SS)
t
SS
where I
and t
are from the Electrical
SS
LIMIT
Characteristics.
Reference Input (REFIN)
The MAX1510/MAX17510 regulate OUTS to the voltage
set at REFIN, making the MAX1510/MAX17510 ideal for
memory applications where the termination supply must
track the supply voltage. Typically, REFIN is set by an
external resistive voltage-divider connected to the
Thermal-Overload Protection
Thermal-overload protection prevents the linear regula-
tor from overheating. When the junction temperature
exceeds +165°C, the linear regulator and reference
buffer are disabled, allowing the device to cool. Normal
operation resumes once the junction temperature cools
by 15°C. Continuous short-circuit conditions result in a
pulsed output until the overload is removed. A continu-
ous thermal-overload condition results in a pulsed out-
put. For continuous operation, do not exceed the
absolute maximum junction-temperature rating
of +150°C.
memory supply (V
) as shown in Figure 1.
DDQ
The maximum output voltage of 1.5V is limited by the
gate-drive voltage of the internal n-channel power
transistor.
Buffered Reference Output (REFOUT)
REFOUT is a unity-gain transconductance amplifier that
generates the DDR reference supply. It sources and
sinks greater than 5mA. The reference buffer is typically
_______________________________________________________________________________________
9
Low-Voltage DDR Linear Regulators
200μs
SHDN
CURRENT LIMIT
OUTPUT OVERLOAD
CONDITION
POWER-GOOD
WINDOW
OUT
2ms STARTUP
DELAY
PGOOD
10μs
PROPAGATION
DELAY
10μs
PROPAGATION
/MAX7510
DELAY
Figure 3. MAX1510/MAX17510 PGOOD and Soft-Start Waveforms
Power-Good (PGOOD)
The MAX1510/MAX17510 provide an open-drain
PGOOD output that goes high 2ms (typ) after the out-
put initially reaches regulation during startup as shown
in Figure 3. PGOOD transitions low 10µs after the out-
put goes out of regulation by 150mV, or when the
device enters shutdown. Connect a pullup resistor from
REFERENCE
VOLTAGE
(V
)
REF
R1
PGOOD to V
for a logic-level output. Use a 100kΩ
CC
MAX1510
MAX17510
resistor to minimize current consumption.
C
REFIN
REFIN
Applications Information
Dynamic Output-Voltage Transitions
By changing the voltage at REFIN, the MAX1510/
MAX17510 can be used in applications that require
dynamic output-voltage changes between two set
points (graphics processors). Figure 4 shows a dynam-
ically adjustable resistive voltage-divider network at
REFIN. Using an external signal MOSFET, a resistor
can be switched in and out of the REFIN resistor-
divider, changing the voltage at REFIN. The two output
voltages are determined by the following equations:
R2
R3
V
OUT(LOW)
V
OUT(HIGH)
R2
V
V
=
V
REF
OUT(LOW)
OUT(HIGH)
)
(
R1 + R2
⎛
⎞
⎟
R2
(R2 + R3)
V
=
V
= V
REF
REF
OUT(LOW)
⎜
R1 + (R2 + R3)
R1 + R2
⎝
⎠
⎡
⎤
⎥
R2 +R3
(
)
V
= V
REF
⎢
OUT(HIGH)
Figure 4. Dynamic Output-Voltage Change
R1 + R2 +R3
(
)
⎢
⎣
⎥
⎦
10 ______________________________________________________________________________________
Low-Voltage DDR Linear Regulators
/MAX7510
For a step voltage change at REFIN, the rate of change
SAFE OPERATING REGION
of the output voltage is limited by the total output
capacitance, the current limit, and the load during the
transition. Adding a capacitor across REFIN and AGND
filters noise and controls the rate of change of the
REFIN voltage during dynamic transitions. With the
additional capacitance, the REFIN voltage slews
between the two set points with a time constant given
3.5
DROPOUT VOLTAGE
3.0 LIMITED
MAXIMUM CURRENT LIMIT
1s RMS
LIMIT
2.5
2.0
1.5
1.0
0.5
°
°
T
= 0 C TO +70 C
A
100s RMS
LIMIT
by R
x C
, where R
is the equivalent parallel
EQ
REFIN
EQ
V
- V
OUT(MIN)
resistance seen by the slew capacitor.
IN(MAX)
Operating Region and Power Dissipation
The maximum power dissipation of the MAX1510/
MAX17510 depends on the thermal resistance of the 10-
pin TDFN package and the circuit board, the tempera-
ture difference between the die and ambient air, and the
rate of airflow. The power dissipated in the device is:
°
T
= +100 C
A
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5
INPUT-OUTPUT DIFFERENTIAL VOLTAGE (V)
P
= I
SINK
x (V – V
IN
SINK
)
OUT
SRC
P
SRC
= I
Figure 5. Power Operating Region—Maximum Output Current
vs. Input-Output Differential Voltage
x V
OUT
The resulting maximum power dissipation is:
V
= R
x I
DROPOUT
DS(ON) OUT
For low output-voltage applications, the sink current is
T
- T
A
J(MAX)
limited by the output voltage and the R
MOSFET.
of the
DS(ON)
P
=
DIS(MAX)
θ
+ θ
CA
JC
Input Capacitor Selection
where T
is the maximum junction temperature
J(MAX)
Bypass IN to PGND with a 10µF or greater ceramic
(+150°C), T is the ambient temperature, θ is the ther-
A
JC
capacitor. Bypass V
to AGND with a 1µF ceramic
CC
mal resistance from the die junction to the package case,
and θ is the thermal resistance from the case through
capacitor for normal operation in most applications.
Typically, the LDO is powered from the output of a
step-down controller (memory supply) that has addi-
tional bulk capacitance (polymer or tantalum) and dis-
tributed ceramic capacitors.
CA
the PCB, copper traces, and other materials to the sur-
rounding air. For optimum power dissipation, use a large
ground plane with good thermal contact to the backside
pad, and use wide input and output traces.
When 1 square inch of copper is connected to the
device, the maximum allowable power dissipation of a
10-pin DFN package is 1951mW. The maximum power
Output Capacitor Selection
The MAX1510/MAX17510 output stability is indepen-
dent of the output capacitance for C
from 10µF to
OUT
dissipation is derated by 24.4mW/°C above T = +70°C.
A
220µF. Capacitor ESR between 2mΩ and 50mΩ is
needed to maintain stability. Within the recommended
capacitance and ESR limits, the output capacitor
should be chosen to provide good transient response:
Extra copper on the PCB increases thermal mass and
reduces thermal resistance of the board. Refer to the
MAX1510 evaluation kit for a layout example.
The MAX1510/MAX17510 deliver up to 3A and oper-
ates with input voltages up to 3.6V, but not simultane-
ously. High output currents can only be achieved when
the input-output differential voltages are low (Figure 5).
ΔI
x ESR = ΔV
OUT(P-P)
is the maximum peak-to-peak load-
OUT(P-P)
where ΔI
OUT(P-P)
current step (typically equal to the maximum source
load plus the maximum sink load), and ΔV is
the allowable peak-to-peak voltage tolerance.
OUT(P-P)
Dropout Operation
A regulator’s minimum input-to-output voltage differen-
tial (dropout voltage) determines the lowest usable sup-
ply voltage. Because the MAX1510/MAX17510 use an
n-channel pass transistor, the dropout voltage is a func-
Using larger output capacitance can improve efficiency
in applications where the source and sink currents
change rapidly. The capacitor acts as a reservoir for
the rapid source and sink currents, so no extra current
is supplied by the MAX1510/MAX17510 or discharged
to ground, improving efficiency.
tion of the drain-to-source on-resistance (R
=
DS(ON)
0.25Ω max) multiplied by the load current (see the
Typical Operating Characteristics):
______________________________________________________________________________________ 11
Low-Voltage DDR Linear Regulators
Noise, PSRR, and Transient Response
PCB Layout Guidelines
The MAX1510/MAX17510 operate with low-dropout
voltage and low quiescent current in notebook comput-
ers while maintaining good noise, transient response,
and AC rejection specifications. Improved supply-noise
rejection and transient response can be achieved by
increasing the values of the input and output capaci-
tors. Use passive filtering techniques when operating
from noisy sources.
The MAX1510/MAX17510 require proper layout to
achieve the intended output power level and low noise.
Proper layout involves the use of a ground plane,
appropriate component placement, and correct routing
of traces using appropriate trace widths. Refer to the
MAX1510 evaluation kit for a layout example:
• Minimize high-current ground loops. Connect the
ground of the device, the input capacitor, and the
output capacitor together at one point.
The MAX1510/MAX17510 load-transient response
graphs (see the Typical Operating Characteristics) show
two components of the output response: a DC shift from
the output impedance due to the load-current change
and the transient response. A typical transient response
for a step change in the load current from -1.5A to
+1.5A is 10mV. Increasing the output capacitor’s value
and decreasing the ESR attenuate the overshoot.
• To optimize performance, a ground plane is essen-
tial. Use all available copper layers in applications
where the device is located on a multilayer board.
• Connect the input filter capacitor less than 10mm
from IN. The connecting copper trace carries large
currents and must be at least 2mm wide, preferably
5mm wide.
• Connect the backside pad to a large ground plane.
Use as much copper as necessary to decrease the
thermal resistance of the device. In general, more
copper provides better heatsinking capabilities.
/MAX7510
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
10 TDFN
T1033+1
21-0137
90-0003
12 ______________________________________________________________________________________
Low-Voltage DDR Linear Regulators
/MAX7510
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
DESCRIPTION
CHANGED
0
1
2
3
5/04
1/05
8/05
4/09
Initial release
—
Raised Absolute Maximum rating
Added MAX1510ETB
1, 14
1
Added automotive-qualified part MAX1510ETB/V+
1, 2, 7, 12, 13
Added MAX17510 to data sheet; added temperature grades for MAX1510ATB+ and
MAX1510ATB/V+; minor edits
1, 2, 3, 6,
7, 12, 13
4
5
7/09
3/11
Added MAX17510 automotive qualified part
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13
© 2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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