MAX5971BETI+ [MAXIM]
Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C; 单端口， 40W ，符合IEEE 802.3af /时， PSE控制器， I²C
| 型号： | MAX5971BETI+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C |
| 文件： | 总46页 (文件大小：2679K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5336; Rev 0; 6/10
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
General Description
Features
S IEEE 802.3af/at Compliant
The MAX5971B is a single-port power controller designed
M
for use in IEEE 802.3af/at-compliant power-sourcing
S Up to 40W for Single-Port PSE Applications
S Integrated Power MOSFET and Sense Resistor
S Supports 54V Single-Supply Operation
S PD Detection and Classification
S I2C-Compatible, 2-Wire Serial Interface
S Instantaneous Readout of Port Current Through
equipment (PSE). This device provides powered device
(PD) discovery, classification, current limit, and DC and
AC load-disconnect detections. The MAX5971B sup-
ports both fully automatic operation and software pro-
grammability, and features an integrated power MOSFET
and sense resistor. The device supports detection and
classification operation from a single 54V supply. In
addition, it supports 2-event classification and new Class
5 classification of high-power PDs. The MAX5971B pro-
vides up to 40W to a single port (Class 5 enabled) and
still provides high-capacitance detection for legacy PDs.
I2C Interface
S Programmable Current Limit for Class 5 PDs
S High-Capacitance Detection for Legacy Devices
S Supports Both DC and AC Load Removal
Detections
The device provides four operating modes to suit differ-
ent system requirements. By default, auto mode allows
the device to operate automatically at its default settings
without any software. Semiautomatic mode automatically
detects and classifies a device connected to the port
after initial software activation, but does not power the
port until instructed to by software. Manual mode allows
total software control of the device and is useful for
system diagnostics. Shutdown mode terminates all port
activities and securely turns off power to the port.
The IC features an I2C-compatible, 2-wire serial inter-
face, and is fully software-configurable and program-
mable. The device provides instantaneous readout of
port current through the I2C interface. The device’s
extensive programmability enhances system flexibility,
enables field diagnosis and allows for uses in other, non
standard applications.
S Current Foldback and Duty-Cycle-Controlled
Current Limit
S LED Indicator for Port Status
S Direct Fast-Shutdown Control Capability
S Space-Saving, 28-Pin TQFN (5mm x 5mm) Power
Package
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX5971BETI+
-40NC to +85NC
28 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Typical Operating Circuit
The device provides input undervoltage lockout (UVLO),
input undervoltage detection, input overvoltage lockout,
overtemperature protection, output voltage slew-rate limit
during startup, and LED status indication. The MAX5971B
programmability includes startup timeout, overcurrent
timeout, and load-disconnect detection timeout.
PSE OUTPUT
AGND
V
V
-54V
EE
OUT
OUTP
EE_DIG
The device is available in a space-saving, 28-pin TQFN
(5mm x 5mm) power package and is rated for the
extended (-40NC to +85NC) temperature range.
LED
PWMEN MAX5971B
LEGACY
DET
ILIM1
ILIM2
MIDSPAN
Applications
Single-Port PSE End-Point Applications
Single-Port PSE Power Injectors (Midspan Applications)
Switches/Routers
OSC
EN
SDA SCL AD0 INT
SERIAL INTERFACE
IEEE is a registered service mark of the Institute of Electrical and Electronics Engineers, Inc.
_______________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to V , unless otherwise noted.)
Continuous Power Dissipation (T = +70NC)
EE
A
AGND, DET, LED ..................................................-0.3V to +80V
OUT .......................................................-0.3V to (AGND + 0.3V)
OUTP........................................................-6V to (AGND + 0.3V)
28-Pin TQFN (derate 34.5mW/NC above +70NC)......2758mW
Package Thermal Resistance (Note 1)
B
...............................................................................29NC/W
.................................................................................2NC/W
JA
V
................................................................-0.3V to +0.3V
B
EE_DIG
JC
OSC.........................................................................-0.3V to +6V
EN, PWMEN, MIDSPAN, LEGACY, ILIM1, ILIM2....-0.3V to +4V
INT, AD0, SCL, SDA................................................-0.3V to +6V
Maximum Current into INT and SDA..................................80mA
Maximum Current into LED................................................40mA
Maximum Current into OUT ........................Internally Regulated
Operating Temperature Range.......................... -40NC to +85NC
Storage Temperature Range............................ -65NC to +150NC
Junction Temperature .....................................................+150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
AGND
- V = 32V to 60V, T = -40NC to +85NC, all voltages are referenced to V , unless otherwise noted. Typical values are at
EE A EE
V
- V = +54V, T = +25NC. Currents are positive when entering the pin and negative otherwise.) (Note 2)
EE A
AGND
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLIES
Operating Voltage Range
V
V
V
- V
EE
32
60
4
V
AGND
AGND
= V , all logic inputs unconnected,
OUT
EE
Supply Current
I
2.5
mA
EE
measured at AGND in power mode
CURRENT LIMIT
Class 0, 1, 2, 3 or ICUT
= 000
400
684
420
720
441
756
Class 4 or ICUT = 001
Maximum
Class 5 if ILIM1 = V
allowed
,
EE
I
LOAD
ILIM2 = unconnected or
ICUT = 101
807
850
900
893
during
current-limit
conditions,
Current Limit
I
mA
LIM
Class 5 if ILIM1 =
unconnected, ILIM2 = V
or ICUT = 110
V
OUT
= 0V
855
902
945
998
EE
(Note 3)
Class 5 if ILIM1 = V
,
EE
950
27
ILIM2 = V or ICUT = 111
EE
V
- V
below which the current limit
OUT
starts folding back
AGND
Foldback Initial OUT Voltage
Foldback Final OUT Voltage
V
V
V
FLBK_ST
V
- V
TH_FB
below which the current limit
OUT
AGND
V
10
FLBK_END
reaches I
Minimum Foldback Current-Limit
Threshold
I
V
OUT
= V
AGND
166
mA
TH_FB
2
______________________________________________________________________________________
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
ELECTRICAL CHARACTERISTICS (continued)
(V
AGND
- V = 32V to 60V, T = -40NC to +85NC, all voltages are referenced to V , unless otherwise noted. Typical values are at
EE A EE
V
- V = +54V, T = +25NC. Currents are positive when entering the pin and negative otherwise.) (Note 2)
EE A
AGND
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OVERCURRENT
Class 0, 1, 2, 3 or ICUT
= 000
351
602
370
634
389
666
Class 4 or ICUT = 001
Class 5 if ILIM1 = V
ILIM2 = unconnected or
ICUT = 101
,
EE
Overcurrent
threshold
allowed for t P
710
748
785
Overcurrent Threshold
I
mA
CUT
t
, V
FAULT OUT
Class 5 if ILIM1 =
unconnected, ILIM2 = V
or ICUT = 110
= 0V (Note 3)
752
794
792
836
832
878
EE
Class 5 if ILIM1 = V
,
EE
ILIM2 = V or ICUT = 111
EE
INTERNAL POWER
Measured from
T
T
= +25NC
= +85NC
0.5
0.6
0.9
A
DMOS On-Resistance
OUT to V , I
=
I
EE OUT
1.3
10
A
100mA
Power-Off OUT Leakage Current
I
V
= V , V
= V
FA
OUT_LEAK
EN
EE OUT
AGND
SUPPLY MONITORS
V
Undervoltage Lockout
V
V
- V , V increasing
EE AGND
28.5
3
V
V
V
V
EE
EE_UVLO
AGND
V
EE
Undervoltage Lockout
Port is shutdown if: V
UVLO
- V < V
EE EE_
AGND
V
EE_UVLOH
Hysteresis
- V
EE_UVLOH
V
V
Overvoltage Lockout
Overvoltage Lockout
V
V
- V > V , V increasing
EE_OV AGND
62.5
1
EE
EE_OV
AGND
EE
EE
V
EE_OVH
Hysteresis
V
V
event bit sets if: V
, V increasing
EE_UV EE
- V
<
EE_UV
AGND
EE
V
EE
Undervoltage
V
40
V
EE_UV
Port is shut down and device resets if the
junction temperature exceeds this limit,
temperature increasing
Thermal Shutdown Threshold
T
150
20
NC
NC
SHD
Thermal Shutdown Hysteresis
OUTPUT MONITOR
T
Temperature decreasing
SHDH
OUT Input Current
I
V
= V , probing phases
AGND
6
FA
FA
BOUT
OUT
OUTP discharge current, detection and
classification off, port shutdown,
Idle Pullup Current at OUT
I
200
1.5
265
DIS
V
OUTP
= V
- 2.8V
AGND
V
OUT
- V
V
decreasing, enabled
EE, OUT
Short to V Detection Threshold
DCN
DCN
2.0
2.5
V
EE
TH
during detection
Short to V Detection Threshold
EE
Hysteresis
220
mV
HY
_______________________________________________________________________________________
3
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
ELECTRICAL CHARACTERISTICS (continued)
(V
AGND
- V = 32V to 60V, T = -40NC to +85NC, all voltages are referenced to V , unless otherwise noted. Typical values are at
EE A EE
V
- V = +54V, T = +25NC. Currents are positive when entering the pin and negative otherwise.) (Note 2)
EE A
AGND
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LOAD DISCONNECT
Minimum load current allowed before
disconnect (DC disconnect active),
DC Load-Disconnect Threshold
I
5
7.5
10
mA
DCTH
V
OUT
= 0V
AC Load-Disconnect Threshold
(Note 4)
Current into DET, for I
powers off (AC disconnect active)
< I
the port
DET
ACTH
I
115
130
145
FA
ACTH
Triangular Wave Peak-to-Peak
Voltage Amplitude
AMP
Measured at DET, referred to AGND
Measured at OSC
3.85
26
4
4.2
39
V
TRW
OSC Pullup/Pulldown Currents
I
32
FA
mV
OSC
V
OSC
- V > V
to activate AC
EE
ACD_EN
ACD_EN Threshold
V
270
330
380
ACD_EN
disconnect
Time from I
< I
(DC
RSENSE
DCTH
disconnect active) or I
disconnect active) to gate shutdown
(Note 5)
< I
(AC
DET
ACTH
Load-Disconnect Timer
t
300
400
ms
DISC
DETECTION
Detection Probe Voltage
(First Phase)
V
- V
- V
during the first detection
during the second detection
during detection, measure
AGND
DET
V
V
3.8
9
4
4.2
9.6
V
V
DPH1
DPH2
DLIM
phase
Detection Probe Voltage
(Second Phase)
V
AGND
phase
DET
9.3
V
DET
= V
AGND
Current-Limit Protection
I
1.50
1.75
2.00
mA
current through DET
If V - V < V after the first
DCP
AGND
OUT
Short-Circuit Threshold
V
detection phase a short circuit to AGND is
detected.
1
V
DCP
First point measurement current threshold
for open condition
Open-Circuit Threshold
Resistor Detection Window
Resistor Rejection Window
I
20
FA
kI
kI
D_OPEN
R
DOK
(Note 6)
19
32
26.5
15.5
Detection rejects lower values
Detection rejects higher values
R
DBAD
CLASSIFICATION
Classification Probe Voltage
V
V
V
- V
during classification
, during classification
AGND
16
65
20
80
V
CL
AGND
DET
= V
DET
Current-Limit Protection
I
mA
ClLIM
measure current through DET
4
______________________________________________________________________________________
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
ELECTRICAL CHARACTERISTICS (continued)
(V
AGND
- V = 32V to 60V, T = -40NC to +85NC, all voltages are referenced to V , unless otherwise noted. Typical values are at
EE A EE
V
- V = +54V, T = +25NC. Currents are positive when entering the pin and negative otherwise.) (Note 2)
EE A
AGND
PARAMETER
SYMBOL
CONDITIONS
Class 0, Class 1
MIN
5.5
13.0
21
TYP
6.5
14.5
23
MAX
7.5
UNITS
Class 1, Class 2
Class 2, Class 3
Class 3, Class 4
16.0
25
Classification current
thresholds between
classes
Classification Current Thresholds
I
mA
CL
31
33
35
Class 4 upper limit
(Note 7)
45
8
48
51
10
80
Mark Event Voltage
V
V
V
- V during mark event
DET
V
MARK
AGND
= V
during mark event measure
DET
AGND
Mark Event Current Limit
55
mA
IMARK_LIM
current through DET
DIGITAL INPUTS/OUTPUTS (Voltages Referenced to V
)
EE
Digital Input Low
Digital Input High
V
0.8
7
V
V
IL
V
IH
2.4
3
Pullup current to internal digital supply to
set default values
Internal Input Pullup Current
I
5
FA
PU
Open-Drain Output Low Voltage
Open-Drain Leakage
V
I
0.4
2
V
FA
V
OL
SINK = 10mA
Open-drain high impedance
= 10mA, PWM disabled, port power-on
I
OL
LED Output Low Voltage
V
I
0.8
LED_LOW
LED
PWM disabled, shutdown mode,
= 60V
LED Output Leakage
I
10
FA
LED_LEAK
V
LED
PWM Frequency
PWM Duty Cycle
TIMING
25
kHz
%
6.25
Time during which a current limit set to
420mA is allowed, starts when power is
turned on (Note 8)
Startup Time
t
t
50
50
60
70
ms
START
FAULT
Maximum allowed time for an overcurrent
Fault Time
60
80
70
90
ms
ms
ms
condition set by I
after startup (Note 8)
CUT
Time allowed for the port voltage to reset
before detection starts
Detection Reset Time
Detection Time
t
ME
Maximum time allowed before detection is
completed
t
330
DET
Midspan Mode Detection Delay
Classification Time
t
2
7
2.2
19
9
2.4
23
11
s
DMID
t
Time allowed for classification
Time allowed for mark event
ms
ms
CLASS
Mark Event Time
Time V
must be above the V
EEUVLO
AGND
V
Turn-On Delay
t
5.2
ms
EEUVLO
DLY
thresholds before the device operates
Time the device waits before turning on
after an overcurrent fault (Note 8)
16 x
FAULT
164
Restart Timer
t
ms
ms
RESTART
t
Watchdog Clock Period
Rate of decrement of the watchdog time
_______________________________________________________________________________________
5
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
ELECTRICAL CHARACTERISTICS (continued)
(V
AGND
- V = 32V to 60V, T = -40NC to +85NC, all voltages are referenced to V , unless otherwise noted. Typical values are at
EE A EE
V
- V = +54V, T = +25NC. Currents are positive when entering the pin and negative otherwise.) (Note 2)
EE A
AGND
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ADC PERFORMANCE (Power-On Mode)
Resolution
Range
9
Bits
A
1.507
2.95
LSB Step Size
mA
T
T
= +25NC
2
A
Gain Error
%
= -40NC to +85NC
4
A
ADC Absolute Accuracy
I
= 400mA
130
1.3
136
0.3
0.3
142
1.7
1.7
LSB
LSB
LSB
OUT
Integral Nonlinearity
INL
Differential Nonlinearity
DNL
TIMING CHARACTERISTICS (For 2-Wire Fast Mode)
Serial Clock Frequency
f
400
kHz
µs
SCL
Bus Free Time Between a STOP
and START Condition
t
BUF
Hold Time for a START Condition
Low Period of the SCL Clock
High Period of the SCL Clock
t
t
0.6
1.3
0.6
µs
µs
µs
HD,STA
t
LOW
t
HIGH
Setup Time for a Repeated
START Condition (Sr)
0.6
µs
SU,STA
Data Hold Time
t
0
150
ns
ns
HD,DAT
Data in Setup Time
t
100
SU,DAT
Rise Time of Both SDA and SCL
Signals, Receiving
20 +
t
(Note 9)
(Note 9)
300
250
ns
R
0.1C
B
Fall Time of SDA Transmitting
Setup Time for STOP Condition
t
ns
µs
F
t
0.6
SU,STO
Capacitive Load for Each
Bus Line
C
(Note 9)
(Note 9)
400
pF
ns
B
Pulse Width of Spike Suppressed
t
50
SP
Note 2: This device is production tested at T = +25°C. Limits to T = -40°C to +85°C are guaranteed by design.
A
A
Note 3: Default thresholds are set by the classification result in auto mode. The thresholds are manually software programmable
through the ICUT Register (R2Ah[2:0]). If ILIM1 and ILIM2 are both unconnected, Class 5 detection is disabled. See the
Class 5 PD Classification section and Table 3 for details and settings.
Note 4: Default value. The AC load-disconnect threshold can be programmed through the AC_TH register (R23h[2:0]).
Note 5: Default value. The load-disconnect time, t
can be programmed through the TDISC register (R16h[1:0]).
DISC
Note 6: R
= (V
- V
)/(I
- I
). V
, V , I , and I represent the voltage at OUT and the current at
DOK
OUT2
OUT1 DET2 DET1 OUT1 OUT2 DET2
DET1
DET during phase 1 and 2 of the detection, respectively.
Note 7: If Class 5 is enabled, this value is the classification current threshold from Class 4 to Class 5.
Note 8: Default values. The startup, fault, and restart timers can be programmed through the TSTART (R16h[5:4]), TFAULT
(R16h[3:2]), and RSRT (R16h[7:6]) registers, respectively.
Note 9: Guaranteed by design. Not subject to production testing.
6
______________________________________________________________________________________
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
ANALOG SUPPLY CURRENT
vs. INPUT VOLTAGE
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
V
UNDERVOLTAGE LOCKOUT
vs. TEMPERATURE
EE
2.7
2.7
2.6
2.5
2.4
2.3
30.0
29.5
29.0
28.5
28.0
27.5
27.0
MEASURED AT AGND
MEASURED AT AGND
2.6
2.5
2.4
2.3
32
36
40
44
48
52
56
60
-40
-15
10
35
60
85
-40
-15
10
35
60
85
V
- V (V)
AGND EE
TEMPERATURE (°C)
TEMPERATURE (°C)
V
OVERVOLTAGE LOCKOUT
vs. TEMPERATURE
INTERNAL FET RESISTANCE
vs. TEMPERATURE
EE
64.0
63.5
63.0
62.5
62.0
61.5
61.0
60.5
60.0
1000
800
600
400
200
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
FOLDBACK CURRENT-LIMIT THRESHOLD
vs. OUTPUT VOLTAGE
DC DISCONNECT THRESHOLD
vs. TEMPERATURE
800
700
600
500
400
300
200
100
0
7.4
7.2
7.0
6.8
6.6
6.4
CLASS 4
CLASS 0, 1, 2, 3
0
10
20
30
40
-40
-15
10
35
60
85
V
- V
(V)
TEMPERATURE (°C)
AGND OUT
_______________________________________________________________________________________
7
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
OVERCURRENT TIMEOUT (240Ω TO 138Ω)
SHORT-CIRCUIT RESPONSE TIME
MAX5971B toc09
MAX5971B toc08
V
- V
AGND OUT
V
- V
AGND OUT
20V/div
20V/div
0V
0V
I
OUT
200mA/div
I
OUT
200mA/div
0mA
0mA
20ms/div
20ms/div
SHORT-CIRCUIT TRANSIENT RESPONSE
EN TO OUT TURN-OFF DELAY
MAX5971B toc10
MAX5971B toc11
V
- V
AGND OUT
20V/div
V
- V
AGND OUT
20V/div
0V
0mA
0V
0V
I
OUT
200mA/div
I
OUT
V
EN
5A/div
5V/div
0mA
10µs/div
100µs/div
ZERO-CURRENT DETECTION WAVEFORM
ZERO-CURRENT DETECTION WAVEFORM
WITH DC DISCONNECT ENABLED
WITH AC DISCONNECT ENABLED
MAX5971B toc12
MAX5971B toc13
V
- V
AGND OUT
V
- V
AGND OUT
20V/div
20V/div
0V
0V
I
I
OUT
OUT
100mA/div
100mA/div
0mA
0mA
100ms/div
100ms/div
8
______________________________________________________________________________________
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
OVERCURRENT RESTART DELAY
STARTUP WITH A VALID PD
MAX5971B toc15
MAX5971B toc14
V
- V
AGND OUT
V
- V
AGND OUT
20V/div
20V/div
0V
0V
I
I
OUT
OUT
200mA/div
100mA/div
0mA
0mA
400ms/div
100ms/div
DETECTION WITH INVALID PD (25kΩ TO 10µF)
DETECTION WITH INVALID PD (15kΩ)
MAX5971B toc16a
MAX5971B toc16b
V
- V
AGND OUT
V
- V
AGND OUT
5V/div
1V/div
0V
0V
I
OUT
I
1mA/div
OUT
1mA/div
0mA
0mA
40ms/div
100ms/div
DETECTION WITH INVALID PD (33kΩ)
DETECTION WITH INVALID PD (OPEN CIRCUIT)
MAX5971B toc16d
MAX5971B toc16c
V
- V
AGND OUT
5V/div
0V
V
- V
AGND OUT
5V/div
0V
I
OUT
I
OUT
1mA/div
0mA
0mA
1mA/div
100ms/div
100ms/div
_______________________________________________________________________________________
9
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
STARTUP IN MIDSPAN WITH A VALID PD
DETECTION IN MIDSPAN WITH INVALID PD (15kΩ)
MAX5971B toc18a
MAX5971B toc17
V
- V
AGND OUT
V
- V
AGND OUT
20V/div
5V/div
0V
0V
I
OUT
100mA/div
I
OUT
0mA
0mA
1mA/div
100ms/div
400ms/div
DETECTION IN MIDSPAN WITH INVALID PD (33kΩ)
DETECTION IN OUTPUT SHORTED TO AGND
MAX5971B toc19
MAX5971B toc18b
V
- V
AGND OUT
5V/div
V
- V
AGND OUT
5V/div
0V
0V
I
OUT
1mA/div
I
OUT
0mA
0mA
1mA/div
400ms/div
40ms/div
CLASSIFICATION WITH DIFFERENT PD CLASSES
CLASSIFICATION WITH DIFFERENT PD CLASSES
(0 TO 3)
(4 AND 5)
MAX5971B toc20a
MAX5971B toc20b
V
- V
AGND OUT
V
- V
AGND OUT
10V/div
10V/div
0V
0V
CLASS 3
CLASS 2
CLASS 5
CLASS 4
I
I
OUT
OUT
10mA/div
20mA/div
CLASS 1
CLASS 0
0mA
0mA
40ms/div
40ms/div
10 _____________________________________________________________________________________
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
STARTUP USING 2-EVENT CLASSIFICATION
WITH A VALID PD
LED DETECTION FAULT WITH PWM ENABLED
MAX5971B toc21
MAX5971B toc22a
V
- V
AGND OUT
10V/div
0V
V
- V
AGND OUT
20V/div
I
OUT
0V
0mA
500mA/div
I
OUT
100mA/div
V
- V
AGND LED
20V/div
0mA
0V
100ms/div
200ms/div
LED DETECTION FAULT WITH PWM DISABLED
LED OVERCURRENT FAULT WITH PWM ENABLED
LED OVERCURRENT FAULT WITH PWM DISABLED
MAX5971B toc22b
MAX5971B toc23a
MAX5971B toc23b
V
- V
V
- V
V
- V
AGND OUT
50V/div
AGND OUT
50V/div
AGND OUT
10V/div
0V
0V
0V
I
I
OUT
OUT
I
OUT
500mA/div
500mA/div
0mA
0mA
0mA
500mA/div
V
- V
AGND LED
V
- V
AGND LED
V
- V
AGND LED
20V/div
20V/div
20V/div
0V
0V
0V
200ms/div
200ms/div
200ms/div
LED PWM TIMING: MINIMUM DUTY
LED PWM TIMING: MAXIMUM DUTY
CYCLE (DEFAULT)
CYCLE (PROGRAMMABLE)
MAX5971B toc24a
MAX5971B toc24b
V
V
AGND - V
AGND - V
OUT
OUT
50V/div
50V/div
OV
OV
I
I
OUT
OUT
500mA/div
500mA/div
OmA
OmA
V
V
AGND - V
AGND - V
LED
LED
20V/div
20V/div
OV
OV
10µs/div
10µs/div
______________________________________________________________________________________ 11
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
Pin Configuration
TOP VIEW
21 20 19 18 17 16 15
14
13
12
11
10
9
N.C. 22
DET 23
EN
LEGACY
V
24
25
26
27
28
N.C.
OUTP
OUT
EE_DIG
AD0
INT
MAX5971B
*EP
6
SCL
SDA
OUT
+
8
N.C.
1
2
3
4
5
7
THIN QFN
*CONNECT TO V
.
EE
Pin Description
PIN
NAME
FUNCTION
Analog Low-Side Supply Input. Bypass with an external 100V, 47FF capacitor in parallel with a
100V, 0.1FF ceramic capacitor between AGND and V
1, 2, 3
V
EE
.
EE
Class 5 Current-Limit Digital Adjust 1. Referenced to V . ILIM1 is internally pulled up to the digital
EE
supply. Use ILIM1 with ILIM2 to enable Class 5 operation and to adjust the Class 5 current-limit
value. See the Electrical Characteristics table and Table 3 in the Class 5 PD Classification section
for details.
4
ILIM1
Class 5 Current-Limit Digital Adjust 2. Referenced to V . ILIM2 is internally pulled up to the digital
EE
supply. Use ILIM2 with ILIM1 to enable Class 5 operation and to adjust the Class 5 current-limit
value. See the Electrical Characteristics table and Table 3 in the Class 5 PD Classification section
for details.
5
6
ILIM2
PWM Control Logic Input. Referenced to V . PWMEN is internally pulled up to the digital sup-
EE
ply. Leave unconnected to enable the internal PWM to drive the LED pin. Force low to disable the
internal PWM.
PWMEN
Detection Collision Avoidance Logic Input. Referenced to V . MIDSPAN is internally pulled up
EE
to the digital supply. Leave unconnected to activate the detection collision avoidance circuitry
for midspan PSE systems. Force low to disable this function for an end-point PSE system. The
MIDSPAN logic level latches after the device is powered up or after a reset condition.
7
8
MIDSPAN
SDA
2-Wire Serial Interface Input/Output Data Line. Referenced to V . Connect to V if the I2C inter-
EE
EE
face is not used.
12 _____________________________________________________________________________________
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
Pin Description (continued)
PIN
NAME
FUNCTION
2-Wire Serial Interface Input Clock Line. Referenced to V . Connect to V if the I2C interface is
not used.
EE
EE
9
SCL
Open-Drain Interrupt Output. Referenced to V . INT is pulled low whenever an interrupt is sent to
EE
the microcontroller. See the Interrupt section for details. Connect to V if the I2C interface is not
10
INT
EE
used.
Address Input. Referenced to V . AD0 is used to form the lower part of the device address. See
EE
11
12
AD0
the Device Address section and Table 5 for details. Connect to V if the I2C interface is not used.
EE
V
Digital Low-Side Supply Input. Connect to V externally.
EE
EE_DIG
Legacy Detection Logic Input. Referenced to V . LEGACY is internally pulled up to the digital
EE
13
LEGACY
supply. Leave unconnected to activate the legacy PD detection. Force low to disable this function.
The LEGACY logic level latches after the device is powered up or after a reset condition.
Enable Input. Referenced to V . EN is internally pulled up to the digital supply. Leave uncon-
EE
nected to enable the device. Force low for at least 40Fs to reset the device. The MIDSPAN, OSC,
and LEGACY states latch-in when the reset condition is removed (low-to-high transition). Bypass
14
15
EN
EN to V with a 1nF ceramic capacitor.
EE
I.C.
Internally Connected. Connect I.C. to V
.
EE
16, 18, 20,
22, 24, 28
N.C.
No Connection. Not internally connected. Leave N.C. unconnected.
LED Indicator Open-Drain Output. Referenced to V . LED can sink 10mA and can drive an exter-
EE
nal LED directly. Blinking functionality is provided to signal different conditions (see the PWM and
LED Signals section). Connect LED to AGND externally (see Figures 15 and 16) or to an external
supply (if available) through a series resistance.
17
LED
AC-Disconnect Triangular Wave Output. Bypass with a 100nF (Q10% tolerance) external capacitor
to V to enable the AC disconnect function. Connect OSC to V to disable the AC disconnect
function and to activate the DC disconnect function. The OSC state latches after the device is
powered up or after a reset condition.
EE
EE
19
21
23
OSC
AGND
DET
High-Side Supply Input
Detection/Classification Voltage Output. DET is used to set the detection and classification probe
voltages and for the AC current sensing when using the AC disconnect function. To use the AC
disconnect function, place a 1kI and 0.47FF RC series in parallel with the external protection
diode to OUTP (see Figure 16).
Port Pullup Output. OUTP is used to pull up the port voltage to AGND when needed. If AC dis-
connect is used, connect OUTP to the anode of the AC-blocking diode. If AC disconnect is not
used, connect OUTP to OUT (see Figures 15 and 17). Bypass OUTP to AGND with a 100V, 0.1FF
ceramic capacitor.
25
OUTP
Integrated MOSFET Output. If DC disconnect is used, connect the port output to OUTP (see
Figures 15 and 17). If the AC disconnect function is used, connect OUT to the cathode of the
AC-blocking diode (see Figure 16).
26, 27
—
OUT
EP
Exposed Pad. Connect EP to V externally. See the Layout Procedure section for details.
EE
______________________________________________________________________________________ 13
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
Simplified Diagram
OSC
SCL
SDA
ADO
CURRENT SENSING
DET
SERIAL PORT
VOLTAGE
PROBING AND
CURRENT-LIMIT
CONTROL
TRIANGLE
WAVE
GENERATOR
AGND
INTERFACE (SPI)
REGISTER FILE
OSC STATUS
MONITOR
EN
OUTP
OUT
LEGACY
DETECTION AND
CLASSIFICATION
CONTROL
VOLTAGE
SENSING
9-BIT ADC
PORT STATE
MACHINE (SM)
MIDSPAN
AC DISCONNECT
ENABLE
FOLDBACK
CONTROL
A = 1
CENTRAL LOGIC
UNIT (CLU)
INT
GATE-
DRIVE
POWER ENABLE
INTERNAL
SUPPLIES
AGND
CONTROL
AC DETECTOR
INTERNAL
MOSFET
AC DISCONNECT
SIGNAL (ACD)
ANALOG
BIAS AND
SUPPLY
VOLTAGE
REFERENCES
ACD
REFERENCE
CURRENT
V
EE
MONITOR
CURRENT
REFERENCES
CURRENT-LIMIT,
OVERCURRENT, AND OPEN-
CIRCUIT SENSING,
AND FOLDBACK CONTROL
THRESHOLD
SETTINGS
LED
INTERNAL
R
SENSE
CLASS 5 ENABLE/DISABLE,
OVERCURRENT AND
MAX5971B
PWM
CURRENT-LIMIT CONTROL
PWMEN
ILIM1
ILIM2
of port current through the I2C interface. The MAX5971B
provides input undervoltage lockout (UVLO), input under-
voltage detection, input overvoltage lockout, overtem-
perature protection, output voltage slew-rate limit dur-
ing startup, and LED status indication. The MAX5971B
programmability includes startup timeout, overcurrent
timeout, and load-disconnect detection timeout.
Detailed Description
The MAX5971B is a single-port power controller designed
for use in IEEE 802.3af/802.3at-compliant PSE. This
device provides PD discovery, classification, current
limit, and DC and AC load-disconnect detections. The
MAX5971B supports both fully automatic operation and
software programmability, and features an integrated
power MOSFET and sense resistor. The device also sup-
ports new Class 5 and 2-event classification for detection
and classification of high-power PDs. The MAX5971B
provides up to 40W to a single port (Class 5 enabled), and
still provides high-capacitance detection for legacy PDs.
Reset
The MAX5971B is reset by any of the following conditions:
1) Power-Up. Reset condition is cleared once V rises
EE
above the UVLO threshold.
2) Hardware Reset. Reset occurs once the EN input is
driven low (> 40Fs, typ) any time after power-up. The
device exits the reset condition once the EN input is
driven high again.
The MAX5971B features an I2C-compatible, 2-wire serial
interface, and is fully software configurable and pro-
grammable. The device provides instantaneous readout
14 _____________________________________________________________________________________
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
3) Software Reset. To initiate a software reset, write a
port operations are immediately stopped and the port
remains idle until shutdown mode is exited.
logical 1 to the RESET_IC register (R1Ah[4]) any time
after power-up. Reset clears automatically and all
registers are set to their default states.
Auto (Automatic) Mode
By default, the MAX5971B enters auto mode after
the reset condition is cleared. To manually place the
MAX5971B into auto mode from any other mode, set
P_M[1:0] (R12h[1:0]) to [11] during normal operation
(see Tables 18 and 19).
4) Thermal Shutdown. The device enters thermal shut-
down at 150NC. The device exits thermal shutdown
and is reset once the temperature drops below 130NC.
At the end of a reset event, the MAX5971B latches in
the state of MIDSPAN, LEGACY, and OSC. During nor-
mal operation, changes to the MIDSPAN and LEGACY
inputs are ignored, and these inputs can be changed
at any time prior to the end of a reset state. Changes to
OSC input during normal operation can impact device
functionality. Therefore, OSC is only changed while the
device is held in a reset state (or powered down), and
OSC then latches in when the reset state ends (other
schematic modifications may be needed, see Figures
15 and 16).
In auto mode, the MAX5971B performs detection and
classification, and powers up the port automatically if a
valid PD is connected to the port. If a valid PD is not con-
nected at the port, the MAX5971B repeats the detection
routine continuously until a valid PD is connected.
When entering auto mode, the DET_EN and CLASS_EN
bits (R14h[0] and R14h[4], Table 21) are set to high
and stay high unless changed by software. Using soft-
ware to set DET_EN and/or CLASS_EN low causes the
MAX5971B to skip detection and/or classification. As a
protection, disabling the detection routine in auto mode
does not allow the corresponding port to power up,
unless the DET_BY bit (R23h[4], Table 32) is set to 1.
Port Reset
Set RESET_P (R1Ah[0]) high anytime during normal
operation to turn off port power and clear the port event
and status registers. Port reset does not initiate a global
device reset.
Semiautomatic (Semi) Mode
The MAX5971B is put into semiautomatic mode by set-
ting P_M[1:0] (R12h[1:0]) to [10] during normal operation
(see Tables 18 and 19). In semi mode, the MAX5971B,
upon request, performs detection and/or classification
repeatedly but does not power up the port. To power
the port, set the PWR_ON bit (R19h[0], Table 26) to 1.
This immediately terminates the detection/classification
routine and turns on power to the port.
Midspan Mode
In midspan mode, the device adopts cadence timing dur-
ing the detection phase. When cadence timing is enabled
and a failed detection occurs, the port waits between 2s
and 2.4s before attempting to detect again. Midspan
mode is activated by setting MIDSPAN high and then
powering or resetting the device. Alternatively, midspan
mode is software enabled by setting BCKOFF (R15h[0],
Table 22) to a logical 1. By default, the MIDSPAN input
is internally pulled high, enabling cadence timing. Force
MIDSPAN low to disable this function.
DET_EN and CLASS_EN (R14h[0] and R14h[4], Table 21)
default to low in semiautomatic mode. Use software to set
DET_EN (R14h[0]) to 1 to start the detection routine and
CLASS_EN (R14h[4]) to 1 to enable classification routine.
They are reset every time the software commands a
power-off of the port, either through a reset event or by
writing a 1 to the PWR_OFF bit (R19h[4]). In any other
case, the status of the bits is left unchanged (including
when the state machine turns off the power when a load
disconnect or a fault condition is encountered).
Operation Modes
The MAX5971B provides four operating modes to suit dif-
ferent system requirements. By default, auto mode allows
the device to operate automatically at its default settings
without any software. Semiautomatic mode automatically
detects and classifies a device connected to the port
after initial software activation, but does not power up the
port until instructed to by software. Manual mode allows
total software control of the device and is useful for sys-
tem diagnostics. Shutdown mode terminates all activities
and securely turns off power to the port.
Manual Mode
The MAX5971B is placed in manual mode by setting
P_M[1:0] (R12h[1:0]) to [01] during normal operation
(see Tables 18 and 19). Manual mode allows the soft-
ware to dictate the sequence of operation. Write a 1 to
both R14h[0] (DET_EN) and R14h[4] (CLASS_EN) to
start detection and classification operations, respec-
tively, and in that priority order. In manual mode, after
Switching between auto, semiautomatic, and manual
mode does not interfere with the operation of the out-
put port. When the port is set into shutdown mode, all
______________________________________________________________________________________ 15
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
execution, the command is cleared from the register(s).
PWR_ON has highest priority. Setting PWR_ON to 1 at
any time causes the device to immediately enter the
powered mode. Setting DET_EN and CLASS_EN to 1 at
the same time causes detection to be performed first.
Once in the powered state, the device ignores DET_EN
or CLASS_EN commands.
(R0Ch[2:0], see Table 13). The DET_END registers are
reset to 0 when read through the CoR (clear-on-read)
register R05h[0], or after a reset event.
During detection, the MAX5971B keeps the internal
MOSFET off and forces two probe voltages through DET.
The current through DET is measured as well as the volt-
age at OUT. A two-point slope measurement is used,
as specified by the IEEE 802.3af/802.3at standard, to
verify the device connected to the port. By default, The
MAX5971B load stability check is disabled. Set LSC_EN
(R29h[4], Table 35) to 1 to enable the load stability
check. The MAX5971B implements appropriate settling
times to reject 50Hz/60Hz power-line noise coupling.
When switching to manual mode from another mode,
DET_EN and CLASS_EN default to low. These bits
become pushbutton rather than configuration bits. Writing
1 to these bits while in manual mode commands the
device to execute one cycle of detection and/or classifica-
tion. They are reset back to 0 at the end of the execution.
An external diode, in series with the DET input, restricts
PD detection to the first quadrant as specified by the
IEEE 802.3af/802.3at standard. To prevent damage to
non-PD devices, and to protect itself from an output short
circuit, the MAX5971B limits the current into DET to less
than 2mA (max) during PD detection.
Shutdown Mode
To put the MAX5971B into shutdown mode, set P_M[1:0]
(R12h[1:0]) to [00] during normal operation (see Table 18
and Table 19). Putting the MAX5971B into shutdown mode
immediately turns off port power, clears the event and sta-
tus bits, and halts all port operations. In shutdown mode
the serial interface is still fully active, however, all DET_EN,
CLASS_EN, and PWR_ON commands are ignored.
In midspan mode, after every failed detection cycle, the
MAX5971B waits at least 2.0s before attempting another
detection cycle. The first detection, however, still hap-
pens immediately after exiting a reset condition.
PD Detection
During normal operation, the MAX5971B probes the
output for a valid PD. A valid PD has a 25kI discov-
ery signature characteristic as specified in the IEEE
802.3af/802.3at standard. Table 1 shows the IEEE 802.3at
specification for a PSE detecting a valid PD signature.
High-Capacitance Detection
High-capacitance detection for legacy PDs is both soft-
ware and pin programmable (LEGACY). To use software
to enable high-capacitance detection, set CLC_EN
(R23h[5]) to 1 during normal operation. Alternatively,
the status of the LEGACY input is latched and writ-
ten to CLC_EN during power-up or after reset condi-
tion is cleared. The LEGACY input is internally pulled
After each detection cycle, the MAX5971B sets DET_
END (R04h[0] and R05h[0]) to 1 and reports the detec-
tion results in the detection status bits, DET_ST[2:0]
Table 1. PSE PI Detection Modes Electrical Requirements (IEEE 802.3at)
PARAMETER
Open-Circuit Voltage
SYMBOL MIN
MAX UNITS
ADDITIONAL INFORMATION
In detection mode only
V
30
5
V
OC
SC
Short-Circuit Current
Valid Test Voltage
I
mA In detection mode only
V
2.8
1
10
V
VALID
Voltage Difference Between Test Points DV
V
TEST
Time Between Any Two Test Points
Slew Rate
t
2
ms This timing implies a 500Hz maximum probing frequency
BP
V
0.1
V/Fs
kI
kI
kI
nF
SLEW
Accept Signature Resistance
Reject Signature Resistance
Open-Circuit Resistance
R
19
26.5
> 33
GOOD
R
< 15
500
BAD
OPEN
GOOD
R
Accept Signature Capacitance
Reject Signature Capacitance
Signature Offset Voltage Tolerance
Signature Offset Current Tolerance
C
150
C
BAD
10
0
FF
V
2.0
12
V
OS
OS
I
0
FA
16 _____________________________________________________________________________________
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
current exceeds 51mA, the MAX5971B does not power
the PD, but returns to idle state before attempting a new
detection cycle.
high, enabling high-capacitance detection. Unless high-
capacitance detection is needed, connect LEGACY to
to disable this function. If high-capacitance detec-
V
EE
tion is enabled, PD signature capacitances up to 47FF
(typ) are accepted.
Class 5 PD Classification
The MAX5971B supports high power beyond the IEEE
802.3at standard by providing an additional classifica-
tion (Class 5) if needed. To enable Class 5 detection
and select the corresponding current-limit/overcurrent
thresholds, ILIM1 and ILIM2 must be set based on
the combinations detailed in Table 3. Once Class 5 is
enabled, during classification, if the MAX5971B detects
currents in excess of the Class 4 upper limit threshold,
the PD is classified as a Class 5 powered device. The PD
is guaranteed to be classified as a Class 5 device for any
classification current from 51mA up to the classification
current-limit threshold.
Powered Device Classification
(PD Classification)
During PD classification, the MAX5971B forces a probe
voltage (-18V, typ) at DET and measures the current into
DET. The measured current determines the class of the PD.
After each classification cycle, the MAX5971B sets
CL_END (R04h[4] and R05h[4]) to 1 and reports the
classification results in the classification status bits,
CLASS[2:0] (R0Ch[6:4], see Table 13). The CL_END reg-
isters are reset to 0 when read through the CoR (clear-
on-read) register, R05h, or after a reset event.
The Class 5 overcurrent threshold and current limit is
set with ILIM1 and ILIM2. ILIM1 and ILIM2 are both
If ILIM1 and ILIM2 are both left unconnected, the
MAX5971B classifies the PD based on Table 33.9 of the
IEEE 802.3at standard (see Table 2). If the measured
referenced to V
and are internally pulled up to the
EE
digital supply. Leave ILIM1 and ILIM2 unconnected to
disable Class 5 detection and to be fully compliant to
IEEE 802.3at standard classification. Class 5 detection
is enabled, and the corresponding overcurrent threshold
and current limit is adjusted, by connecting one or both
Table 2. PSE Classification of a PD (Table
33.9 of the IEEE 802.3at Standard)
MEASURED I
(mA)
CLASSIFICATION
CLASS
to V (see Table 3).
EE
0 to 5
Class 0
> 5 and < 8
8 to 13
Can be Class 0 or 1
Class 1
2-Event PD Classification
If the result of the first classification event is Class 0
through Class 3, then only a single classification event
occurs as shown in Figure 1. However, if the result is
Class 4 or Class 5 (when enabled), the device performs
a second classification event as shown in Figure 2.
Between the classification cycles, the MAX5971B per-
forms a first and second mark event as required by the
IEEE 802.3at standard, forcing a -9.3V probing voltage
at DET.
> 13 and < 16
16 to 21
Either Class 1 or 2
Class 2
> 21 and < 25
25 to 31
Either Class 2 or 3
Class 3
> 31 and < 35
35 to 45
Either Class 3 or 4
Class 4
> 45 and < 51
Either Class 4 or Invalid
Table 3. Class 5 Overcurrent Threshold and Current-Limit Settings
ILIM1
CONFIGURATION
ILIM2
CONFIGURATION
OVERCURRENT
THRESHOLD (mA)
CURRENT
LIMIT (mA)
Unconnected
Unconnected
Unconnected
Class 5 disabled
Class 5 disabled
V
748
792
836
850
900
950
EE
Unconnected
V
V
EE
EE
V
EE
______________________________________________________________________________________ 17
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
80ms
150ms
150ms
DET(2)
19ms
t
t
t
DET(1)
CLASS
t
0V
-4V
-9.3V
-18V
-54V
V
OUT
Figure 1. Detection, Classification, and Port Power-Up Sequence
9ms
9ms
19ms
19ms
80ms
150ms
150ms
t
t
t
t
CLASS(2)
DET(1)
DET(2)
CLASS(1)
t
0V
-4V
-9.3V
-18V
-54V
V
OUT
Figure 2. Detection, 2-Event Classification, and Port Power-Up Sequence
18 _____________________________________________________________________________________
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
the MAX5971B powers down the port and asserts the
IMAX_FLT bits (R06h[0] and R07h[0]). For a continuous
Powered State
When the MAX5971B enters a powered state, the
overstress, a fault occurs exactly after a period of t
.
t
and t
timers are reset. When the startup
FAULT
FAULT
DISC
The timing is software programmable through the timing
register (R16h, Table 23).
timer (t
) has timed out, the device enters a normal
START
powered condition, allowing power delivery to the PD.
PGOOD (R10h[4], Table 16) is set to 1 when the device
enters the normal Power condition. PGOOD immediately
resets to 0 whenever the power to the port is turned off.
The power-good change bits, PG_CHG ([R02h[4] and
R03h[4], Table 9) are set both when the port powers up
and when it powers down. PWR_EN (R10h, Table 16) is
set to 1 when the port powers up and resets to 0 when a
port shuts down. Set PWR_OFF (R19h[4], Table 26) to 1
to immediately turn off power to the port.
After a power-off due to an overcurrent fault, the t
FAULT
timer is not immediately reset but starts decrementing.
The MAX5971B allows the port to be powered on only
when the t
counter reaches zero. This feature
FAULT
sets an automatic port power duty-cycle protection to
the internal MOSFET to avoid overheating. Through pro-
grammable registers, the MAX5971B allows the rate of
decrement to be adjusted or for the restart timeout to be
disabled entirely (see Tables 23 and 24).
Overcurrent Protection
In the normal powered state, the I
and I
thresh-
CUT
LIM
The MAX5971B has an internal sense resistor, R
olds are set automatically according to the classification
result (see Table 4 for classification results based on
detection current, and the Electrical Characteristics table
for the corresponding thresholds). The thresholds can
also be set manually by programming the ICUT register
SENSE
(see the Functional Diagram), connected between the
source of the internal MOSFET and V to monitor the
EE
load current. Under normal operating conditions, the
current through R (I ) never exceeds the
SENSE RSENSE
threshold I . If I
exceeds I , an internal
(R2Ah[2:0]). During startup, I is always set to 420mA
LIM
RSENSE
LIM
LIM
current-limiting circuit regulates the gate voltage of the
internal MOSFET, limiting the current. During transient
regardless of the detected class.
The ICUT Register
conditions, if I
fast pulldown circuit activates to quickly recover from the
current overshoot.
exceeds I
by more than 2A, a
RSENSE
LIM
The ICUT register determines the maximum current limit
allowed for the MAX5971B during the powered state.
The ICUT bits (R2Ah[2:0]) allow manual programming of
In the normal powered state, the MAX5971B checks for
overcurrent conditions, as determined by I
the current limit (I ) and overcurrent (I ) thresholds
CUT
LIM
= ~88%
CUT
(see Tables 36 and 37). The ICUT register can be written
to directly through the I2C interface when the automatic
ICUT programming bit, CL_DISC (R17h[2]), is set to 1
(see Table 4). In this case, the current limit of the port is
configured regardless of the status of the classification.
By setting the CL_DISC bit to 0 (default), the MAX5971B
automatically sets the ICUT register based upon the
classification result (see Tables 4, 36, and 37 in the
Register Map and Description section).
of I . The t
counter sets the maximum-allowed
LIM
FAULT
continuous overcurrent period. This timer is incremented
both in startup and in normal powered state, but under
different conditions. During startup it increases when
I
exceeds I , while in the normal powered state
RSENSE
LIM
the counter increases when I
decreases at a slower pace when I
exceeds I . It
CUT
RSENSE
drops below
RSENSE
I
or I . A slower decrement for the t
CUT
counter
LIM
FAULT
allows for detection of repeated short-duration overcur-
rent events. When the counter reaches the t limit,
FAULT
Table 4. Automatic ICUT Programming
CL_DISC
(R17h[2])
PORT CLASSIFICATION
RESULT
ILIM1
SETTING
ILIM2
SETTING
RESULTING ICUT REGISTER
BITS (R2Ah[2:0])
CURRENT LIMIT
(mA)
1
0
0
0
0
0
Any
—
—
—
—
User programmed
ICUT = 000
ICUT = 001
ICUT = 101
ICUT = 110
ICUT = 111
—
0, 1, 2, 3
—
—
420
720
850
900
950
4
5
5
5
V
Unconnected
EE
Unconnected
V
EE
EE
V
V
EE
______________________________________________________________________________________ 19
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
Foldback Current
During startup and normal operation, an internal circuit
senses the port voltage and reduces the current-limit
As a response to an interrupt, the controller can read
the status of the event register(s) to determine the cause
of the interrupt and take appropriate action. Each inter-
rupt event register is paired with a clear-on-read (CoR)
register. When an interrupt event register is read through
the corresponding CoR register, the interrupt register
is reset to 0. INT remains low and the interrupt is not
reset when the interrupt event register is read through
the read-only addresses. For example, to clear a sup-
ply event fault, read R0Bh (CoR) not R0Ah (read only,
see Table 12). Use the CLR_INT bit (R1Ah[7]) to clear
an interrupt, or the RESET_IC (R1Ah[4]) or RESET_P
(R1Ah[0]) bit to initiate a software reset (see Table 27).
value and the overcurrent threshold when (V
-
AGND
V ) < 27V. The foldback function helps to reduce the
OUT
power dissipation on the internal MOSFET. The current
limit eventually reduces down to I (166mA, typ)
TH_FB
when (V
- V ) < 10V (see Figure 3).
OUT
AGND
Digital Logic
The MAX5971B internally generates digital supplies
(referenced to V ) to power the internal logic circuitry.
EE
All logic inputs and outputs are referenced to V
.
EE
See the Electrical Characteristics table for digital input
thresholds. If digital logic inputs are driven externally, the
nominal digital logic level is 3.3V.
Undervoltage and Overvoltage Protection
The MAX5971B contains both undervoltage and over-
voltage protection features. Table 12 in the Register
Map and Description section shows a detailed list of
the undervoltage and overvoltage protection features.
Interrupt
The MAX5971B contains an open-drain logic output
(INT) that goes low when an interrupt condition exists.
The interrupt register (R00h, Table 7) contains the inter-
rupt flag bits and the interrupt mask register (R01h,
Table 8) determines which events can trigger an inter-
rupt. When an event occurs, the appropriate interrupt
event register bits (in R02h through R0Bh) and the cor-
responding interrupt (in R00h) are set to 1 and INT is
asserted low (unless masked).
An internal V
undervoltage lockout (V ) cir-
EE_UVLO
EE
cuit keeps the port off and the MAX5971B in reset until
- V exceeds 28.5V (typ) for more than 2.5ms.
V
AGND
EE
An internal V overvoltage (V
) circuit shuts down
EE_OV
EE
the port when V
- V
exceeds 62.5V (typ). The
AGND
EE
MAX5971B also features a V
undervoltage interrupt
EE
(V ) that triggers when V - V drops below
EE_UV AGND EE
I
RSENSE
I
LIM
I
TH_FB
10V
27V
V
- V
AGND OUT
Figure 3. Foldback Current Characteristics
20 _____________________________________________________________________________________
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
40V (typ). A fault latches into the supply event regis-
ter V (R0Ah[2] and R0Bh[2], Table 12) but the
MAX5971B does not power down the port in this case.
4V
amplitude wave is forced on DET. The common
P-P
mode of the output signal probed on DET is 5V below
AGND. If the AC current peak at DET falls below I
EE_UV
ACTH
for more than t
asserts LD_DISC (R06h[4] and R07h[4]). The AC load-
disconnect threshold (I ) is programmable using the
, the device powers down the port and
DISC
DC Disconnect Monitoring
Force OSC to V and power or reset the device to acti-
EE
ACTH
vate DC load-disconnect monitoring. DCD_EN (R13h[0])
AC_TH[2:0] bits (R23h[2:0], see Table 32 for settings).
is set to 1 to enable DC load disconnect. If I
(the
RSENSE
current across R
nect threshold, I
turns off port power and sets LD_DISC in the fault event
registers (R06h[4] and R07h[4]) to 1.
) falls below the DC load-discon-
PWM and LED Signals
The MAX5971B includes a multifunction LED driver to
inform the user of the port status. LED is an open-drain,
SENSE
DCTH
, for more than t , the device
DISC
multifunction output referenced to V
and can sink
EE
10mA (typ) while driving an external LED. The LED is
turned on when the port is connected to a valid PD and
powered. If the port is not powered or is disconnected,
the LED is off.
AC Disconnect Monitoring
The MAX5971B features AC load-disconnect monitoring.
Bypass OSC with a 100nF (Q10% tolerance) external
capacitor to V and power or reset the device to auto-
EE
For two other conditions, the MAX5971B blinks a code
to communicate the port status. A series of two flashes
indicates an overcurrent fault occurred during port pow-
er-on, and has a timing characteristic detailed by Figure
4. A series of five flashes indicates that during detection
an invalid low or high discovery signature resistance
was detected, and has a timing characteristic detailed
by Figure 5.
matically enable AC disconnect. ACD_EN (R13h[4]) is
set to 1 to enable AC disconnect (the bypass from OSC
to V must be in place as well). When AC disconnect
EE
is enabled, a blocking diode in series to OUT and an
RC circuit in parallel to the DET diode must be used, as
shown in the typical operating circuit of Figure 16.
The AC disconnect uses an internal triangle-wave gen-
erator to supply the probing signal. Then the resulting
PORT POWERED ON
LED ON
PORT POWERED DOWN, DUE TO OVERCURRENT FAULT
PORT POWERED ON AGAIN
LED ON
LED OFF
223ms
LED ON
74ms
LED OFF
223ms
LED ON
74ms
LED OFF
Figure 4. LED Code Timing for Overcurrent Fault During Port Power-On
INVALID HIGH OR LOW DISCOVERY SIGNATURE RESISTANCE DETECTED
LED
ON
LED
OFF
LED
ON
LED
OFF
LED
ON
LED
OFF
LED
ON
LED
OFF
LED
ON
LED
OFF
74ms
223ms
74ms
223ms
74ms
1.4s
74ms
223ms
74ms
223ms
SEQUENCE REPEATS
Figure 5. LED Code Timing for Detection Fault Due to High- or Low-Discovery Signature Resistance
______________________________________________________________________________________ 21
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
The MAX5971B also contains an internal square wave,
PWM signal generator. The PWM runs at a typical fre-
quency of 25kHz with a default duty cycle of 6.25%.
The duty cycle is programmable from 6.25% up to 25%
through the PWM_TH[1:0] bits (R24h[5:4], Tables 33
and 34). PWMEN is used to enable or disable the PWM.
PWMEN is internally pulled up to the digital supply, and
can be left unconnected to enable the internal PWM.
When enabled, the LED pulses are driven by the PWM
to reduce the power dissipation and increase the system
efficiency. Force PWMEN low to disable the internal
PWM; LED is then driven directly.
must exceed the digital input logic-high threshold (V
CC
> 2.4V, see Table 5), but should not exceed 5.5V. An
external regulated 3.3V or 5V supply is recommended
for V
.
CC
I2C-Compatible Serial Interface
The MAX5971B operates as a slave that sends and
receives data through an I²C-compatible 2-wire inter-
face. The interface uses a serial-data line (SDA) and
a serial-clock line (SCL) to achieve communication
between master(s) and slave(s). A master (typically a
microcontroller) initiates all data transfers to and from the
MAX5971B, and generates the SCL clock that synchro-
nizes the data transfer (see Figure 6).
Thermal Shutdown
If the MAX5971B die temperature reaches +150NC (typ),
an overtemperature fault is generated and the device
shuts down. The die temperature must cool down below
130NC (typ) to remove the overtemperature fault con-
dition. After a thermal shutdown condition clears, the
device is reset.
The MAX5971B SDA line operates as both an input and
an output. A pullup resistor, typically 4.7kI, may be
required on SDA. The MAX5971B SCL line operates only
as an input. A pullup resistor may be required (typically
4.7kI) on SCL if there are multiple masters, or if the
master in a single-master system has an open-drain SCL
output.
Watchdog
The R1Eh and R1Fh registers control the watchdog
operation. The watchdog function, when enabled, allows
the MAX5971B to automatically take over control and
securely shut down the power to the port in case of
software/firmware crashes. See the Register Map and
Description section for register configuration and set-
tings (Tables 29, 30, and 31).
Table 5. Programmable Device Address
Settings
DEVICE ADDRESS
AD0
A7
0
A6
1
A5
0
A4
0
A3
0
A2
0
A1
0
V
V
EE
Device Address (AD0)
The MAX5971B is programmable to one of four unique
slave addresses. To program the device address,
0
1
0
0
0
0
1
CC
SCL
SDA
0
1
0
0
0
1
0
connect AD0 to V , SCL, SDA or to an external V
EE
CC
0
1
0
0
0
1
1
supply referenced to V . This external V
(at AD0)
EE
CC
SDA
t
BUF
t
SU,STA
t
t
SU,STO
SU,DAT
t
HD,STA
t
LOW
t
HD,DAT
SCL
t
HIGH
t
HD,STA
t
R
t
F
START
CONDITION
REPEATED
START CONDITION
STOP
CONDITION
START
CONDITION
Figure 6. 2-Wire Serial Interface Timing Details
22 _____________________________________________________________________________________
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
Serial-Addressing
Each transmission consists of a START condition sent by
a master, followed by the MAX5971B 7-bit slave address
plus R/W bit, a register address byte, one or more data
bytes, and finally a STOP condition.
Bit Transfer
Each clock pulse transfers one data bit (Figure 8). The
data on SDA must remain stable while SCL is high.
Acknowledge
The acknowledge bit is a clocked 9th bit (Figure 9), which
the recipient uses to handshake receipt of each byte of
data. Thus each byte transferred effectively requires 9
bits. The master generates the 9th clock pulse, and the
recipient pulls down SDA during the acknowledge clock
pulse, so that the SDA line is stable low during the high
period of the clock pulse. When the master transmits to
the MAX5971B, the device generates the acknowledge
bit. When the MAX5971B transmits to the master, the
master generates the acknowledge bit.
START and STOP Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START condition by transitioning SDA from
high to low while SCL is high. When the master finishes
communicating with the slave, the master issues a STOP
condition by transitioning SDA from low to high while
SCL is high. The stop condition frees the bus for another
transmission (see Figure 7).
SDA
SCL
S
P
START
STOP
Figure 7. START and STOP Conditions
SDA
SCL
DATA LINE STABLE; CHANGE OF
DATA VALID
DATA ALLOWED
Figure 8. Bit Transfer
START
CONDITION
CLOCK PULSE FOR
ACKNOWLEDGEMENT
SCL
1
2
8
9
SDA BY
TRANSMITTER
S
SDA BY
RECEIVER
Figure 9. Acknowledge
______________________________________________________________________________________ 23
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
Slave Address
The MAX5971B has a 7-bit long slave address (Figure
10). The bit following the 7-bit slave address (bit 8) is the
R/W bit, which is low for a write command and high for a
read command. The upper five bits of the slave address
cannot be changed and are always [01000]. Using the
AD0 input, the lowest two bits can be programmed to
assign the MAX5971B one of 4 unique slave addresses
(see Table 5). The MAX5971B monitors the bus con-
tinuously, waiting for a START condition followed by the
MAX5971B’s slave address. When a MAX5971B rec-
ognizes its slave address, it acknowledges and is then
ready for continued communication.
data it is delivering. If it is not, it then backs off and frees
the data line. This litigation protocol always allows the
part with the lowest address to complete the transmis-
sion. The microcontroller then responds to that interrupt
and takes proper action. The MAX5971B does not reset
its own interrupt at the end of the alert response protocol.
The microcontroller has to do it by clearing the event
register through their CoR addresses or activating the
CLR_INT pushbutton (R1Ah[7]).
General Call
In compliance with the I2C specification, the MAX5971B
responds to the general call through the global address 30h.
Message Format for Writing the MAX5971B
A write to the MAX5971B comprises the device slave
address transmission with the R/W bit set to 0, followed by
at least one byte of information. The first byte of informa-
tion is the command byte (Figure 11). The command byte
determines which register of the MAX5971B is written to
by the next byte, if received. If the MAX5971B detects a
STOP condition after receiving the command byte but
before receiving any data, then the MAX5971B takes no
further action beyond storing the command byte.
Global Addressing and Alert Response Protocol
The global address call is used in writing mode to write
the same register to multiple devices (address 0x60).
In read mode (address 0x61), the global address call is
used as the alert response address. When responding
to a global call, the MAX5971B puts out on the data line
its own address whenever its interrupt is active (as does
every other device connected to the SDA line that has an
active interrupt). After every bit transmitted, the MAX5971B
checks that the data line effectively corresponds to the
MSB
LSB
SDA
SCL
0
1
0
0
0
X
X
R/W
ACK
Figure 10. Slave Address
CB7
CONTROL BYTE STORED ON STOP CONDITION
ACKNOWLEDGE FROM THE MAX5971B
CB6 CB5 CB4 CB3 CB2 CB1 CB0
S
SLAVE ADDRESS
0
ACK
CONTROL BYTE
ACK
P
R/W
ACKNOWLEDGE FROM THE MAX5971B
Figure 11. Write Format: Control Byte Received
24 _____________________________________________________________________________________
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
Message Format for Reading
A read command for the MAX5971B comprises the
device slave address transmission with the R/W bit set
to 1, followed by at least one byte of information. As
with a write command, the first byte of information is the
command byte. The MAX5971B then reads using the
internally stored command byte as an address pointer,
the same way the stored command byte is used as an
address pointer for a write. This pointer autoincrements
after reading each data byte using the same rules as for
a write, though the master now sends the acknowledge
bit after each read receipt (Figure 14). When performing
read-after-write verification, remember to reset the com-
mand byte’s address because the stored control byte
address autoincrements after the write.
Any bytes received after the command byte are data
bytes. The first data byte goes into the internal register
of the MAX5971B selected by the command byte (Figure
12). The control byte address then autoincrements, if
possible (see Table 6), and then waits for the next data
byte or a STOP condition.
If multiple data bytes are transmitted before a STOP con-
dition is detected, these bytes are stored in subsequent
MAX5971B internal registers as the control byte address
autoincrements (Figure 13). If the control byte address
can no longer increment, any subsequent data sent con-
tinues to write to that address.
ACKNOWLEDGE FROM THE MAX5971B
CONTROL BYTE STORED ON STOP CONDITION
ACKNOWLEDGE FROM THE MAX5971B
CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0
D7 D6 D5 D4 D3 D2 D1 D0
S
SLAVE ADDRESS
0
ACK
CONTROL BYTE
ACK
DATA BYTE (1 BYTE)
ACK
P
R/W
WORD ADDRESS AUTOINCREMENT
Figure 12. Write Format: Control and Single Data Byte Written
ACKNOWLEDGE FROM THE MAX5971B
CONTROL BYTE STORED ON STOP CONDITION
ACKNOWLEDGE FROM THE MAX5971B
CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0
D7 D6 D5 D4 D3 D2 D1 D0
S
SLAVE ADDRESS
0
ACK
CONTROL BYTE
ACK
DATA BYTE (n BYTES)
ACK
P
R/W
WORD ADDRESS AUTOINCREMENT
REPEAT FOR n BYTES
Figure 13. Write Format: Control and n Data Bytes Written
ACKNOWLEDGE FROM THE MAX5971B
ACKNOWLEDGE FROM THE MASTER
CONTROL BYTE STORED ON STOP CONDITION
ACKNOWLEDGE FROM THE MAX5971B
CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0
D7 D6 D5 D4 D3 D2 D1 D0
S
SLAVE ADDRESS
0
ACK
CONTROL BYTE
ACK
DATA BYTE (n BYTES)
ACK
P
R/W
WORD ADDRESS AUTOINCREMENT
REPEAT FOR n BYTES
Figure 14. Read Format: Control and n Data Bytes Read
______________________________________________________________________________________ 25
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
Operation with Multiple Masters
When the MAX5971B operates on a 2-wire interface
with multiple masters, a master reading the MAX5971B
should use repeated starts between the write that sets
the MAX5971B’s address pointer, and the read(s) that
take the data from the location(s). It is possible for
master 2 to take over the bus after master 1 has set up
the MAX5971B’s address pointer but before master 1
has read the data. If master 2 subsequently resets the
MAX5971B’s address pointer, then master 1’s read may
be from an unexpected location.
overwrites on unavailable register addresses and unin-
tentional wraparound of addresses.
Register Map and Description
The MAX5971B contains a bank of volatile registers that
store its settings and status. The device features an I2C-
compatible, 2-wire serial interface, allowing the registers
to be fully software configurable and programmable. In
addition to this, several registers are also pin program-
mable to allow the MAX5971B to operate in auto mode
and still be partially configurable even without the assis-
tance of software.
Command Address Autoincrementing
Address autoincrementing allows the MAX5971B to be
configured with fewer transmissions by minimizing the
number of times the command address needs to be
sent. The command address stored in the MAX5971B
generally increments after each data byte is written or
read (Table 6). The MAX5971B is designed to prevent
The Interrupts Registers (R00h to R01h)
Interrupt Register (R00h)
The interrupt register (R00h, Table 7) summarizes the
event register status and is used to send an interrupt
signal to the controller. On power-up or after a reset
condition, interrupt (R00h) is set to a default value of
00h. INT goes low to report an interrupt event if any one
of the active interrupt bits is set to 1 (active high) and
it is not masked by the interrupt mask register (R01h,
Table 8). INT does not go low to report an interrupt if
the corresponding mask bit (R01h) is set. Writing a 1
to CLR_INT (R1Ah[7], Table 27) clears all interrupt and
events registers (resets to low). INT_EN (R17h[7], Table
25) is a global interrupt enable and writing a 0 to INT_EN
disables the INT output, putting it into a state of high
impedance.
Table 6. Autoincrement Rules
COMMAND BYTE
AUTOINCREMENT BEHAVIOR
ADDRESS RANGE
Command address autoincrements
0x00 to 0x37
after byte read or written
Command address remains at 0x37
0x37
after byte written or read
Table 7. Interrupt Register
ADDRESS = 00h
DESCRIPTION
SYMBOL
SUP_INT
Reserved
IMAX_INT
BIT NO.
TYPE
Interrupt signal for supply faults. SUP_INT is the logic OR of all the active bits in the supply
event register (R0Ah/R0Bh, Table 12).
7
6
5
R
R
R
Reserved
Interrupt signal for current-limit violations. IMAX_INT reports the status of IMAX_FLT (bit 0) in
the fault event register (R06h/R07h, Table 11).
Interrupt signal for completion of classification. CL_INT reports the status of CL_END (bit 4)
in the detect event register (R04h/R05h, Table 10).
CL_INT
DET_INT
LD_INT
PG_INT
PE_INT
4
3
2
1
0
R
R
R
R
R
Interrupt signal for completion of detection. DET_INT reports the status of DET_END (bit 0) in
the detect event register (R04h/R05h, Table 10).
Interrupt signal for load disconnection. LD_INT reports the status of LD_DISC (bit 4) in the
fault event register (R06h/R07h, Table 11).
Interrupt signal for PGOOD (R10h[4]) status changes. PG_INT reports the status of PG_CHG
(bit 4) in the power event register (R02h/R03h, Table 9).
Interrupt signal for power enable status change. PEN_INT reports the status of PWEN_CHG
(bit 0) in the power event register (R02h/R03h, Table 9).
26 _____________________________________________________________________________________
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
Interrupt Mask Register (R01h)
The Event Registers (R02h to R08h)
The interrupt mask register (R01h, Table 8) contains
MASK_ bits that mask the corresponding interrupt bits
in register R00h (active high). Setting MASK_ bits low
individually disables the corresponding interrupt signal.
When masked (set low), the corresponding bits are still
set in the interrupt register (R00h) but the masking bit
(R01h) suppresses the generation of an interrupt signal
(INT). On power-up or a reset condition, the interrupt
mask register is set to a default state of A4h.
Power Event Register (R02h/R03h)
The power event register (R02h/R03h, Table 9) records
changes in the power status of the port. On power-up or
after a reset condition, the power event register is set to
a default value of 00h. Any change in PGOOD (R10h[4])
sets PG_CHG to 1. Any change in PWR_EN (R10h[0])
sets PWEN_CHG to 1. PG_CHG and PWEN_CHG trig-
ger on the edges of PGOOD and PWR_EN and do not
depend on the actual logic status of the bits. The power
event register has two addresses. When read through
the R02h address, the content of the register is left
unchanged. When read through the CoR R03h address,
the register content is reset to the default state.
Table 8. Interrupt Mask Register
ADDRESS = 01h
DESCRIPTION
SYMBOL
BIT NO.
TYPE
R/W
Interrupt mask bit 7. A logic-high enables the SUP_INT interrupts. A logic-low disables the
SUP_FLT interrupts.
MASK7
7
6
5
Reserved
MASK5
R/W
Reserved
Interrupt mask bit 5. A logic-high enables the IMAX_INT interrupts. A logic-low disables the
IMAX_FLT interrupts.
R/W
Interrupt mask bit 4. A logic-high enables the CL_INT interrupts. A logic-low disables the
CL_END interrupts.
MASK4
MASK3
MASK2
MASK1
MASK0
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
Interrupt mask bit 3. A logic-high enables the DET_INT interrupts. A logic-low disables the
DET_END interrupts.
Interrupt mask bit 2. A logic-high enables the LD_INT interrupts. A logic-low disables the
LD_DISC interrupts.
Interrupt mask bit 1. A logic-high enables the PG_INT interrupts. A logic-low disables the
PG_INT interrupts.
Interrupt mask bit 0. A logic-high enables the PE_INT interrupts. A logic-low disables the
PE_INT interrupts.
Table 9. Power Event Register
ADDRESS =
02h
TYPE
—
03h
R/W
—
DESCRIPTION
SYMBOL
BIT NO.
Reserved
Reserved
Reserved
PG_CHG
Reserved
Reserved
Reserved
PWEN_CHG
7
6
5
4
3
2
1
0
Reserved
—
—
Reserved
—
—
Reserved
R
CoR
—
PGOOD change event for the port
—
Reserved
Reserved
Reserved
—
—
—
—
R
CoR
Power enable change event for the port
______________________________________________________________________________________ 27
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
Detect Event Register (R04h/R05h)
The detect event register (R04h/R05h, Table 10) records
detection/classification events for the port. On power-up
or after a reset condition, the detect event register is set
to a default value of 00h. DET_END and CL_END are
set high whenever detection/classification is completed.
As with the other event registers, the detect event reg-
ister has two addresses. When read through the R04h
address, the content of the register is left unchanged.
When read through the CoR R05h address, the register
content is reset to the default state.
a default value of 00h. LD_DISC is set to 1 whenever
the port shuts down due to detection of load removal.
IMAX_FLT is set to 1 when the port shuts down due to an
extended overcurrent event after a successful startup.
As with the other events registers, the fault event reg-
ister has two addresses. When read through the R06h
address, the content of the register is left unchanged.
When read through the CoR R07h address, the register
content is reset to the default state.
Reserved Registers (R08h/R09h)
Registers R08h/R09h are at this time reserved. Writing
to this register has no effect (the address autoincre-
ment still updates) and any attempt to read this register
returns all zeros.
Fault Event Register (R06h/R07h)
The fault event register (R06h/R07h, Table 11) records load
removal and overcurrent events for the port. On power-up
or after a reset condition, the fault event register is set to
Table 10. Detect Event Register
ADDRESS =
04h
TYPE
—
05h
R/W
—
DESCRIPTION
SYMBOL
BIT NO.
Reserved
Reserved
Reserved
CL_END
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
—
—
—
—
R
CoR
—
Classification completed on the port
Reserved
Reserved
Reserved
Reserved
DET_END
—
—
—
Reserved
—
—
Reserved
R
CoR
Detection completed on the port
Table 11. Fault Event Register
ADDRESS =
06h
TYPE
—
07h
TYPE
—
DESCRIPTION
SYMBOL
BIT NO.
Reserved
Reserved
Reserved
LD_DISC
Reserved
Reserved
Reserved
IMAX_FLT
7
6
5
4
3
2
1
0
Reserved
—
—
Reserved
—
—
Reserved
R
CoR
—
Disconnect on the port
Reserved
—
—
—
Reserved
—
—
Reserved
R
CoR
Overcurrent on the port
28 _____________________________________________________________________________________
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
As with any of the other event registers, the supply
event register has two addresses. When read through
the R0Ah address, the content of the register is left
unchanged. When read through the CoR R0Bh address,
the register content is reset to the default state.
Supply Event Register (R0Ah/R0Bh)
The MAX5971B continuously monitors the power sup-
plies and sets the appropriate bits in the supply event
register (R0Ah/R0Bh, Table 12). On power-up or after
a reset condition, the supply event register is set to a
default value of 00h. V
exceeds its overvoltage threshold. V
is set to 1 whenever V
EE_OV
EE
The Status Registers (R0Ch to R11h)
is set to 1
EE_UV
Port Status Register (R0Ch)
The port status register (R0Ch, Table 13) records the
results of the port detection and classification at the end
of each phase in three encoded bits. On power-up or
after a reset condition, the port status register is set to a
default value of 00h. Tables 14 and 15 show the detection
and classification result decoding charts, respectively.
For CLC_EN = 0 (R23h[5]), the detection result is shown
in Table 13. When CLC_EN = 1, the MAX5971B allows
valid detection of high capacitive loads of up to 47FF, typ.
As a protection, when POFF_CL (R12h[3], Table 18) is set
to 1, the MAX5971B prohibits turning on power to the port
that returns a status 111 after classification.
whenever V falls below its undervoltage threshold.
EE
A thermal shutdown circuit monitors the temperature
of the die and resets the MAX5971B if the temperature
exceeds +150NC. TSD is set to 1 after the MAX5971B
returns to normal operation.
When V is below its UVLO threshold, the MAX5971B is
EE
in reset mode and securely holds the port off. When V
rises above its UVLO threshold, the device comes out of
EE
reset and the V
is set to 1.
bit in the supply event register
EE_UVLO
Table 12. Supply Event Register
ADDRESS =
0Ah
TYPE
R
0Bh
TYPE
CoR
—
DESCRIPTION
SYMBOL
BIT NO.
TSD
7
6
5
4
3
2
1
0
Overtemperature shutdown
Reserved
Reserved
—
Reserved
Reserved
—
—
V
R
CoR
CoR
CoR
—
V
EE
V
EE
V
EE
undervoltage lockout condition
overvoltage condition
EE_UVLO
V
V
R
EE_OV
R
undervoltage condition
EE_UV
Reserved
Reserved
—
Reserved
Reserved
—
—
Table 13. Port Status Register
ADDRESS = 0Ch
DESCRIPTION
SYMBOL
BIT NO.
TYPE
—
R
Reserved
7
6
5
4
3
2
1
0
Reserved
CLASS[2]
CLASS[1]
CLASS[0]
Reserved
DET[2]
CLASS
Reserved
DET_ST
R
R
—
R
R
DET[1]
R
DET[0]
______________________________________________________________________________________ 29
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
Table 14. Detection Result Decoding Chart
DET_ST[2:0]
(ADDRESS = 0Ch)
DETECTED
DESCRIPTION
000
001
010
011
100
101
110
111
None
DCP
Detection status unknown (default)
Positive DC supply connected at the port (V
High capacitance at the port (> 8.5FF, typ)
- V
< 1V)
AGND
OUT_
HIGH CAP
RLOW
DET_OK
RHIGH
OPEN
Low resistance at the port (R
< 15kI)
DET
Detection pass (15kI> R
> 33kI)
DET
High resistance at the port (R
> 33kI)
DET
Open port (I
< 20FA)
DET
DCN
Negative DC bias on the port (V
- V < 2V)
OUT EE
Table 15. Classification Result Decoding Chart
CLASS[2:0]
(ADDRESS = 0Ch)
CLASS RESULT
000
001
010
011
100
101
110
111
Unknown
1
2
3
4
5
0
Class FAIL
Table 16. Power Status Register
ADDRESS = 10h
DESCRIPTION
SYMBOL
Reserved
Reserved
Reserved
PGOOD
BIT NO.
TYPE
—
7
6
5
4
3
2
1
0
Reserved
—
Reserved
—
Reserved
R
Power-good condition on the port
Reserved
Reserved
Reserved
Reserved
PWR_EN
—
—
Reserved
—
Reserved
R
Power is enabled on the port
Reserved Registers (R0Dh to R0Fh)
status register is set to its default value of 00h. PGOOD
(R10h[4]) is set to 1 at the end of the power-up startup
period. PGOOD is reset to 0 whenever a fault condition
occurs. PWR_EN (R10h[0]) is set to 1 when the port
power is turned on. PWR_EN resets to 0 as soon as the
port turns off. Any transition of PGOOD and PWR_EN
bits set the corresponding bit in the power event register
(R02h/R03h, Table 9).
Registers R0Dh to R0Fh are unconnected; writing to
them has no effect (address autoincrement still func-
tions) and a read always returns logical zeros.
Power Status Register (R10h)
The power status register (R10h, Table 16) records the
current status of port power. On power-up or after a reset
condition, the port is initially unpowered and the power
30 _____________________________________________________________________________________
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
Pin Status Register (R11h)
The pin status register (R11h, Table 17) records the state
of the OSC, LEGACY, and MIDSPAN pins. The states
of OSC, LEGACY, and MIDSPAN are latched into the
corresponding bits after a power-up or reset condition
clears. Therefore, the default state of the pin status reg-
ister depends on those inputs (0000 to xxx1). Changes
to those inputs during normal operation are ignored and
do not change the register contents.
Configuration Registers (R12h to R17h)
Mode Register (R12h)
The mode register (R12h, Table 18) contains two bits that
set the MAX5971B mode of operation. Table 19 details
how to set the mode of operation for the device. On a
power-up or after a reset condition, the mode register is
set to a default value of 03h. Use software to program
the mode of operation. The software port specific reset
using RESET_P (R1Ah[0], Table 27) does not affect the
mode register. Setting POFF_CL (R12h[3]) to 1 prevents
power-up after a classification failure.
Table 17. Pin Status Register
To ADDRESS = 11h
DESCRIPTION
SYMBOL
Reserved
Reserved
Reserved
Reserved
OSC
BIT NO.
TYPE
—
—
—
—
R
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
OSC input latched-in status
LEGACY input latched-in status
LEGACY
MIDSPAN
Reserved
R
R
MIDSPAN input latched-in status
Reserved
—
Table 18. Mode Register
ADDRESS = 12h
DESCRIPTION
SYMBOL
Reserved
Reserved
Reserved
Reserved
POFF_CL
Reserved
BIT NO.
TYPE
—
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
—
—
—
R/W
—
A logic-high prevents power-up after a classification failure (I > 50mA, valid only in auto mode)
Reserved
R/W
R/W
MODE[1] for the port
MODE[0] for the port
P_M
Table 19. Port Operating Mode Status
MODE
00
DESCRIPTION
Shutdown
01
Manual
10
Semiautomatic
Auto (Automatic)
11
______________________________________________________________________________________ 31
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
Disconnect Enable Register (R13h)
Detection and Classification
Enable Register (R14h)
The disconnect enable register (R13h, Table 20) is used
The detection and classification enable register (R14h,
Table 21) is used to enable detection and classification
routines for the port. On a power-up or after a reset con-
dition, this register is set to a default value of FFh (which
corresponds to the default auto mode). Setting DET_EN
(R14h[0]) and CLASS_EN (R14h[4]) to 1 enables load
detection and classification, respectively. Detection
always has priority over classification. For classifica-
tion without detection, set the DET_EN bit to 0 and the
CLASS_EN bit to 1.
to enable AC and DC load-disconnect detection. On
power-up or after a reset condition, this register is reset to
a default value of 000x to 000x, where the status latched
in from the OSC input determines if AC or DC disconnect
is set (see the AC/DC Disconnect Monitoring sections
for details). Setting DCD_EN (R13h[0]) to 1 enables the
DC load-disconnect detection feature. Setting ACD_EN
(R13h[4]) to 1 enables the AC load-disconnect feature.
If enabled, the load-disconnect detection starts during
power mode and after startup when the PGOOD bit
(R10h[4], Table 16) goes high.
When entering auto mode, R14h defaults to FFh. When
entering semi or manual modes, R14h defaults to 00h.
In manual mode, R14h works like a pushbutton. Set the
bits high to launch the corresponding routine. The bit
then clears after one complete detection or classification
cycle finishes.
Table 20. Disconnect Enable Register
ADDRESS = 13h
DESCRIPTION
SYMBOL
Reserved
Reserved
Reserved
ACD_EN
Reserved
Reserved
Reserved
DCD_EN
BIT NO.
TYPE
—
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
—
—
R/W
—
Enable AC disconnect detection on the port
Reserved
—
Reserved
—
Reserved
R/W
Enable DC disconnect detection on the port
Table 21. Detection And Classification Enable Register
ADDRESS = 14h
DESCRIPTION
SYMBOL
Reserved
Reserved
Reserved
CLASS_EN
Reserved
Reserved
Reserved
DET_EN
BIT NO.
TYPE
—
7
6
5
4
3
2
1
0
Reserved
—
Reserved
—
Reserved
R/W
—
Enable classification on the port
Reserved
—
Reserved
—
Reserved
R/W
Enable detection on the port
32 _____________________________________________________________________________________
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
TDISC[1:0] (R16h[1:0]) is used to program the load-
Backoff Enable Register (R15h)
The backoff enable register (R15h, Table 22) is used
to control cadence timing (midspan) for the port. On a
power-up or after a reset condition, this register is set to
a default value of 0000 to 000x where x is the latched in
value of the MIDSPAN input. Setting BCKOFF (R15h[0])
to 1 enables cadence timing where the port backs off and
waits 2.2s (typ) after each failed load detection. The IEEE
802.3af/at standard requires a PSE that delivers power
through the spare pairs (midspan) to have cadence tim-
ing (see the Midspan Mode section for details).
disconnect detection time (t
). The device turns off
DISC
power to the port if it fails to provide a minimum power
maintenance signal for longer than the programmed
load-disconnect detection time. TFAULT[1:0] (R16h[3:2])
programs the overcurrent fault time (t
). Fault time
FAULT
is the time allowed for the port to remain in an overcur-
rent state both during startup and normal operation
(see the Overcurrent Protection section). TSTART[1:0]
(R16h[5:4]) programs the startup timer (t
time is the time the port is allowed to be in current limit
during startup. RSTR[1:0] programs the discharge rate
). Startup
START
Timing Register (R16h)
The timing register (R16h, Table 23) is used to program
the restart, startup, overcurrent, and load-disconnect
timers for the port. On a power-up or after a reset con-
dition, the timing register is set to a default value of
00h. To program the timer values, set the bits in R16h
of the TFAULT counter (t
) and effectively sets
RESTART
the time the port remains off after an overcurrent fault.
When the MAX5971B shuts down a port due to an
extended overcurrent condition (either during startup or
normal operation), if RSTR_EN (R17h[6]) is set high, the
part does not allow the port to power back on before the
to scale the t
, t
, t
, and t
to a
DISC FAULT START
RESTART
restart timer (t ) returns to zero. This effectively
RESTART
multiple of their nominal value specified in the Electrical
Characteristics table.
sets a minimum duty cycle that protects the external
MOSFET from overheating during a prolonged output
overcurrent condition.
Table 22. Backoff Enable Register
ADDRESS = 15h
DESCRIPTION
SYMBOL
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
BCKOFF
BIT NO.
TYPE
—
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
—
—
—
—
—
—
R/W
Enable cadence timing on the port
Table 23. Timing Register
ADDRESS = 16h
DESCRIPTION
SYMBOL
RSTR[1]
BIT NO.
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Restart timer programming bit 1
RSTR[0]
Restart timer programming bit 0
TSTART[1]
TSTART[0]
TFAULT[1]
TFAULT[0]
TDISC[1]
TDISC[0]
Startup timer programming bit 1
Startup timer programming bit 0
Overcurrent timer programming bit 1
Overcurrent timer programming bit 0
Load-disconnect timer programming bit 1
Load-disconnect timer programming bit 0
______________________________________________________________________________________ 33
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
Table 24. Timer Values for Timing Register
BIT [1:0]
(ADDRESS = 16h)
t
t
t
t
FAULT
RESTART
DISC
START
t
nominal
t
nominal
(60ms, typ)
t
nominal
(60ms, typ)
DISC
START
FAULT
00
16 x t
FAULT
(350ms, typ)
01
10
11
32 x t
64 x t
¼ x t
nominal
½ x t
nominal
nominal
nominal
½ x t
nominal
nominal
nominal
FAULT
FAULT
FAULT
DISC
DISC
DISC
START
START
START
FAULT
FAULT
FAULT
½ x t
2 x t
nominal
nominal
2 x t
4 x t
2 x t
4 x t
0 x t
Table 25. Miscellaneous Configurations 1 Register
ADDRESS = 17h
DESCRIPTION
SYMBOL
INT_EN
BIT NO.
TYPE
R/W
R/W
—
7
6
5
4
3
A logic-high enables INT functionality
RSTR_EN
Reserved
Reserved
Reserved
A logic-high enables the autorestart protection timer (set by the RSRT[1:0] bits)
Reserved
Reserved
Reserved
—
—
A logic-high enables current-limit programming regardless of the classification result through
the ICUT[2:0] register
CL_DISC
2
R/W
OUT_ISO
HP_TIME
1
0
R/W
R/W
A logic-high forces DET to a high-impedance state. Does not interfere with other circuit operation.
A logic-high enables the higher current limit for Type 2 PDs during startup.
Miscellaneous Configuration 1 Register (R17h)
The miscellaneous configuration 1 register (R17h, Table
25) is used for several functions that do not cleanly fit
within one of the other configuration categories. On a
power-up or after a reset condition, this register is set to
a default value of 0xC0h. Therefore, by default, INT_EN
(R17h[7]) and RSTR_EN (R17h[6]) are set to 1, enabling
both INT functionality and the autorestart protection timer.
Power Enable Pushbutton Register (R19h)
The power enable pushbutton register (R19h, Table
26) is used to manually power the port on or off. On a
power-up or after a reset condition, this register is set to
a default value of 0x00h. Setting PWR_ON (R19h[0]) to
1 turns on power to the port. PWR_ON commands are
ignored when the port is already powered and during
shutdown. During detection or classification, if a 1 is
written to PWR_ON, the MAX5971B gracefully terminates
the detection/classification routine and turns on power
to the port. The MAX5971B also ignores PWR_ON com-
mands when operating in auto mode. Setting PWR_OFF
(R19h[4]) to 1 turns off power to the port. PWR_OFF
commands are ignored when the port is already off and
during shutdown. After the appropriate command is
executed (port power on or off), the PWR_ON/PWR_OFF
bit resets back to 0.
Setting CL_DISC (R17h[2] to 1 enables current-limit
programming regardless of the classification result
through the ICUT[2:0] register (R2Ah). Setting OUT_ISO
(R17h[1]) to 1, forces DET to a high-impedance state.
Setting HP_TIME high enables the higher current limits
needed for type 2 PDs even during startup (during the
time after port power-up but before t
has expired).
START
Pushbutton Registers (R18h to R1Ah)
Reserved Register (R18h)
Register R18h is at this time reserved. Writing to this
register has no effect (the address autoincrement still
updates) and any attempt to read this register returns
all zeros.
Global Pushbutton Register (R1Ah)
The global pushbutton register (R1Ah, Table 27) is used
to manually clear interrupts and to initiate global and
port resets. On a power-up or after a reset condition, this
register is set to a default value of 0x00h. Writing a 1 to
34 _____________________________________________________________________________________
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
Table 26. Power Enable Pushbutton Register
ADDRESS = 19h
DESCRIPTION
DESCRIPTION
DESCRIPTION
SYMBOL
BIT NO.
TYPE
—
Reserved
Reserved
Reserved
PWR_OFF
Reserved
Reserved
Reserved
PWR_ON
7
6
5
4
3
2
1
0
Reserved
—
Reserved
—
Reserved
R/W
—
A logic-high powers off the port
Reserved
—
Reserved
—
Reserved
R/W
A logic-high powers on the port
Table 27. Global Pushbutton Register
ADDRESS = 1Ah
SYMBOL
CLR_INT
Reserved
Reserved
RESET_IC
Reserved
Reserved
Reserved
RESET_P
BIT NO.
TYPE
R/W
—
7
6
5
4
3
2
1
0
A logic-high clears all interrupts
Reserved
—
Reserved
R/W
—
A logic-high resets the entire device
Reserved
—
Reserved
—
Reserved
R/W
A logic-high resets the port
Table 28. ID Register
ADDRESS = 1Bh
SYMBOL
BIT NO.
TYPE
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
ID_CODE[4]
ID_CODE[3]
ID_CODE[2]
ID_CODE[1]
ID_CODE[0]
REV [2]
ID_CODE
REV
REV [1]
REV [0]
CLR_INT (R1Ah[7]) clears all the event registers and the
corresponding interrupt bits in the interrupt register (R00h,
Table 7). Writing a 1 to RESET_IC (R1Ah[4]) causes a
global software reset, after which all registers are set back
to default values (after reset condition clears). Writing a
1 to RESET_P (R1Ah[0]) turns off power to the port and
resets only the port status and event registers. After the
appropriate command is executed, the bits in the global
pushbutton register all reset to 0.
General Registers (R1Bh to R1Fh)
ID Register (R1Bh)
The ID register (R1Bh, Table 28) keeps track of the
device ID number and revision. The MAX5971B’s ID
code is stored in ID_CODE[4:0] (R1Bh[7:3]) and is
10000. Contact the factory for the value of the revision
code stored in REV[2:0] (R1Bh[2:0]) that corresponds to
the device lot number.
______________________________________________________________________________________ 35
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
SMODE Register (R1Ch)
The SMODE register (R1Ch, Table 29) contains the port
hardware control flag. On a power-up or after a reset
condition, this register is set to a default value of 0x00h.
Enable the SMODE function by setting EN_WHDOG
(R1Fh[7], Table 31) to 1. The SMODE bit goes high when
the watchdog counter reaches zero and the port switch-
es over to hardware-controlled mode. SMODE also goes
high each and every time the software tries to power on
a port, but is denied since the port is in hardware mode.
value of 0x00h. Set EN_WHDOG (R1Fh[7], Table 31) to 1
to enable the watchdog function.
When activated, the watchdog timer counter,
WDTIME[7:0] (R1Eh[7:0]), continuously decrements
toward zero once every 164ms. Use software to initially
set WDTIME[7:0] to a nonzero value. Then, once the
watchdog function is active the software must continue
to set the watchdog register to a nonzero value before
the decrementing value stored in the register reaches
zero. Once the counter reaches zero (also called watch-
dog expiry), the MAX5971B enters hardware-controlled
mode and the port shifts to an operating mode set by
the HWMODE bit (R1Fh[0], Table 31). In this way, the
hardware can gracefully manage the port power during
a software crash, system crash or switchover condition.
Reserved Register (R1Dh)
Register R1Dh is at this time reserved. Writing to this reg-
ister is not recommended as it is internally connected. If
the software needs to do a large batch write command
using the address autoincrement function, write a code
of 0x00h to this register to safely autoincrement past it,
and then continue the write commands as normal.
While in hardware-controlled mode, the MAX5971B
ignores all requests to turn the power on and the flag
SMODE indicates that the hardware has taken control of
the MAX5971B operation. In addition, the software is not
allowed to change the mode of operation in hardware-
controlled mode.
Watchdog Register (R1Eh)
The watchdog register (R1Eh, Table 30) is used to con-
figure the watchdog timer duration. On a power-up or
after a reset condition, this register is set to a default
Table 29. SMODE Register
ADDRESS = 1Ch
DESCRIPTION
SYMBOL
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SMODE
BIT NO.
TYPE
—
7
6
5
4
3
2
1
0
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
CoR
Port hardware control flag
Table 30. Watchdog Register
ADDRESS = 1Eh
DESCRIPTION
SYMBOL
BIT NO.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
WDTIME[7]
WDTIME[6]
WDTIME[5]
WDTIME[4]
WDTIME[3]
WDTIME[2]
WDTIME[1]
WDTIME[0]
WDTIME
36 _____________________________________________________________________________________
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
Switch Mode Register (R1Fh)
the software needs to do a large batch write command
using the address autoincrement function, write a code
of 0x00h to these registers to safely autoincrement past
them, and then continue the write commands as normal.
The switch mode register (R1Fh, Table 31) is used to
enable the watchdog timer, interrupt, and watchdog
expiry port state. On a power-up or after a reset condi-
tion, this register is set to a default value of 0x00h.
Program Register (R23h)
The program register (R23h, Table 32) is used to enable
large capacitor detection, skipping detection in AUTO
mode and for setting the AC disconnect threshold. On a
power-up or after a reset condition, this register is set to
a default value of 00x0 to 0100.
Set EN_WHDOG (R1Fh[7], Table 31) to 1 to enable
the watchdog function. When the watchdog counter
reaches zero, the hardware-controlled mode activates
and sets the port to the operating mode determined by
the HWMODE bit (R1Fh[0]). A 0 in HWMODE places
the port into shutdown mode by setting the P_M[1:0]
bits (R12h[1:0]) to 00. A 1 in HWMODE places the port
into auto mode by setting the P_M[1:0] bits to 11. If
WD_INT_EN is set to 1, an interrupt is sent if the SMODE
bit is set.
CLC_EN (R23h[5]) enables the large capacitor detec-
tion feature. The CLC_EN register can be programmed
directly by the software or by using the LEGACY input
(see the High Capacitance Detection section). When
CLC_EN = 1 the device can recognize a capacitor load
up to 47FF, typ. If the CLC_EN = 0, the MAX5971B per-
forms normal detection.
Special and Reserved Registers
(R20h to R2Fh)
Reserved Registers
(R20h to R22h, R25h to R28h, and R2Bh to R2Fh)
These registers are reserved. Writing to these registers
is not recommended as they are internally connected. If
DET_BY (R23h[4]) is used to allow the port to power
when skipping the detection routine in auto mode. When
DET_BY is set to 0 (default), the port cannot power up
if the port detection sequence was bypassed in auto
Table 31. Switch Mode Register
ADDRESS = 1Fh
DESCRIPTION
SYMBOL
EN_WHDOG
WD_INT_EN
Reserved
Reserved
Reserved
Reserved
Reserved
BIT NO.
R/W
R/W
R/W
—
7
6
5
4
3
2
1
A logic-high enables the watchdog function
Enables interrupt on SMODE bit
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
Port switches to auto mode if logic-high and to shutdown mode if logic-low when watchdog
timer expires
HWMODE
0
R/W
Table 32. Program Register
ADDRESS = 23h
DESCRIPTION
SYMBOL
BIT NO.
R/W
R/W
R/W
R/W
R/W
—
7
6
5
4
3
2
1
0
Reserved
Internally connected. For a write command, always write a zero to this bit.
CLC_EN
DET_BY
Reserved
Large capacitor detection enable
Enables skipping detection in auto mode
Reserved
AC_TH[2]
AC_TH[1]
AC_TH[0]
R/W
R/W
R/W
AC_TH
______________________________________________________________________________________ 37
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
mode. When DET_BY is set to 1 however, the MAX5971B
can power the port without doing the detection routine.
where N
default N
is the decimal value of AC_TH[2:0]. The
is 4 (AC_TH[2:0] = 100) which corre-
AC_TH
AC_TH
sponds to a default I
of ~128FA.
AC_TH
AC_TH[2:0] (R23h[2:0]) allows direct programming of
the AC disconnect threshold. The threshold is defined
as a current since the comparator verifies that the peak
current pulses sensed at the DET input exceeds a preset
threshold. The current threshold is defined as follows:
PWM Register (R24h)
The PWM register (R24h, Table 33) is used to program
the PWM duty cycle. On a power-up or after a reset
condition, this register is set to a default value of 0x00h.
PWM_TH[1:0] (R24h[5:4]) is used to set the PWM duty
cycle. The default PWM_TH[1:0] value of 00 corresponds
to a 6.25% duty cycle, while the maximum PWM_TH[1:0]
value of 11 corresponds to a 25% duty cycle (see Table 34).
I
= 85.28FA + 10.64FA x N
AC_TH
AC_TH
Table 33. PWM Register
ADDRESS = 24h
DESCRIPTION
SYMBOL
Reserved
Reserved
BIT NO.
R/W
—
7
6
5
4
3
2
1
0
Reserved
—
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
PWM_TH[1]
PWM_TH[0]
PWM_TH
Reserved
Internally connected. For a write command, always write a zero to this bit.
Table 34. PWM Duty-Cycle Settings
PWM_TH[1:0]
DUTY CYCLE (%)
00
01
10
11
6.25
12.5
18.75
25.0
38 _____________________________________________________________________________________
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
Miscellaneous Configurations 2 Register (R29h)
ICUT Register (R2Ah)
The ICUT register (R2Ah, Table 36) is used to adjust
the device current limit and corresponding overcurrent
thresholds. On a power-up or after a reset condition, this
register is set to a default value of 0x00h. The MAX5971B
can automatically set the ICUT register (see Table 4) or
ICUT[2:0] can be manually written to by the software
(see Table 37) to manually adjust the current-limit and
overcurrent thresholds.
The miscellaneous configurations 2 register (R29h, Table
35) is used to enable the load stability safety check (see
the PD Detection section). On a power-up or after a reset
condition, this register is set to a default value of 0x00h.
Table 35. Miscellaneous Configurations 2 Register
ADDRESS = 29h
DESCRIPTION
SYMBOL
Reserved
Reserved
Reserved
LSC_EN
BIT NO.
R/W
—
7
6
5
4
3
2
1
0
Reserved
—
Reserved
—
Reserved
R/W
R/W
R/W
—
Enables the load stability safety check
Reserved
Reserved
Reserved
Reserved
Internally connected. For a write command, always write a zero to this bit.
Reserved
Reserved
—
Table 36. ICUT Register
ADDRESS = 2Ah
DESCRIPTION
SYMBOL
Reserved
Reserved
Reserved
Reserved
Reserved
BIT NO.
R/W
—
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
ICUT[2]
—
—
—
—
R/W
R/W
R/W
ICUT
ICUT[1]
ICUT[0]
Table 37. ICUT Current-Limit Threshold Settings
TYPICAL CURRENT-LIMIT THRESHOLD
TYPICAL OVERCURRENT THRESHOLD
(mA)
ICUT_[2:0]
(mA)
000
001
420
720
370
634
010, 011, 100
101
Not Used
850
Not Used
748
110
900
792
111
950
836
______________________________________________________________________________________ 39
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
When the port is powered, the port output current can
be calculated as:
Current Readout Registers
(R30h to R37h)
Port Current Registers (R30h to R31h)
The port current registers (R30h to R31h, Tables 38 and
39) provide port current readout during classification
and normal power mode. On a power-up or after a reset
condition, these registers are both set to a default value
of 0x00h. The port current readout has 9 bits of overall
resolution. The MAX5971B has 8-bit registers, so the
data is split between 2 consecutive registers. R30h[7:0]
contains the highest 8 bits (MSB) and R31h[0] contains
the lowest bit (LSB). To avoid the LSB register changing
while reading the MSB, the register contents are frozen if
the addressing byte points to either of the current read-
out registers.
I
= N
x 2.95mA
OUT
IPD
During classification, the port current is:
= N x 0.0975mA
I
CLASS
IPD
where N
is the decimal value of the 9-bit port current
IPD
readout. The ADC saturates both at full scale and at
zero, resulting in poor current readout accuracy near the
top and bottom codes.
Reserved Registers (R32h to R37h)
Registers R32h to R37h are unconnected; writing to them
has no effect (address autoincrement still functions) and
a read always returns logical zeros.
Table 38. Port Current Register (MSB)
ADDRESS = 30h
DESCRIPTION
SYMBOL
BIT NO.
R/W
R
7
6
5
4
3
2
1
0
IPD[8] (MSB)
IPD[7]
R
R
IPD[6]
R
IPD[5]
IPD
R
IPD[4]
R
IPD[3]
R
IPD[2]
R
IPD[1]
Table 39. Port Current Register (LSB)
ADDRESS = 31h
DESCRIPTION
SYMBOL
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IPD
BIT NO.
R/W
—
—
—
—
—
—
—
R
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IPD[0] (LSB)
40 _____________________________________________________________________________________
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
Table 40. Register Summary
RESET
STATE
ADDR REGISTER NAME
INTERRUPTS
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0000 to
0000
00h Interrupt
R
SUP_INT Reserved IMAX_INT
CL_INT
MASK4
DET_INT
MASK3
LD_INT
MASK2
PG_INT
MASK1
PE_INT
MASK0
1010 to
0100
01h Interrupt Mask
R/W
MASK7
Reserved
MASK5
EVENTS
02h Power Event
03h Power Event CoR
04h Detect Event
05h Detect Event CoR
06h Fault Event
R
CoR
R
0000 to
0000
Reserved Reserved Reserved
Reserved Reserved Reserved
Reserved Reserved Reserved
PG_CHG Reserved Reserved Reserved PWEN_CHG
0000 to
0000
CL_END
Reserved Reserved Reserved DET_END
CoR
R
0000 to
0000
LD_DISC Reserved Reserved Reserved IMAX_FLT
07h Fault Event CoR
08h Startup Event
09h Startup Event CoR
0Ah Supply Event
0Bh Supply Event CoR
STATUS
CoR
R
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
—
CoR
R
0000 to
0000
TSD
Reserved Reserved
V
V
V
EE_UV
Reserved Reserved
EE_UVLO
EE_OV
CoR
0000 to
0000
0Ch Port Status
R
Reserved CLASS[2] CLASS[1] CLASS[0] Reserved DET_ST[2] DET_ST[1] DET_ST[0]
0Dh Reserved
0Eh Reserved
0Fh Reserved
—
—
—
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
—
—
—
0000 to
0000
10h Power Status
R
R
Reserved Reserved Reserved
PGOOD
Reserved Reserved Reserved PWR_EN
OSC LEGACY MIDSPAN Reserved
0000 to
xxx1
11h Pin Status
Reserved Reserved Reserved Reserved
CONFIGURATION
12h Operating Mode
0000 to
0011
R/W
R/W
R/W
R/W
R/W
R/W
Reserved Reserved Reserved Reserved POFF_CL Reserved
P_M[1]
P_M[0]
000x to
000x
13h Disconnect Enable
14h Det/Class Enable
15h Backoff Enable
Reserved Reserved Reserved ACD_EN Reserved Reserved Reserved DCD_EN
0001 to
0001
Reserved Reserved Reserved CLASS_EN Reserved Reserved Reserved DET_EN
Reserved Reserved Reserved Reserved Reserved Reserved Reserved BCKOFF
0000 to
000x
Timing
16h
0000 to
0000
RSRT[1]
INT_EN
RSRT[0] TSTART[1] TSTART[0] TFAULT[1] TFAULT[0] TDISC[1] TDISC[0]
RSRT_EN Reserved Reserved Reserved CL_DISC OUT_ISO HP_TIME
Configuration
Miscellaneous
17h
1100 to
0000
Configurations 1
______________________________________________________________________________________ 41
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
Table 40. Register Summary (continued)
RESET
STATE
ADDR REGISTER NAME
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PUSHBUTTONS
18h Reserved
—
W
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved PWR_OFF Reserved Reserved Reserved PWR_ON
—
0000 to
0000
19h Power Enable
0000 to
0000
1Ah Global
GENERAL
1Bh ID
W
R
CLR_INT Reserved Reserved RESET_IC Reserved Reserved Reserved RESET_P
1000 to
0xxx
ID_CODE[4] ID_CODE[3] ID_CODE[2] ID_CODE[1] ID_CODE[0] REV [2]
REV [1]
REV [0]
SMODE
0000 to
0000
1Ch SMODE
1Dh Reserved
1EH Watchdog
CoR
—
Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
—
0000 to
0000
R/W WDTIME[7] WDTIME[6] WDTIME[5] WDTIME[4] WDTIME[3] WDTIME[2] WDTIME[1] WDTIME[0]
R/W EN_WHDOG WD_INT_EN Reserved Reserved Reserved Reserved Reserved HWMODE
0000 to
0000
1FH Switch Mode
SPECIAL/RESERVED
20H Reserved
—
—
—
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
—
—
—
21H Reserved
22H Reserved
00x0 to
0100
23H Program
24h PWM
R/W
R/W
Reserved Reserved CLC_EN
DET_BY
Reserved AC_TH[2] AC_TH[1] AC_TH[0]
0000 to
0000
Reserved Reserved PWM_TH[1] PWM_TH[0] Reserved Reserved Reserved Reserved
25h Reserved
26h Reserved
27H Reserved
28H Reserved
—
—
—
—
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
—
—
—
—
Miscellaneous
29H
R/W
R/W
Reserved Reserved Reserved
LSC_EN
Reserved Reserved Reserved Reserved 0000-0000
0000 to
Configurations 2
2AH ICUT
Reserved Reserved Reserved Reserved Reserved
ICUT[2]
ICUT[1]
ICUT[0]
0000
—
2BH Reserved
2CH Reserved
2DH Reserved
2EH Reserved
2FH Reserved
—
—
—
—
—
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
—
—
—
—
42 _____________________________________________________________________________________
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
Table 40. Register Summary (continued)
RESET
STATE
ADDR REGISTER NAME
CURRENT READOUT
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0000 to
0000
30H Port Current (MSB)
R
R
IPD[8]
IPD[7]
IPD[6]
IPD[5]
IPD[4]
IPD[3]
IPD[2]
IPD[1]
IPD[0]
0000 to
0000
31H Port Current (LSB)
Reserved Reserved Reserved Reserved Reserved Reserved Reserved
32H Reserved
33H Reserved
34H Reserved
35H Reserved
36H Reserved
37H Reserved
—
—
—
—
—
—
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
—
—
—
—
—
—
3) Use short, wide traces whenever possible for high-
power paths.
Applications Information
Layout Procedure
Careful PCB layout is critical to achieve high efficiency
and low EMI. Follow these layout guidelines for optimal
performance.
4) Use the MAX5971B Evaluation Kit as a design and
layout reference.
5) The EP must be soldered evenly to the PCB ground
plane (V ) for proper operation and power dissipa-
EE
1) Place the high-frequency input bypass capacitor (0.1FF
tion. Use multiple vias beneath the EP for maximum
heat dissipation. A 1.0mm to 1.2mm pitch is the
recommended spacing for these vias and should
be plated (1oz copper) with a small barrel diameter
(0.30mm to 0.33mm).
ceramic capacitor from AGND to V ) and the output
EE
bypass capacitor (0.1FF ceramic capacitor from AGND
to OUTP) as close as possible to the MAX5971B.
2) Use large SMT component pads for power dissipat-
ing devices, such as the MAX5971B and the external
diodes in the high-power path.
0.1µF
2.2MI
100V
1N4448
10mH
SMJ58A
PSE OUTPUT
47µF
100V
0.1µF
100V
LED
AGND
OUT
LED
EN
5.1kI
OUTP
1N4448
1nF
MAX5971B
DET
-54V
V
V
EE
ILIM1
-54V
EE_DIG
1kI
1kI
LEGACY
MIDSPAN
OSC
ILIM2
PWMEN
SDA SCL AD0 INT
SERIAL INTERFACE
Figure 15. Typical Operating Circuit 1 (DC Load Removal Detection, Internal PWM Enabled for LED Indication, and Class 5
Detection Enabled)
______________________________________________________________________________________ 43
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
0.1µF
100V
2.2MI
PSE OUTPUT
1N4448
10mH
SMJ58A
47µF
100V
0.1µF
100V
LED
AGND
OUT
LED
EN
5.1kI
OUTP
0.47µF
100V
1N4448
1nF
DET
MAX5971B
-54V
V
1kI
EE
V
EE_DIG
ILIM1
-54V
1kI
1kI
LEGACY
MIDSPAN
OSC
ILIM2
PWMEN
SDA SCL AD0 INT
0.1µF
SERIAL INTERFACE
Figure 16. Typical Operating Circuit 2 (AC Load Removal Detection, Internal PWM Enabled for LED Indication, and Class 5
Detection Enabled)
47µF
100V
0.1µF
100V
0.1µF
100V
2.2MI
SMJ58A
PSE OUTPUT
AGND
V
V
-54V
EE
OUT
OUTP
EE_DIG
EN
1N4448
1nF
MAX5971B
LED
DET
ILIM1
ILIM2
PWMEN
LEGACY
MIDSPAN
OSC
SDA SCL AD0 INT
SERIAL INTERFACE
Figure 17. Typical Operating Circuit 3 (IEEE 802.3at Compliant, Minimal Application Circuit with DC Load Removal Detection and
No LED Indication)
44 _____________________________________________________________________________________
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
Chip Information
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PROCESS: BiCMOS
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
28 TQFN-EP
T2855+6
21-0140
90-0026
______________________________________________________________________________________ 45
Single-Port, 40W, IEEE 802.3af/at,
2
PSE Controller with I C
Revision History
REVISION REVISION
DESCRIPTION
PAGES
CHANGED
NUMBER
DATE
0
6/10
Initial release
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
46
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
©
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