UPD8873CY [NEC]
(5400 ?5400) PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR; ( 5400 ? 5400 )像素× 3彩色CCD线性图像传感器型号: | UPD8873CY |
厂家: | NEC |
描述: | (5400 ?5400) PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR |
文件: | 总32页 (文件大小:252K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD8873
(5400 × 5400) PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR
DESCRIPTION
The µPD8873 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to
electrical signal and has the function of color separation.
The µPD8873 has 3 rows of (5400 + 5400) staggered pixels, and each row has a dual-sided readout-type charge
transfer register. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for
1200 dpi/A4 color image scanners, color facsimiles and so on.
FEATURES
• Valid photocell : (5400 + 5400) staggered pixels × 3
• Photocell pitch : 5.25 µm
• Line spacing
: 63 µm (12 lines) Red line - Green line, Green line - Blue line
10.5 µm (2 lines) Odd line - Even line (for each color)
• Color filter
• Resolution
: Primary colors (red, green and blue), pigment filter (with light resistance 107 lx•hour)
: 48 dot/mm A4 (210 × 297 mm) size (shorter side)
1200 dpi US letter (8.5” × 11”) size (shorter side)
• Drive clock level : CMOS output under 5 V operation
• Data rate
: 12.5 MHz Max.
: +12 V
• Power supply
• On-chip circuits : Reset feed-through level clamp circuits
Voltage amplifiers
ORDERING INFORMATION
Part Number
Package
CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
µPD8873CY
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S16614EJ2V0DS00 (2nd edition)
Date Published July 2003 NS CP (K)
Printed in Japan
2003
µPD8873
BLOCK DIAGRAM
φ
φ
φ
φ
1
SEL
19
2
2
V
OD
GND GND
11
20
2
17
15
14
CCD analog shift register
Transfer gate
φ
TG1
(Blue)
13
12
10
V
(Blue)
OUT
1
21
22
1
Photocell
(Blue)
······
······
······
Transfer gate
CCD analog shift register
CCD analog shift register
Transfer gate
φ
TG2
(Green)
V
OUT2
Photocell
(Green)
(Green)
Transfer gate
CCD analog shift register
CCD analog shift register
Transfer gate
φ
TG3
(Red)
V
(Red)
OUT3
Photocell
(Red)
Transfer gate
CCD analog shift register
4
3
5
9
8
φ
φ
φ
1
φ
1
2
φ
R
CLB
2
Data Sheet S16614EJ2V0DS
µPD8873
PIN CONFIGURATION (Top View)
CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
• µPD8873CY
Output signal 3 (Red)
Ground
V
OUT
3
1
2
22
21
20
19
V
V
V
φ
OUT
OUT
OD
2
1
Output signal 2 (Green)
GND
Output signal 1 (Blue)
Output drain voltage
Reset gate clock
φ
3
R
Reset feed-through level clamp clock
Shift register clock 1
No connection
φ
4
SEL dpi selector
CLB
φ
1
5
18 NC
17
16 NC
No connection
NC
NC
6
φ
2
Shift register clock 2
No connection
No connection
7
Shift register clock 1
Shift register clock 2
φ
φ
1
2
8
15
14
13
12
φ
φ
φ
φ
2
Shift register clock 2
Shift register clock 1
9
1
Transfer gate clock 3
(for Red)
Transfer gate clock 1
(for Blue)
φ
10
TG1
TG2
TG3
Transfer gate clock 2
(for Green)
GND 11
Ground
Caution Connect the No connection pins (NC) to GND.
3
Data Sheet S16614EJ2V0DS
µPD8873
PHOTOCELL STRUCTURE DIAGRAM
2.5
µ
m
2.75
µ
m
µ
Channel stopper
Aluminum
shield
PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing)
5.25 µm
5.25 µm
5.25 µm
Blue photocell array
Blue photocell array
2 lines
(10.5
µ
m)
12 lines
(63 m)
µ
10 lines
(52.5
µ
m)
5.25 µm
5.25 µm
5.25 µm
Green photocell array
Green photocell array
2 lines
(10.5
µ
m)
12 lines
(63 m)
µ
10 lines
(52.5
µ
m)
5.25
5.25
5.25
µ
µ
µ
m
m
m
Red photocell array
Red photocell array
2 lines
(10.5
µ
m)
4
Data Sheet S16614EJ2V0DS
µPD8873
ABSOLUTE MAXIMUM RATINGS (TA = +25°C)
Parameter
Output drain voltage
Symbol
Ratings
−0.3 to +15
−0.3 to +8
−0.3 to +8
−0.3 to +8
−0.3 to +8
−0.3 to +8
0 to +60
Unit
V
VOD
Shift register clock voltage
Vφ 1, Vφ 2
Vφ R
V
Reset gate clock voltage
V
Reset feed-through level clamp clock voltage
dpi select signal voltage
Vφ CLB
Vφ SEL
Vφ TG1 to Vφ TG3
TA
V
V
Transfer gate clock voltage
Operating ambient temperature Note
Storage temperature
V
°C
°C
Tstg
−40 to +70
Note Use at the condition without dew condensation.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (TA = +25°C)
Parameter
Output drain voltage
Symbol
Min.
11.4
4.75
0
Typ.
12.0
5.0
0
Max.
12.6
5.5
Unit
V
VOD
Shift register clock high level
Shift register clock low level
Reset gate clock high level
Reset gate clock low level
Vφ 1H, Vφ 2H
Vφ 1L, Vφ 2L
Vφ RH
V
0.15
5.5
V
4.75
0
5.0
0
V
Vφ RL
0.15
5.5
V
Reset feed-through level clamp clock high level
Reset feed-through level clamp clock low level
dpi select signal high level
dpi select signal low level
Vφ CLBH
4.75
0
5.0
0
V
Vφ CLBL
0.15
5.5
V
Vφ SELH
4.75
0
5.0
0
V
Vφ SELL
0.15
V
Note
Note
Transfer gate clock high level
Transfer gate clock low level
Data rate
Vφ TG1H to Vφ TG3H
Vφ TG1L to Vφ TG3L
fφ R
4.75
0
Vφ 1H
Vφ 1H
V
0
0.15
12.5
12.5
V
−
2.0
2.0
MHz
MHz
Clock pulse frequency
fφ 1, fφ 2
−
Note When Transfer gate clock high level (Vφ TG1H to Vφ TG3H) is higher than Shift register clock high level (Vφ 1H),
Image lag can increase.
5
Data Sheet S16614EJ2V0DS
µPD8873
ELECTRICAL CHARACTERISTICS
TA = +25°C, VOD = 12 V, data rate (fφ R) = 2 MHz, storage time = 5.5 ms, input signal clock = 5 Vp-p,
light source : 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm) + HA-50 (heat absorbing filter, t = 3 mm)
Parameter
Saturation voltage
Saturation exposure
Symbol
Vsat
Test Conditions
Min.
Typ.
2.7
Max.
−
Unit
V
2.4
Red
SER
SEG
SEB
PRNU
ADS
DSNU
PW
−
0.423
0.431
0.668
6
−
lx•s
lx•s
lx•s
%
Green
Blue
−
−
−
−
Photo response non-uniformity
Average dark signal
VOUT = 1.0 V
−
20
2.0
5.0
540
1.00
8.30
8.14
5.25
7.0
7.0
−
Light shielding
Light shielding
−
0.2
mV
mV
mW
kΩ
Dark signal non-uniformity
Power consumption
−
1.5
−
360
0.35
6.38
6.26
4.04
3.0
Output impedance
ZO
−
Response
Red
RR
4.47
V/lx•s
V/lx•s
V/lx•s
%
Green
Blue
RG
4.38
RB
2.83
Image lag
IL
VOUT = 1.0 V
−
Offset level
VOS
td
5.0
6.0
V
Output fall delay time Note
Total transfer efficiency
Register imbalance
Response peak
VOUT = 1.0 V, t1, t2 = 25 ns
VOUT = 1.0 V, data rate = 12.5 MHz
VOUT = 1.0 V
−
20
ns
TTE
RI
92
98
−
%
−
1.0
4.0
−
%
Red
−
630
540
460
1800
2700
−100
500
1.0
nm
Green
Blue
−
−
nm
−
−
nm
Dynamic range
DR1
Vsat/DSNU
−
−
times
times
mV
mV
mV
DR2
Vsat/σCDS
−
−
Reset feed-through noise
Random noise (CDS)
RFTN
Light shielding
−2000
+500
800
−
PRFTN Light shielding
σCDS Light shielding
−
−
Note When the fall time of φ 1 and φ 2 (t1, t2) is the Typ. value (refer to TIMING CHART 2-1 to 2-3).
6
Data Sheet S16614EJ2V0DS
µPD8873
INPUT PIN CAPACITANCE (TA = +25°C, VOD = 12 V)
Parameter
Symbol
Pin name Pin No.
Min.
−
Typ.
370
370
370
1110
370
370
370
1110
10
Max.
−
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Shift register clock pin capacitance 1
Cφ 1
φ 1
5
8
−
−
14
−
−
φ 1 total capacitance
φ 2
−
−
Shift register clock pin capacitance 2
Reset gate clock pin capacitance
Cφ 2
9
−
−
15
17
−
−
−
−
φ 2 total capacitance
−
−
Cφ R
φ R
3
−
−
Reset feed-through level clamp clock pin capacitance Cφ CLB
φ CLB
φ SEL
φ TG1
φ TG2
φ TG3
4
−
10
−
dpi select signal pin capacitance
Transfer gate clock pin capacitance
Cφ SEL
19
13
12
10
−
10
−
Cφ TG
−
100
100
100
−
−
−
−
−
Remarks 1. Pin 5, 8, 14 (φ 1) and pin 9, 15, 17 (φ 2) are each connected inside of the device.
2. Cφ 1 and Cφ 2 show the equivalent capacity of the real drive including the capacity of between φ 1 and
φ 2.
7
Data Sheet S16614EJ2V0DS
TIMING CHART 1-1 (1200 dpi, bit clamp mode, for each color)
φ
TG1 to
φ
TG3
φ
φ
1
2
φ
R
Note
Note
φ
φ
CLB
SEL
“H”
V
OUT1 to VOUT3
Optical black
(47 pixels)
Valid photocell
(10800 pixels)
Invalid photocell
(4 pixels)
Invalid photocell
(4 pixels)
µ
Note Set the φ R to low level and φ CLB to high level during this period.
TIMING CHART 1-2 (1200 dpi, line clamp mode, for each color)
φ
TG1 to φTG3
φ
φ
1
2
φ
R
Note
Note
φ
CLB
(φ TG1 to φ
TG3)
“H”
φ
SEL
V
OUT1 to VOUT3
Optical black
(47 pixels)
Valid photocell
(10800 pixels)
Invalid photocell
(4 pixels)
Invalid photocell
(4 pixels)
µ
Note Set the φ R and φ CLB to low level during this period.
Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB.
TIMING CHART 1-3 (600 dpi, bit clamp mode, for each color)
φ
TG1 to
φ
TG3
φ
φ
1
2
φ
R
Note
Note
φ
φ
CLB
SEL
“L”
VOUT1 to VOUT3
Optical black
(24 pixels)
Valid photocell
(5400 pixels)
Invalid photocell
(2 pixels)
Invalid photocell
(2 pixels)
µ
Note Set the φ R to low level and φ CLB to high level during this period.
TIMING CHART 1-4 (600 dpi, line clamp mode, for each color)
φ
TG1 to φTG3
φ
φ
1
2
φ
R
Note
Note
φ
CLB
(φ TG1 to φ
TG3)
φ
SEL
“L”
VOUT1 to VOUT3
Optical black
(24 pixels)
Valid photocell
(5400 pixels)
Invalid photocell
(2 pixels)
Invalid photocell
(2 pixels)
µ
Note Set the φ R and φ CLB to low level during this period.
Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB.
TIMING CHART 1-5 (300 dpi, bit clamp mode, for each color)
φ
TG1 to
φ
TG3
φ
φ
1
2
φ
R
Note
Note
φ
φ
CLB
SEL
“L”
V
OUT1 to VOUT3
Optical black
(12 pixels)
Valid photocell
(2700 pixels)
Invalid photocell
(1 pixels)
Invalid photocell
(1 pixels)
µ
Note Set the φ R to low level and φ CLB to high level during this period.
TIMING CHART 1-6 (300 dpi, line clamp mode, for each color)
φ
TG1 to φTG3
φ
φ
1
2
φ
R
Note
Note
φ
CLB
(φ TG1 to φ
TG3)
φ
SEL
“L”
V
OUT1 to VOUT3
Optical black
(12 pixels)
Valid photocell
(2700 pixels)
Invalid photocell
(1 pixels)
Invalid photocell
(1 pixels)
µ
Note Set the φ R and φ CLB to low level during this period.
Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB.
µPD8873
TIMING CHART 2-1 (1200 dpi, for each color)
t1
t2
90%
10%
φ
φ
1
2
90%
10%
90%
10%
φ
R
t3
t3
t5
t4
t5
t4
t8
t9
t8
t9
t7
t6
t7
t6
t10
t10
90%
10%
φ
CLB
(Bit clamp mode)
“H”
(Line clamp mode)
φ
CLB
t11
t12
td
td
VOUT
10%
Symbol
t1, t2
Min.
Typ. Note
25
Max.
Unit
0
20
0
−
−
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
t3
50
t4, t5
t6
20
15
10
0
25
t7
50
t8, t9
t10
t11
t12
20
5
45
40
40
−
−
Note Typ. is the case of φ R = 2 MHz.
14
Data Sheet S16614EJ2V0DS
µPD8873
TIMING CHART 2-2 (600 dpi, for each color)
t2
t1
90%
10%
φ
φ
1
2
90%
10%
90%
10%
φ
R
t3
t4
t5
t8
t9
t7
t6
t10
90%
10%
φ
CLB
(Bit clamp mode)
“H”
(Line clamp mode)
φ
CLB
t11
t12
td
VOUT
10%
Symbol
t1, t2
Min.
Typ. Note
25
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
20
0
−
−
−
−
−
−
−
−
−
t3
50
t4, t5
t6
20
15
10
0
25
t7
50
t8, t9
t10
t11
t12
20
5
45
40
40
−
−
Note Typ. is the case of φ R = 2 MHz.
15
Data Sheet S16614EJ2V0DS
µPD8873
TIMING CHART 2-3 (300 dpi, for each color)
t2
90%
t1
φ
φ
1
2
10%
90%
10%
90%
10%
φ
R
t3
t4 t5
t8 t9
t6 t7
t10
90%
10%
φ
CLB
(Bit clamp mode)
“H”
(Line clamp mode)
φ
CLB
t11
t12
t
d
V
OUT
10%
Symbol
t1, t2
Min.
0
Typ. Note
25
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
−
−
−
−
−
−
−
−
−
t3
20
0
50
t4, t5
t6
20
15
10
0
25
t7
50
t8, t9
t10
t11
t12
20
5
45
40
40
−
−
Note Typ. is the case of φ R = 1 MHz.
16
Data Sheet S16614EJ2V0DS
µPD8873
φ TG1 to φ TG3, φ 1, φ 2 TIMING CHART
t14
90%
10%
t16
t15
t13
φ
TG1 to φ TG3
t17
90%
φ
φ
1
2
t18
Note 1
t19
φ
R
10%
t6
90%
φ
CLB
(Bit clamp mode)
t21
t22
t23
Note 2
t24
90%
10%
φ
CLB
(Line clamp mode)
t8
t20
t9
Symbol
Min.
Typ.
25
Max.
Unit
t6
15
0
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t8, t9
t13
20
−
5000
0
10000
50
50000
t14, t15
t16, t17
t18, t19
t20
−
900
200
t13
0
1000
400
t13
−
−
50000
t21, t22
t23
50
−
−
−
t6
t6
t24
0
350
Notes 1. Set the φ R to low level and φ CLB to high level during this period.
2. Set the φ R to low level during this period.
Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB.
17
Data Sheet S16614EJ2V0DS
µPD8873
φ 1, φ 2 CROSS POINTS
t25
t27
φ
φ
1
2
4.75 V
0.25 V
1.5 V to 3.5 V
t26
Symbol
t25
Min.
Typ.
Max.
Unit
80
35
−
−
−
−
ns
ns
t26, t27
φ TG, φ SEL TIMING CHART
90%
φ
TG
t28
φ
φ
SEL (High to Low)
SEL (Low to High)
90%
10%
Symbol
Min.
0
Typ.
Max.
Unit
ns
t28
0
−
18
Data Sheet S16614EJ2V0DS
µPD8873
SELECTION OF RESOLUTION MODE
The µPD8873 has function of two readout modes, High Resolution Mode and Low Resolution Mode. These two
modes can be selected by φ SEL switch.
Read Mode
High Resolution Mode
Low Resolution Mode
Description
φ SEL
1200 dpi (Max.)
600 dpi (Max.) (even line readout mode)
High level
Low level
(1) High Resolution Mode
In this mode, both signals in even lines and odd lines can be read out. This mode enables 1200 dpi (Max.)
resolution with A4 size (210 × 297 mm, shorter side).
Please refer to TIMING CHART 1-1, 1-2 and 2-1.
(2) Low Resolution Mode
In this mode, only signal in even lines can be read out.
This mode enables 600 dpi (Max.) resolution with A4 size.
To use intermittent reset drive enable signal charges of adjacent pixels in even line to add at the charge to voltage
conversion area. Then it can achieve low resolution with A4 size such as 300, 200 or 150 dpi.
Please refer to TIMING CHART 1-3 to 1-6, 2-2 and 2-3.
19
Data Sheet S16614EJ2V0DS
µPD8873
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage : Vsat
Output signal voltage at which the response linearity is lost.
2. Saturation exposure : SE
Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs.
3. Photo response non-uniformity : PRNU
The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light
of uniform illumination. This is calculated by the following formula.
x
∆
PRNU (%) =
× 100
x
∆
x : maximum of x
j
− x
10800
x
j
Σ
j = 1
10800
: Output voltage of valid pixel number j
x =
xj
VOUT
x
Register Dark
DC level
∆
x
4. Average dark signal : ADS
Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following
formula.
10800
d
j
Σ
j = 1
10800
ADS (mV) =
d
j
: Dark signal of valid pixel number j
20
Data Sheet S16614EJ2V0DS
µPD8873
5. Dark signal non-uniformity : DSNU
Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the
valid pixels at light shielding. This is calculated by the following formula.
DSNU (mV) : maximum of d
j
− ADS j = 1 to 10800
d
j
: Dark signal of valid pixel number j
VOUT
ADS
Register Dark
DC level
DSNU
6. Output impedance : ZO
Impedance of the output pins viewed from outside.
7. Response : R
Output voltage divided by exposure (lx•s).
Note that the response varies with a light source (spectral characteristic).
8. Image lag : IL
The rate between the last output voltage and the next one after read out the data of a line.
φ
TG
Light
ON
OFF
V
OUT
V
1
V
OUT
V
1
IL (%) =
× 100
OUT
V
21
Data Sheet S16614EJ2V0DS
µPD8873
9. Register imbalance: RI
The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the
average output voltage of all the valid pixels.
n
2
2
n
∑
(V2j –1 – V2j
n
)
j = 1
RI (%) =
× 100
1
n
∑
V
j
j = 1
n
V
: Number of valid pixels
: Output voltage of each pixel
j
10. Offset level : VOS
DC level of output signal is defined as follows.
11. Reset feed-through noise : RFTN, PRFTN
Reset feed-through noise (RFTN) and peak of RFTN (PRFTN) are defined as follows.
+
PRFTN
PRFTN
RFTN
–
VOUT
VOS
22
Data Sheet S16614EJ2V0DS
µPD8873
12. Random noise (CDS) : σCDS
Random noise σCDS is defined as the standard deviation of a valid pixel output signal with 100 times (=100
lines) data sampling at dark (light shielding). σCDS is calculated by the following procedure.
1. One valid photocell in one reading is fixed as measurement point.
2. The output level is measured during the reset feed-through period which is averaged over 100 ns to get
“VDi”.
3. The output level is measured during the video output time averaged over 100 ns to get “VOi”.
4. The correlated double sampling output is defined by the following formula.
VCDSi = VDi – VOi
5. Repeat the above procedure (1 to 4) for 100 times (= 100 lines).
6. Calculate the standard deviation σ CDS using the following formula equation.
100
100
(VCDS
100
i
– V)2
1
Σ
σ
CDS (mV) =
, V =
VCDS
i
100 Σ
i = 1
i = 1
Reset feed-through
Video output
23
Data Sheet S16614EJ2V0DS
µPD8873
STANDARD CHARACTERISTIC CURVES (Reference Value)
DARK OUTPUT TEMPERATURE
CHARACTERISTIC
STORAGE TIME OUTPUT VOLTAGE
CHARACTERISTIC (T = +25°C)
A
8
2
4
1
2
1
0.5
0.2
0.25
0.1
0.1
0
10
20
30
40
50
1
5
10
Operating Ambient Temperature T
A
(°C)
Storage Time (ms)
TOTAL SPECTRAL RESPONSE CHARACTERISTICS
(without infrared cut filter and heat absorbing filter) (T = +25°C)
A
100
80
R
B
G
60
40
20
G
B
0
400
500
600
700
800
Wavelength (nm)
24
Data Sheet S16614EJ2V0DS
µPD8873
APPLICATION CIRCUIT EXAMPLE
+5 V
+12 V
+
+
µ
PD8873
1
2
22
21
20
19
18
17
16
15
14
13
12
10 µF/16 V 0.1 µF
B3
V
OUT
3
V
OUT
OUT
2
1
B2
B1
0.1
0.1
µ
µ
F 47
µ
µ
F/25 V
+5 V
GND
V
47
Ω
3
+
φ
R
φ
φ
φ
R
V
OD
47 Ω
150 Ω
4
φ
CLB
CLB
1
φ
SEL
NC
F 10
F/16 V
4.7 Ω
5
φ
SEL
4.7 Ω
6
NC
NC
φ
2
7
NC
4.7 Ω
4.7 Ω
10 Ω
4.7 Ω
4.7 Ω
10 Ω
10 Ω
8
φ
φ
φ
1
φ
φ
2
1
9
2
φ
φ
1
φ
2
10
11
TG3
φ
φ
TG1
TG2
TG
GND
Caution Connect the No connection pins (NC) to GND.
Remarks 1. The inverters shown in the above application circuit example are the 74HC04 (fφ R < 2 MHz) or the
74AC04 (2 MHz ≤ fφ R ≤ 12.5 MHz).
2. Inverters B1 to B3 in the above application circuit example are shown in the figure below.
B1 to B3 EQUIVALENT CIRCUIT
12 V
+
µ
47 F/25 V
100 Ω
CCD
2SC945
2 kΩ
V
OUT
100 Ω
25
Data Sheet S16614EJ2V0DS
µPD8873
PACKAGE DRAWING
µ
PD8873CY
CCD LINEAR IMAGE SENSOR 22-PIN PLASTIC DIP (10.16 mm (400))
(Unit : mm)
44.0 0.3
1st valid pixel
1
9.25 0.3
0.5 0.3
22
12
11
1
4
4
2.0
37.5
2
10.16 0.2
(1.72)
1.02 0.15
4.39 0.4
3
2.62 0.2
(5.42)
4.21 0.5
0.25 0.05
0.46 0.1
2.54 0.25
+0.7
10.16
−0.2
Name
Dimensions
42.7×8.35×0.8(0.7
Refractive index
5
Plastic cap
)
1.5
1 1st valid pixel
The center of the pin1
2 The surface of the CCD chip
3 The bottom of the package
4 Mirror finished surface
The top of the cap
The surface of the CCD chip
5 Thickness of mirror finished surface
22C-1CCD-PKG17
26
Data Sheet S16614EJ2V0DS
µPD8873
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below.
If other soldering processes are used, or if the soldering is performed under different conditions, please make sure
to consult with our sales offices.
Type of Through-hole Device
µPD8873CY : CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
Process
Conditions
Partial heating method
Pin temperature : 300 °C or below, Heat time : 3 seconds or less (per pin)
Cautions 1.
2.
During assembly care should be taken to prevent solder or flux from contacting the plastic
cap. The optical characteristics could be degraded by such contact.
Soldering by the solder flow method may have deleterious effects on prevention of plastic
cap soiling and heat resistance. So the method cannot be guaranteed.
27
Data Sheet S16614EJ2V0DS
µPD8873
NOTES ON HANDLING THE PACKAGES
1
DUST AND DIRT PROTECTING
The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. Don’t either
touch plastic cap surface by hand or have any object come in contact with plastic cap surface. Should dirt
stick to a plastic cap surface, blow it off with an air blower. For dirt stuck through electricity ionized air is
recommended. And if the plastic cap surface is grease stained, clean with our recommended solvents.
CLEANING THE PLASTIC CAP
Care should be taken when cleaning the surface to prevent scratches.
We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below.
Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is
recommended that a clean surface or cloth be used.
RECOMMENDED SOLVENTS
The following are the recommended solvents for cleaning the CCD plastic cap.
Use of solvents other than these could result in optical or physical degradation in the plastic cap.
Please consult your sales office when considering an alternative solvent.
Solvents
Ethyl Alcohol
Symbol
EtOH
MeOH
IPA
Methyl Alcohol
Isopropyl Alcohol
N-methyl Pyrrolidone
NMP
2
MOUNTING OF THE PACKAGE
The application of an excessive load to the package may cause the package to warp or break, or cause chips
to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't
have any object come in contact with plastic cap. You should not reform the lead frame. We recommended to
use a IC-inserter when you assemble to PCB.
Also, be care that the any of the following can cause the package to crack or dust to be generated.
1. Applying heat to the external leads for an extended period of time with soldering iron.
2. Applying repetitive bending stress to the external leads.
3. Rapid cooling or heating
3
4
OPERATE AND STORAGE ENVIRONMENTS
Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject
to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid
storage or usage in such conditions.
Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the
devices are transported from a low-temperature environment to a high-temperature environment. Avoid such
rapid temperature changes.
For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E)
ELECTROSTATIC BREAKDOWN
CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes
detected. Before handling be sure to take the following protective measures.
1. Ground the tools such as soldering iron, radio cutting pliers of or pincer.
2. Install a conductive mat or on the floor or working table to prevent the generation of static electricity.
3. Either handle bare handed or use non-chargeable gloves, clothes or material.
4. Ionized air is recommended for discharge when handling CCD image sensor.
5. For the shipment of mounted substrates, use box treated for prevention of static charges.
6. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on
which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle
straps which are grounded via a series resistance connection of about 1 MΩ.
28
Data Sheet S16614EJ2V0DS
µPD8873
[MEMO]
29
Data Sheet S16614EJ2V0DS
µPD8873
[MEMO]
30
Data Sheet S16614EJ2V0DS
µPD8873
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
31
Data Sheet S16614EJ2V0DS
µPD8873
•
The information in this document is current as of July, 2003. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
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and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
相关型号:
UPD8874CY-A
CCD Sensor, 5400 Horiz pixels, 5400 Vert pixels, 2-2.50V, Rectangular, Through Hole Mount, 10.16 MM, PLASTIC, DIP-22
NEC
UPD8894CY-A
CCD Sensor, 5340 Horiz pixels, 5340 Vert pixels, 2.50-2.80V, Rectangular, Through Hole Mount, PLASTIC, DIP-32
NEC
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