PBSS5255PAPS-Q [NEXPERIA]
55V, 2A PNP/PNP low VCEsat (BISS) double transistorProduction;
| 型号： | PBSS5255PAPS-Q |
| 厂家： | 
Nexperia |
| 描述： | 55V, 2A PNP/PNP low VCEsat (BISS) double transistorProduction |
| 文件： | 总15页 (文件大小：279K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PBSS5255PAPS-Q
55V, 2A PNP/PNP low VCEsat (BISS) double transistor
23 September 2021
Product data sheet
1. General description
PNP/PNP low VCEsat Breakthrough In Small Signal (BISS) double transistor in a leadless medium
power DFN2020D-6 (SOT1118D) Surface-Mounted Device (SMD) plastic package with visible and
solderable side pads.
2. Features and benefits
•
Very low collector-emitter saturation voltage VCEsat
•
•
•
•
•
•
•
High collector current capability IC and ICM
High collector current gain hFE at high IC
Reduced Printed-Circuit Board (PCB) requirements
Exposed heat sink for excellent thermal and electrical conductivity
High energy efficiency due to less heat generation
Suitable for Automatic Optical Inspection (AOI) of solder joints
Qualified according to AEC-Q101 and recommended for use in automotive applications
3. Applications
•
•
•
•
•
•
Load switch
Battery-driven devices
Power management
Charging circuits
LED lighting
Power switches (e.g. motors, fans)
4. Quick reference data
Table 1. Quick reference data
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Per transistor
VCEO
collector-emitter
voltage
open base
-
-
-55
V
IC
collector current
-
-
-
-
-2
A
ICM
peak collector current single pulse; tp ≤ 1 ms
-
-3
A
VCEsat
collector-emitter
saturation voltage
IC = -0.7 A; IB = -7 mA; pulsed; tp ≤
300 µs; δ ≤ 0.02; Tamb = 25 °C
-300
-420
mV
Nexperia
PBSS5255PAPS-Q
55V, 2A PNP/PNP low VCEsat (BISS) double transistor
5. Pinning information
Table 2. Pinning information
Pin
1
Symbol
E1
Description
emitter TR1
base TR1
Simplified outline
Graphic symbol
6
5
4
3
C1 B2
E2
2
B1
3
C2
collector TR2
emitter TR2
base TR2
7
8
TR2
4
E2
TR1
5
B2
1
2
E1
B1 C2
6
C1
collector TR1
collector TR1
collector TR2
Transparent top view
7
C1
sym138
DFN2020D-6 (SOT1118D)
8
C2
6. Ordering information
Table 3. Ordering information
Type number
Package
Name
Description
Version
PBSS5255PAPS-Q
DFN2020D-6 plastic, leadless thermally enhanced ultra thin and small
outline package with side-wettable flanks (SWF); 6
SOT1118D
terminals; 0.65 mm pitch; 2 mm x 2 mm x 0.65 mm body
7. Marking
Table 4. Marking codes
Type number
Marking code
3N
PBSS5255PAPS-Q
©
PBSS5255PAPS-Q
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Nexperia B.V. 2021. All rights reserved
Product data sheet
23 September 2021
2 / 15
Nexperia
PBSS5255PAPS-Q
55V, 2A PNP/PNP low VCEsat (BISS) double transistor
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
Per transistor
VCBO
VCEO
VEBO
IC
collector-base voltage
open emitter
-
-
-
-
-
-
-
-
-
-
-
-55
-55
-7
V
collector-emitter voltage open base
V
emitter-base voltage
collector current
open collector
V
-2
A
ICM
peak collector current
base current
single pulse; tp ≤ 1 ms
-3
A
IB
-0.3
-1
A
IBM
peak base current
total power dissipation
single pulse; tp ≤ 1 ms
Tamb ≤ 25 °C
A
Ptot
[1]
[2]
[3]
[4]
370
570
530
700
mW
mW
mW
mW
Per device
Ptot
total power dissipation
Tamb ≤ 25 °C
[1]
[2]
[3]
[4]
-
510
780
730
960
150
150
150
mW
mW
mW
mW
°C
-
-
-
Tj
junction temperature
ambient temperature
storage temperature
-
Tamb
Tstg
-55
-65
°C
°C
[1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint.
[2] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1 cm2.
[3] Device mounted on an FR4 PCB, 4-layer copper, tin-plated and standard footprint.
[4] Device mounted on an FR4 PCB, 4-layer copper, tin-plated and mounting pad for collector 1 cm2.
©
PBSS5255PAPS-Q
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
23 September 2021
3 / 15
Nexperia
PBSS5255PAPS-Q
55V, 2A PNP/PNP low VCEsat (BISS) double transistor
aaa-020729
1
P
tot
(W)
0.8
0.6
0.4
0.2
0
(4)
(3)
(2)
(1)
-75
-25
25
75
125
175
(°C)
T
amb
(1) FR4 PCB, single-sided copper, standard footprint
(2) FR4 PCB, 4-layer copper, standard footprint
(3) FR4 PCB, single-sided copper, 1 cm2
(4) FR4 PCB, 4-layer copper, 1 cm2
Fig. 1. Power derating curves
©
PBSS5255PAPS-Q
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
23 September 2021
4 / 15
Nexperia
PBSS5255PAPS-Q
55V, 2A PNP/PNP low VCEsat (BISS) double transistor
9. Thermal characteristics
Table 6. Thermal characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Per transistor
Rth(j-a)
thermal resistance from in free air
junction to ambient
[1]
[2]
[3]
[4]
-
-
-
-
-
-
-
-
338
219
236
179
K/W
K/W
K/W
K/W
Per device
Rth(j-a)
thermal resistance from in free air
junction to ambient
[1]
[2]
[3]
[4]
-
-
-
-
-
-
-
-
246
161
172
131
K/W
K/W
K/W
K/W
[1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
[2] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1 cm2.
[3] Device mounted on an FR4 PCB, 4-layer copper, tin-plated and standard footprint.
[4] Device mounted on an FR4 PCB, 4-layer copper, tin-plated, mounting pad for collector 1 cm2.
aaa-020730
3
10
duty cycle = 1
Z
th(j-a)
(K/W)
0.75
0.50
2
10
0.33
0.20
0.10
0.05
10
0.02
0.01
0
1
-1
10
-5
-4
-3
-2
10
-1
2
3
10
10
10
10
1
10
10
10
t
(s)
p
FR4 PCB, standard footprint
Fig. 2. Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
©
PBSS5255PAPS-Q
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Nexperia B.V. 2021. All rights reserved
Product data sheet
23 September 2021
5 / 15
Nexperia
PBSS5255PAPS-Q
55V, 2A PNP/PNP low VCEsat (BISS) double transistor
aaa-020731
3
10
Z
th(j-a)
(K/W)
duty cycle = 1
0.75
0.50
2
10
0.33
0.20
0.10
0.05
0.02
10
0.01
0
1
-1
10
-5
-4
-3
-2
10
-1
2
3
10
10
10
10
1
10
10
10
t
(s)
p
FR4 PCB, mounting pad for collector 1 cm2
Fig. 3. Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
aaa-020733
3
10
Z
th(j-a)
(K/W)
duty cycle = 1
0.75
2
10
0.50
0.33
0.20
0.10
10
0.05
0.02
0.01
0
1
-1
10
-5
-4
-3
-2
10
-1
2
3
10
10
10
10
1
10
10
10
t
(s)
p
FR4 PCB, 4-layer copper, standard footprint
Fig. 4. Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
aaa-020734
3
10
Z
th(j-a)
(K/W)
2
duty cycle = 1
0.75
10
0.50
0.33
0.20
0.10
10
0.05
0.02
0.01
0
1
-1
10
-5
-4
-3
-2
10
-1
2
3
10
10
10
10
1
10
10
10
t
(s)
p
FR4 PCB, 4-layer copper, mounting pad for collector 1 cm2
Fig. 5. Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
©
PBSS5255PAPS-Q
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Nexperia B.V. 2021. All rights reserved
Product data sheet
23 September 2021
6 / 15
Nexperia
PBSS5255PAPS-Q
55V, 2A PNP/PNP low VCEsat (BISS) double transistor
10. Characteristics
Table 7. Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Per transistor
ICBO
collector-base cut-off
current
VCB = -44 V; IE = 0 A; Tamb = 25 °C
VCB = -44 V; IE = 0 A; Tj = 150 °C
-
-
-
-
-
-
-100
-50
nA
µA
nA
ICES
IEBO
hFE
collector-emitter cut-off VCE = -44 V; VBE = 0 V; Tamb = 25 °C
current
-100
emitter-base cut-off
current
VEB = -5 V; IC = 0 A; Tamb = 25 °C
-
-
-100
-
nA
DC current gain
VCE = -2 V; IC = -100 mA; pulsed; tp ≤
300 µs; δ ≤ 0.02; Tamb = 25 °C
170
250
200
150
75
VCE = -2 V; IC = -500 mA; pulsed; tp ≤
300 µs; δ ≤ 0.02; Tamb = 25 °C
140
-
VCE = -2 V; IC = -1 A; pulsed; tp ≤
300 µs; δ ≤ 0.02; Tamb = 25 °C
110
-
VCE = -2 V; IC = -2 A; pulsed; tp ≤
300 µs; δ ≤ 0.02; Tamb = 25 °C
50
-
-
VCEsat
collector-emitter
saturation voltage
IC = -0.5 A; IB = -50 mA; pulsed; tp ≤
300 µs; δ ≤ 0.02; Tamb = 25 °C
-80
-170
-300
-300
-
-120
-250
-420
-450
250
mV
mV
mV
mV
mΩ
V
IC = -1 A; IB = -50 mA; pulsed; tp ≤
300 µs; δ ≤ 0.02; Tamb = 25 °C
-
IC = -0.7 A; IB = -7 mA; pulsed; tp ≤
300 µs; δ ≤ 0.02; Tamb = 25 °C
-
IC = -2 A; IB = -200 mA; pulsed; tp ≤
300 µs; δ ≤ 0.02; Tamb = 25 °C
-
RCEsat
VBEsat
collector-emitter
saturation resistance
IC = -1 A; IB = -50 mA; pulsed; tp ≤
300 µs; δ ≤ 0.02; Tamb = 25 °C
-
base-emitter saturation IC = -0.5 A; IB = -50 mA; pulsed; tp ≤
-
-0.89 -1
voltage
300 µs; δ ≤ 0.02; Tamb = 25 °C
IC = -1 A; IB = -50 mA; pulsed; tp ≤
300 µs; δ ≤ 0.02; Tamb = 25 °C
-
-0.93 -1
V
IC = -2 A; IB = -200 mA; pulsed; tp ≤
300 µs; δ ≤ 0.02; Tamb = 25 °C
-
-1.13 -1.25
-0.76 -0.9
V
VBE
base-emitter voltage
VCE = -2 V; IC = -0.5 A; pulsed; tp ≤
300 µs; δ ≤ 0.02; Tamb = 25 °C
-
V
td
tr
delay time
IC = -1 A; IBon = -50 mA; IBoff = 50 mA;
Tamb = 25 °C
-
-
-
-
-
-
-
10
-
-
-
-
-
-
-
ns
rise time
80
ns
ton
ts
turn-on time
storage time
fall time
90
ns
195
75
ns
tf
ns
toff
fT
turn-off time
transition frequency
270
100
ns
VCE = -10 V; IC = -500 mA; f = 100 MHz;
Tamb = 25 °C
MHz
Cc
collector capacitance
VCB = -10 V; IE = 0 A; ie = 0 A;
f = 1 MHz; Tamb = 25 °C
-
16
-
pF
©
PBSS5255PAPS-Q
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
23 September 2021
7 / 15
Nexperia
PBSS5255PAPS-Q
55V, 2A PNP/PNP low VCEsat (BISS) double transistor
aaa-020736
aaa-020735
600
-3.0
I
(mA) = -50
B
IC
(A)
-45
-40
-35
-30
-25
h
FE
(1)
-2.4
-20
-15
400
-1.8
-1.2
-0.6
-0
(2)
(3)
-10
-5
200
0
-1
-10
2
3
4
-1
-10
-10
-10
-10
(mA)
0
-1
-2
-3
-4
-5
I
C
V
(V)
CE
VCE = −2 V
Tamb = 25 °C
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb = −55 °C
Fig. 7. Collector current as a function of collector-
emitter voltage; typical values
Fig. 6. DC current gain as a function of collector
current; typical values
aaa-020738
aaa-020740
-1.2
-1.2
V
BE
(V)
V
BEsat
(V)
-0.8
-0.8
-0.4
0
(1)
(1)
(2)
(3)
(2)
(3)
-0.4
0
-1
-10
2
3
4
-1
-10
2
3
4
-1
-10
-10
-10
-10
(mA)
-1
-10
-10
-10
-10
I (mA)
C
I
C
VCE = −2 V
IC/IB = 20
(1) Tamb = −55 °C
(2) Tamb = 25 °C
(3) Tamb = 100 °C
(1) Tamb = −55 °C
(2) Tamb = 25 °C
(3) Tamb = 100 °C
Fig. 8. Base-emitter voltage as a function of collector Fig. 9. Base-emitter saturation voltage as a function of
current; typical values
collector current; typical values
©
PBSS5255PAPS-Q
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Nexperia B.V. 2021. All rights reserved
Product data sheet
23 September 2021
8 / 15
Nexperia
PBSS5255PAPS-Q
55V, 2A PNP/PNP low VCEsat (BISS) double transistor
aaa-020741
aaa-020743
-1
-1
V
V
CEsat
(V)
CEsat
(V)
-1
-1
-10
-10
-10
-10
-10
-10
(1)
(2)
(3)
(1)
(2)
(3)
-2
-2
-3
-1
-10
-3
-1
-10
2
3
4
2
3
4
-1
-10
-10
-10
-10
(mA)
-1
-10
-10
-10
-10
I (mA)
C
I
C
IC/IB = 20
Tamb = 25 °C
(1) IC/IB = 100
(2) IC/IB = 50
(3) IC/IB = 10
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb = −55 °C
Fig. 10. Collector-emitter saturation voltage as a
function of collector current; typical values
Fig. 11. Collector-emitter saturation voltage as a
function of collector current; typical values
aaa-020744
aaa-020745
3
3
10
10
R
CEsat
(Ω)
R
CEsat
(Ω)
2
2
10
10
(1)
(2)
(3)
10
10
(1)
(2)
(3)
1
1
-1
-1
10
10
10
10
-2
-2
-1
2
3
4
-1
2
3
4
-10
-1
-10
-10
-10
-10
(mA)
-10
-1
-10
-10
-10
-10
I (mA)
C
I
C
IC/IB = 20
Tamb = 25 °C
(1) IC/IB = 100
(2) IC/IB = 50
(3) IC/IB = 10
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb = −55 °C
Fig. 12. Collector-emitter saturation resistance as a
function of collector current; typical values
Fig. 13. Collector-emitter saturation resistance as a
function of collector current; typical values
©
PBSS5255PAPS-Q
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
23 September 2021
9 / 15
Nexperia
PBSS5255PAPS-Q
55V, 2A PNP/PNP low VCEsat (BISS) double transistor
11. Test information
-
I
B
input pulse
90 %
(idealized waveform)
-
I
(100 %)
Bon
10 %
-
I
Boff
output pulse
-
(idealized waveform)
I
C
90 %
-
I
(100 %)
C
10 %
t
t
t
f
t
t
r
s
d
006aaa266
t
t
off
on
Fig. 14. BISS transistor switching time definition
V
V
CC
BB
R
B
R
C
V
o
(probe)
450 Ω
(probe)
oscilloscope
450 Ω
oscilloscope
R2
V
DUT
I
R1
mgd624
Fig. 15. Test circuit for switching times
Quality information
This product has been qualified in accordance with the Automotive Electronics Council (AEC)
standard Q101 - Stress test qualification for discrete semiconductors, and is suitable for use in
automotive applications.
©
PBSS5255PAPS-Q
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
23 September 2021
10 / 15
Nexperia
PBSS5255PAPS-Q
55V, 2A PNP/PNP low VCEsat (BISS) double transistor
12. Package outline
DFN2020D-6: plastic, thermally enhanced ultra thin and small outline package; no leads;
6 terminals; body 2 x 2 x 0.65 mm
SOT1118D
b
v
A B
p
(6x)
D
A
B
E
A
A
1
pin 1
index area
detail X
solderable lead end
protrusion maximum 0.035 mm (6x)
D
1
C
(2x)
pin 1
index area
e
e
1
y
C
1
y
1
3
1
L
(6x)
p
cut-off end of
non-fuctional
bonding wire
(8x)
E
1
(2x)
4
6
X
e
e
0
1
2 mm
scale
Dimensions (mm are the original dimensions)
Unit
max 0.65 0.04 0.35 2.1 0.77 2.1
A
A
b
D
D
1
E
E
e
e
1
L
p
v
y
y
1
1
p
1
1.0
0.9 0.65 0.49 0.25 0.1 0.05 0.05
0.8 0.44 0.20
0.54 0.30
nom
mm
0.62
0.30 2.0 0.67 2.0
0.25 1.9 0.57 1.9
min 0.59
Note
1. Dimension A is including plating thickness.
sot1118d_po
References
Outline
version
IEC
European
projection
Issue date
JEDEC
- - -
JEITA
14-07-16
14-10-16
SOT1118D
Fig. 16. Package outline DFN2020D-6 (SOT1118D)
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PBSS5255PAPS-Q
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Nexperia B.V. 2021. All rights reserved
Product data sheet
23 September 2021
11 / 15
Nexperia
PBSS5255PAPS-Q
55V, 2A PNP/PNP low VCEsat (BISS) double transistor
13. Soldering
SOT1118D
2.2
1.65
0.2
0.45
0.35
0.3
0.25
0.65
0.43 0.33
0.53
solder lands
solder paste
0.12 0.22
2.5 2.3
0.9
1
1.1
solder resist
0.935
occupied area
Dimensions in mm
0.49
0.31
0.21
0.57
0.67
0.77
1.65
sot1118d_fr
Fig. 17. Reflow soldering footprint for DFN2020D-6 (SOT1118D)
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Nexperia B.V. 2021. All rights reserved
Product data sheet
23 September 2021
12 / 15
Nexperia
PBSS5255PAPS-Q
55V, 2A PNP/PNP low VCEsat (BISS) double transistor
14. Revision history
Table 8. Revision history
Data sheet ID
Release date
Data sheet status
Change notice
Supersedes
PBSS5255PAPS-Q v.1 20210923
Product data sheet
-
-
©
PBSS5255PAPS-Q
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Nexperia B.V. 2021. All rights reserved
Product data sheet
23 September 2021
13 / 15
Nexperia
PBSS5255PAPS-Q
55V, 2A PNP/PNP low VCEsat (BISS) double transistor
equipment, nor in applications where failure or malfunction of an Nexperia
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. Nexperia and its suppliers accept
no liability for inclusion and/or use of Nexperia products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
15. Legal information
Data sheet status
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Document status Product
Definition
[1][2]
status [3]
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
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Definitions
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Limiting values — Stress above one or more limiting values (as defined in
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damage to the device. Limiting values are stress ratings only and (proper)
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given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Short data sheet — A short data sheet is an extract from a full data sheet
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Disclaimers
Export control — This document as well as the item(s) described herein
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Limited warranty and liability — Information in this document is believed
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In no event shall Nexperia be liable for any indirect, incidental, punitive,
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Notwithstanding any damages that customer might incur for any reason
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for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
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Suitability for use in automotive applications — This Nexperia product
has been qualified for use in automotive applications. Unless otherwise
agreed in writing, the product is not designed, authorized or warranted to
be suitable for use in life support, life-critical or safety-critical systems or
©
PBSS5255PAPS-Q
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
23 September 2021
14 / 15
Nexperia
PBSS5255PAPS-Q
55V, 2A PNP/PNP low VCEsat (BISS) double transistor
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Applications.................................................................. 1
4. Quick reference data....................................................1
5. Pinning information......................................................2
6. Ordering information....................................................2
7. Marking..........................................................................2
8. Limiting values............................................................. 3
9. Thermal characteristics............................................... 5
10. Characteristics............................................................7
11. Test information........................................................10
12. Package outline........................................................ 11
13. Soldering................................................................... 12
14. Revision history........................................................13
15. Legal information......................................................14
© Nexperia B.V. 2021. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 23 September 2021
©
PBSS5255PAPS-Q
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
23 September 2021
15 / 15
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