NJU6824CJ [NJRC]
Liquid Crystal Driver, 518-Segment, CMOS, 22.07 X 2.55 MM, DIE-817;
| 型号： | NJU6824CJ |
| 厂家： | 
NEW JAPAN RADIO |
| 描述： | Liquid Crystal Driver, 518-Segment, CMOS, 22.07 X 2.55 MM, DIE-817 驱动 接口集成电路 |
| 文件： | 总110页 (文件大小：957K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NJU6824
Preliminary
(128+2) x RGB-Segment, 128-common 4096-Color
STN LCD DRIVER
ꢀꢀ GENERAL DESCRIPTION
ꢀ PACKAGE OUTLINE
The NJU6824 is a (128+2) x RGB segment, 128-
common 4096-color STN LCD driver consisted of
384(128xRGB)-segment + 6(2xRGB)-icon segment and
128-common drivers, serial and parallel MPU interface
circuits, internal power supply circuits, color palettes and
196,608-bit for graphic display data RAM.
Each of the 128-RGB segment drivers outputs 16
gradation levels out of 32-gradation level of color palette.
The display rotate function makes easily rotated display
without original display data change.
NJU6824CJ
Since the NJU6824 provides a low operating voltage of
1.7V and low operating current, it is ideally suited for
battery-powered handheld applications.
ꢀꢀ FEATURES
ꢀꢀ 4096-color STN LCD driver
ꢀꢀ LCD drivers
ꢀꢀ Display data RAM (DDRAM)
ꢀꢀ Color display mode
ꢀꢀ Black & white display mode
ꢀꢀ 256-color driving mode
128 x 3(RGB) segments, 2 x 3(RGB) icon segments, 128 commons
196,608-bit for graphic display
16 gradation levels out of 32 gradation levels of color palette
128 x 384 pixels 16 gradation levels or 128 x 384 pixels in B&W display
ꢀꢀ 8/16bit Parallel interface direct connection to 68/80 series MPU
ꢀꢀ Programmable 8- or 16-bit data bus length for display data
ꢀꢀ Serial interface 3-/4-line
ꢀꢀ Programmable duty and bias ratios
ꢀꢀ Programmable internal voltage booster (6-times maximum)
ꢀꢀ Programmable clock frequency for internal voltage booster operation (1/2, 1, 2, 4times)
ꢀꢀ Programmable contrast control using 128-step EVR
ꢀꢀ Display Rotate Function / Display Mirror Inverse Function
ꢀꢀ Various instructions
Display data read/write, Display ON/OFF, Reverse display ON/OFF, All pixels ON/OFF,
column address, row address, N-line inversion, Initial display line, Initial COM line, Read-modify-write,
Gradation mode control, Increment control, Data bus length, Discharge ON/OFF,
Duty cycle ratio, LCD bias ratio, Boost level, EVR control, Power save ON/OFF, etc
ꢀꢀ Low operating current
ꢀꢀ Low logic supply voltage
ꢀꢀ LCD driving supply voltage
ꢀꢀ C-MOS technology
ꢀꢀ Package
1.7V to 3.3V
5.0V to 18.0V
Bumped chip / TCP
02/05/11
- 1 -
NJU6824
ꢀꢀ PAD LOCATION
DMY44
DMY45
DMY46
COM114
COM127
DMY47
DMY71
1
Note1) The PADs of (L), (R) and (C) are shorted mutually in the LSI.
Note2) The DMY PADs are electrically open.
Chip Center
Chip Size
:X= 0µm, Y= 0µm
:22.07mm x 2.55mm
Chip Thickness
Bump Size
:625µm ± 25µm
:28µm x 110µm(COM/SEG Output, DMY10 ~ DMY71),
60µm x 100µm(Interface),
28µm x 100µm(DMY0 ~ DMY9)
:43µm(Min)
Bump Pitch
Bump Height
Bump Material
:14.0~22.5µm (Typical 18µm) <tolerance : ±3µm >
:Au
Alignment marks
a
a: 30µm
b: 6µm
d
c: 120µm
d: 27µm
d
b
Alignment mark coordinates
a
X=-10866µm, Y= 1106µm
X= 10866µm, Y=-1106µm
b
c
- 2 -
NJU6824
Y
X
- 3 -
NJU6824
DMY37
DMY36
DMY35
COM50
Y
X
COM63
DMY34
DMY10
- 4 -
NJU6824
ꢀꢀ PAD COORDINATES 1
Chip Size 22070µm x 2550µm (Chip Center 0µm x 0µm )
PAD
No.
1
2
3
4
5
6
PAD
No.
PAD
Terminal
X(µm)
Y(µm)
Terminal
X(µm)
Y(µm)
Terminal
X(µm)
Y(µm)
No.
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
DMY0
DMY1
DMY2
VSSA
VSSA
SEL68
SEL68
VDDA
VDDA
P/S
-10642.5 -1090.0 52
-10599.5 -1090.0 53
-10556.5 -1090.0 54
-10475.5 -1090.0 55
-10402.5 -1090.0 56
-10293.0 -1090.0 57
-10220.0 -1090.0 58
-10110.5 -1090.0 59
-10037.5 -1090.0 60
-9928.0 -1090.0 61
-9855.0 -1090.0 62
-9745.5 -1090.0 63
-9672.5 -1090.0 64
-9563.0 -1090.0 65
-9490.0 -1090.0 66
-9380.5 -1090.0 67
-9271.0 -1090.0 68
-9198.0 -1090.0 69
-9088.5 -1090.0 70
-8979.0 -1090.0 71
-8906.0 -1090.0 72
-8796.5 -1090.0 73
-8687.0 -1090.0 74
-8614.0 -1090.0 75
-8504.5 -1090.0 76
-8395.0 -1090.0 77
-8322.0 -1090.0 78
-8212.5 -1090.0 79
-8139.5 -1090.0 80
-7993.5 -1090.0 81
-7920.5 -1090.0 82
-7774.5 -1090.0 83
-7701.5 -1090.0 84
-7555.5 -1090.0 85
-7482.5 -1090.0 86
D10
D10
D11
D11
D12
D12
D13
D13
D14
-5584.5 -1090.0
-5511.5 -1090.0
-5365.5 -1090.0
-5292.5 -1090.0
-5146.5 -1090.0
-5073.5 -1090.0
-4927.5 -1090.0
-4854.5 -1090.0
-4708.5 -1090.0
-4635.5 -1090.0
-4489.5 -1090.0
-4416.5 -1090.0
-4197.5 -1090.0
-4124.5 -1090.0
-4051.5 -1090.0
-3978.5 -1090.0
-3905.5 -1090.0
-3832.5 -1090.0
-3759.5 -1090.0
-3613.5 -1090.0
-3540.5 -1090.0
-3394.5 -1090.0
-3321.5 -1090.0
-3175.5 -1090.0
-3102.5 -1090.0
-2956.5 -1090.0
-2883.5 -1090.0
-2701.0 -1090.0
-2628.0 -1090.0
-2409.0 -1090.0
-2336.0 -1090.0
-2044.0 -1090.0
-1971.0 -1090.0
-1898.0 -1090.0
-1825.0 -1090.0
-1752.0 -1090.0
-1679.0 -1090.0
-1606.0 -1090.0
-1460.0 -1090.0
-1387.0 -1090.0
-1277.5 -1090.0
-1204.5 -1090.0
-1095.0 -1090.0
-1022.0 -1090.0
V4A2
VSSA
VSSA
VLCD
VLCD
VLCD
VLCD
VLCD
VLCD
V1
V1
V1
V1
V1
V1
V2
V2
V2
V2
V2
V2
V3
V3
V3
V3
V3
V3
V4
V4
V4
V4
V4
V4
VREG
VREG
VREG
VREG
VREG
VREG
VREF
VREF
VREF
VREF
VREF
VREF
VBA
VBA
VBA
VBA
VBA
VBA
-292.0
-182.5
-109.5
0.0
-1090.0
-1090.0
-1090.0
-1090.0
-1090.0
-1090.0
-1090.0
-1090.0
-1090.0
-1090.0
-1090.0
-1090.0
-1090.0
-1090.0
-1090.0
73.0
146.0
219.0
292.0
365.0
511.0
584.0
657.0
730.0
803.0
876.0
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
D14
D15
D15
P/S
VSSA
VSSA
RES
RES
DMY3
CS
CS
DMY4
RS
RS
DMY5
WR
WR
DMY6
RD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CL
1022.0 -1090.0
1095.0 -1090.0
1168.0 -1090.0
1241.0 -1090.0
1314.0 -1090.0
1387.0 -1090.0
1533.0 -1090.0
1606.0 -1090.0
1679.0 -1090.0
1752.0 -1090.0
1825.0 -1090.0
1898.0 -1090.0
2044.0 -1090.0
2117.0 -1090.0
2190.0 -1090.0
2263.0 -1090.0
2336.0 -1090.0
2409.0 -1090.0
2555.0 -1090.0
2628.0 -1090.0
2701.0 -1090.0
2774.0 -1090.0
2847.0 -1090.0
2920.0 -1090.0
3029.5 -1090.0
3102.5 -1090.0
3175.5 -1090.0
3248.5 -1090.0
3321.5 -1090.0
3394.5 -1090.0
3504.0 -1090.0
3577.0 -1090.0
3650.0 -1090.0
3723.0 -1090.0
3796.0 -1090.0
3869.0 -1090.0
CL
FLM
FLM
FR
FR
CLK
CLK
OSC1
OSC1
OSC2
OSC2
VSS
VSS
VSS
VSS
VSS
RD
VDDA
VDDA
D0/SCL
D0/SCL
D1/SDA
D1/SDA
D2
D2
36 D3/SMODE -7336.5 -1090.0 87
37 D3/SMODE -7263.5 -1090.0 88
VSS
VSS
38
39
40
41
42
43
44
45
46
47
48
49
50
51
D4/SPOL
D4/SPOL
D5
-7117.5 -1090.0 89
-7044.5 -1090.0 90
-6898.5 -1090.0 91
-6825.5 -1090.0 92
-6679.5 -1090.0 93
-6606.5 -1090.0 94
-6460.5 -1090.0 95
-6387.5 -1090.0 96
-6241.5 -1090.0 97
-6168.5 -1090.0 98
-6022.5 -1090.0 99
-5949.5 -1090.0 100
-5803.5 -1090.0 101
-5730.5 -1090.0 102
V1A1
V1A1
VDDA
VDDA
V1A2
V1A2
VSSA
VSSA
V4A1
V4A1
VDDA
VDDA
V4A2
D5
D6
D6
D7
D7
-912.5
-839.5
-730.0
-657.0
-547.5
-474.5
-365.0
-1090.0
-1090.0
-1090.0
-1090.0
-1090.0
-1090.0
-1090.0
VSSA
VSSA
D8
D8
D9
D9
- 5 -
NJU6824
ꢀꢀ PAD COORDINATES 2
Chip Size 22070µm x 2550µm (Chip Center 0µm x 0µm )
PAD
PAD
No.
PAD
Terminal
X(µm)
Y(µm)
Terminal
X(µm)
Y(µm)
Terminal
X(µm)
Y(µm)
No.
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
No.
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
VSSH
VSSH
VSSH
VSSH
VSSH
VSSH
VSSH
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VEE
VEE
VEE
VEE
VEE
VEE
VEE
C1+
C1+
C1+
C1+
C1+
C1+
C1-
4051.5 -1090.0 205
4124.5 -1090.0 206
4197.5 -1090.0 207
4270.5 -1090.0 208
4343.5 -1090.0 209
4416.5 -1090.0 210
4489.5 -1090.0 211
4672.0 -1090.0 212
4745.0 -1090.0 213
4818.0 -1090.0 214
4891.0 -1090.0 215
4964.0 -1090.0 216
5037.0 -1090.0 217
5110.0 -1090.0 218
5292.5 -1090.0 219
5365.5 -1090.0 220
5438.5 -1090.0 221
5511.5 -1090.0 222
5584.5 -1090.0 223
5657.5 -1090.0 224
5730.5 -1090.0 225
5840.0 -1090.0 226
5913.0 -1090.0 227
5986.0 -1090.0 228
6059.0 -1090.0 229
6132.0 -1090.0 230
6205.0 -1090.0 231
6314.5 -1090.0 232
6387.5 -1090.0 233
6460.5 -1090.0 234
6533.5 -1090.0 235
6606.5 -1090.0 236
6679.5 -1090.0 237
6789.0 -1090.0 238
6862.0 -1090.0 239
6935.0 -1090.0 240
7008.0 -1090.0 241
7081.0 -1090.0 242
7154.0 -1090.0 243
7263.5 -1090.0 244
7336.5 -1090.0 245
7409.5 -1090.0 246
7482.5 -1090.0 247
7555.5 -1090.0 248
7628.5 -1090.0 249
7738.0 -1090.0 250
7811.0 -1090.0 251
7884.0 -1090.0 252
7957.0 -1090.0 253
8030.0 -1090.0 254
8103.0 -1090.0 255
C3-
C3-
C3-
C3-
C3-
C3-
C4+
C4+
C4+
C4+
C4+
C4+
C4-
C4-
C4-
C4-
C4-
C4-
C5+
C5+
C5+
C5+
C5+
C5+
C5-
C5-
C5-
C5-
C5-
8212.5 -1090.0
8285.5 -1090.0
8358.5 -1090.0
8431.5 -1090.0
8504.5 -1090.0
8577.5 -1090.0
8687.0 -1090.0
8760.0 -1090.0
8833.0 -1090.0
8906.0 -1090.0
8979.0 -1090.0
9052.0 -1090.0
9161.5 -1090.0
9234.5 -1090.0
9307.5 -1090.0
9380.5 -1090.0
9453.5 -1090.0
9526.5 -1090.0
9636.0 -1090.0
9709.0 -1090.0
9782.0 -1090.0
9855.0 -1090.0
9928.0 -1090.0
10001.0 -1090.0
10110.5 -1090.0
10183.5 -1090.0
10256.5 -1090.0
10329.5 -1090.0
10402.5 -1090.0
10475.5 -1090.0
10556.5 -1090.0
10599.5 -1090.0
10642.5 -1090.0
10845.0 -881.5
10845.0 -838.5
10845.0 -795.5
10845.0 -752.5
10845.0 -709.5
10845.0 -666.5
10845.0 -623.5
10845.0 -580.5
10845.0 -537.5
10845.0 -494.5
10845.0 -451.5
10845.0 -408.5
10845.0 -365.5
10845.0 -322.5
10845.0 -279.5
10845.0 -236.5
10845.0 -193.5
10845.0 -150.5
DMY28
DMY29
DMY30
DMY31
DMY32
DMY33
DMY34
COM63
COM62
COM61
COM60
COM59
COM58
COM57
COM56
COM55
COM54
COM53
COM52
COM51
COM50
DMY35
DMY36
DMY37
DMY38
DMY39
DMY40
COM49
COM48
COM47
COM46
COM45
COM44
COM43
COM42
COM41
COM40
COM39
COM38
COM37
COM36
COM35
COM34
COM33
COM32
COM31
COM30
COM29
COM28
COM27
COM26
10845.0 -107.5
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10642.5 1085.0
10599.5 1085.0
10556.5 1085.0
10513.5 1085.0
10470.5 1085.0
10427.5 1085.0
10384.5 1085.0
10341.5 1085.0
10298.5 1085.0
10255.5 1085.0
10212.5 1085.0
10169.5 1085.0
10126.5 1085.0
10083.5 1085.0
10040.5 1085.0
-64.5
-21.5
21.5
64.5
107.5
150.5
193.5
236.5
279.5
322.5
365.5
408.5
451.5
494.5
537.5
580.5
623.5
666.5
709.5
752.5
795.5
838.5
881.5
C1-
C1-
C1-
C1-
C5-
DMY7
DMY8
DMY9
DMY10
DMY11
DMY12
DMY13
DMY14
DMY15
DMY16
DMY17
DMY18
DMY19
DMY20
DMY21
DMY22
DMY23
DMY24
DMY25
DMY26
DMY27
C1-
C2+
C2+
C2+
C2+
C2+
C2+
C2-
C2-
C2-
C2-
C2-
9997.5
9954.5
9911.5
9868.5
9825.5
9782.5
9739.5
9696.5
9653.5
9610.5
9567.5
9524.5
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
C2-
C3+
C3+
C3+
C3+
C3+
C3+
- 6 -
NJU6824
ꢀꢀ PAD COORDINATES 3
Chip Size 22070µm x 2550µm (Chip Center 0µm x 0µm )
PAD
PAD
No.
PAD
Terminal
X(µm)
Y(µm)
Terminal
X(µm)
Y(µm)
Terminal
X(µm)
Y(µm)
No.
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
No.
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
9481.5 1085.0 358
9438.5 1085.0 359
9395.5 1085.0 360
9352.5 1085.0 361
9309.5 1085.0 362
9266.5 1085.0 363
9223.5 1085.0 364
9180.5 1085.0 365
9137.5 1085.0 366
9094.5 1085.0 367
9051.5 1085.0 368
9008.5 1085.0 369
8965.5 1085.0 370
8922.5 1085.0 371
8879.5 1085.0 372
8836.5 1085.0 373
8793.5 1085.0 374
8750.5 1085.0 375
8707.5 1085.0 376
8664.5 1085.0 377
8621.5 1085.0 378
8578.5 1085.0 379
8535.5 1085.0 380
8492.5 1085.0 381
8449.5 1085.0 382
8406.5 1085.0 383
8363.5 1085.0 384
8320.5 1085.0 385
8277.5 1085.0 386
8234.5 1085.0 387
8191.5 1085.0 388
8148.5 1085.0 389
8105.5 1085.0 390
8062.5 1085.0 391
8019.5 1085.0 392
7976.5 1085.0 393
7933.5 1085.0 394
7890.5 1085.0 395
7847.5 1085.0 396
7804.5 1085.0 397
7761.5 1085.0 398
7718.5 1085.0 399
7675.5 1085.0 400
7632.5 1085.0 401
7589.5 1085.0 402
7546.5 1085.0 403
7503.5 1085.0 404
7460.5 1085.0 405
7417.5 1085.0 406
7374.5 1085.0 407
7331.5 1085.0 408
SEGB7
SEGC7
SEGA8
SEGB8
SEGC8
SEGA9
7288.5 1085.0
7245.5 1085.0
7202.5 1085.0
7159.5 1085.0
SEGB24
SEGC24
SEGA25
SEGB25
SEGC25
SEGA26
SEGB26
SEGC26
SEGA27
SEGB27
SEGC27
SEGA28
SEGB28
SEGC28
SEGA29
SEGB29
SEGC29
SEGA30
SEGB30
SEGC30
SEGA31
SEGB31
SEGC31
SEGA32
SEGB32
SEGC32
SEGA33
SEGB33
SEGC33
SEGA34
SEGB34
SEGC34
SEGA35
SEGB35
SEGC35
SEGA36
SEGB36
SEGC36
SEGA37
SEGB37
SEGC37
SEGA38
SEGB38
SEGC38
SEGA39
SEGB39
SEGC39
SEGA40
SEGB40
SEGC40
SEGA41
5095.5
5052.5
5009.5
4966.5
4923.5
4880.5
4837.5
4794.5
4751.5
4708.5
4665.5
4622.5
4579.5
4536.5
4493.5
4450.5
4407.5
4364.5
4321.5
4278.5
4235.5
4192.5
4149.5
4106.5
4063.5
4020.5
3977.5
3934.5
3891.5
3848.5
3805.5
3762.5
3719.5
3676.5
3633.5
3590.5
3547.5
3504.5
3461.5
3418.5
3375.5
3332.5
3289.5
3246.5
3203.5
3160.5
3117.5
3074.5
3031.5
2988.5
2945.5
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
7116.5
1085.0
7073.5 1085.0
7030.5 1085.0
6987.5 1085.0
6944.5 1085.0
6901.5 1085.0
6858.5 1085.0
6815.5 1085.0
6772.5 1085.0
6729.5 1085.0
6686.5 1085.0
6643.5 1085.0
6600.5 1085.0
6557.5 1085.0
6514.5 1085.0
6471.5 1085.0
6428.5 1085.0
6385.5 1085.0
6342.5 1085.0
6299.5 1085.0
6256.5 1085.0
6213.5 1085.0
6170.5 1085.0
6127.5 1085.0
6084.5 1085.0
6041.5 1085.0
5998.5 1085.0
5955.5 1085.0
5912.5 1085.0
5869.5 1085.0
5826.5 1085.0
5783.5 1085.0
5740.5 1085.0
5697.5 1085.0
5654.5 1085.0
SEGB9
SEGC9
SEGA10
SEGB10
SEGC10
SEGA11
SEGB11
SEGC11
SEGA12
SEGB12
SEGC12
SEGA13
SEGB13
SEGC13
SEGA14
SEGB14
SEGC14
SEGA15
SEGB15
SEGC15
SEGA16
SEGB16
SEGC16
SEGA17
SEGB17
SEGC17
SEGA18
SEGB18
SEGC18
SEGA19
SEGB19
SEGC19
SEGA20
SEGB20
SEGC20
SEGA21
SEGB21
SEGC21
SEGA22
SEGB22
SEGC22
SEGA23
SEGB23
SEGC23
SEGA24
COM0
SEGSA0
SEGSB0
SEGSC0
SEGA0
SEGB0
SEGC0
SEGA1
SEGB1
SEGC1
SEGA2
SEGB2
SEGC2
SEGA2
SEGB3
SEGC3
SEGA4
SEGB4
SEGC4
SEGA5
SEGB5
SEGC5
SEGA6
SEGB6
SEGC6
SEGA7
5611.5
1085.0
5568.5 1085.0
5525.5 1085.0
5482.5 1085.0
5439.5 1085.0
5396.5 1085.0
5353.5 1085.0
5310.5 1085.0
5267.5 1085.0
5224.5 1085.0
5181.5 1085.0
5138.5 1085.0
- 7 -
NJU6824
ꢀꢀ PAD COORDINATES 4
Chip Size 22070µm x 2550µm (Chip Center 0µm x 0µm )
PAD
PAD
No.
PAD
Terminal
X(µm)
Y(µm)
Terminal
X(µm)
Y(µm)
Terminal
X(µm)
Y(µm)
No.
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
No.
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
SEGB41
SEGC41
SEGA42
SEGB42
SEGC42
SEGA43
SEGB43
SEGC43
SEGA44
SEGB44
SEGC44
SEGA45
SEGB45
SEGC45
SEGA46
SEGB46
SEGC46
SEGA47
SEGB47
SEGC47
SEGA48
SEGB48
SEGC48
SEGA49
SEGB49
SEGC49
SEGA50
SEGB50
SEGC50
SEGA51
SEGB51
SEGC51
SEGA52
SEGB52
SEGC52
SEGA53
SEGB53
SEGC53
SEGA54
SEGB54
SEGC54
SEGA55
SEGB55
SEGC55
SEGA56
SEGB56
SEGC56
SEGA57
SEGB57
SEGC57
SEGA58
2902.5 1085.0
2859.5 1085.0
2816.5 1085.0
2773.5 1085.0
2730.5 1085.0
2687.5 1085.0
2644.5 1085.0
2601.5 1085.0
2558.5 1085.0
2515.5 1085.0
2472.5 1085.0
2429.5 1085.0
2386.5 1085.0
2343.5 1085.0
2300.5 1085.0
2257.5 1085.0
2214.5 1085.0
2171.5 1085.0
2128.5 1085.0
2085.5 1085.0
2042.5 1085.0
1999.5 1085.0
1956.5 1085.0
1913.5 1085.0
1870.5 1085.0
1827.5 1085.0
1784.5 1085.0
1741.5 1085.0
1698.5 1085.0
1655.5 1085.0
1612.5 1085.0
1569.5 1085.0
1526.5 1085.0
1483.5 1085.0
1440.5 1085.0
1397.5 1085.0
1354.5 1085.0
1311.5 1085.0
1268.5 1085.0
1225.5 1085.0
1182.5 1085.0
1139.5 1085.0
1096.5 1085.0
1053.5 1085.0
1010.5 1085.0
967.5 1085.0
924.5 1085.0
881.5 1085.0
838.5 1085.0
795.5 1085.0
752.5 1085.0
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
SEGB58
SEGC58
SEGA59
SEGB59
SEGC59
SEGA60
SEGB60
SEGC60
SEGA61
SEGB61
SEGC61
SEGA62
SEGB62
SEGC62
SEGA63
SEGB63
SEGC63
SEGA64
SEGB64
SEGC64
SEGA65
SEGB65
SEGC65
SEGA66
SEGB66
SEGC66
SEGA67
SEGB67
SEGC67
SEGA68
SEGB68
SEGC68
SEGA69
SEGB69
SEGC69
SEGA70
SEGB70
SEGC70
SEGA71
SEGB71
SEGC71
SEGA72
SEGB72
SEGC72
SEGA73
SEGB73
SEGC73
SEGA74
SEGB74
SEGC74
SEGA75
709.5
666.5
623.5
580.5
537.5
494.5
451.5
408.5
365.5
322.5
279.5
236.5
193.5
150.5
107.5
64.5
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
SEGB75
SEGC75
SEGA76
SEGB76
SEGC76
SEGA77
SEGB77
SEGC77
SEGA78
SEGB78
SEGC78
SEGA79
SEGB79
SEGC79
SEGA80
SEGB80
SEGC80
SEGA81
SEGB81
SEGC81
SEGA82
SEGB82
SEGC82
SEGA83
SEGB83
SEGC83
SEGA84
SEGB84
SEGC84
SEGA85
SEGB85
SEGC85
SEGA86
SEGB86
SEGC86
SEGA87
SEGB87
SEGC87
SEGA88
SEGB88
SEGC88
SEGA89
SEGB89
SEGC89
SEGA90
SEGB90
SEGC90
SEGA91
SEGB91
SEGC91
SEGA92
-1483.5 1085.0
-1526.5 1085.0
-1569.5 1085.0
-1612.5 1085.0
-1655.5 1085.0
-1698.5 1085.0
-1741.5 1085.0
-1784.5 1085.0
-1827.5 1085.0
-1870.5 1085.0
-1913.5 1085.0
-1956.5 1085.0
-1999.5 1085.0
-2042.5 1085.0
-2085.5 1085.0
-2128.5 1085.0
-2171.5 1085.0
-2214.5 1085.0
-2257.5 1085.0
-2300.5 1085.0
-2343.5 1085.0
-2386.5 1085.0
-2429.5 1085.0
-2472.5 1085.0
-2515.5 1085.0
-2558.5 1085.0
-2601.5 1085.0
-2644.5 1085.0
-2687.5 1085.0
-2730.5 1085.0
-2773.5 1085.0
-2816.5 1085.0
-2859.5 1085.0
-2902.5 1085.0
-2945.5 1085.0
-2988.5 1085.0
-3031.5 1085.0
-3074.5 1085.0
-3117.5 1085.0
-3160.5 1085.0
-3203.5 1085.0
-3246.5 1085.0
-3289.5 1085.0
-3332.5 1085.0
-3375.5 1085.0
-3418.5 1085.0
-3461.5 1085.0
-3504.5 1085.0
-3547.5 1085.0
-3590.5 1085.0
-3633.5 1085.0
21.5
-21.5
-64.5
-107.5
-150.5
-193.5
-236.5
-279.5
-322.5
-365.5
-408.5
-451.5
-494.5
-537.5
-580.5
-623.5
-666.5
-709.5
-752.5
-795.5
-838.5
-881.5
-924.5
-967.5
-1010.5 1085.0
-1053.5 1085.0
-1096.5 1085.0
-1139.5 1085.0
-1182.5 1085.0
-1225.5 1085.0
-1268.5 1085.0
-1311.5 1085.0
-1354.5 1085.0
-1397.5 1085.0
-1440.5 1085.0
- 8 -
NJU6824
ꢀꢀ PAD COORDINATES 5
Chip Size 22070µm x 2550µm (Chip Center 0µm x 0µm )
PAD
PAD
No.
PAD
Terminal
SEGB92
SEGC92 -3719.5 1085.0
SEGA93
SEGB93
SEGC93 -3848.5 1085.0
SEGA94
SEGB94
SEGC94 -3977.5 1085.0
SEGA95
SEGB95
SEGC95 -4106.5 1085.0
SEGA96
SEGB96
SEGC96 -4235.5 1085.0
SEGA97
SEGB97
SEGC97 -4364.5 1085.0
SEGA98
SEGB98
SEGC98 -4493.5 1085.0
SEGA99
SEGB99
SEGC99 -4622.5 1085.0
SEGA100 -4665.5 1085.0
SEGB100 -4708.5 1085.0
SEGC100 -4751.5 1085.0
SEGA101 -4794.5 1085.0
SEGB101 -4837.5 1085.0
SEGC101 -4880.5 1085.0
SEGA102 -4923.5 1085.0
SEGB102 -4966.5 1085.0
SEGC102 -5009.5 1085.0
SEGA103 -5052.5 1085.0
SEGB103 -5095.5 1085.0
SEGC103 -5138.5 1085.0
SEGA104 -5181.5 1085.0
SEGB104 -5224.5 1085.0
SEGC104 -5267.5 1085.0
SEGA105 -5310.5 1085.0
SEGB105 -5353.5 1085.0
SEGC105 -5396.5 1085.0
SEGA106 -5439.5 1085.0
SEGB106 -5482.5 1085.0
SEGC106 -5525.5 1085.0
SEGA107 -5568.5 1085.0
SEGB107 -5611.5 1085.0
SEGC107 -5654.5 1085.0
SEGA108 -5697.5 1085.0
SEGB108 -5740.5 1085.0
SEGC108 -5783.5 1085.0
SEGA109 -5826.5 1085.0
X(µm)
Y(µm)
Terminal
X(µm)
Y(µm)
Terminal
X(µm)
Y(µm)
No.
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
No.
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
-3676.5 1085.0
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
SEGB109
SEGC109
SEGA110
SEGB110
SEGC110
SEGA111
SEGB111
SEGC111
SEGA112
SEGB112
SEGC112
SEGA113
SEGB113
SEGC113
SEGA114
SEGB114
SEGC114
SEGA115
SEGB115
SEGC115
SEGA116
SEGB116
SEGC116
SEGA117
SEGB117
SEGC117
SEGA118
SEGB118
SEGC118
SEGA119
SEGB119
SEGC119
SEGA120
SEGB120
SEGC120
SEGA121
SEGB121
SEGC121
SEGA122
SEGB122
SEGC122
SEGA123
SEGB123
SEGC123
SEGA124
SEGB124
SEGC124
SEGA125
SEGB125
SEGC125
SEGA126
-5869.5 1085.0
-5912.5 1085.0
-5955.5 1085.0
-5998.5 1085.0
-6041.5 1085.0
-6084.5 1085.0
-6127.5 1085.0
-6170.5 1085.0
-6213.5 1085.0
-6256.5 1085.0
-6299.5 1085.0
-6342.5 1085.0
-6385.5 1085.0
-6428.5 1085.0
-6471.5 1085.0
-6514.5 1085.0
-6557.5 1085.0
-6600.5 1085.0
-6643.5 1085.0
-6686.5 1085.0
-6729.5 1085.0
-6772.5 1085.0
-6815.5 1085.0
-6858.5 1085.0
-6901.5 1085.0
-6944.5 1085.0
-6987.5 1085.0
-7030.5 1085.0
-7073.5 1085.0
-7116.5 1085.0
-7159.5 1085.0
-7202.5 1085.0
-7245.5 1085.0
-7288.5 1085.0
-7331.5 1085.0
-7374.5 1085.0
-7417.5 1085.0
-7460.5 1085.0
-7503.5 1085.0
-7546.5 1085.0
-7589.5 1085.0
-7632.5 1085.0
-7675.5 1085.0
-7718.5 1085.0
-7761.5 1085.0
-7804.5 1085.0
-7847.5 1085.0
-7890.5 1085.0
-7933.5 1085.0
-7976.5 1085.0
-8019.5 1085.0
SEGB126
SEGC126
SEGA127
SEGB127
SEGC127
SEGSA1
SEGSB1
SEGSC1
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COM80
COM81
COM82
COM83
COM84
COM85
COM86
COM87
COM88
COM89
COM90
COM91
COM92
COM93
COM94
COM95
COM96
COM97
COM98
COM99
COM100
COM101
COM102
COM103
COM104
COM105
COM106
-8062.5 1085.0
-8105.5 1085.0
-8148.5 1085.0
-8191.5 1085.0
-8234.5 1085.0
-8277.5 1085.0
-8320.5 1085.0
-8363.5 1085.0
-8406.5 1085.0
-8449.5 1085.0
-8492.5 1085.0
-8535.5 1085.0
-8578.5 1085.0
-8621.5 1085.0
-8664.5 1085.0
-8707.5 1085.0
-8750.5 1085.0
-8793.5 1085.0
-8836.5 1085.0
-8879.5 1085.0
-8922.5 1085.0
-8965.5 1085.0
-9008.5 1085.0
-9051.5 1085.0
-9094.5 1085.0
-9137.5 1085.0
-9180.5 1085.0
-9223.5 1085.0
-9266.5 1085.0
-9309.5 1085.0
-9352.5 1085.0
-9395.5 1085.0
-9438.5 1085.0
-9481.5 1085.0
-9524.5 1085.0
-9567.5 1085.0
-9610.5 1085.0
-9653.5 1085.0
-9696.5 1085.0
-9739.5 1085.0
-9782.5 1085.0
-9825.5 1085.0
-9868.5 1085.0
-9911.5 1085.0
-9954.5 1085.0
-9997.5 1085.0
-10040.5 1085.0
-10083.5 1085.0
-10126.5 1085.0
-10169.5 1085.0
-10212.5 1085.0
-3762.5 1085.0
-3805.5 1085.0
-3891.5 1085.0
-3934.5 1085.0
-4020.5 1085.0
-4063.5 1085.0
-4149.5 1085.0
-4192.5 1085.0
-4278.5 1085.0
-4321.5 1085.0
-4407.5 1085.0
-4450.5 1085.0
-4536.5 1085.0
-4579.5 1085.0
- 9 -
NJU6824
ꢀꢀ PAD COORDINATES 6
Chip Size 22070µm x 2550µm (Chip Center 0µm x 0µm )
PAD
PAD
No.
817
PAD
No.
Terminal
X(µm)
Y(µm)
Terminal
DMY71
X(µm)
Y(µm)
Terminal
X(µm)
Y(µm)
No.
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
COM107 -10255.5 1085.0
COM108 -10298.5 1085.0
COM109 -10341.5 1085.0
-10845.0 -881.5
COM110
COM111
COM112
COM113
DMY41
DMY42
DMY43
DMY44
DMY45
DMY46
COM114
COM115
COM116
COM117
COM118
COM119
COM120 -10845.0 494.5
COM121 -10845.0 451.5
COM122 -10845.0 408.5
COM123 -10845.0 365.5
COM124 -10845.0 322.5
COM125 -10845.0 279.5
COM126 -10845.0 236.5
COM127 -10845.0 193.5
DMY47
DMY48
DMY49
DMY50
DMY51
DMY52
DMY53
DMY54
DMY55
DMY56
DMY57
DMY58
DMY59
DMY60
DMY61
DMY62
DMY63
DMY64
DMY65
DMY66
DMY67
DMY68
DMY69
DMY70
-10384.5 1085.0
-10427.5 1085.0
-10470.5 1085.0
-10513.5 1085.0
-10556.5 1085.0
-10599.5 1085.0
-10642.5 1085.0
-10845.0 881.5
-10845.0 838.5
-10845.0 795.5
-10845.0 752.5
-10845.0 709.5
-10845.0 666.5
-10845.0 623.5
-10845.0 580.5
-10845.0 537.5
-10845.0 150.5
-10845.0 107.5
-10845.0
-10845.0
64.5
21.5
-10845.0 -21.5
-10845.0 -64.5
-10845.0 -107.5
-10845.0 -150.5
-10845.0 -193.5
-10845.0 -236.5
-10845.0 -279.5
-10845.0 -322.5
-10845.0 -365.5
-10845.0 -408.5
-10845.0 -451.5
-10845.0 -494.5
-10845.0 -537.5
-10845.0 -580.5
-10845.0 -623.5
-10845.0 -666.5
-10845.0 -709.5
-10845.0 -752.5
-10845.0 -795.5
-10845.0 -838.5
- 10 -
NJU6824
ꢀꢀ BLOCK DIAGRAM
VSSH
VSS
VSSA
VVDDA
VDD
Segment Driver
Common Driver
5
V
LCD, V1 -V4
Gradation Circuit
Data Latch Circuit
Shift Register
V1A1, V1A2,
V4A1, V4A2
4
C1+
C1-
C2+
C2-
C3+
C3-
C4+
C4-
C5+
C5-
Voltage
booster
Voltage
regulator
VOUT
VEE
Display Data RAM
(DD RAM)
128x128x(4+4+4)bit
VREF
VBA
VREG
D15
Column Address Decoder
Column Address Counter
Column Address Register
D14
FR
D13
RAM
Interface
Display
Timing
Generator
FLM
CL
D12
D11
D10
D9
CLK
D8
OSC2
OSC1
Oscillator
D7
D6
D5
D4/SPOL
D3/SMODE
D2
Instruction
Decoder
Register Read
Control
Bus Holder
Pole Control
Internal Bus
D1/SDA
D0/SCL
MPU Interface
CS
RS
RD
WR
P/S
SEL68 RES
- 11 -
NJU6824
ꢀPOWER SUPPLY CIRCUITS BLOCK DIAGRAM
Reference
Voltage
Generator
+
-
-
VBA
VLCD
-
Voltage regulator
VREG
V1
VREF
+
-
-
V2
Gain
Control
(1x-7x)
-
V3
E.V.R
1/2VREG
-
V4
EVR register
V1/V4 Bias Voltage
Adjustment
Boost level register
V1A1
V1A2
V4A1
C1+
C1-
C2+
C2-
C3+
C3-
C4+
C4-
C5+
C5-
Voltage
Booster
VOUT
VEE
- 12 -
NJU6824
ꢀꢀ TERMINAL DESCRIPTION 1
No.
Symbol
VDD
VSS
VSSH
VDDA
I/O
Function
Power supply for logic circuits
GND for logic circuits
64~70
83~89
154~160
8,9,
28,29,
92,93,
100,101
4,5,
12,13,
46,47,
Power
Power
Power
Power
GND for high voltage circuits
This terminal is internally connected to the VDD level.
•This terminal is used to fix the select-terminals of the SEL68
and P/S to the VDD level.
Note) Do not use this terminal for a main power supply.
This terminal is internally connected to the VSS level.
•This terminal is used to fix the select-terminals of the SEL68
and P/S to the VSS level.
VSSA
Power
96,97,
Note) Do not use this terminal for a main GND.
104,105
106~111
112~117
118~123
124~129
130~135
VLCD
V1
V2
V3
V4
Power/O LCD driving voltages
•When the internal voltage booster is not used, external LCD
driving voltages (V1 to V4 and VLCD) should be supplied onto
these terminals. The external voltages should be maintained
with the following relationship.
VSS<V4<V3<V2<V1<VLCD
• When the internal voltage booster is used, the LCD driving
voltages (V1 to V4 and VLCD) are enabled by the “Power control”
instruction. The capacitors between these terminals and Vss
terminal must be connected.
175~180
181~186
187~192
193~198
199~204
205~210
211~216
217~222
223~228
229~234
148~153
142~147
168~174
C1+
C1-
C2+
C2-
C3+
C3-
C4+
C4-
C5+
C5-
VBA
VREF
VEE
O
O
O
O
O
Capacitor connection terminal for the voltage booster
Capacitor connection terminal for the voltage booster
Capacitor connection terminal for the voltage booster
Capacitor connection terminal for the voltage booster
Capacitor connection terminal for the voltage booster
O
I
Power
Reference-voltage generator output
Voltage regulator input
Voltage booster input
•This terminal is normally connected to the VDD level.
161~167
VOUT
Power/O Voltage booster output for high voltage circuits (in external
power supply)
136~141
90,91
94,95
98,99
102,103
VREG
V1A1
V1A2
V4A1
V4A2
RES
O
I
Voltage regulator output
V1 bias voltage adjustment terminal
I
I
I
V4 bias voltage adjustment terminal
14,15
Reset
Active “0”
MPU interface type select
6,7
SEL68
SEL86
Status
H
L
68 series
80 series
- 13 -
NJU6824
ꢀꢀ TERMINAL DESCRIPTION 2
No.
30,31
Symbol
D0/SCL
I/O
I/O
Function
Parallel interface:
D7 to D0 : 8-bit bi-directional bus
•In the parallel interface mode (P/S=“1”), these terminals should
be connected to 8-bit bi-directional bus of MPU.
32,33
36,37
D1/SDA
I/O
I/O
Serial interface:
SDA : serial data
SCL : serial clock
D3/SMODE
SMODE : 3-/4-line serial interface mode select
SPOL : RS polarity select (in the 3-line serial interface mode)
38,39
D4/SPOL
I/O
I/O
•In the 3-/4-line serial interface mode (P/S=“0”), the D0 terminal is
assigned to the SCL and the D1 terminal to the SDA.
•In the 3-line serial interface mode, the D4 terminal is assigned to
the SPOL.
•The serial data on the SDA is fetched at the rising edge of the
SCL signal in the order of the D7, D6…D0, and the fetched data
is converted into 8-bit parallel data at the falling edge of the 8th
SCL signal.
34,35
40,41
42,43
44,45
D2
D5
D6
D7
•The SCL signal should be set to “0” after data transmissions or
during non-access.
48,49
50,51
52,53
54,55
56,57
58,59
60,61
62,63
17,18
D8
D9
I/O
8-bit bi-directional bus
•In the 16-bit data bus mode, these terminals are assigned to the
upper 8-bit data bus.
•In the serial interface mode or 8-bit data bus mode in the parallel
interface, these terminals should be fixed to “1” or “0”.
D10
D11
D12
D13
D14
D15
I
I
Chip select
Active “0”
Resister select
CS
RS
20,21
•This signal distinguishes an instruction data and display data for
transferred data.
RS
H
L
Distinct.
Instruction
Display data
26,27
23,24
I
I
80 series MPU interface (P/S=“1”, SEL68=“0”)
RD signal. Active “0”.
RD (E)
68 series MPU interface (P/S=“1”, SEL68=“1”)
Enable signal. Active “1”.
80 series MPU interface (P/S=“1”, SEL68=“0”)
WR signal. Active “0”.
WR (R/W)
68 series MPU interface (P/S=“1”, SEL68=“1”)
R/W signal.
R/W
H
L
Status
Read
Write
- 14 -
NJU6824
ꢀꢀ TERMINAL DESCRIPTION 3
No.
10,11
Symbol
P/S
I/O
I
Function
Parallel / serial interface mode select
Chip
Select
Data/
Instruction
Read/Writ
e
P/S
Data
Serial clock
-
H
L
RS
RS
D0 ~ D7
CS
CS
RD, WR
SDA (D1)
Write only
SCL (D0)
•In the serial interface mode (P/S=“0”), the D15 to D5 and D2 terminals
are in the high impedance status therefore those terminals should be
fixed to “1” or “0”. The RD and WR terminals also should be “1” or “0”.
This terminal should be opened.
71,72
CL
O
73,74
75,76
77,78
FLM
FR
CLK
O
O
O
This terminal should be opened.
This terminal should be opened.
This terminal should be opened.
79,80
81,82
OSC1
OSC2
I
O
OSC
•When the internal oscillator clock is used, OSC1 terminal must be
fixed to “1” or “0”. OSC2 terminal should be opened. When the
oscillation frequency from the internal oscillator is adjusted by an
external resistor between OSC1 terminal and OSC2
•When an external oscillator is used, external clocks should be input
onto the OSC1 terminal or an external resistor should be connected
between the OSC1 and OSC2 terminals.
- 15 -
NJU6824
ꢀꢀ TERMINAL DESCRIPTION 4
No.
336~719
Symbol
SEGA0 ~ SEGA127
SEGB0 ~ SEGB127
SEGC0 ~ SEGC127
I/O
O
Function
,
,
Segment output
REF Mode
Turn-off
Turn-on
0
1
1
0
Normal
Reverse
•These terminals output LCD driving waveforms in accordance
with the combination of FR signal and display data.
In the B/W mode
FR signal
Display data
Normal display mode
V2
VLCD
V2
V 3
VSS
V3
Reverse
mode
display
VLCD
VSS
333,720
334,721
335,722
332~283,
276~263,
723~772,
779~792
SEGSA0, SEGSA1
SEGSB0, SEGSB1
SEGSC0, SEGSC1
COM0 ~ COM127
O
O
Icon segment output terminal
•These terminals are assigned at both edge of normal segment
output terminals line for out line frame display.
Common output
•These terminals output LCD driving waveforms in accordance
with the combination of the FR signal and scanning data.
Data
H
L
H
L
FR
H
H
L
Output level
VSS
V1
VLCD
V4
L
(Terminal No. 1~3,16,19,22,25,235~262,277~282,773~778,793~817 are dummy.)
- 16 -
NJU6824
ꢀꢀ Functional Description
(1) MPU Interface
(1-1) Parallel / serial interface mode select
The P/S terminal is used to select parallel or serial interface mode as shown in the following table. In the
serial interface mode, it is impossible to read out display data from the DDRAM and status from the
internal resistor.
Table1
WR
WR
-
P/S
H
P/S mode
Parallel I/F
Serial I/F
CS
CS
CS
RS
RS
RS
RD
RD
-
SEL68
SEL68
-
SDA
SDA
SCL
SCL
Data
D7-D0 (D15-D0)
-
L
Note 1) “ -” : Fix to “1” or “0”.
(1-2) MPU interface type select
In the parallel interface mode, the SEL68 terminal is used to select 68- or 80-series MPU interface type
as shown in the following table.
Table2
WR
R/W
WR
SEL68
MPU type
CS
CS
CS
RS
RS
RS
RD
E
Data
D7-D0 (D15-D0)
D7-D0 (D15-D0)
H
L
68 series MPU
80 series MPU
RD
(1-3) Data distinction
In the parallel interface mode, the combination of RS, RD, and WR (R/W) signals distinguishes an
instruction data or display data for the transferred data from or to MPU as shown in the following table.
Table3
68 series
80 series
Function
RS
RD
WR
H
R/W
H
Read out instruction data
Write instruction data
Read out display data
Write display data
H
H
L
L
H
L
L
L
H
H
L
L
H
L
(1-4) 3- / 4-line serial interface mode select
In the serial interface mode, the SMODE is used to select 3- or 4-line serial interface mode as shown in
the following table.
Table4
SMODE
Serial interface mode
H
L
3-line
4-line
- 17 -
NJU6824
(1-5) 4-line serial interface mode
In the 4-line serial interface mode, during the chip select is active (CS=“0”), the SDA and SCL are
enabled. During the chip select is not active (CS=“1”), the SDA and SCL are disabled and the internal shift
register and counter are being initialized. The 8-bit serial data on the SDA is fetched at the rising edge of
the SCL signal (serial clock) in order of the D7, D6…D0, and the fetched data is converted into the 8-bit
parallel data at the rising edge of the 8th SCL signal.
In the 4-line serial interface mode, the transferred data on the SDA is distinguished as display data or
instruction data in accordance with the condition of the RS signal.
Table5
RS
H
Data distinction
Instruction data
Display data
L
Since the serial interface operation is sensitive to external noises, the SCL should be set to “0” after data
transmissions or during non-access. To prevent for the continuous mal-function caused by the external
noises, the chip-selected status should be released (CS=“1”) after each of the 8-bit data transmissions.
The following figure illustrates the interface timing for the 4-line serial interface operation.
CS
RS
VALID
D0
SDA
D7
1
D6
2
D5
3
D4
4
D3
5
D2
D1
SCL
6
7
8
Fig1 4-line serial interface timing
(1-6) 3-line serial interface mode
In the 3-line serial interface mode, during the chip select is active (CS=“0”), the SDA and SCL are
enabled. During the chip select is not active (CS=“1”), the SDA and SCL are disabled and the internal shift
register and counter are being initialized. The 9-bit serial data on the SDA is fetched at the rising edge of
the SCL signal in order of the RS, D7, D6…D0, and the fetched data is converted into the 9-bit parallel data
at the rising edge of the 9th SCL signal.
In the 3-line serial interface mode, the data on the SDA is distinguished as display data or instruction
data in accordance with the condition of the RS bit of SDA data and the status of the SPOL, as follows.
Table6
SPOL=L
Data distinction
SPOL=H
Data distinction
RS
L
RS
L
Display data
Instruction data
Display data
H
Instruction data
H
- 18 -
NJU6824
Since the serial interface operation is sensitive to external noises, the SCL should be set to “0” after data
transmissions or during non-access. To prevent for the continuous mal-function caused by the external
noises, the chip-selected status should be released (CS=“1”) after each of the 9-bit data transmissions.
The following figure illustrates the interface timing for the 3-line serial interface operation.
CS
SDA
SCL
RS
1
D7
2
D6
D5
4
D4
5
D3
D2
D1
D0
3
6
7
8
9
Fig2 3-line serial interface timing
- 19 -
NJU6824
(2) Access to the DDRAM
During the CS signal is ”0”, the transferred data is written into the DDRAM or instruction register in
accordance with the condition of the RS signal.
In condition that the RS signal is “1”, the transferred data is distinguished as display data. After the “column
address” and “row address” instructions are executed, the display data is written into the DDRAM by the
“display data write” instruction. The data is written at the rising edge of the WR signal in the 80 series MPU
mode or falling edge of the E signal in the 68 series MPU mode.
Table6
RS
L
Data
Display RAM Data
H
Internal Command Register
In the sequence of the “display data read” operation, the transferred data from MPU is temporarily held in the
internal bus-holder and then transferred to the internal data-bus. When the “display data read” operation is
executed just after the “column address” and “row address” instructions or “display data write” instruction,
unexpected data on the bus-holder is read out at the 1st execution and then the correct designated DDRAM
address data is read out from the 2nd execution. For this reason, a dummy read cycle must be executed to
avoid the unexpected 1st data read.
Display data write operation
n
n+1
n+2
n+3
n+4
D0 to D15
WR
n
n+1
n+2
n+3
n+4
Bus Holder
WR
Display data read operation
WR
D0 to D7(D0 to D15)
n
n
n+1
Data Read
n+1 Address n+2 Address
n+2
Address Set
n
Dummy
Read
Data Read
n Address
Data Read
RD
Fig3
Note) In 16-bit operation mode, command operation must set “Write” or “Read” with 16-bit data length as same
as the access to RAM.
- 20 -
NJU6824
(3) Access to the instruction register
Each of the instruction resisters is assigned to the address in between 0H and FH in order that it is possible to
read out the content of the instruction registers by the combination instructions of the “Instruction resister
address” and ”Instruction resister read”.
WR
M
m
N
n
D0 to D7
Instruction resister
address set
Instruction resister Instruction resister Instruction resister
contents read
address set
contents read
RD
Fig4
(4) 8-/16-bit data bus length for display data (in the parallel interface mode)
The 8- or 16-bit data bus length for display data is determined by the “WLS” in the “Data bus length”
instruction.
In the 16-bit data bus mode, not only the display data but also the instruction data is required to be
transferred by 16-bit data (D15 to D0). However, in case of the access to the instruction register, the only lower
8-bit data (D7 to D0) of the 16-bit data is valid. In case of the access to the DDRAM, all of the 16-bit data (D15 to
D0) is valid.
Table8
WLS
L
Data bus length mode
8-bit
H
16-bit
(5) Initial display line register
The initial display line resister specifies the line address, corresponding to the initial COM line, by the “Initial
display line” instruction. The initial COM line signifies the common driver, starting scanning the display data in
the DDRAM, and specified by the “Initial COM line” instruction.
The line address, established in the initial display line resister, is preset into the line counter whenever the
FLM signal becomes “1”. At the rising edge of the CL signal, the line counter is counted-up and addressed 384-
bit display data is latched into the data latch circuit. At the falling edge of the CL signal, the latched data output
to the segment drivers.
- 21 -
NJU6824
(6) DDRAM mapping
The DDRAM is capable of 1,536-bit (12-bit x 128-segment) for the column address and 128-bit for the row
address.
In the gradation mode, each pixel for RGB corresponds to the successive 3-segment drivers with 16-
gradation per segment, so that the LSI can drive a 4096-color display (16-gradation x 16-gradation x 16-
gradation) with up to 128x128 pixels.
In 8-bit access mode(C256 mode) for DDRAM, sequential twice accesses to DDRAM complete one pixel
data access. Therefore, it must be accessed with a couple of operation.
ꢁ In the 8-bit data bus length mode
column-address
0H
7FH
0 H
7bit
5bit
7bit
5bit
row-address
7FH
7bit
4bit
5bit
8bit
7bit
4bit
5bit
8bit
column-address
0H
7FH
ABS=’1’
0 H
row-address
7FH
4bit
8bit
4bit
8bit
column-address
0H
8bit
1H
8bit
7EH
8bit
7FH
8bit
C256=’1’
0 H
row-address
7FH
8bit
8bit
8bit
8bit
Fig5
- 22 -
NJU6824
ꢁ In the 16-bit data bus length mode
column-address
0H
7FH
0 H
12bit
12bit
row-address
7FH
12bit
12bit
Fig6
In the B&W mode, only MSB data from each 4-bit display data group in the DDRAM is used. Therefore, 384 x
128 pixels B&W display or 128 x 128 pixels 8 kinds display is also available.
The column address range varies depending on the data bus length. The range between 00H and 7FH is used
in the 8-bit or 16-bit data bus length.
The DDRAM is accessing 8-bit or 16-bit unit addressed by column and row address. In the 8-bit or 16-bit data
bus length mode, over 80H address setting is prohibited.
The increment for the column address and row address can be set in the auto-increment mode by
programming “AXI” and “AYI” registers in the “Increment control” instruction. In this mode, the contents of the
column address and row address counters automatically increment whenever the DDRAM is accessed.
The column address and row address counters are independent of the line counter. They are used to
designate the column address and row address for the display data transferred from MPU. On the other hand,
the line counter is used to generate the line address and output the display data to the segment drivers, being
synchronized with the display control timing of the FLM and CL signals.
- 23 -
NJU6824
SWAP
A3
WLS
ABS
256
WLS
ABS
256
A2
A1
A0
A3
A3
B3
A2
A1
A0
B3
B2
B1
B0
C3
C2
C1
C0
A3
A2
A1
A0
B3
B2
B1
B0
C3
C2
C1
C0
A2
A1
A0
B3
B2
B1
B0
C3
C2
C1
C0
A3
A2
A1
A0
B3
B2
B1
B0
C3
C2
C1
C0
B2
B1
B0
C3
C2
C1
C0
A3
A2
A1
A0
B3
B2
B1
B0
C3
C2
C1
C0
A3
A2
A1
A0
B3
B2
B1
B0
C3
C2
C1
C0
A3
A2
A1
A0
B3
B2
B1
B0
C3
C2
C1
C0
A3
A2
A1
A0
B3
B2
B1
B0
C3
C2
C1
C0
- 24 -
NJU6824
SWAP
A3
WLS
ABS
256
WLS
ABS
256
A2
A1
A0
B3
A3
A3
B2
A2
A1
A0
B3
B2
B1
B0
C3
C2
C1
C0
A3
A2
A1
A0
B3
B2
B1
B0
C3
C2
C1
C0
A2
A1
A0
B3
B2
B1
B0
C3
C2
C1
C0
A3
A2
A1
A0
B3
B2
B1
B0
C3
C2
C1
C0
B1
B0
C3
C2
C1
C0
- 25 -
NJU6824
(7) Window addressing mode
Window area must be designated before RAM access.
In the window addressing mode, the address space of the DDRAM designated by the start and end point is
defined. The start point is determined by the “column address” and “row address” instructions, and the end
point is determined by the “Window end column address “and ”Window end row address” instructions. The
setting for the window addressing is listed in the following.
1. “Increment control” instruction set (HV, XD, YD)
2. Set “column address” and “row address” instructions for the start point
3. Set “Window end column address” and “Window end row address” instructions for the end point
4. Enable to access to the DDRAM by the window addressing mode
In addition, the read-modify-write operation is available by setting “AIM” register to ”L” in the “Increment
control” instruction.
For the window area designation, the address directions of RAM (HV, XD, YD) must be set first, and Column
address and Row of Start point must be set second, Column address and Row of Stop point must be set third,
then RAM should be accessed. Low address must be set first and High address must be set second in all of
addresses. The directions of HV, XD, YD should be check to keep the area in RAM.
Also in the window addressing mode, correct start and end point setting is required to abide to access invalid
addressing space.
column address
(X, Y)
Start point
End point
Window display area
(X, Y)
Whole DDRAM area
Fig7
(8) Reverse display ON/OFF
The “Reverse display ON/OFF” function is used to reverse the display data without changing the display data
in the DDRAM.
Table9
REV
Display
Normal
DDRAM data → Display data
0
1
0
1
0
1
1
0
0
1
Reverse
(9) Address directions of RAM access (Display rotation)
The bellow picture shows display image after set of HV, XD and YD for address directions. The display data
from CPU can be written into RAM with rotation to 90 degrees or 180 degrees or 270 degrees, and also
mirrored.
The address directions of RAM access is set by HV, XD and YD.
* : The segments of Icon are not rotated.
- 26 -
NJU6824
No.
HVXDYD
Valid address
Xs < Xe
Data writing direction
(Xs, Ys)
Display image
1 0 0 0
2 0 0 1
3 0 1 0
4 0 1 1
5 1 0 0
6 1 0 1
7 1 1 0
8 1 1 1
Ys < Ye
Xs < Xe
Ys > Ye
Xs > Xe
Ys < Ye
Xs > Xe
Ys > Ye
Xs < Xe
Ys < Ye
Xs < Xe
Ys > Ye
Xs > Xe
Ys < Ye
Xs > Xe
Ys > Ye
(Xe, Ye)
(Xe, Ye)
(Xs, Ys)
(Xs, Ys)
(Xe, Ye)
(Xe, Ye)
(Xs, Ys)
(Xs, Ys)
(Xe, Ye)
(Xe, Ye)
(Xs, Ys)
(Xs, Ys)
(Xe, Ye)
(Xe, Ye)
(Xs, Ys)
*:The display image shows the display direction when the same data as No.1 are written into RAM for
condition change.
*: The outside address of RAM must not be set for correct operation.
Xs : start address of X , Ys : Start address of Y, Xe : End address of X, Ye : End address of Y
- 27 -
NJU6824
(10) The relationship among the DDRAM column address, display data and segment drivers
Color mode, 16-bit data bus mode
ABS SWAP
X address / bit / segment assign
0
0
X=00H
X=00H
X=00H
X=00H
ꢂꢃ
X=7FH
X=7FH
X=7FH
X=7FH
ꢂꢃ
ꢂꢃ
ꢂꢃ
ABS SWAP
0
X address / bit / segment assign
1
ꢂꢃ
ꢂꢃ
ꢂꢃ
ꢂꢃ
ABS SWAP
1
X address / bit / segment assign
0
ꢂꢃ
ꢂꢃ
ꢂꢃ
ꢂꢃ
ABS SWAP
1
X address / bit / segment assign
1
ꢂꢃ
ꢂꢃ
ꢂꢃ
ꢂꢃ
- 28 -
NJU6824
Color mode, 8-bit data bus mode
ABS SWAP
X address / bit / segment assign
0
0
X=00H(Upper)
X=00H(Lower)
ꢂꢃ
X=7FH(Upper)
X=7FH(Lower)
ꢂꢃ
ꢂꢃ
ꢂꢃ
ABS SWAP
X address / bit / segment assign
0
1
X=00H(Upper)
X=00H(Lower)
ꢂꢃ
X=7FH(Upper)
X=7FH(Lower)
ꢂꢃ
ꢂꢃ
ꢂꢃ
ABS SWAP
X address / bit / segment assign
1
0
X=00H(Upper)
X=00H(Lower)
ꢂꢃ
X=7FH(Upper)
X=7FH(Lower)
ꢂꢃ
ꢂꢃ
ꢂꢃ
ABS SWAP
X address / bit / segment assign
1
1
X=00H(Upper)
X=00H(Lower)
ꢂꢃ
X=7FH(Upper)
X=7FH(Lower)
ꢂꢃ
ꢂꢃ
ꢂꢃ
- 29 -
NJU6824
Color mode, 8-bit data bus mode, C256 mode (C256=1)
ABS SWAP
X address / bit / segment assign
*
0
X=00H
ꢂꢃ
X=7FH
ꢂꢃ
ꢂꢃ
ꢂꢃ
ABS SWAP
X address / bit / segment assign
*
1
X=00H
ꢂꢃ
X=7FH
ꢂꢃ
ꢂꢃ
ꢂꢃ
- 30 -
NJU6824
B&W mode, 16-bit data bus mode
ABS SWAP
X address / bit / segment assign
0
0
X=00H
X=00H
X=00H
X=00H
ꢂꢃ
X=7FH
X=7FH
X=7FH
X=7FH
ꢂꢃ
ꢂꢃ
ABS SWAP
0
X address / bit / segment assign
1
ꢂꢃ
ꢂꢃ
ꢂꢃ
ABS SWAP
1
X address / bit / segment assign
0
ꢂꢃ
ꢂꢃ
ꢂꢃ
ABS SWAP
1
X address / bit / segment assign
1
ꢂꢃ
ꢂꢃ
ꢂꢃ
- 31 -
NJU6824
B&W mode, 8-bit data bus mode
ABS SWAP
X address / bit / segment assign
0
0
X=00H(Upper)
X=00H(Lower)
ꢂꢃ
X=7FH(Upper)
X=7FH(Lower)
ꢂꢃ
ꢂꢃ
ABS SWAP
X address / bit / segment assign
0
1
X=00H(Upper)
X=00H(Lower)
ꢂꢃ
X=7FH(Upper)
X=7FH(Lower)
ꢂꢃ
ꢂꢃ
ABS SWAP
X address / bit / segment assign
1
0
X=00H(Upper)
X=00H(Lower)
ꢂꢃ
X=7FH(Upper)
X=7FH(Lower)
ꢂꢃ
ꢂꢃ
ABS SWAP
X address / bit / segment assign
1
1
X=00H(Upper)
X=00H(Lower)
ꢂꢃ
X=7FH(Upper)
X=7FH(Lower)
ꢂꢃ
ꢂꢃ
- 32 -
NJU6824
Write and read data bit assignment (in the 16-bit data bus mode)
ABS=0
Write data
D15
D14
D13
D12
D11
D10
D9
D8
D7
D7
D6
*
D5
*
D4
D4
D3
D3
D2
D2
D1
D1
D0
*
Read data
D15
D14
D13
D12
*
D10
D9
D8
ABS=1
Write data
D15
D14
D13
D12
D11
D11
D10
D10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Read data
*
*
*
*
Examples for write and read display data (In 8 bit bus mode)
ABS=0, C256=0 (Address; Upper bit)
Write data
D7
D6
D5
D4
D3
D2
D1
D0
D0
Read data
D7
D6
D5
D4
*
D2
D1
ABS=0, C256=0 (Address; Lower bit)
Write data
D7
D6
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
*
Read data
D7
*
*
ABS=1, C256=0 (Address; Upper bit)
Write data
D7
D6
D5
D4
*
D3
D3
D2
D2
D1
D1
D0
D0
Read data
*
*
*
ABS=1, C256=0 (Address; Lower bit)
Write data
D7
D6
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Read data
D7
D6
D5
ABS=0, C256=1
Write data
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Read data
*: Invalid Data
- 33 -
NJU6824
Icon segment register address bit assignment
Color mode, 16-bit data bus mode
ABS SWAP
X address / bit / segment assign
0
0
X=00H
X=01H
ABS SWAP
X address / bit / segment assign
0
1
X=00H
X=01H
ABS SWAP
X address / bit / segment assign
1
0
X=00H
X=01H
ABS SWAP
X address / bit / segment assign
1
1
X=00H
X=01H
- 34 -
NJU6824
Color mode, 8-bit data bus mode
ABS SWAP
X address / bit / segment assign
0
0
X=00H(Upper)
X=00H(Lower)
X=01H(Upper)
X=01H(Lower)
ABS SWAP
X address / bit / segment assign
0
1
X=00H(Upper)
X=00H(Lower)
X=01H(Upper)
X=01H(Lower)
ABS SWAP
X address / bit / segment assign
1
0
X=00H(Upper)
X=00H(Lower)
X=01H(Upper)
X=01H(Lower)
ABS SWAP
X address / bit / segment assign
1
1
X=00H(Upper)
X=00H(Lower)
X=01H(Upper)
X=01H(Lower)
- 35 -
NJU6824
B/W mode, 16-bit data bus mode
ABS SWAP
X address / bit / segment assign
X address / bit / segment assign
X address / bit / segment assign
X address / bit / segment assign
0
0
X=00H
X=00H
X=00H
X=00H
X=01H
X=01H
X=01H
X=01H
ABS SWAP
0
1
ABS SWAP
1
0
ABS SWAP
1
1
- 36 -
NJU6824
B/W mode, 8-bit data bus mode
ABS SWAP
X address / bit / segment assign
0
0
X=00H(Upper)
X=00H(Lower)
X=01H(Upper)
X=01H(Lower)
ABS SWAP
X address / bit / segment assign
0
1
X=00H(Upper)
X=00H(Lower)
X=01H(Upper)
X=01H(Lower)
ABS SWAP
X address / bit / segment assign
1
0
X=00H(Upper)
X=00H(Lower)
X=01H(Upper)
X=01H(Lower)
ABS SWAP
X address / bit / segment assign
1
1
X=00H(Upper)
X=00H(Lower)
X=01H(Upper)
X=01H(Lower)
- 37 -
NJU6824
(11) Gradation palette
In the gradation mode, variable or fixed gradation mode is selected by programming the “PWM” register in
the “Gradation control” instruction.
PWM=0:
PWM=1:
Variable gradation mode
(Select 16 gradation levels out of a palette consisting of 32-gradation levels)
Fixed gradation mode
(Fixed 8-gradation levels)
In the gradation mode, each of the gradation palettes Aj, Bj and Cj can select 16-gradation levels out of a
palette consisting of 32-gradation levels by setting 5-bit palette value into the “PA” registers in the “Gradation
palette j” instructions (j=0 to Fh).
The gradation palettes Aj correspond to the SEGAi, the Bj to SEGBj and the Cj to SEGCi (j=0 to 15, i=0 to
127).
- 38 -
NJU6824
The correspondence between display data and gradation palettes
Table 10 (Palette Aj, Palette Bj, Palette Cj (j=0 to 15))
(MSB) Display data (LSB)
Gradation palette
Palette 0
Palette 1
Palette 2
Palette 3
Palette 4
Palette 5
Palette 6
Palette 7
Palette 8
Palette 9
Palette10
Palette11
Palette12
Palette13
Palette14
Palette15
Default palette value
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Gradation palette table (PWM=”0”, MON=”0”, Variable gradation mode)
Table 11 (Palette Aj, Palette Bj, Palette Cj (j=0 to 15))
Palette
value
Gradation
level
Palette value
Gradation level
Gradation palette
Palette 0(default)
Gradation palette
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 1 0 0
0 0 1 0 1
0 0 1 1 0
0 0 1 1 1
0 1 0 0 0
0 1 0 0 1
0 1 0 1 0
0 1 0 1 1
0 1 1 0 0
0 1 1 0 1
0 1 1 1 0
0 1 1 1 1
0
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1
1 0 1 0 0
1 0 1 0 1
1 0 1 1 0
1 0 1 1 1
1 1 0 0 0
1 1 0 0 1
1 1 0 1 0
1 1 0 1 1
1 1 1 0 0
1 1 1 0 1
1 1 1 1 0
1 1 1 1 1
16/31
17/31
18/31
19/31
20/31
21/31
22/31
23/31
24/31
25/31
26/31
27/31
28/31
29/31
30/31
31/31
1/31
2/31
3/31
4/31
5/31
6/31
7/31
8/31
9/31
10/31
11/31
12/31
13/31
14/31
15/31
Palette 0(default)8
Palette 9(default)
Palette 10(default)
Palette 11(default)
Palette 12(default)
Palette 13(default)
Palette 14(default)
Palette 15(default)
Palette 1(default)
Palette 2(default)
Palette 3(default)
Palette 4(default)
Palette 5(default)
Palette 6(default)
Palette 7(default)
- 39 -
NJU6824
Gradation palette table (PWM=”1”, MON=”0”, Fixed gradation mode)
Table 12 8-gradation segment drivers
Gradation
level
(MSB) Display data (LSB)
Gradation level
0/7
(MSB) Display data (LSB)
0/7
0
0
*
*
0
0
0
*
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
*
*
*
*
*
*
*
1/7
2/7
3/7
4/7
5/7
6/7
7/7
0
0
0
1
1
1
1
0
1
1
0
0
1
1
*
*
*
*
*
*
*
*
*
*
*
*
*
*
3/7
5/7
7/7
The correspondence between display data and gradation level (MON=”1”, B&W mode)
Table 13
Gradation
level
(MSB) Display data (LSB)
0
1
*
*
*
*
*
*
0
1
*:Don’t care
- 40 -
NJU6824
(12) Gradation control and display data
(12-1)Gradation mode
In the graduation mode, each pixel for RGB corresponds to the successive 3 segment drivers that each
segment driver provides 16-gradation PWM output, so that NJU6824 can drive a 4096-color display (16-
gradation x 16-gradation x 16-gradation = 4-bit x 4-bit x 4-bit) with up to 128x128 pixels. The 16-gradation
segment drivers can generate 16-gradation levels controlled by using 4-bit of display data in the DDRAM.
In addition, the LSI can transfer 16-bit display data for 1-pixel RGB by one-time access or 8-bit by two-
time access. The display data assignments for the gradation palettes and segment drivers vary in
accordance with the setting for the “SWAP” bit in the "Display control (2)" instruction.
- SWAP = 0
SEGAi
SEGBi
SEGCi
(i=0 to 127)
Gradation palette
j=0 to 15
Paltte Aj
Palette Bj
Palette Cj
Gradation control circuit
Display data in DDRAM
0
0
0
0
0
0
0
1
1
1
1
1
MSB
LSB MSB
LSB MSB
LSB
Display data from MPU
0
0
0
0
D4
D0
*
0
0
0
1
D7
D4
*
1
1
1
D2
D1
*
1
D7
D6
D5
D1
D5
D2
D7
D4
D1
D6
D3
D0
D5
D2
D4
D3
D1
D3
D2
D0
D1
D0)
* )
(Upper bit / Lower bit)
ABS=1
(D3 D2
(D7 D6
C256=1
- SWAP = 1
SEGAi
SEGBi
SEGCi
(i=0 to 127)
Gradation palette
j=0 to 15
Palette Aj
Palette Bj
Palette Cj
Gradation control circuit
Display data in DDRAM
1
1
1
1
1
0
0
0
0
0
0
0
LSB
MSB LSB
MSB LSB
MSB
Display data from MPU
0
0
0
0
0
0
0
1
1
1
1
1
D7
D6
D5
D1
D4
D0
D2
D7
D1
D6
D0
D5
D7
D4
D4
D3
D3
D2
D2
D1
D1
D0)
(Upper bit / Lower bit)
ABS=1
(D3 D2
(D7 D6
C256=1
D5
*
D4
D3
D2
*
D1
D0
*
* )
- 41 -
NJU6824
In the 16-bit data bus mode, the display data assignments for the gradation palettes and segment
drivers vary in accordance with the setting for the “SWAP” bit in the "Display control (2)" instruction as well
as the assignment in the 8-bit data bus mode.
- SWAP = 0
SEGAi
SEGBi
SEGCi
(i=0 to 127)
Gradation palette
j=0 to 15
Paltte Aj
Palette Bj
Palette Cj
Gradation control circuit
Display data in DDRAM
0
0
0
0
0
0
0
0
0
1
1
1
1
1
MSB
LSB MSB
LSB MSB
LSB
Display data from MPU
0
0
0
0
0
1
1
1
1
1
D15 D14 D13 D12 D10 D9
D8
D5
D7
D4
D4
D3
D3
D2
D2
D1
D1
D0)
ABS=1
(D11 D10 D9
D8
D7
D6
- SWAP = 1
SEGAi
SEGBi
SEGCi
(i=0 to 127)
Gradation palette
j=0 to 15
Palette Aj
Palette Bj
Palette Cj
Gradation control circuit
Display data in DDRAM
1
1
0
1
0
1
1
0
0
0
0
0
0
0
0
LSB
MSB LSB
MSB LSB
MSB
Display data from MPU
0
0
0
0
1
1
1
1
1
D15 D14 D13 D12 D10 D9
D8
D5
D7
D4
D4
D3
D3
D2
D2
D1
D1
D0)
ABS=1
(D11 D10 D9
D8
D7
D6
- 42 -
NJU6824
(12-2)B&W mode (MON=”1”)
In the B&W mode, only 3 of MSB of each display data are used for the display by the 16-bit data bus
mode and 8-bit.
16-bit data bus access example (Similarly 8-bit data bus access)
- SWAP = 0
SEGAi
SEGBi
SEGCi
(i=0 to 127)
Gradation palette
j=0 to 15
Palette Aj
Palette Bj
Palette Cj
Gradation control circuit
Display data in DDRAM
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
MSB
LSB MSB
LSB MSB
LSB
Display data in DDRAM
0
0
0
0
1
1
1
1
1
D15 D14 D13 D12 D10 D9
(D11 D10 D9 D8 D7 D6
D8
D5
D7
D4
D4
D3
D3
D2
D2
D1
D1
D0)
ABS=1
- SWAP = 1
SEGAi
SEGBi
SEGCi
(i=0 to 127)
Gradation palette
j=0 to 15
Palette Aj
Palette Bj
Palette Cj
Gradation control circuit
Display data in DDRAM
1
1
0
1
0
1
1
0
0
0
0
0
0
0
1
0
1
0
LSB
MSB LSB
MSB LSB
MSB
Display data in DDRAM
0
0
0
1
1
1
D15 D14 D13 D12 D10 D9
(D11 D10 D9 D8 D7 D6
D8
D5
D7
D4
D4
D3
D3
D2
D2
D1
D1
Column address; nH
D0)
ABS=1
The correlation of display data with gradation control is also applied to Icon segment.
- 43 -
NJU6824
(13) Display timing generator
The display-timing generator creates the timing pulses such as the CL, FLM, FR and CLK by dividing the
oscillation frequency oscillate an external or internal resister mode. The each of timing pulses is outputted
through the each output terminals by “SON” = 1.
(14) LCD line clock (CL)
The LCD line clock (CL) is used as the count-up signal for the line counter and the latch signal for the data
latch circuit. At the rising edge of the CL signal, the line counter is counted-up and the 384-bit display data,
corresponding to the counted-up line address, is latched into the data latch circuit. And at the falling edge of the
CL signal, the latched data output onto the segment drivers. The read out operation from DDRAM to the latch
is completely independent from the MPU accessing. Therefore, MPU can access to the LSI regardless the
internal operation.
(15) LCD alternate signal (FR) and LCD synchronous signal (FLM)
Both of the FR and FLM signals are created from the CL signal. The FR signal is used to alternate inverse
driving for the LCD panel. It can be programmed so that the FR signal is toggle on every frame in the default
setting or once every N frames in the N-line inversion mode. The FLM signal is used to indicate the start line of
a new display frame. It presets an initial display line address into the line counter when the FLM signal
becomes ”1”.
(16) Data latch circuit
The data latch circuit is used temporarily store the display data that will output to the segment drivers. The
display data in this circuit is updated in synchronization of the CL signal.
The “All pixels ON/OFF”, “Display ON/OFF” and “Reverse display ON/OFF” instructions change the display
data in this circuit but do not change the display data in the DDRAM.
(17) Common and segment drivers
The LSI includes 384+6-segment drivers and 128-common drivers for a graphic display. The common drivers
generate the LCD driving waveforms composed of the VLCD, V1, V4 and VSS in accordance with the FR signal
and scanning data. The segment drivers generate the waveforms composed of the VLCD, V2, V3 and VSS in
accordance with the FR signal and display data.
- 44 -
NJU6824
LCD Driving waveforms (Reverse display OFF, 1/129 duty, B&W mode)
COM0
1
2
3
4
5
1
2
3
4
5
1
129
163
129
COM1
CL
FLM
FR
VLCD
V1
V2
V3
COM0
V4
VSS
VLCD
V1
V2
V3
V4
VSS
COM1
SEG0
VLCD
V1
V2
V3
V4
VSS
VLCD
V1
V2
SEG1
V3
V4
VSS
Fig 8
- 45 -
NJU6824
(18) Icon Segment Driver Circuit
Each 3 outputs (SEGSA0 to SEGSA1, SEGSB0 to SEGSB1, SEGSC0 to SEGSC1) placed at both edges of
normal segment output terminals line are Segment outputs for Icon. Although normal Segment output generates
the LCD driving voltage corresponding with the data in Display Data RAM, Icon segment driver provides the
register instead of the display data RAM. The data corresponding to SEGSA0, SEGSB0 and SEGSC0 are in 12-
bit register and output the same driving voltage on the row direction. (The data corresponding to SEGSA1,
SEGSB1 and SEGSC1 are same as SEGSA0, SEGSB0 and SEGSC0.)
The outputs of SEGSA0 to SEGSA1 assign the same gradation pallet as SEGA0 to SEGA127, SEGSB0 to
SEGSB1 are SEGB0 to SEGB127 and SEGSC0 to SEGSC1 are SEGC0 to SEGC127.
Icon Segment Driver Circuit operates for the outline frame display or background. These displays are
changed in accordance with attribute of ALLON or REV command, but no change by LREV command.
The capacity of register corresponding with Icon segment driver (SEGSA0 to SEGSA1, SEGSB0 to SEGSB1,
SEGSC0 to SEGSC1) is 24 bits. The access to from this register performed at DMY="1"..
Table14
80 type
68type
RS
DMY
Function
Display data read
Display data write
Icon segment register read
Icon segment register read
R/W
H
L
H
L
RD
WR
H
L
H
L
L
L
L
L
0
0
1
1
L
H
L
H
Read out function from the Icon segment register is restricted as same as the display data read out function
from Display Data RAM. After address set, the addressed data does not come out by the first read instruction
immediately but comes out by the second read instruction. Therefore, one dummy read out function is required
for data read from Icon segment register after the address set or the data write operation.
When the Icon segment registers are accessed in DMY="1", the valid addressing is just a column address.
Because of 24 bits Icon register, the valid addresses are "00h" and "01h" in 8-bit or 16-bit mode.
When the Icon segment registers are accessed in DMY="1", the data write operation into Icon register is
enabled with the increment / decrement operation.
The column address increment operates as shown below. But the auto carry up operation like as the
maximum address to "00h" does not operate of the display data RAM access.
00h -> Max.
•
8-bit or 16-bit data bus mode (DMY=”1”)
Column address
00H:
01H:
SEGSA0, SEGSB0, SEGSC0
SEGSA1, SEGSB1, SEGSC1
Note) Refer the “Icon segment register address bit assignment” in (10) The relationship among the DDRAM
column address, display data and segment drivers. Both of Icon segment register and Display data RAM
operate a same address counter so that the address is set again in the status transition of DMY = "0" to "1"
or "1" to "0".
The access to Icon register must be operated in the condition of HV=0.
- 46 -
NJU6824
Examples for the dummy segment registers (DMY=”1”)
(In the 16-bit data bus mode, gradation mode, (REF,SWAP)=(0,0))
Column address: 00H
SEGSA0
SEGSB0
SEGSC0
Gradation palette
j=0 to 15
Palette Aj
Palette Bj
Palette Cj
Gradation control circuit
Display data in DDRAM
Display data in DDRAM
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
MSB
LSB MSB
LSB MSB
LSB
0
0
0
0
1
1
1
1
1
D15 D14 D13 D12 D10 D9
D8
D7
D4
D3
D2
D1
(D11 D10 D9 D8 D7 D6
D5
D4
D3
D2
D1
D0)
ABS=1
Column address: 01H
SEGSA1
SEGSB1
SEGSC1
Gradation palette
j=0 to 15
Palette Aj
Palette Bj
Palette Cj
Gradation control circuit
Display data in DDRAM
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
MSB
LSB MSB
LSB MSB
LSB
Display data in DDRAM
0
0
0
0
1
1
1
1
1
D15 D14 D13 D12 D10 D9
D8
D7
D4
D3
D2
D1
(D11 D10 D9 D8 D7 D6
D5
D4
D3
D2
D1
D0)
ABS=1
- 47 -
NJU6824
(19) Oscillator
The oscillator generates the internal clock for the display timing and voltage booster. The C and R for the
oscillator are on chipped, therefore, there is no C, R required as an external components. Use an external R
instead of internal R is also available (CSK=1), in this time connect the resister between OSC1 and OSC2
terminals. However, when the internal oscillator is not used, an external clock, which duty should be 50%,
inputs onto the OSC1 terminal.
In addition, the value of the feed back resister for the oscillator can be varied by programming the “Rf”
register in the “Frequency control” instruction so that it is possible to optimize the frame frequency for a LCD
panel.
[Setting of MON(B&W /Gradation) and PWM(Variable gradation/Fixed gradation)]
In case of the internal oscillation mode (CSK=0)
Symbol
FR1
FR2
MON PWM
Display mode
0
0
1
0
1
*
Variable gradation mode
Fixed gradation mode
B&W mode
FR3
*: Don’t care
In case of the external resistor oscillation mode(CSK=1)
In case of the external resistor oscillation, clock frequency should be adjusted with resistor as same as
the frequency of internal oscillation. And also MON and PWM should be set.
In case of the external clock input mode(CSK=1)
In case of the external clock input operation, clock frequency should be input as same as the frequency
of internal oscillation on a display mode. And also MON and PWM should be set. Because the frame
frequency and the internal voltage booster circuit operation frequency are determined by the external clock
frequency and conditions of MON and PWM.
(20) Power supply circuits
The internal power supply circuits are composed of the voltage booster, electrical variable resister (EVR),
voltage regulator, reference voltage generator and voltage followers.
The status of the power supply circuits is arranged by programming the “DCON” and “AMPON” registers in
the “Power control” instruction. For this arrangement, the part of the internal power supply circuits can be used
in combination with an external power supply as described in the following table.
Table 15
Voltage followers
DCON
AMPON
Voltage booster
Voltage regulator
EVR
External voltage
Note
0
0
1
0
1
1
Disable
Disable
Enable
Disable
Enable
Enable
1, 3
2, 3
−
V
OUT, VLCD, V1, V2, V3, V4
VOUT
−
Note1) The internal power circuits are not used. The C1+, C1-, C2+, C2-, C3+, C3-, C4+, C4-, C5+, C5-, VOUT, VREF
VREG and VEE terminals should be open.
,
Note2) The internal power circuits are used, excluding the voltage booster. The external VOUT voltage is required
and the C1+, C1-, C2+, C2-, C3+, C3-, C4+, C4-, C5+, C5- and VEE terminals should be open. The reference
voltage is required into VREF terminal.
Note3) The relation among the voltages should be maintained.
VOUT
≥ VLCD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS
- 48 -
NJU6824
(21) Voltage booster
The voltage booster generates maximum 6x voltage of the VEE level. It is programmed so that the boost level
can be selected out of 1x, 2x, 3x, 4x, 5x and 6x by the “Boost level select” instruction. The boosted voltage
VOUT must not exceed beyond 18.0V, otherwise the voltage stress may cause a permanent damage to the LSI.
Boosted voltages
VOUT=18V
VOUT=9V
VEE=3V
VSS=0V
VEE=3V
VSS=0V
6-time boost
3-time boost
Capacitor connections for the voltage Booster
6-time boost
5-time boost
C1+
C1-
C2+
C2-
C3+
C3-
C4+
C4-
C5+
C5-
VOUT
VSS
C1+
+
+
+
+
+
+
+
+
+
+
C1-
C2+
C2-
C3+
C3-
C4+
C4-
C5+
C5-
VOUT
VSS
+
4-time boost
3-time boost
2-time boost
C1+
C1-
C2+
C2-
C3+
C3-
C1+
C1-
C2+
C2-
C3+
C3-
C1+
C1-
C2+
C2-
C3+
C3-
+
+
+
+
+
+
C4+
C4-
C4+
C4-
C4+
C4-
C5+
C5-
C5+
C5-
C5+
C5-
VOUT
VSS
VOUT
VSS
VOUT
VSS
+
+
+
Fig 9
- 49 -
NJU6824
(22) Reference voltage generator
The reference voltage generator is used to produce the reference voltage (VBA) that is output from the VBA
terminal and input to the VREF terminal.
VBA = VEE x 0.9
(23) Voltage regulator
The voltage regulator, composed of the gain control circuit and operational amplifier, is used to gain the
reference voltage (VREF) and create the regulated voltage (VREG). The VREG is used for the input voltage for the
EVR by programming the “VU” register in the “Boost level” instruction.
VREG = VREF x N
(N: register value for the boost level)
(24) Electrical variable resister (EVR)
The EVR, variable with 128-step, is used to fine-tune the LCD driving voltage (VLCD) by programming the “DV”
register in the “EVR control” instruction, so that it is possible to optimize the contrast level for a LCD panel.
VLCD = 0.5 x VREG + M (VREG - 0.5 x VREG) / 127 (M: register value for the EVR)
(25) LCD driving voltage generation circuit
LCD driving voltage generation circuit generates the VLCD voltage levels as VLCD, V1, V2, V3 and V4 with
internal E.V.R and Bleeder resistors. And a BIAS ratio of LCD driving voltage can be selected out of follows; 1/5,
1/6, 1/7, 1/8, 1/9, 1/10, 1/11 or 1/12.
In case of internal power supply operation, a voltage stabilization capacitor CA2 must be connected to VLCD
V1, V2, V3 and V4 terminals, and the value of CA2 is fixed with the result of actual LCD display evaluation.
,
In case of external power supply operation, the LCD driving voltages as VLCD, V1, V2, V3 and V4 should be
supplied from the external power supply in OFF state of internal power supply (DCON = AMPON = "0"). In this
mode, voltage booster terminals as C1+, C1-, C2+, C2-, C3+, C3-, C4+, C4-, C5+, C5-, VEE, VREF and VREG
should be opened.
In case of external power supply operation and a part of internal (Voltage converter), C1+, C1-, C2+, C2-,
C3+, C3-, C4+, C4-, C5+ and C5- terminals should be opened because the voltage booster circuit does not
operate, a power for the voltage converter circuit should supply into VOUT terminal, and a reference voltage is
supplied into VREF terminal.
In addition, a capacitor CA3 should connect into VREG terminal for stabilization.
< Bias adjustment function >
NJU6823 prepares bias adjustment terminals V1A1, V1A2, V4A1 and V4A2 for fine adjustment of V1 and V4
out of voltages.
The status combination of V1A1 terminal and V1A2 can adjust V1 voltage in below table and V4A1 and V4A2
can adjust V4 voltage. These adjustment performs by the connection change between the Bleeder resistors
and the output buffer operational amplifier as voltage follower circuit.
V1A1
V1A2
Fluctuation
V4A1
V4A2
Fluctuation
terminal
terminal
voltage [mV] *1
terminal
terminal
voltage [mV] *1
0
0
1
1
0
1
0
1
0
+5
-5
0
0
1
1
0
1
0
1
0
+5
-5
+10
-10
Note 1) The fluctuation voltage is a adjusted voltage against the default voltage at (V1A1, V1A2 = "0, 0" and
V4A1, V4A2 = "0, 0"). The "+" mark means a direction of voltage fluctuation to VLCD and the "-" is to VSS.
Note 2) The fluctuation voltage is an ideal value.
Note 3) The fluctuation voltage is at VLCD=13.5V.
Note 4) "0" of V1A1, V1A2, V4A1 and V4A2 means VSS and "1" means VDD
.
- 50 -
NJU6824
Capacitor connections for the voltage booster
All of the internal power supply circuits
(6-time boost)
None of the internal power supply circuits
VDD
VDD
VDD
VDD
VEE
VEE
VBA
VBA
VREF
VREF
VREG
CA3
VREG
CA3
VSS
VSS
C1-
C1-
C1+
C2-
C2+
C3-
C3+
C4-
C4+
C5-
C5+
CA1
C1+
C2-
CA1
C2+
C3-
CA1
C3+
C4-
NJU6824
NJU6824
CA1
C4+
C5-
CA1
C5+
VOUT
VOUT
CA1
VSS
VLCD
CA2
VLCD
V1
VLCD
V1
V1
CA2
External
V2
V2
V3
V4
V2
Power
circuit
CA2
V3
V3
CA2
V4
V4
CA2
VSS
Fig 10
Fig11
Reference values
CA1
CA2
CA3
1.0 to 4.7uF
1.0 to 2.2uF
0.1uF
Note) B grade capacitors are required.
- 51 -
NJU6824
The internal power supply circuits
The internal power supply circuit
Excluding the reference voltage generator(1)
(6-time boost)
Excluding the reference voltage generator(2)
(6-time boost, temperature compensation)
VDD
VDD
VDD
VDD
VEE
VBA
VREF
VEE
VBA
VREF
VREG
VREG
CA3
VSS
CA3
VSS
C1-
C1-
CA1
C1+
CA1
C1+
C2-
CA1
C2-
CA1
C2+
C2+
C3-
CA1
C3-
CA1
C3+
C3+
C4-
C4-
CA1
CA1
NJU6824
NJU6824
C4+
C4+
C5-
CA1
C5-
CA1
C5+
C5+
VOUT
VOUT
CA1
CA1
VSS
VSS
VLCD
CA2
VLCD
CA2
V1
V1
CA2
CA2
V2
V2
CA2
CA2
V3
V3
CA2
CA2
V4
V4
CA2
VSS
CA2
VSS
Fig 12
Fig 13
Reference value
CA1
CA2
CA3
1.0 to 4.7
1.0 to 2.2
µ
µ
F
F
0.1µF
Note) B grade capacitors are required.
- 52 -
NJU6824
The internal power supply circuits
Excluding the voltage booster
VDD
VDD
VEE
VBA
CA3
VREF
VREG
CA3
VSS
C1-
C1+
C2-
C2+
C3-
C3+
C4-
C4+
C5-
C5+
VSS
NJU6824
External
power
circuit
VOUT
VLCD
V1
CA2
CA2
V2
CA2
CA2
CA2
V3
V4
VSS
Fig 14
Reference value
CA1
CA2
CA3
1.0 to 4.7
1.0 to 2.2
µ
µ
F
F
0.1µF
Note) B grade capacitors are required.
- 53 -
NJU6824
(26) Partial display function
The partial display function is used to specify the partial display area on a LCD panel in the condition of lower
duty cycle ratio, lower LCD bias ratio, lower boost level and lower LCD driving voltage, so that it is possible to
display a time and calendar in the extremely low power consumption. It can be programmed to select a duty
cycle ratio (1/17, 1/25, 1/33, 1/41, 1/49, 1/57, 1/65, 1/73, 1/81, 1/89, 1/97, 1/105, 1/113, 1/121, 1/129, in case of
DSE=0), LCD bias ratio, boost level and EVR value by the instructions so that it is possible to optimize the LSI
condition in accordance with the display status.
Partial display image
NJRC
LCD DRIVER
Low Power and
Low Voltage
LCD DRIVER
Partial display
Normal display
Partial display sequence
Optional status
Display OFF (ON/OFF=”0”)
Internal Power supply OFF (DCON=”0”, AMPON=”0”)
WAIT
Setting for LCD driving voltage-related functions
Internal Power supply ON (DCON=”1”, AMPON=”1”)
- Boost level
- EVR value
- LCD bias ratio
WAIT
- Duty cycle ratio
- Initial display line
- Initial COM line
- Other instructions
Setting for display-related functions
Display ON (ON/OFF =”1”)
Partial display Status
- 54 -
NJU6824
(27) Discharge circuit
The discharge circuit is used to discharge the electric charge in the capacitors connected to the V1 to V4 and
VLCD terminals. It is activated by setting “0” into the “DIS” register in the “Discharge” instruction or by setting
“RES” terminal to ”0” level. The “Discharge ON/OFF” instruction is usually required just after the internal power
supply is turned off by setting “0” into the “DCON” and “AMPON” registers, or just after the external power
supply is turned off. During the discharge operation, it is required that no supply the power neither from an
internal or external power supply to the LSI.
(28) Reset circuit
The reset circuit initializes the LSI into the following default status. It is activated by setting the RES terminal
to “0” level. The RES terminal is usually required to connect to the MPU’s reset terminal in order that the LSI
can be initialized at the same timing of the MPU reset.
ꢀꢀ Default status
1. DDRAM display data
2. column address
:Undefined
:(00)H
3. row address
:(00)H
4. Initial display line
5. Display ON/OFF
6. Reverse display ON/OFF
7. Duty cycle ratio
8. N-line Inversion ON/OFF
9. COM scan direction
10. Address direction of RAM
11. Read modify write
12. SWAP mode
:(0)H (1st line)
:OFF
:OFF (normal)
:1/129 duty(DSE=0)
:OFF
:COM0
→ COM127
:(HV, XD, YD) = (0, 0, 0)
:OFF (AIM=0)
:OFF (normal)
:(0, 0, 0, 0, 0, 0, 0)
:OFF
13. EVR value
14. Internal power supply
15. Display mode
:Gradation display mode
:1/9 bias
16. LCD bias ratio
17. Gradation Palette 0
18. Gradation Palette 1
19. Gradation Palette 2
20. Gradation Palette 3
21. Gradation Palette 4
22. Gradation Palette 5
23. Gradation Palette 6
24. Gradation Palette 7
25. Gradation Palette 8
26. Gradation Palette 9
27. Gradation Palette 10
28. Gradation Palette 11
29. Gradation Palette 12
30. Gradation Palette 13
31. Gradation Palette 14
32. Gradation Palette 15
33. Gradation mode control
34. Data bus length
:(0, 0, 0, 0, 0)
:(0, 0, 0, 1, 1)
:(0, 0, 1, 0, 1)
:(0, 0, 1, 1, 1)
:(0, 1, 0, 0, 1)
:(0, 1, 0, 1, 1)
:(0, 1, 1, 0, 1)
:(0, 1, 1, 1, 1)
:(1, 0, 0, 0, 1)
:(1, 0, 0, 1, 1)
:(1, 0, 1, 0, 1)
:(1, 0, 1, 1, 1)
:(1, 1, 0, 0, 1)
:(1, 1, 0, 1, 1)
:(1, 1, 1, 0, 1)
:(1, 1, 1, 1, 1)
:Variable gradation mode
:8-bit data bus length
:OFF
35. Discharge circuit
- 55 -
NJU6824
(29) Power supply ON/OFF sequences
The following paragraphs describes the power supply ON/OFF sequences to prevent high current flowing into
the LSI, otherwise the current may cause a permanent damage to the LSI.
(29-1)Using an external power supply
ꢁ
ꢁ
Power supply ON sequence
The logic voltage (VDD) is turned on first, and then the LCD driving voltages (V1 to V4 and VLCD) can
be turned on. When supply the VOUT from outside, turn on the logic voltage (VDD), then reset, after
then supply the VOUT is required.
Power supply OFF sequence
The reset operation, cut off the V1 to V4 and VLCD from the LSI by the RES terminal or the “Power
control” instruction first, and then the VDD can be turned off. It is recommended that a series-resister
between 50 ohms and 100 ohms is inserted in the VLCD line (or VOUT line in case of using only an
external VOUT voltage) in order to protect the LSI from an over current.
(29-2)Using the internal power supply circuits
ꢁ
Power supply ON sequence
The VDD is turned on and the reset operation is required first, and then the V1 to V4 and VLCD can be
turned on by setting “1” into the “DCON” and “AMPON” registers in the “Power control” instruction.
ꢁ
Power supply OFF sequence
The reset operation is required first in order to cut off the V1 to V4 and VLCD from the LSI, and then
the input voltage for the voltage booster (VEE) and the VDD can be turned off.
In case that the VEE and VDD are supplied from deferent voltage sources, the VEE is required to be
turned off first, and then the VDD can be turned off.
- 56 -
NJU6824
(30) Referential instruction sequences
(30-1)Initialization in using the internal power supply circuits
VDD, VEE power ON
Wait for power-ON stabilization
RESET Input
WAIT
Setting for LCD driving voltage-related functions
End of initialization
- EVR value
- LCD bias ratio
- Power control (DCON=”1”, AMPON=”1”)
(30-2)Display data writing
End of Initialization
Setting for display-related functions
- Initial display line
- Address direction of RAM (HV, XD, YD)
- Column address / -Row address (Start)
- Column address / -Row address (End)
Display data write
Display ON (ON/OFF =”1”)
*: Before display data write / read operation, the address directions should be set first , then Column
address set / Row address set of start point and end are set in order. (Display data write / read for whole
display area or a portion requires the same procedure as above.)
To avoid incorrect data writing into registers by noise and so forth, the written data from registers should
be checked after write operation.
- 57 -
NJU6824
(30-3)Power OFF
Optional status
- All COM/SEG output VSS level.
Power save or reset operation
Discharge ON
WAIT
VEE, VDD power OFF
- 58 -
NJU6824
(31) Instruction table
Instruction Table (1)
Code (80 series MPU I/F)
Code
Functions
Instructions
CS RS RD WR RE2 RE1 RE0 D7 D6 D5 D4 D3
D2
D1
D0
Display data write
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0/1 0/1 0/1
0/1 0/1 0/1
Write Data
Read Data
Write display data to DDRAM
Display data read
column address
Read display data from DDRAM
DDRAM column address
DDRAM column address
DDRAM row address
AX3
AX7
AY3
*
AX2
AX6
AY2
AY6
LA2
LA6
N2
AX1
AX5
AY1
AY5
LA1
LA5
N1
AX0
AX4
AY0
AY4
LA0
LA4
N0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
(Lower) [0H]
column address
(Upper) [1H]
row address
(Lower) [2H]
row address
(Upper) [3H]
DDRAM row address
Initial display line
(Lower) [4H]
Sets row address corresponding to
initial COM line (scan-starting line)
LA3
*
Initial display line
(Upper) [5H]
Sets row address corresponding to
initial COM line (scan-starting line)
N-line inversion
(Lower) [6H]
N3
*
Sets the number of N-line inversion
N-line inversion
(Upper) [7H]
N6
N5
N4
Sets the number of N-line inversion
SHIFT: Common direction
Display control (1)
Display control (2)
Increment control
ALL
ON
ON/ MON: Gradation or B/W display mode
SHIFT MON
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
0
1
0
OFF
ALLON: All pixels ON/OFF
ON/OFF: Display ON/OFF
[8H]
[9H]
[AH]
REV: Reverse display ON/OFF
NLIN: N-line inversion ON/OFF,
SWAP: SWAP mode ON/OFF
REV NLIN SWAP
*
AIM: Read-modify-write ON/OFF
HV: Increment / Decrement direction
XD: Column Increment / Decrement set
YD: Row Increment / Decrement set
AMPON: Voltage followers ON/OFF
HALT: Power save ON/OFF
AIM
HV
XD
YD
Power control
AMP
ON
DC
ON
HALT
ACL
0
1
1
0
0
0
0
1
0
1
1
DCON: Voltage booster ON/OFF
ACL: Reset
[BH]
Duty cycle ratio
Boost level
DS3 DS2 DS1 DS0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
Sets LCD duty cycle ratio
Sets boost level
[CH]
[DH]
[EH]
[FH]
VU2 VU1 VU0
*
*
LCD bias ratio
RE register
B2
B1
B0
Sets LCD bias ratio
RE flag set
TST0 RE2 RE1 RE0
0/1 0/1 0/1
Note 1)
Note 2) [ ]
Note 3)
*
: Don’t care.
: Instruction register address
The dual instructions including upper and lower bytes is enabled after either upper or lower
bytes are set into the register. The only “EVR control” instruction is enabled after both of the
upper and lower bytes are set.
- 59 -
NJU6824
Instruction Table (2)
Instructions
Code (80 series MPU I/F)
Code
Functions
CS RS RD WR RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 D0
Gradation palette A0/A8
(Lower) [0H]
Sets palette values to gradation
palette A0(PS=0)/A8(PS=1)
PA03/ PA02/ PA01/ PA00/
PA83 PA82 PA81 PA80
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
Gradation palette A0/A8
(Upper) [1H]
Sets palette values to gradation
palette A0(PS=0)/A8(PS=1)
PA04/
PA84
*
*
*
Gradation palette A1/A9
(Lower) [2H]
Sets palette values to gradation
palette A1(PS=0)/A9(PS=1)
PA13/ PA12/ PA11/ PA10/
PA93 PA92 PA91 PA90
Gradation palette A1/A9
(Upper) [3H]
Sets palette values to gradation
palette A1(PS=0)/A9(PS=1)
PA14/
PA94
*
*
*
Gradation palette A2/A10
(Lower) [4H]
Sets palette values to gradation
palette A2(PS=0)/A10(PS=1)
PA23/ PA22/ PA21/ PA20/
PA103 PA102 PA101 PA100
Gradation palette A2/A10
(Upper) [5H]
Sets palette values to gradation
palette A2(PS=0)/A10(PS=1)
PA24/
PA104
*
*
*
Gradation palette A3/A11
(Lower) [6H]
Sets palette values to gradation
palette A3(PS=0)/A11(PS=1)
PA33/ PA32/ PA31/ PA30/
PA113 PA112 PA111 PA110
Gradation palette A3/A11
(Upper) [7H]
Sets palette values to gradation
palette A3(PS=0)/A11(PS=1)
PA34/
PA114
*
*
*
Gradation palette A4/A12
(Lower) [8H]
Sets palette values to gradation
palette A4(PS=0)/A12(PS=1)
PA43/ PA42/ PA41/ PA40/
PA123 PA122 PA121 PA120
Gradation palette A4/A12
(Upper) [9H]
Sets palette values to gradation
palette A4(PS=0)/A12(PS=1)
PA44/
PA124
*
*
*
Gradation palette A5/A13
(Lower) [AH]
Sets palette values to gradation
palette A5(PS=0)/A13(PS=1)
PA53/ PA52/ PA51/ PA50/
PA133 PA132 PA131 PA130
Gradation palette A5/A13
(Upper) [BH]
Sets palette values to gradation
palette A5(PS=0)/A13(PS=1)
PA54/
PA134
*
*
*
Gradation palette A6/A14
(Lower) [CH]
Sets palette values to gradation
palette A6(PS=0)/A14(PS=1)
PA63/ PA62/ PA61/ PA60/
PA143 PA142 PA141 PA140
Gradation palette A6/A14
(Upper) [DH]
Sets palette values to gradation
palette A6(PS=0)/A14(PS=1)
PA64/
PA144
*
*
*
RE register
[FH]
TST0 RE2 RE1 RE0
0/1 0/1 0/1
RE flag set
Note 1)
Note 2) [ ]
Note 3)
*
: Don’t care.
: Instruction register address
The dual instructions including upper and lower bytes is enabled after either upper or lower
bytes are set into the register. The only “EVR control” instruction is enabled after both of the
upper and lower bytes are set.
- 60 -
NJU6824
Instruction Table (3)
Code (80 series MPU I/F)
Code
Instructions
Functions
CS RS RD WR RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 D0
Gradation palette A7/A15
(Lower) [0H]
Sets palette values to gradation
palette A7(PS=0)/A15(PS=1)
PA73/ PA72/ PA71/ PA70/
PA153 PA152 PA151 PA150
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
Gradation palette A7/A15
(Upper) [1H]
Sets palette values to gradation
palette A7(PS=0)/A15(PS=1)
PA74/
PA154
*
*
*
Gradation palette B0/B8
(Lower) [2H]
Sets palette values to gradation
palette B0(PS=0)/B8(PS=1)
PB03/ PB02/ PB01/ PB00/
PB83 PB82 PB81 PB80
Gradation palette B0/B8
(Upper) [3H]
Sets palette values to gradation
palette B0(PS=0)/B8(PS=1)
PB04/
PB84
*
*
*
Gradation palette B1/B9
(Lower) [4H]
Sets palette values to gradation
palette B1(PS=0)/B9(PS=1)
PB13/ PB12/ PB11/ PB10/
PB93 PB92 PB91 PB90
Gradation palette B1/B9
(Upper) [5H]
Sets palette values to gradation
palette B1(PS=0)/B9(PS=1)
PB14/
PB94
*
*
*
Gradation palette B2/B10
(Lower) [6H]
Sets palette values to gradation
palette B2(PS=0)/B10(PS=1)
PB23/ PB22/ PB21/ PB20/
PB103 PB102 PB101 PB100
Gradation palette B2/B10
(Upper) [7H]
Sets palette values to gradation
palette B2(PS=0)/B10(PS=1)
PB24/
PB104
*
*
*
Gradation palette B3/B11
(Lower) [8H]
Sets palette values to gradation
palette B3(PS=0)/B11(PS=1)
PB33/ PB32/ PB31/ PB30/
PB113 PB112 PB111 PB110
Gradation palette B3/B11
(Upper) [9H]
Sets palette values to gradation
palette B3(PS=0)/B11(PS=1)
PB34/
PB114
*
*
*
Gradation palette B4/B12
(Lower) [AH]
Sets palette values to gradation
palette B4(PS=0)/B12(PS=1)
PB43/ PB42/ PB41/ PB40/
PB123 PB122 PB121 PB120
Gradation palette B4/B12
(Upper) [BH]
Sets palette values to gradation
palette B4(PS=0)/B12(PS=1)
PB44/
PB124
*
*
*
Gradation palette B5/B13
(Lower) [CH]
Sets palette values to gradation
palette B5(PS=0)/B13(PS=1)
PB53/ PB52/ PB51/ PB50/
PB133 PB132 PB131 PB130
Gradation palette B5/B13
(Upper) [DH]
Sets palette values to gradation
palette B5(PS=0)/B13(PS=1)
PB54/
PB134
*
*
*
RE register
[FH]
TST0 RE2 RE1 RE0
0/1 0/1 0/1
RE flag set
Note 1)
Note 2) [ ]
Note 3)
*
: Don’t care.
: Instruction register address
The dual instructions including upper and lower bytes is enabled after either upper or lower
bytes are set into the register. The only “EVR control” instruction is enabled after both of the
upper and lower bytes are set.
- 61 -
NJU6824
Instruction Table (4)
Instructions
Code (80 series MPU I/F)
Code
Functions
CS RS RD WR RE2 RE1 RE0 D7
D6
0
D5
0
D4
D3 D2
D1 D0
Gradation palette B6/B14
(Lower) [0H]
Sets palette values to gradation
palette B6(PS=0)/B14(PS=1)
PB63/ PB62/ PB61/ PB60/
PB143 PB142 PB141 PB140
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
Gradation palette B6/B14
(Upper) [1H]
Sets palette values to gradation
palette B6(PS=0)/B14(PS=1)
PB64/
PB144
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
*
*
*
Gradation palette B7/B15
(Lower) [2H]
Sets palette values to gradation
palette B7(PS=0)/B15(PS=1)
PB73/ PB72/ PB71/ PB70/
PB153 PB152 PB151 PB150
Gradation palette B7/B15
(Upper) [3H]
Sets palette values to gradation
palette B7(PS=0)/B15(PS=1)
PB74/
PB154
*
*
*
Gradation palette C0/C8
(Lower) [4H]
Sets palette values to gradation
palette C0(PS=0)/C8(PS=1)
PC03/ PC02/ PC01/ PC00/
PC83 PC82 PC81 PC80
Gradation palette C0/C8
(Upper) [5H]
Sets palette values to gradation
palette C0(PS=0)/C8(PS=1)
PC04/
PC84
*
*
*
Gradation palette C1/C9
(Lower) [6H]
Sets palette values to gradation
palette C1(PS=0)/C9(PS=1)
PC13/ PC12/ PC11/ PC10/
PC93 PC92 PC91 PC90
Gradation palette C1/C9
(Upper) [7H]
Sets palette values to gradation
palette C1(PS=0)/C9(PS=1)
PC14/
PC94
*
*
*
Gradation palette C2/C10
(Lower) [8H]
Sets palette values to gradation
palette C2(PS=0)/C10(PS=1)
PC23/ PC22/ PC21/ PC20/
PC103 PC102 PC101 PC100
Gradation palette C2/C10
(Upper) [9H]
Sets palette values to gradation
palette C2(PS=0)/C10(PS=1)
PC24/
PC104
*
*
*
Gradation palette C3/C11
(Lower) [AH]
Sets palette values to gradation
palette C3(PS=0)/C11(PS=1)
PC33/ PC32/ PC31/ PC30/
PC113 PC112 PC111 PC110
Gradation palette C3/C11
(Upper) [BH]
Sets palette values to gradation
palette C3(PS=0)/C11(PS=1)
PC34/
PC114
*
*
*
Gradation palette C4/C12
(Lower) [CH]
Sets palette values to gradation
palette C4(PS=0)/C12(PS=1)
PC43/ PC42/ PC41/ PC40/
PC123 PC122 PC121 PC120
Gradation palette C4/C12
(Upper) [DH]
Sets palette values to gradation
palette C4(PS=0)/C12(PS=1)
PC44/
PC124
*
*
*
RE register
[FH]
TST0 RE2 RE1 RE0
0/1 0/1 0/1
RE flag set
Note 1)
Note 2) [ ]
Note 3)
*
: Don’t care.
: Instruction register address
The dual instructions including upper and lower bytes is enabled after either upper or lower
bytes are set into the register. The only “EVR control” instruction is enabled after both of the
upper and lower bytes are set.
- 62 -
NJU6824
Instruction Table (5)
Code (80 series MPU I/F)
Code
Instructions
Functions
CS RS RD WR RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 D0
Gradation palette C5/C13
(Lower) [0H]
Sets palette values to gradation
palette C5(PS=0)/C13(PS=1)
PC53/ PC52/ PC51/ PC50/
PC133 PC132 PC131 PC130
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
*
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
*
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
0
*
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
*
Gradation palette C5/C13
(Upper) [1H]
Sets palette values to gradation
palette C5(PS=0)/C13(PS=1)
PC54/
PC134
*
*
*
Gradation palette C6/C14
(Lower) [2H]
Sets palette values to gradation
palette C6(PS=0)/C14(PS=1)
PC63/P PC62/ PC61/ PC60/
C143 PC142 PC141 PC140
Gradation palette C6/C14
(Upper) [3H]
Sets palette values to gradation
palette C6(PS=0)/C14(PS=1)
PC64/
PC154
*
*
*
Gradation palette C7/C15
(Lower) [4H]
Sets palette values to gradation
palette C7(PS=0)/C15(PS=1)
PC73/ PC72/ PC71/ PC70/
PC153 PC152 PC151 PC150
Gradation palette C7/C15
(Upper) [5H]
Sets palette values to gradation
palette C7(PS=0)/C15(PS=1)
PC74/
PC154
*
*
*
Initial COM line
[6H]
SC3 SC2 SC1 SC0
Sets scan-starting common driver
Display control Signal/
Duty Select
[7H]
SON : CL, FLM, FR, CLK signal
DSE : Duty select
SON
DSE
*
*
PWM : Variable 16 Gradation Mode
Stability 8 Gradation Mode
C256 : 256 Color Mode
Gradation mode control
[8H]
PWM C256 FDC1 FDC2
FDC : Boost Clock
ABS : 12bits RAM Data Select
ABS CKS WLS CKS : OSC Select
Data bus length
[9H]
*
WLS : Data Length at Data Access
EVR control
Sets EVR level
(Lower bit)
DV3 DV2 DV1 DV0
(Lower) [AH]
EVR control
Sets EVR level
(Upper bit)
DV6 DV5 DV4
RF2 RF1 RF0
*
*
*
(Upper) [BH]
Frequency control
[DH]
Controls oscillation frequency
Discharge ON/OFF
[EH]
Discharge the electric charge in
capacitors on V1 to V4 and VLCD
DIS
DIS2
*
RE register
[FH]
TST0 RE2 RE1 RE0
Reading register address
Read Data
0/1 0/1 0/1
RE flag
Instruction register address
[CH]
1
0
0
Sets instruction register address
Read out instruction register data
Instruction register read
0/1 0/1 0/1
Note 1)
Note 2) [ ]
Note 3)
*
: Don’t care.
: Instruction register address
The dual instructions including upper and lower bytes is enabled after either upper or lower
bytes are set into the register. The only “EVR control” instruction is enabled after both of the
upper and lower bytes are set.
Note 4)
CKS=0: Internal oscillation mode (default)
CKS=1: External oscillation mode
- 63 -
NJU6824
Instruction Table (6)
Instructions
Code (80 series MPU I/F)
Code
Functions
CS RS RD WR RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 D0
Window end
column address
(Lower) [0H]
Window end
column address
(Upper) [1H]
EX3 EX2 EX1 EX0
EX7 EX6 EX5 EX4
EY3 EY2 EY1 EY0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Sets column address for end point
Sets column address for end point
Sets row address for end point
Sets row address for end point
Sets address for reverse line
Sets address for reverse line
Sets address for reverse line
Sets address for reverse line
Window end row address
(Lower) [2H]
Window end row address
(Upper) [3H]
*
EY6 EY5 EY4
Initial reverse line
(Lower) [4H]
LS3 LS2 LS1 LS0
Initial reverse line
(Upper) [5H]
*
LS6 LS5 LS4
Last reverse line
(Lower) [6H]
LE3 LE2 LE1 LE0
Last reverse line
(Upper) [7H]
*
LE6 LE5 LE4
Reverse line display
ON/OFF
BT : Blink type setting
LREV : Reverse line display ON/OFF
BT LREV
*
*
*
[8H]
Gradation palette setting
control
address
[9H]
/
Icon SEG
set
PS : gradation setting
DMY : Icon SEG address set
PS
DMY
0
1
1
0
1
1
0
0
1
1
1
0
0
1
*
PWM control
PWM PWM PWM PWM
0
0
1
1
1
1
0
0
1
1
0
1
1
1
0
1
Sets PWM mode
RE flag
S
A
B
C
[AH]
[FH]
RE register
TST0 RE2 RE1 RE0
0/1 0/1 0/1
Note 1)
Note 2) [ ]
Note 3)
*
: Don’t care.
: Instruction register address
The dual instructions including upper and lower bytes is enabled after either upper or lower
bytes are set into the register. The only “EVR control” instruction is enabled after both of the
upper and lower bytes are set.
- 64 -
NJU6824
(32) Instruction descriptions
This chapter provides detail description of the instructions, registers, their settings and programming
examples. The non-existent instruction codes in the instruction tables (1), (2)…(6) are required not to be
programmed.
(32-1)Display data write
The “Display data write” instruction is used to write 8-bit display data into the DDRAM.
CS
0
RS
0
RD WR RE2 RE1 RE0
0/1 0/1 0/1
D7
D6
D5
D4
D3
D2
D1
D0
1
0
Display data
(32-2)Display data read
The “Display data read” instruction is used to read out 8-bit display data from the DDRAM, where the
column address and row address are required to be specified beforehand by the “column address” and
“row address” instructions. The dummy read is required just after the “column address” and “row address”
instructions.
CS
0
RS
0
RD WR RE2 RE1 RE0
0/1 0/1 0/1
D7
D6
D5
D4
D3
D2
D1
D0
0
1
Display data
(32-3)Column address
The “column address” instruction is used to specify the column address for the display data read and
write operations. It includes dual instructions for lower 4-bit and upper 4-bit data. The instruction for the
lower 4-bit data is required to be executed first.
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
D0
1
0
0
0
0
AX3 AX2 AX1 AX0
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
1
D3
D2
D1
D0
1
0
0
0
0
AX7 AX6 AX5 AX4
(32-4)Row address
The “row address” instruction is used to specify the row address for the display data read and write
operations. It includes dual instructions for lower 4-bit and upper 3-bit data. The instruction for the lower 4-
bit data is required to be executed first.
The row address can be specified in between 00H and 7FH. The setting for the non-existence row
address between 80H and FFH is prohibited.
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
0
D3
D2
D1
D0
1
0
0
0
0
AY3
AY2
AY1 AY0
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
1
D3
*
D2
D1
D0
1
0
0
0
0
AY6
AY5 AY4
- 65 -
NJU6824
(32-5) Initial display line
The “Initial display line” instruction is used to specify the line address corresponding to the initial COM
line. The initial COM line indicates the common driver that starts scanning the display data, which is
specified by the “Initial COM line” instruction.
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
0
D3
D2
D1
D0
1
0
0
0
0
LA3
LA2
LA1 LA0
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
1
D3
*
D2
D1
D0
1
0
0
0
0
LA6
LA5 LA4
LA6
0
LA5
LA4
0
LA3
0
LA2
LA1
0
LA0
Line address
0
0
0
0
0
1
0
1
0
0
0
0
:
:
:
:
1
1
1
1
1
1
1
127
(32-6)N-line inversion
The “N-line inversion” instruction is used to control the alternate rates of the liquid crystal direction. It is
programmed to select the N value between 2 and 128, so that the FR signal toggles once every N frames
by setting “1” into the “NLIN” register in the “Display control (2)” instruction. In case that the N-line
inversion is disabled by setting “0” into “NLIN” register, the FR signal toggles by the frame.
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
0
D3
D2
D1
D0
1
0
0
0
0
N3
N2
N1
N0
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
1
D3
*
D2
D1
D0
1
0
0
0
0
N6
N5
N4
N6
N5
0
N4
0
N3
N2
0
N1
N0
0
N value
Inhibited
2
0
0
0
0
0
0
0
0
0
1
:
:
:
:
0
1
0
0
0
0
0
128
- 66 -
NJU6824
ꢁ
N-line Inversion Timing (1/129 duty cycle ratio)
N-line inversion OFF
1st line
3rd line
128th line
1st line
2nd line
129th line
CL
FLM
FR
N-line inversion ON
N-line control
1st line
3rd line
N line
2nd line
2nd line
1st line
CL
FR
(32-7)Display control (1)
The “Display control (1)” instruction is used to control the display conditions for the “Display ON/OFF”,
“All pixels ON/OFF”, Display mode” and “Common direction” registers.
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
0
D3
D2
D1
D0
SHIFT
MON
ALLON ON/OFF
1
0
0
0
0
ꢁ
ꢁ
ON/OFF register
ON/OFF=0 : Display OFF (All COM/SEG output Vss level.)
ON/OFF=1 : Display ON
All ON register
The “All pixels ON/OFF” register is used to turn on all pixels without changing the display data in the
DDRAM. The setting for the “All pixels ON/OFF” register has a priority over the “Reverse display
ON/OFF” register.
ALLON=0
ALLON=1
: Normal
: All pixels turn on.
ꢁ
ꢁ
MON register
MON=0
MON=1
: Gradation mode
: B&W mode
SHIFT register
SHIFT=0
SHIFT=1
: COM0
: COM127
→
→
COM127
COM0
- 67 -
NJU6824
(32-8)Display control (2)
The “Display control (2)” instruction is used to control the display conditions for the “SWAP mode
ON/OFF”, “N-line inversion ON/OFF” and “Reverse display ON/OFF”.
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
1
D3
D2
D1
D0
REV
NLIN
SWAP
*
1
0
0
0
0
ꢁ
SWAP register
The “SWAP” register is used to reverse the arrangement for the display data in the DDRAM.
SWAP=0
SWAP=1
: SWAP mode OFF
: SWAP mode ON
(Normal)
SWAP=”0”
SWAP=”1”
Write data
D7 D6 D5 D4 D3 D2 D1 D0
D7 d6 d5 d4 d3 d2 d1 d0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
RAM data
d0 d1 d2 d3 d4 d5 d6 d7
D7 D6 D5 D4 D3 D2 D1 D0
Read data
ꢁ
ꢁ
NLIN register
The “NLIN” is used to enable or disable the N-line inversion.
NLIN=0
NLIN=1
: N-line inversion OFF
: N-line inversion ON
(The FR signal toggles by the flame.)
(The FR signal toggles once every N frames.)
REV register
The “REV” register is used to enable or disable the reverse display mode that reverses the polarity
of the display data without changing the display data in the DDRAM.
REV=0
REV=1
: Reverse display mode OFF
: Reverse display mode ON
REV
Display
Normal
DDRAM data
→
Display data
0
1
0
1
0
1
1
0
0
1
Reverse
- 68 -
NJU6824
(32-9)Increment control
The “Increment control” instruction is used to control the conditions for the increment mode. In the auto-
increment mode, the DDRAM address is automatically incremented (+1) whenever the DDRAM is
accessed by the “Display data write” and “Display data read” instructions, so that it is possible to
continuously access to the DDRAM without executing the “column address” and “row address” instructions
after each “Display data write” or “Display data read” instruction. The settings for the “AIM”, “HV”, “XD” and
“YD” registers are listed in the following tables.
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
0
D3
D2
D1
D0
1
0
0
0
0
AIM HV
XD
YD
ꢁ
AIM, HV, XD and YD registers
AIM
Increment mode
Note
Auto-increment for both of the display data read and write operations
Auto-increment for the display write operation (Read modify write)
0
1
1
2
Note 1) It is valid during continuing to write or read serial address area.
Note 2) It is valid at writing modified data that read, write, and read every address.
HV
0
0
0
0
1
1
1
1
XD
0
0
1
1
0
0
1
1
YD
0
1
0
1
0
1
0
1
Increment / Decrement mode / Scanning Direction
Column increment / Row increment / Horizontal direction
Column increment / Row decrement / Horizontal direction
Column decrement / Row increment / Horizontal direction
Column decrement / Row decrement / Horizontal direction
Column increment / Row increment / Vertical direction
Column increment / Row decrement / Vertical direction
Column decrement / Row increment / Vertical direction
Column decrement / Row decrement / Vertical direction
For the window area designation, the address directions of RAM (HV, XD, YD) must be set first, and
Column address and Row of Start point must be set second, Column address and Row of Stop point must
be set third, then RAM should be accessed. Low address must be set first and High address must be set
second in all of addresses. The directions of HV, XD, YD should be check to keep the area in RAM.
- 69 -
NJU6824
(32-10)Power control
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
1
D3
D2
D1
D0
AMPON HALT DCON
ACL
1
0
0
0
0
ꢁ
ACL register
The “ACL” register is used to initialize the internal power supply circuits. It is available only in the
master mode.
ACL=0
ACL=1
: Initialization OFF (Normal)
: Initialization ON
When the data in the “ACL register” is read out by the “Instruction register read” instruction, the
read-out data is “1” during the initialization and “0” after the initialization. This initialization is
performed using the internal reset signal produced by 2 clocks on the OSC1. For this reason, the wait
time for 2 clocks on the OSC1 is required until the next instruction after the initialization by
programming “ACL” register.
ꢁ
ꢁ
DCON register
The “DCON” register is used to enable or disable the voltage booster.
DCON=0
DCON=1
: Voltage booster OFF
: Voltage booster ON
HALT register
The “HALT” register is used to enable or disable the power save mode. It is possible to reduce the
operating current down to the stand-by level in the power save mode. The internal status in the power
save mode is listed below.
HALT=0
HALT=1
: Power save OFF (Normal)
: Power save ON
Internal status in the power save mode
•
•
•
•
•
•
The oscillation circuits and internal power supply circuits are halted.
All segment and common drivers output VSS level.
The display data in the DDRAM is maintained.
The operational modes before the power save mode are maintained.
The V1 to V4 and VLCD are in the high impedance.
The clock input into the OSC1 is inhibited.
In the power save ON sequence, it is required that the “Display OFF” instruction is executed before
the “Power save ON” instruction, so that all common and segment drivers output VSS level. And in the
power save OFF sequence, it is required that the “Power save OFF” instruction is executed first and
then the “Display ON” instruction is executed. If the “Power save OFF” instruction is executed in the
display ON status, unexpected pixels may be instantly turned on.
ꢁ
AMPON register
The “AMPON” register is used to enable or disable the voltage followers, voltage regulator and EVR.
AMPON=0 : The voltage followers, voltage regulator and EVR OFF
AMPON=1 : The voltage followers, voltage regulator and EVR ON
- 70 -
NJU6824
(32-11)Duty cycle ratio
The “Duty cycle ratio” instruction is used to select the LCD duty cycle ratio for the partial display function.
The partial display function specifies the partial display area on a LCD panel in the condition of lower duty
cycle ratio, lower LCD bias ratio, lower boost level and lower LCD driving voltage, so that it is possible to
display a time and calendar in the extremely low power consumption.
It can be also programmed to select not only the duty cycle ratio but also the LCD bias ratio, boost level
and EVR value by the instructions so that it is possible to optimize the LSI conditions in accordance with
the display.
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
0
D3
D2
D1
D0
1
0
0
0
0
DS3 DS2 DS1 DS0
DS3
0
0
0
0
0
0
0
0
DS2
0
0
0
0
1
1
1
1
DS1
DS0
0
1
0
1
0
1
0
1
Duty cycle ratio
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Row way 128 dots display, 1/129 Duty
Row way 120 dots display, 1/121 Duty
Row way 112 dots display, 1/113 Duty
Row way 104 dots display, 1/105 Duty
Row way 96 dots display, 1/97 Duty
Row way 88 dots display, 1/89 Duty
Row way 80 dots display, 1/81 Duty
Row way 72 dots display, 1/73 Duty
Row way 64 dots display, 1/75 Duty
Row way 56 dots display, 1/57 Duty
Row way 48 dots display, 1/49 Duty
Row way 40 dots display, 1/41 Duty
Row way 32 dots display, 1/33 Duty
Row way 24 dots display, 1/25 Duty
Row way 16 dots display, 1/17 Duty
Inhibited
1
1
0
0
0
1
1
1
1
1
1
1
0
0
1
1
1
1
0
1
0
1
0
1
All of duty value are decreased “1” by Duty selection set (DSE=1).
Ex.) In case of (DS3,DS2,DS1,DS0)=(0,0,0,0)
DSE=”0”
DSE=”1”
:1/129Duty
:1/128Duty
In period of last Common driving, all of Commons are not selected and Segment outputs are not change from
previous condition.
Ex.) Conditions of Commons and segments at 129th line in case of 1/129 duty
COM output : All of Commons are not selected
SEG output : Not change from previous condition (same 128 line).
(32-12)Boost level
The “Boost level” is used to select the multiple for the voltage booster for the partial display function.
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
1
D3
*
D2
D1
D0
1
0
0
0
0
VU2 VU1 VU0
VU2
0
0
VU1
0
0
VU0
0
1
Boost level
1-time (No boost)
2-time
0
1
0
3-time
0
1
1
4-time
1
0
0
5-time
1
0
1
6-time
1
1
1
1
0
1
Inhibited
Inhibited
- 71 -
NJU6824
(32-13)LCD bias ratio
The “LCD bias ratio” is used to select the LCD bias ratio for the partial display function.
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
1
D5
1
D4
0
D3
*
D2
B2
D1
B1
D0
B0
1
0
0
0
0
B2
0
0
0
0
1
1
1
1
B1
0
0
1
1
0
0
1
1
B0
0
1
0
1
0
1
0
1
LCD bias ratio
1/9
1/8
1/7
1/6
1/5
1/10
1/11
1/12
(32-14)RE flag
The “RE flag” registers are used to determine the contents for the RE registers (RE2, RE1 and RE0) in
order that it is possible to access to the instruction registers.
The data in the “TST0” register must be “0”, which is used only for maker tests.
CS
0
RS
1
RD WR RE2 RE1 RE0
0/1 0/1 0/1
D7
1
D6
1
D5
1
D4
1
D3
D2
D1
D0
1
0
TST0 RE2 RE1 RE0
- 72 -
NJU6824
(32-15)Gradation palette A, B and C
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
D0
PA03
PA83
/
PA02
PA82
/
PA01
PA81
/
PA00/
PA80
1
0
0
0
1
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PA04
PA84
/
1
0
0
0
1
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
0
D3
D2
D1
D0
PA13
PA93
/
PA12
PA92
/
PA11/ PA10/
PA91
1
0
0
0
1
PA90
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
1
D3
*
D2
*
D1
*
D0
PA14
PA94
/
1
0
0
0
1
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
0
D3
D2
D1
D0
PA23
/
PA22
/
PA21
/
PA20/
1
0
0
0
1
PA103 PA102 PA101 PA100
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PA24
PA104
/
1
0
0
0
1
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
0
D3
D2
D1
D0
PA33
/
PA32
/
PA31
/
PA30/
1
0
0
0
1
PA113 PA112 PA111 PA110
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
1
D3
*
D2
*
D1
*
D0
PA34
PA114
/
1
0
0
0
1
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
0
D3
D2
D1
D0
PA43
/
PA42
/
PA41
/
PA40/
1
0
0
0
1
PA123 PA122 PA121 PA120
- 73 -
NJU6824
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PA44
PA124
/
1
0
0
0
1
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
0
D3
D2
D1
D0
PA53
/
PA52
/
PA51
/
PA50/
1
0
0
0
1
PA133 PA132 PA131 PA130
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
1
D3
*
D2
*
D1
*
D0
PA54
PA134
/
1
0
0
0
1
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
0
D3
D2
D1
D0
PA63
/
PA62
/
PA61
/
PA60/
1
0
0
0
1
PA143 PA142 PA141 PA140
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PA64
PA144
/
1
0
0
0
1
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
D0
PA73
/
PA72
/
PA71
/
PA70/
1
0
0
1
0
PA153 PA152 PA151 PA150
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PA74
PA154
/
1
0
0
1
0
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
0
D3
D2
D1
D0
PB03
PB83
/
PB02
PB82
/
PB01
PB81
/
PB00/
PB80
1
0
0
1
0
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
1
D3
*
D2
*
D1
*
D0
PB04
PB84
/
1
0
0
1
0
- 74 -
NJU6824
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
0
D3
D2
D1
D0
PB13
PB93
/
PB12
PB92
/
PB11/ PB10/
PB91
1
0
0
1
0
PB90
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PB14
PB94
/
1
0
0
1
0
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
0
D3
D2
D1
D0
PB23
/
PB22
/
PB21
/
PB20/
1
0
0
1
0
PB103 PB102 PB101 PB100
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
1
D3
*
D2
*
D1
*
D0
PB24
PB104
/
1
0
0
1
0
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
0
D3
D2
D1
D0
PB33
/
PB32
/
PB31
/
PB30/
1
0
0
1
0
PB113 PB112 PB111 PB110
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PB34
PB114
/
1
0
0
1
0
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
0
D3
D2
D1
D0
PB43
/
PB42
/
PB41
/
PB40/
1
0
0
1
0
PB123 PB122 PB121 PB120
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
1
D3
*
D2
*
D1
*
D0
PB44
PB124
/
1
0
0
1
0
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
0
D3
D2
D1
D0
PB53
/
PB52
/
PB51
/
PB50/
1
0
0
1
0
PB133 PB132 PB131 PB130
- 75 -
NJU6824
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PB54
PB134
/
1
0
0
1
0
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
D0
PB63
/
PB62
/
PB61
/
PB60/
1
0
0
1
1
PB143 PB142 PB141 PB140
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PB64
PB144
/
1
0
0
1
1
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
0
D3
D2
D1
D0
PB73
/
PB72
/
PB71
/
PB70/
1
0
0
1
1
PB153 PB152 PB151 PB150
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
1
D3
*
D2
*
D1
*
D0
PB74
PB154
/
1
0
0
1
1
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
0
D3
D2
D1
D0
PC03/ PC02/ PC01/ PC00/
PC83
1
0
0
1
1
PC82
PC81
PC80
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PC04/
PC84
1
0
0
1
1
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
0
D3
D2
D1
D0
PC13/ PC12/ PC11/ PC10/
PC93
1
0
0
1
1
PC92
PC91
PC90
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
1
D3
*
D2
*
D1
*
D0
PC14/
PC94
1
0
0
1
1
- 76 -
NJU6824
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
0
D3
D2
D1
D0
PC23/ PC22/ PC21/ PC20/
PC103 PC102 PC101 PC100
1
0
0
1
1
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PC24/
PC104
1
0
0
1
1
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
0
D3
D2
D1
D0
PC33/ PC32/ PC31/ PC30/
PC113 PC112 PC111 PC110
1
0
0
1
1
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
1
D3
*
D2
*
D1
*
D0
PC34/
PC114
1
0
0
1
1
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
0
D3
D2
D1
D0
PC43/ PC42/ PC41/ PC40/
PC123 PC122 PC121 PC120
1
0
0
1
1
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PC44/
PC124
1
0
0
1
1
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
D0
PC53/ PC52/ PC51/ PC50/
PC133 PC132 PC131 PC130
1
0
1
0
0
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PC54/
PC134
1
0
1
0
0
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
0
D3
D2
D1
D0
PC63/ PC62/ PC61/ PC60/
PC143 PC142 PC141 PC140
1
0
1
0
0
- 77 -
NJU6824
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
1
D3
*
D2
*
D1
*
D0
PC64/
PC144
1
0
1
0
0
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
0
D3
D2
D1
D0
PC73/ PC72/ PC71/ PC70/
PC153 PC152 PC151 PC150
1
0
1
0
0
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PC74/
PC154
1
0
1
0
0
Gradation Level Table
(PAj, PBj, PCj, j=0
Note
−15)
Gradation
Level
Gradation
Level
Palette Value
Note
Palette Value
Gradation Palette 0
Initial Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0/31
1/31
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
16/31
17/31
18/31
19/31
20/31
21/31
22/31
23/31
24/31
25/31
26/31
27/31
28/31
29/31
30/31
31/31
Gradation Palette 8
Initial Value
2/31
Gradation Palette 1
Initial Value
Gradation Palette 9
Initial Value
3/31
4/31
Gradation Palette2
Initial Value
Gradation Palette 10
Initial Value
5/31
6/31
Gradation Palette 3
Initial Value
Gradation Palette 11
Initial Value
7/31
8/31
Gradation Palette 4
Initial Value
Gradation Palette 12
Initial Value
9/31
10/31
11/31
12/31
13/31
14/31
15/31
Gradation Palette 5
Initial Value
Gradation Palette 13
Initial Value
Gradation Palette 6
Initial Value
Gradation Palette 14
Initial Value
Gradation Palette 7
Initial Value
Gradation Palette 15
Initial Value
- 78 -
NJU6824
(32-16)Initial COM line
The “Initial COM line” instruction is used to specify the common driver that starts scanning the display
data. The line address, corresponding to the initial COM line, is specified by the “Initial display line”
instruction.
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
0
D3
D2
D1
D0
1
0
1
0
0
SC3 SC2 SC1 SC0
SC3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SC2 SC1 SC0
Initial COM line (SHIFT=0)
COM0
Initial COM line (SHIFT=1)
COM127
COM123
COM119
COM111
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
COM4
COM8
COM16
COM24
COM32
COM40
COM48
COM56
COM64
COM72
COM80
COM88
COM96
COM104
COM112
COM103
COM95
COM87
COM79
COM71
COM63
COM55
COM47
COM39
COM31
COM23
COM15
SHIFT=0: Positive scan direction
SHIFT=1: Negative scan direction
(for instance, COM0 → COM127
(for instance, COM127 → COM0)
)
(32-17)Display control signal / Duty select
CL, FLM, FR, and CLK signal outputs control ON/OFF and Duty select.
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
1
D3
*
D2
*
D1
D0
SON
1
0
1
0
0
DSE
SON=0:
SON=1:
CL, FLM, FR, and CLK outputs level “0”.
CL, FLM, FR, and CLK outputs are active.
DSE=0:
DSE=1:
Refer the table of (32-11) Duty cycle ratio. (Default)
The duty ratio is set by the value subtracted "1" from the content of the table.
- 79 -
NJU6824
(32-18)Gradation mode control
The “Gradation mode control” is selecting the gradation mode, selecting the 256-color mode, and setting
boost clock.
CS
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
0
D3
D2
D1
D0
PWM C256
0
1
0
1
0
0
FDC1 FDC2
ꢁ
ꢁ
PWM register
PWM=0:
Variable gradation mode
(16-gradation levels out of a palette consisting of 32-gradation levels)
Fixed gradation mode
PWM=1:
(Fixed 8-gradation levels)
C256 register
C256=0
Variable gradation mode
(16-gradation levels out of a palette consisting of 32-gradation levels.)
C256=1
256-color mode
(8-gradation levels out of a palette consisting of 32-gradation levels.)
(4-gradation levels out of a palette consisting of 32-gradation levels at the palette
B.)
ꢁ
FDC1 and FDC2 register
FDC1
FDC2
Boost Clock
0
0
1
1
0
1
0
1
×
×
×
1
2
4
×1/2
- 80 -
NJU6824
(32-19)Data bus length
The “Data bus length” instruction is used to select the 8- or 16- bit data bus length and determine the
internal or external oscillation. In the 16-bit data bus mode, not only the display data but also the
instruction data is required to be transferred by 16-bit data (D15 to D0). However, in case of the access to
the instruction register, the only lower 8-bit data (D7 to D0) of the 16-bit data is valid. In case of the access
to the DDRAM, all of the 16-bit data (D15 to D0) is valid.
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
1
D3
*
D2
D1
D0
1
0
1
0
0
ABS CKS WLS
ꢁ
ꢁ
ꢁ
ABS register
ABS=0:
ABS=1:
Normal Mode
ABS Mode
WLS register
WLS=0:
WLS =1:
8-bit data bus length
16-bit data bus length
CKS register
CKS =0:
Internal oscillation
(The OSC1 terminal must be fixed “1” or “0”.)
External oscillation
CKS =1:
(By the external clock into the OSC1 or external resister between the OSC1 and
OSC2. OSC2 should be open when clock is inputted from OSC1.)
- 81 -
NJU6824
(32-20)EVR control
The “EVR control” instruction is used to fine-tune the LCD driving voltage (VLCD) so that it is possible to
optimize the contrast level for the display.
The “EVR control” instruction requires to be programmed by the upper 3-bit data first and then lower 4-
bit data, where programming the only upper 3-bit data has not enabled it, so that it is possible to prevent
unexpected high voltage for the VLCD
.
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
0
D3
D2
D1
D0
1
0
1
0
0
DV3 DV2 DV1 DV0
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
1
D3
*
D2
D1
D0
1
0
1
0
0
DV6 DV5 DV4
DV6 DV5 DV4 DV3 DV2 DV1 DV0
VLCD
0
0
0
0
0
0
0
0
:
0
0
0
0
0
1
Low
:
:
:
:
1
1
1
1
1
1
1
High
The VLCD is calculated by the following equation.
VLCD [V] = 0.5 x VREG + M (VREG – 0.5 x VREG) / 127
VBA = VEE x 0.9
VREG = VREF x N
VBA
VREF
VREG
N
: Output voltage of the reference voltage generator
: Input voltage of the voltage regulator
: Output voltage of the voltage regulator
: Register value for the voltage booster
: Register value for the EVR
M
- 82 -
NJU6824
(32-21)Frequency control
The “Frequency control” instruction is used to control the frame frequency for a LCD panel.
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
1
D3
*
D2
D1
D0
1
0
1
0
0
Rf2
Rf1
Rf0
ꢀRfx register (x=0, 1, 2)
The “Rfx” register is used to determine the feed back resister value for the internal oscillator in
order that it is possible to adjust the frame frequency.
Rf 2 Rf 1 Rf 0
Feedback resistor value
Reference value
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0.8 x reference value
0.9 x reference value
1.1 x reference value
1.2 x reference value
0.7 x reference value
1.3 x reference value
Inhibited
(32-22)Discharge ON/OFF
The “Discharge ON/OFF” instruction is used to enable or disable the discharge circuits, so that it is
possible to prevent unexpected pixels turned on just after the internal or external power supply is turned
off. During the discharge operation, do not supply the power neither from an internal or external power
supplies to the LSI.
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
1
D5
1
D4
0
D3
*
D2
*
D1
D0
1
0
1
0
0
DIS2 DIS
DIS=0:
DIS=1:
Discharge OFF: Capacitors for VLCD, V1, V2, V3 and V4
Discharge ON : Capacitors for VLCD, V1, V2, V3 and V4
DIS2=0:
DIS2=1:
Discharge OFF: Resistance between VOUT and VEE
Discharge ON : Resistance between VOUT and VEE
*In the power on, 100kΩ (Typ.) resistance is connected between VOUT and VEE.
- 83 -
NJU6824
(32-23)Instruction register address
The “Instruction register address” is used to specify the instruction register address, so that it is possible
to read out the contents of the instruction registers in combination with the “Instruction register read”
instruction.
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
0
D3
D2
D1
D0
1
0
1
0
0
RA3 RA2 RA1 RA0
(32-24)Instruction register read
The “Instruction register read” instruction is used to read out the contents of the instruction register in
combination with the “Instruction register address” instruction.
CS
0
RS
1
RD WR RE2 RE1 RE0
0/1 0/1 0/1
D7
*
D6
*
D5
*
D4
*
D3
D2
D1
D0
0
1
Internal register data read
(32-25)Window end column address
The “Window end column address” is used to specify the column address for the window end point. The
lower 4-bit data is required to be programmed first and then the upper 4-bit data can be programmed.
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
D0
1
0
1
0
1
EX3 EX2 EX1 EX0
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
1
D3
D2
D1
D0
1
0
1
0
1
EX7 EX6 EX5 EX4
(32-26)Window end row address set
The “Window end row address” is used to specify the row address for the window end point. The lower
4-bit data is required to be programmed first and then the upper 3-bit data can be programmed.
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
0
D3
D2
D1
D0
1
0
1
0
1
EY3 EY2 EY1 EY0
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
1
D3
*
D2
D1
D0
1
0
1
0
1
EY6 EY5 EY4
- 84 -
NJU6824
(32-27)Initial reverse line
The “Initial reverse line” instruction is used to specify the initial reverse line address for the reverse line
display. The lower 4-bit data is required to be programmed first and then the upper 3-bit data can be
programmed. It can be programmed in between 00H and 7FH and the line address beyond 7FH is inhibited.
The address relationship: LSi < LEi (i=7 to 0) must be maintained in the reverse line display.
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
0
D3
D2
D1
D0
1
0
1
0
1
LS3 LS2 LS1 LS0
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
1
D3
*
D2
D1
D0
1
0
1
0
1
LS6 LS5 LS4
(32-28)Last reverse line
The “Last reverse line” instruction is used to specify the last reverse line address for the reverse line
display. The lower 4-bit data is required to be programmed first and then the upper 3-bit data can be
programmed. It can be programmed in between 00H and 7FH and the line address beyond 7FH is inhibited.
The address relationship: LSi < LEi (i=7 to 0) must be maintained in the reverse line display.
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
0
D3
D2
D1
D0
1
0
1
0
1
LE3 LE2 LE1 LE0
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
1
D3
*
D2
D1
D0
1
0
1
0
1
LE6 LE5 LE4
(32-29)Reverse line display ON/OFF
The “Reverse line display ON/OFF” is used to enable or disable the reverse line display for the blink
operation and determine the reverse line display mode.
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
0
D3
*
D2
*
D1
D0
1
0
1
0
1
BT LREV
ꢁ
LREV register
The “LREV” register is used to enable or disable the reverse line display.
LREV =0:
LREV =1:
Reverse line display OFF (Normal)
Reverse line display ON
- 85 -
NJU6824
ꢁ
BT register
The “BT” register is used to determine the reverse line display mode in the reverse line display ON
(LREV=1) status.
BT =0:
BT =1:
Normal reverse line display
Blink once every 32 frames
Display examples in the LREV=”1” and BT=”1”
ꢀ ꢀ
ꢀ ꢀ ꢀ
ꢀ ꢀ ꢀ ꢀ
ꢀ ꢀ
ꢀꢀ ꢀ ꢀ
ꢀ ꢀ ꢀ
ꢀ ꢀ
ꢀꢀ ꢀ ꢀ ꢀ
ꢀ ꢀ ꢀ
ꢀ ꢀ
ꢀ
ꢀ ꢀ ꢀ
ꢀ
ꢀ ꢀ
ꢀ ꢀ ꢀ
Blink once every 32 frames
NJRC
LCD DRIVER
Low Power and
Low Voltage
Blink once every 32 frames
NJRC
←
Initial reverse line address
Last reverse line address
LCD DRIVER
←
Low Power and
Low Voltage
- 86 -
NJU6824
(32-30)Gradation palette setting control / Icon SEG address set
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
1
D3
*
D2
*
D1
D0
1
0
1
0
1
DMY PS
ꢁ
ꢁ
PS register
PS=0: Lower 8 Gradation setting
PS=1: Upper 8 Gradation setting
DMY register
Although segment drivers in normal condition output LCD driving voltage corresponding to data in
Display data RAM, Icon segment driver output LCD driving voltage corresponding to registers. The 24
bits register corresponds to SEGSA0 ~ SEGSA1, SEGSB0 ~ SEGSB1, SEGSC0 ~ SEGSC1.
DMY=0: Normal RAM access
DMY=1: Icon segment driver RAM access
- 87 -
NJU6824
(32-31)PWM control
The “PWM control” is used to determine the PWM type for the segment waveforms, where the type can
be specified for each of the SEGAi, SEGBi and SEGCi (i=0-127) drivers.
CS
0
RS
1
RD WR RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
0
D3
D2
D1
D0
PWMS PWMA PWMB PWMC
1
0
1
0
1
ꢁ
ꢁ
PWMS register
PWMS=0: Type 1
PWMS=1: Type 2
PWMA, B and C registers
The “PWMA, PWMB and PWMC” registers are used to select the type 1-O or type 1-E.
PWMZ=0 (Z=A, B and C): Type 1-O
PWMZ=1 (Z=A, B and C): Type 1-E
PWM type1 (PWMS=”0”)
Odd line
Even line
“H”
CL
“L”
VLCD
→
←
Type-O
Type-E
V2
VLCD
V2
SEG
→
←
PWM type2 (PWMS=”1”)
“H”
CL
“L”
VLCD
V2
SEG
→
→
- 88 -
NJU6824
(33) The relationship between Common driver and row address
The row address assignment for the common driver can be programmed by the “SHIF” register in the
“Display control (1), and “Duty cycle ratio”, “Initial display line” and “Initial COM line” instructions.
ꢁ
When initial display line is “0”
The relation between common drivers and row address of DDRAM (MY) is changing by the “Duty
cycle ratio” and “Initial COM line” instructions. If the shift bit is “0”, the order of common scanning is
normal and if it is “1”, the common scanning order is inversed. When LA0 to LA6 of initial display line
setting is “0”, the “MY” corresponding to the Initial COM line is also “0”. And “MY” is increasing.
ꢁ
When initial display line is not “0”
The relation between common drivers and row address of DDRAM (MY) is changing by the “Duty
cycle ratio” and “Initial COM line” instructions. If the shift bit is “0”, the order of common scanning is
normal and if it is “1”, the common scanning order is inversed. When LA0 to LA6 of initial display line
setting is not “0”, the “MY” corresponding to the Initial COM line is biased by the setting value. During
the display, “MY” is increasing up to “127”. When “MY” over than “127”, its back to “0”. And “MY” is
increasing from 0 continuously.
The following are Examples of setting the start-line 0 or 5 at 1/129, 1/128, or 1/17 duty.
- 89 -
NJU6824
(33-1)Initial display line “0”, 1/129 duty cycle (Common forward scan)
SHIFT=”0”(Common forward scan), DS3, 2, , 0=”0000”, LA7….LA0=”00000000”(Initial display line 0)
1
SC3
SC2
SC1
SC0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
48
1100
40
1101
32
1110
24
1111
16
COM0
0
124
120
112
104
96
88
80
72
64
56
COM1
COM2
COM3
COM4
127
0
COM5
COM6
COM7
COM8
127
0
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COM80
COM81
COM82
COM83
COM84
COM85
COM86
COM87
COM88
COM89
COM90
COM91
COM92
COM93
COM94
COM95
COM96
:
127
0
127
0
127
0
127
0
127
0
127
0
127
0
127
0
127
0
127
0
127
0
COM103
COM104
:
127
0
COM111
COM112
:
127
0
COM125
COM126
COM127
(129th COM period) *1
127
127
123
127
119
127
111
103
127
95
87
79
71
63
55
47
39
31
23
15
127
127
127
127
127
127
127
127
127
127
127
127
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
*1 : 129th COM period is not selected.
- 90 -
NJU6824
(33-2)Initial display line “0”, 1/17 duty cycle (Common forward scan)
SHIFT=”0”(Common forward scan), DS3, 2, , 0=”1110”, LA7….LA0=”00000000”(Initial display line 0)
1
SC3
SC2
SC1
SC0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COM80
COM81
COM82
COM83
COM84
COM85
COM86
COM87
COM88
:
0
0
0
15
0
15
15
0
15
0
15
0
15
0
15
0
15
0
15
0
15
0
15
0
COM95
COM96
:
15
0
COM103
COM104
:
15
0
COM111
COM112
:
15
0
COM119
:
COM127
(17th COM period) *1
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
*1 : 17th COM period is not selected.
- 91 -
NJU6824
(33-3)Initial display line “0”, 1/129 duty cycle (Common backward scan)
SHIFT=”1”(Common backward scan), DS3, 2, , 0=”0000”, LA7….LA0=”00000000”(Initial display line 0)
1
SC3
SC2
SC1
SC0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
47
1100
39
1101
31
1110
23
1111
15
COM0
127
123
119
111
103
95
87
79
71
63
55
COM1
COM2
COM3
COM4
COM5
COM6
COM7
:
COM15
COM16
:
0
127
COM23
COM24
:
0
127
COM31
COM32
:
0
127
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COM80
COM81
COM82
COM83
COM84
COM85
COM86
COM87
COM88
COM89
COM90
COM91
COM92
COM93
COM94
COM95
COM96
COM97
COM98
COM99
COM100
COM101
COM102
COM103
COM104
COM105
COM106
COM107
COM108
COM109
COM110
COM111
COM112
COM113
COM114
COM115
COM116
COM117
COM118
COM119
COM120
COM121
COM122
COM123
COM124
COM125
COM126
COM127
0
127
0
127
0
127
0
127
0
127
0
127
0
127
0
127
0
127
0
127
0
127
0
127
0
124
127
120
127
112
127
104
127
96
88
80
72
64
56
48
40
32
24
16
(129th COM period) *1
127
127
127
127
127
127
127
127
127
127
127
127
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
*1 : 129th COM period is not selected.
- 92 -
NJU6824
(33-4)Initial display line “5”, 1/129 duty cycle (Common forward scan)
SHIFT=”0”(Common forward scan), DS3, 2, , 0=”0000”, LA7….LA0=”00000101”(Initial display line 5)
1
SC3
SC2
SC1
SC0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
53
1100
45
1101
37
1110
29
1111
21
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
:
5
1
125
126
127
0
117
109
101
93
85
77
69
61
5
5
127
0
5
127
0
5
127
0
5
127
0
5
127
0
5
127
0
5
127
0
5
127
0
5
127
0
COM80
COM81
COM82
COM83
:
5
127
0
COM88
COM89
COM90
COM91
:
5
127
0
COM96
COM97
COM98
COM99
:
5
127
0
COM104
COM105
COM106
COM107
:
5
127
0
COM112
:
5
COM122
COM123
COM124
COM125
COM126
COM127
127
0
:
127
0
4
124
127
116
127
108
127
100
127
92
84
76
68
60
52
44
38
28
20
(129th COM period) *1
127
127
127
127
127
127
127
127
127
127
127
127
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
*1 : 129th COM period is not selected.
- 93 -
NJU6824
(33-5)Initial display line “0”, 1/128 duty cycle (Common forward scan, DSE=”1”)
SHIFT=”0”(Common forward scan), DS3, 2, , 0=”0000”, LA7….LA0=”00000000”(Initial display line 0) DSE=”1”
1
SC3
SC2
SC1
SC0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
48
1100
40
1101
32
1110
24
1111
16
COM0
0
124
120
112
104
96
88
80
72
64
56
COM1
COM2
COM3
COM4
127
0
COM5
COM6
COM7
COM8
127
0
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COM80
COM81
COM82
COM83
COM84
COM85
COM86
COM87
COM88
COM89
COM90
COM91
COM92
COM93
COM94
COM95
COM96
:
127
0
127
0
127
0
127
0
127
0
127
0
127
0
127
0
127
0
127
0
127
0
COM103
COM104
:
127
0
COM111
COM112
:
127
0
COM125
COM126
COM127
127
123
119
111
103
95
87
79
71
63
55
47
39
31
23
15
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
- 94 -
NJU6824
ꢀꢀ ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage (1)
Supply Voltage (2)
Supply Voltage (3)
Supply Voltage (4)
Supply Voltage (5)
Supply Voltage (6)
Input Voltage
SYMBOL
VDD
VEE
VOUT
VREG
VLCD
V1, V2, V3, V4
VI
CONDITION
TERMINAL
VDD
RATING
-0.3 to +4.0
-0.3 to +4.0
UNIT
V
V
V
V
V
V
V
°C
VEE
VOUT
VREG
VLCD
-0.3 to +20.0
-0.3 to +20.0
-0.3 to +20.0
-0.3 to VLCD + 0.3
-0.3 to VDD + 0.3
-45 to +125
VSS=0V
Ta = +25°C
V1, V2, V3, V4
*1
Storage Temperature
Tstg
Note 1) D0 to D15, CS, RS, RD, WR, OSC1, RES terminals.
ꢀ
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
VDD1
VDD2
VEE
VLCD
VOUT
VREG
VREF
TERMINAL
VDD
MIN
1.7
2.4
2.4
5
TYP
MAX
3.3
3.3
3.3
18.0
18.0
UNIT
V
V
V
V
V
V
V
NOTE
*1
*2
*3
*4
Supply Voltage
VEE
VLCD
VOUT
VREG
VREF
Operating Voltage
V
OUT × 0.9
3.3
2.1
-30
*5
Operating
Temperature
Topr
85
°C
Note1) Applies to the condition when the reference voltage generator is not used.
Note2) Applies to the condition when the reference voltage generator is used.
Note3) Applies to the condition when the voltage booster is used.
Note4) The following relationship among the supply voltages must be maintained.
VSS<V4<V3<V2<V1<VLCD<VOUT
Note5) The relationship: VREF<VEE must be maintained.
- 95 -
NJU6824
ꢀꢀ DC CHARACTERISTICS 1
VSS = 0V, VDD = +1.7 to +3.3V, Ta = -30 to +85°C
SYM
PARAMETER
BOL
CONDITION
MIN
TYP
MAX
UNIT NOTE
VIH
VIL
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
High level output voltage
Low level output voltage
Input leakage current
0.8 VDD
0
VDD - 0.4
VDD
0.2VDD
V
V
V
V
V
V
µA
µA
*1
*1
*2
*2
*3
*3
*4
*5
VOH1
VOL1
VOH2
VOL2
ILI
IOH = -0.4mA
IOL = 0.4mA
IOH = -0.1mA
IOL = 0.1mA
VI = VSS or VDD
VI = VSS or VDD
0.4
VDD - 0.4
0.4
10
10
2
-10
-10
ILO
Output leakage current
VLCD = 10V
VLCD = 6V
1
2
RON1
Driver ON-resistance
Stand-by current
*6
|∆VON| = 0.5V
kΩ
µA
4
ISTB
VDD = 3V
15
*7
CS=VDD, Ta=25°C
fOSC1
fOSC2
fOSC3
fr1
490
110
15.5
600
135.5
19.4
575
135
19.6
710
160
22.9
*8
*9
*10
VDD = 3V
Ta = 25°C
Internal oscillation
Frequency
kHz
Rf=12kΩ
Rf=62kΩ
Rf=470kΩ
N-time booster (N=2 to 6)
RL = 500kΩ (VOUT - VSS
VDD = 3V, 6-time booster
Whole ON pattern
VDD = 3V, 6-time booster
Checker pattern
VDD = 3V, 5-time booster
Whole ON pattern
VDD = 3V, 5-time booster
Checker pattern
VDD = 3V, 4-time booster
Whole ON pattern
VDD = 3V, 4-time booster
Checker pattern
External oscillation
Frequency
fr2
kHz
V
*11
*12
fr3
Voltage converter
output voltage
(N x VEE
x 0.95
)
VOUT
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
VBA
)
Supply current (1)
Supply current (2)
Supply current (3)
Supply current (4)
Supply current (5)
Supply current (6)
VBA Operating voltage
760
930
1140
1400
780
520
*13
µA
650
980
360
540
450
680
(0.9 VEE
x 0.98
)
(0.9 VEE
x 1.02
)
VEE = 2.4 to 3.3V
0.9 VEE
V
V
*14
*15
VEE = 2.4 to 3.3V
(VREF x N)
x 0.97
(VREF x N)
x 1.03
VREG
(VREF x N)
VREG Operating voltage
V
REF = 0.9 x VEE
N-time booster (N=2 to 6)
V2
-100
-100
-30
-30
-30
0
0
0
0
0
+100
+100
+30
+30
+30
V3
Output Voltage
VD12
VD34
VD24
mV
*16
- 96 -
NJU6824
ꢀꢀ CLOCK and FRAME FREQUENCY
Display duty cycle ratio (1/D) <DSE=0>
1/73 to 1/41 1/33 to 1/25
PARAMETER SYMBOL
NOTE
1/17
Display mode
1/129 to 1/81
fOSC / (62xD)
16 Gradation mode
fOSC / (62xDx2) fOSC / (62xDx4) fOSC / (62xDx8)
fOSC / (14xDx2) fOSC / (14xDx4) fOSC / (14xDx8)
Internal
fOSC
Simplified
8 gradation mode
f
OSC / (14xD)
OSC / (2xD)
fCK / (62xD)
CK / (14xD)
CK / (2xD)
clock
B&W mode
f
fOSC / (2xDx2)
fCK / (62xDx2)
fCK / (14xDx2)
fCK / (2xDx2)
fOSC / (2xDx4)
fCK / (62xDx4)
fCK / (14xDx4)
fCK / (2xDx4)
fOSC / (2xDx8)
fCK / (62xDx8)
fCK / (14xDx8)
fCK / (2xDx8)
FLM
16 Gradation mode
External
fCK
Simplified
8 gradation mode
f
clock
B&W mode
f
- 97 -
NJU6824
APPLIED TERMINALS and CONDITIONS
Note 1) D0-D15, CS, RS, RD, WR, P/S, SEL68, RES
Note 2) D0-D15
Note 3) CL, FLM, FR, CLK
Note 4) CS, RS, SEL68, RD, WR, P/S, RES, OSC1
Note 5) D0-D15 in the high impedance
Note 6) - SEGA0-SEGA127, SEGB0-SEGB127, SEGC0-SEGC127, COM0-COM127 and
SEGSA0-SEGSA1, SEGSB0-SEGSB1, SEGSC0-SEGSC1
Defines the resistance between each of the SEG and COM terminals and each of the power supply
terminals (VLCD, V1, V2, V3 and V4) in the 0.5V deference and 1/9 LCD bias ratio.
Note 7) VDD
The oscillator is halted, CS=”1” (disabled), No-load onto the segment and common drivers
Note 8) OSC
Defines the internal oscillation frequency at (Rf2, Rf1, Rf0)=(0,0,0) in the variable gradation mode.
Note 9) OSC
Defines the internal oscillation frequency at (Rf2, Rf1, Rf0)=(0,0,0) in the fixed gradation mode.
Note 10) OSC
Defines the internal oscillation frequency at (Rf2, Rf1, Rf0)=(0,0,0) in the Black & White mode.
Note 11) VDD=3V, Ta=25°C
Note 12) VOUT
Applies to the condition when the internal voltage booster (N=2-6), internal oscillator and internal
power circuits are used. VEE=2.4V to 3.3V, EVR= (1,1,1,1,1,1,1)
1/5 to 1/12 LCD bias, 1/129 duty cycle, No-load on segment and common drivers
RL=500Kohm between VOUT and VSS, CA1=CA2=1.0uF, CA3=0.1uF, DCON=”1”, AMPON=”1”
Note 13) VDD
Applies to the condition when using the internal oscillator and internal power circuits without any
access from MPU. EVR= (1,1,1,1,1,1,1), All pixels turned-on or checkerboard display in gradation
mode.
No-load onto the segment and common drivers
VDD=VEE, VREF=0.9VEE, CA1=CA2=1.0uF, CA3=0.1uF, DCON=”1”, AMPON=”1”, NLIN=”0”
1/129 Duty cycle, Ta=25°C
Note 14) VBA
Applies to the condition that VBA=VREF and voltage booster N= 1.
When DCON=”0”, VOUT=13.5V input.
Note 15) VREG
VEE=2.4V to 3.3V, VREF=0.9VEE, VOUT=18V, 1/5 to 1/12 LCD bias ratio, 1/129 duty cycle,
EVR=(1,1,1,1,1,1,1), Checkerboard display, No-load onto the segment and common drivers,
voltage booster N=2 to 6, V1A1, V1A2, V4A1, V4A2=”0”.
CA1=CA2=1.0uF, CA3=0.1uF, DCON=”0”, AMPON=”1”, NLIN=”0”.
Note 16) VLCD, V1, V2, V3, V4
VEE=3.0V, VREF=0.9VEE, VOUT=15V, 1/5 to 1/12 LCD Bias, EVR= (1,1,1,1,1,1,1), Display OFF, No-
load onto the segment and common drivers, voltage booster N=5, V1A1, V1A2, V4A1, V4A2=”0”.
CA1=CA2=1.0uF, CA3=0.1uF, DCON=”0”, AMPON=”1”
VLCD
(1)
(2)
VD12: (1)-(2)
VD34: (3)-(4)
VD24: (2)-(4)
V1
V2
V3
V4
VSS
(3)
(4)
- 98 -
NJU6824
ꢀꢀ AC CHARACTERISTICS
ꢁ
Write operation (80-type MPU)
tAS8
tAH8
CS
RS
WR
tWRLW8
tWRHW8
tDS8
tDH8
D0 to D15
tCYC8
(VDD=2.5 to 3.3V, Ta=-30 to +85
°
C)
C)
C)
PARAMETER
SYMBOL CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
tAH8
tAS8
0
0
ns
ns
CS
RS
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC8
tWRLW8
tWRHW8
90
35
35
ns
ns
ns
WR
Data setup time
Data hold time
tDS8
tDH8
30
5
ns
ns
D0 to D15
(VDD=2.2 to 2.5V, Ta=-30 to +85
°
PARAMETER
SYMBOL CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
tAH8
tAS8
0
0
ns
ns
CS
RS
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC8
tWRLW8
tWRHW8
160
70
70
ns
ns
ns
WR
Data setup time
Data hold time
tDS8
tDH8
40
5
ns
ns
D0 to D15
(VDD=1.7 to 2.2V, Ta=-30 to +85
°
PARAMETER
SYMBOL CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
tAH8
tAS8
0
0
ns
ns
CS
RS
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC8
tWRLW8
tWRHW8
180
80
80
ns
ns
ns
WR
Data setup time
Data hold time
tDS8
tDH8
70
10
ns
ns
D0 to D15
Note) Each timing is specified based on 20% and 80% of VDD
.
- 99 -
NJU6824
ꢁ
Read operation (80-type MPU)
tAH8
tAS8
CS
RS
tWRLR8
RD
tWRHR8
tRDH8
D0 to D15
tRDD8
tCYC8
(VDD=2.5 to 3.3V, Ta=-30 to +85
°
C)
C)
C)
PARAMETER
SYMBOL CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
tAH8
tAS8
0
0
ns
ns
CS
RS
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC8
tWRLR8
tWRHR8
180
80
80
ns
ns
ns
RD
Read Data setup time
Read Data hold time
TRDD8
60
ns
ns
CL=15pF
TRDH8
D0 to D15
0
(VDD=2.2 to 2.5V, Ta=-30 to +85
°
PARAMETER
SYMBOL CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
tAH8
tAS8
0
0
ns
ns
CS
RS
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC8
tWRLR8
tWRHR8
180
80
80
ns
ns
ns
RD
Read Data setup time
Read Data hold time
TRDD8
60
ns
ns
CL=15pF
TRDH8
D0 to D15
0
(VDD=1.7 to 2.2V, Ta=-30 to +85
°
PARAMETER
SYMBOL CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
tAH8
tAS8
0
0
ns
ns
CS
RS
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC8
tWRLR8
tWRHR8
250
120
120
ns
ns
ns
RD
Read Data setup time
Read Data hold time
tRDD8
110
ns
ns
CL=15pF
tRDH8
D0 to D15
0
Note) Each timing is specified based on 20% and 80% of VDD
.
- 100 -
NJU6824
ꢁ
Write operation (68-type MPU)
tAS6
tAH6
CS
RS
R/W
(WR)
tELW6
tEHW6
E
(RD)
tDS6
tDH6
D0 to D15
tCYC6
(VDD=2.5 to 3.3V, Ta=-30 to +85
°C)
PARAMETER
SYMBOL CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
tAH6
tAS6
0
0
ns
ns
CS
RS
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC6
tELW6
tEHW6
90
35
35
ns
ns
ns
E
Data setup time
Data hold time
tDS6
tDH6
40
5
ns
ns
D0 to D15
(VDD=2.2 to 2.5V, Ta=-30 to +85
°C)
PARAMETER
SYMBOL CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
tAH6
tAS6
0
0
ns
ns
CS
RS
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC6
tELW6
tEHW6
160
70
70
ns
ns
ns
E
Data setup time
Data hold time
tDS6
tDH6
50
5
ns
ns
D0 to D15
(VDD=1.7 to 2.2V, Ta=-30 to +85
°C)
PARAMETER
SYMBOL CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
tAH6
tAS6
0
0
ns
ns
CS
RS
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC6
tELW6
tEHW6
180
80
80
ns
ns
ns
E
Data setup time
Data hold time
tDS6
tDH6
70
10
ns
ns
D0 to D15
Note) Each timing is specified based on 20% and 80% of VDD
.
- 101
NJU6824
ꢁ
Read operation (68-type MPU)
tAS6
tAH6
CS
RS
R/W
(WR)
tELR6
tEHR6
E
(RD)
tRDH6
D0 to D15
tRDD6
tCYC6
(VDD=2.5 to 3.3V, Ta=-30 to +85°C)
PARAMETER
SYMBOL
tAH6
CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
0
0
ns
ns
CS
RS
tAS6
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC6
tELR6
tEHR6
180
80
80
ns
ns
ns
E
Read Data setup time
Read Data hold time
tRDD6
tRDH6
ns
ns
70
CL=15pF
D0 to D15
0
(VDD=2.2 to 2.5V, Ta=-30 to +85°C)
PARAMETER
SYMBOL
CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
tAH6
tAS6
0
0
ns
ns
CS
RS
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC6
tELR6
tEHR6
180
80
80
ns
ns
ns
E
Read Data setup time
Read Data hold time
tRDD6
tRDH6
ns
ns
70
CL=15pF
D0 to D15
0
(VDD=1.7 to 2.2V, Ta=-30 to +85°C)
PARAMETER
SYMBOL
CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
tAH6
tAS6
0
0
ns
ns
CS
RS
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC6
tELR6
tEHR6
250
120
120
ns
ns
ns
E
Read Data setup time
Read Data hold time
tRDD6
tRDH6
ns
ns
110
CL=15pF
D0 to D15
0
Note) Each timing is specified based on 20% and 80% of VDD
.
- 102 -
NJU6824
ꢁ
Serial interface
tCSH
tCSS
CS
RS
tASS
tAHS
tSLW
tSHW
SCL
tCYCS
tDSS
tDHS
SDA
(VDD=2.5 to 3.3V, Ta=-30 to +85°C)
UNIT
PARAMETER
Serial clock cycle
SCL ”H” level pulse width
SCL ”L” level pulse width
Address setup time
Address hold time
Data setup time
SYMBOL CONDITION
MIN.
MAX.
TERMINAL
tCYCS
tSHW
tSLW
tASS
tAHS
tDSS
tDHS
50
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
SCL
RS
SDA
Data hold time
CS – SCL time
CS hold time
tCSS
tCSH
20
20
ns
ns
CS
(VDD=2.2 to 2.5V, Ta=-30 to +85°C)
UNIT
PARAMETER
SYMBOL CONDITION
MIN.
MAX.
TERMINAL
Serial clock cycle
tCYCS
tSHW
tSLW
tASS
tAHS
tDSS
tDHS
50
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
SCL ”H” level pulse width
SCL ”L” level pulse width
Address setup time
Address hold time
Data setup time
SCL
RS
SDA
Data hold time
CS – SCL time
CS hold time
tCSS
tCSH
20
20
ns
ns
CS
(VDD=1.7 to 2.2V, Ta=-30 to +85°C)
UNIT
PARAMETER
SYMBOL CONDITION
MIN.
MAX.
TERMINAL
Serial clock cycle
tCYCS
tSHW
tSLW
tASS
tAHS
tDSS
tDHS
80
35
35
35
35
35
35
ns
ns
ns
ns
ns
ns
ns
SCL ”H” level pulse width
SCL ”L” level pulse width
Address setup time
Address hold time
Data setup time
SCL
RS
SDA
Data hold time
CS – SCL time
CS hold time
tCSS
tCSH
35
35
ns
ns
CS
Note) Each timing is specified based on 20% and 80% of VDD
.
- 103
NJU6824
ꢁ
Display control timing
CLK
tDCL
CL
tDFLM
tDFLM
FLM
tFR
FR
Output timing
(VDD=2.4 to 3.3V, Ta=-30 to +85°C)
PARAMETER
FLM delay time
FR delay time
SYMBOL CONDITION
tDFLM CL=15pF
tFR
MIN.
MAX.
500
500
UNIT
ns
ns
TERMINAL
0
0
0
FLM
FR
CL
CL delay time
tDCL
200
ns
Output timing
(VDD=1.7 to 2.4V, Ta=-30 to +85
°C)
PARAMETER
FLM delay time
FR delay time
SYMBOL CONDITION
tDFLM CL=15pF
tFR
MIN.
MAX.
1000
1000
200
UNIT
ns
ns
TERMINAL
0
0
0
FLM
FR
CL
CL delay time
tDCL
ns
Note) Each timing is specified based on 20% and 80% of VDD
.
- 104 -
NJU6824
ꢁ
Input clock timing
tCKLW
tCKHW
OSC1
(VDD=1.7 to 3.3V, Ta=-30 to +85°C)
UNIT
PARAMETER
SYMBOL CONDITION
MIN.
MAX.
1.02
1.02
4.55
4.55
31.4
31.4
TERMINAL
OSC1
1
OSC1 “H” level pulse width (1)
OSC1 “L” level pulse width (1)
OSC1 “H” level pulse width (2)
OSC1 “L” level pulse width (2)
OSC1 “H” level pulse width (3)
OSC1 “L” level pulse width (3)
tCKHW1
tCKLW1
tCKHW2
tCKLW2
tCKHW3
tCKLW3
0.70
0.70
3.13
3.13
21.8
21.8
µs
µs
µs
µs
µs
µs
OSC1
2
OSC1
3
Note) Each timing is specified based on 20% and 80% of VDD
.
Note 1) Applied in the variable gradation mode MON=”0”,PWM=”0”
Note 2) Applied in the fixed gradation mode MON=”0”,PWM=”1”
Note 3) Applied in the B&W mode MON=”1”
- 105
NJU6824
ꢁ
Reset input timing
tRW
RES
tR
Internal circuit
status
During reset
End of reset
(VDD=2.4 to 3.3V, Ta=-30 to +85°C)
UNIT
PARAMETER
Reset time
SYMBOL CONDITION
MIN.
10.0
MAX.
Terminal
tR
1.0
µ
s
s
RES
RES “L” level pulse width
tRW
µ
(VDD=1.7 to 2.4V, Ta=-30 to +85°C)
UNIT
PARAMETER
Reset time
SYMBOL CONDITION
MIN.
10.0
MAX.
Terminal
tR
1.5
µ
s
s
RES
RES “L” level pulse width
tRW
µ
Note) Each timing is specified based on 20% and 80% of VDD
.
- 106 -
NJU6824
ꢁ
ꢁ
Typical characteristic
PARAMETER
Basic delay time of gate
SYMBOL
MIN
TYP
10
MAX
UNIT
ns
Ta=+25
°
C, VSS=0V, VDD=3.0V
Input output terminal type
(a) Input circuit
VDD
Terminals:
CS, RS, RD, WR, SEL68,
P/S, RES
I
Input signal
VSS(0V)
(b) Output circuit
Terminals:
FLM, CL, FR, CLK
VDD
Output control signal
Output signal
O
VSS(0V)
(c) Input/Output circuit
VDD
Terminals:
D0 to D15
Input signal
VSS(0V)
VSS(0V)
Input control signal
VDD
Output control signal
Output signal
VSS(0V)
- 107
NJU6824
(d) Display output circuit
VLCD
VLCD
VLCD
V1/V2
Output control
signal 1
Output control signal 2
Output control signal 4
O
Output control
signal 3
VSS(0V)
V3/V4
VSS(0V)
VSS(0V)
Terminals:
SEGA0 to SEGA127
SEGB0 to SEGB127
SEGC0 to SEGC127
COM0 to COM127
SEGSA0 to SEGSA1
SEGSB0 to SEGSB1
SEGSC0 to SEGSC1
- 108 -
NJU6824
ꢀꢀ APPLICATION CIRCUIT EXAMPLES
(1) MPU Connections
80-type MPU interface
1.7V to 3.3V
VCC
VDD
A0
RS
CS
A1 to A7
Decoder
8
7
(80-type MPU)
IORQ
D0 to D7
D0 to D7
RD
RD
WR
WR
RES
GND
RES
VSS
RESET
68-type MPU interface
1.7V to 3.3V
VCC
VDD
A0
RS
CS
A1 to A15
Decoder
8
15
(68-type MPU) VMA
D0 to D7
E
D0 to D7
RD(E)
R/W
WR(R/W)
RES
GND
RES
VSS
RESET
Serial interface
1.7V to 3.3V
VCC
VDD
RS
A0
A1 to A7
Decoder
7
CS
(MPU)
PORT1
PORT2
SDA
SCL
RES
RES
VSS
GND
RESET
- 109
NJU6824
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
- 110 -
相关型号：
©2020 ICPDF网 联系我们和版权申明