600F101JT250XT [NXP]
RF Power LDMOS Transistor;
| 型号： | 600F101JT250XT |
| 厂家： | 
NXP |
| 描述： | RF Power LDMOS Transistor |
| 文件： | 总10页 (文件大小：221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: A2V09H400--04S
Rev. 2, 02/2021
NXP Semiconductors
Technical Data
RF Power LDMOS Transistor
N--Channel Enhancement--Mode Lateral MOSFET
A2V09H400--04S
This 102 W asymmetrical Doherty RF power LDMOS transistor is designed
for cellular base station applications covering the frequency range of 720 to
960 MHz.
900 MHz
720–960 MHz, 102 W AVG., 48 V
AIRFAST RF POWER LDMOS
TRANSISTOR
Typical Doherty Single--Carrier W--CDMA Performance: VDD = 48 Vdc,
IDQA = 750 mA, VGSB = 0.8 Vdc, Pout = 102 W Avg., Input Signal
PAR = 9.9 dB @ 0.01% Probability on CCDF.
G
Output PAR
(dB)
ACPR
(dBc)
ps
D
Frequency
920 MHz
940 MHz
960 MHz
(dB)
18.7
18.9
18.5
(%)
53.5
54.0
53.4
7.2
7.0
6.8
–29.5
–29.2
–28.8
700 MHz
NI--780S--4L
Typical Doherty Single--Carrier W--CDMA Performance: VDD = 46 Vdc,
DQA = 300 mA, VGSB = 2.3 Vdc, Pout = 81 W Avg., Input Signal
PAR = 9.9 dB @ 0.01% Probability on CCDF.
I
G
Output PAR
(dB)
P3dB
(dBm)
ACPR
(dBc)
ps
D
Carrier
Frequency
758 MHz
780 MHz
803 MHz
(dB)
18.3
18.7
18.8
(%)
56.1
55.8
55.5
RF /V
RF /V
outA DSA
3
4
1
2
inA GSA
7.9
8.0
8.0
57.4
57.5
57.5
–29.7
–31.0
–33.0
RF /V
inB GSB
RF /V
outB DSB
Peaking
Features
(Top View)
Advanced high performance in--package Doherty
Greater negative gate--source voltage range for improved Class C
operation
Figure 1. Pin Connections
Designed for digital predistortion error correction systems
2019, 2021 NXP B.V.
Table 1. Maximum Ratings
Rating
Symbol
Value
Unit
Vdc
Vdc
Vdc
C
Drain--Source Voltage
V
–0.5, +105
–6.0, +10
55, +0
DSS
Gate--Source Voltage
V
GS
DD
Operating Voltage
V
Storage Temperature Range
Case Operating Temperature Range
T
stg
–65 to +150
–40 to +150
–40 to +225
T
C
C
(1,2)
Operating Junction Temperature Range
T
J
C
Table 2. Thermal Characteristics
(2,3)
Characteristic
Symbol
Value
Unit
Thermal Resistance, Junction to Case
R
0.51
C/W
JC
Case Temperature 81C, 107 W Avg., W--CDMA, 48 Vdc, I
= 750 mA,
DQA
V
= 0.8 Vdc, 940 MHz
GSB
Table 3. ESD Protection Characteristics
Test Methodology
Class
2
Human Body Model (per JS--001--2017)
Charge Device Model (per JS--002--2014)
C3
Table 4. Electrical Characteristics (T = 25C unless otherwise noted)
A
Characteristic
Symbol
Min
Typ
Max
Unit
(4)
Off Characteristics
Zero Gate Voltage Drain Leakage Current
I
I
—
—
—
—
—
—
10
1
Adc
Adc
Adc
DSS
DSS
GSS
(V = 105 Vdc, V = 0 Vdc)
DS
GS
Zero Gate Voltage Drain Leakage Current
(V = 55 Vdc, V = 0 Vdc)
DS
GS
Gate--Source Leakage Current
(V = 5 Vdc, V = 0 Vdc)
I
1
GS
DS
On Characteristics — Side A, Carrier
Gate Threshold Voltage
V
1.3
2.0
0.1
1.7
2.4
0.2
2.3
2.8
0.4
Vdc
Vdc
Vdc
GS(th)
(V = 10 Vdc, I = 137 Adc)
DS
D
Gate Quiescent Voltage
(V = 48 Vdc, I = 750 mAdc, Measured in Functional Test)
V
GSA(Q)
DD
D
Drain--Source On--Voltage
(V = 10 Vdc, I = 1.4 Adc)
V
DS(on)
GS
D
On Characteristics — Side B, Peaking
Gate Threshold Voltage
V
1.3
0.1
1.8
0.2
2.3
0.5
Vdc
Vdc
GS(th)
(V = 10 Vdc, I = 211 Adc)
DS
D
Drain--Source On--Voltage
(V = 10 Vdc, I = 2.1 Adc)
V
DS(on)
GS
D
1. Continuous use at maximum temperature will affect MTTF.
2. MTTF calculator available at http://www.nxp.com.
3. Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to http://www.nxp.com/RF and search for AN1955.
4. Each side of device measured separately.
(continued)
A2V09H400--04S
RF Device Data
NXP Semiconductors
2
Table 4. Electrical Characteristics (T = 25C unless otherwise noted) (continued)
A
Characteristic
Symbol
Min
Typ
Max
Unit
(1)
Functional Tests (In NXP Doherty Production Test Fixture, 50 ohm system) V = 48 Vdc, I
= 750 mA, V = 0.8 Vdc,
GSB
DD
DQA
P
= 102 W Avg., f = 920 MHz, Single--Carrier W--CDMA, IQ Magnitude Clipping, Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF.
out
ACPR measured in 3.84 MHz Channel Bandwidth @ 5 MHz Offset.
Power Gain
G
18.0
48.5
18.7
53.5
21.0
—
dB
%
ps
D
Drain Efficiency
P
@ 3 dB Compression Point, CW
P3dB
55.4
56.9
—
dBm
dBc
out
Adjacent Channel Power Ratio
ACPR
—
–29.5
–27.5
Wideband Ruggedness (In NXP Doherty Production Test Fixture, 50 ohm system) I
= 750 mA, V
= 0.8 Vdc, f = 940 MHz, Additive
GSB
DQA
White Gaussian Noise (AWGN) with 10 dB PAR
ISBW of 400 MHz at 55 Vdc, 239 W Avg. Modulated Output Power
(5 dB Input Overdrive from 107 W Avg. Modulated Output Power)
No Device Degradation
Typical Performance (In NXP Doherty Production Test Fixture, 50 ohm system) V = 48 Vdc, I
= 750 mA, V = 0.8 Vdc,
GSB
DD
DQA
920–960 MHz Bandwidth
(2)
P
@ 3 dB Compression Point
P3dB
—
—
512
–16
—
—
W
out
AM/PM
(Maximum value measured at the P3dB compression point across
the 920–960 MHz frequency range)
VBW Resonance Point
VBW
—
80
—
MHz
res
(IMD Third Order Intermodulation Inflection Point)
Gain Flatness in 40 MHz Bandwidth @ P = 102 W Avg.
G
—
—
0.6
—
—
dB
out
F
Gain Variation over Temperature
G
0.031
dB/C
(–40C to +85C)
Output Power Variation over Temperature
P1dB
—
0.009
—
dB/C
(–40C to +85C)
Table 5. Ordering Information
Device
Tape and Reel Information
Package
A2V09H400--04SR3
R3 Suffix = 250 Units, 32 mm Tape Width, 13--inch Reel
NI--780S--4L
1. Part internally input matched.
2. P3dB = P
+ 7.0 dB where P
is the average output power measured using an unclipped W--CDMA single--carrier input signal where
avg
avg
output PAR is compressed to 7.0 dB @ 0.01% probability on CCDF.
A2V09H400--04S
RF Device Data
NXP Semiconductors
3
C11
V
DDA
V
GGA
C12
C1
C2
C14
C3
D126606
C15
C13
R2
C4
C
R1
C16
C5
Z1
C6
P
C17
cut out
area
C8
C7
R3
C19
A2V09H400-04S
Rev. 0
C18
C9
C10
C21
C20
C22
V
DDB
V
GGB
aaa--035151
Figure 2. A2V09H400--04S Test Circuit Component Layout
Table 6. A2V09H400--04S Test Circuit Component Designations and Values
Part
Description
10 F Chip Capacitor
Part Number
Manufacturer
C1, C9, C12, C21
C5750X7S2A106M230KB
600F470JT250XT
600F3R3BT250XT
600F5R6BT250XT
600F6R2BT250XT
MCGPR100V477M16X32
600F110JT250XT
600F100JT250XT
600F120JT250XT
600F7R5JT250XT
600F3R9BT250XT
600F5R1BT250XT
C10A50Z4
TDK
C2, C3, C7, C10, C13, C20
47 pF Chip Capacitor
ATC
C4, C8
C5
3.3 pF Chip Capacitor
ATC
5.6 pF Chip Capacitor
ATC
C6
6.2 pF Chip Capacitor
ATC
C11, C22
C14
470 F, 100 V Electrolytic Capacitor
11 pF Chip Capacitor
Multicomp
ATC
C15
10 pF Chip Capacitor
ATC
C16
12 pF Chip Capacitor
ATC
C17
7.5 pF Chip Capacitor
ATC
C18
3.9 pF Chip Capacitor
ATC
C19
5.1 pF Chip Capacitor
ATC
R1
50 , 10 W Termination Chip Resistor
4.75 , 1/4 W Chip Resistor
800–1000 MHz, 90, 2 dB Asymmetric Coupler
Anaren
Vishay
RN2 Technologies
MTL
R2, R3
Z1
CRCW12064R75FKEA
CMX09Q02
PCB
Rogers RO4350B, 0.020, = 3.66
D126606
r
A2V09H400--04S
RF Device Data
NXP Semiconductors
4
P3dB LOAD PULL PERFORMANCE, CARRIER — 758–821 MHz
Table 7. Carrier Side Load Pull Performance — Maximum Power Tuning
V
= 48 Vdc, I
= 750 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
DD
DQA
Max Output Power
P3dB
(1)
Z
f
Z
Z
in
()
load
()
source
()
Gain (dB)
(dBm)
D
(%)
AM/PM ()
(MHz)
758
3.20 – j1.77
2.80 – j2.10
2.50 – j2.50
3.30 – j2.30
3.30 + j2.10
2.80 – j0.20
2.70 – j0.30
2.80 – j0.20
2.40 + j0.20
18.4
54.8
62.7
60.8
61.2
60.6
-- 1 4
790
803
821
3.00 + j2.50
2.90 + j2.60
2.90 + j2.80
18.5
18.5
18.9
54.7
54.7
54.6
-- 1 5
-- 1 5
-- 1 5
(1) Load impedance for optimum P3dB power.
Z
Z
Z
= Measured impedance presented to the input of the device at the package reference plane.
= Impedance as measured from gate contact to ground.
= Measured impedance presented to the output of the device at the package reference plane.
source
in
load
Table 8. Carrier Side Load Pull Performance — Maximum Efficiency Tuning
V
= 48 Vdc, I
= 750 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
DD
DQA
Max Drain Efficiency
P3dB
(1)
Z
f
Z
Z
in
()
load
()
source
()
Gain (dB)
(dBm)
D
(%)
AM/PM ()
(MHz)
758
3.20 – j1.77
2.80 – j2.10
2.50 – j2.50
3.30 – j2.30
3.04 + j2.10
2.60 + j1.70
2.70 + j1.70
2.50 + j2.10
2.30 + j2.20
20.2
53.9
73.3
-- 2 0
790
803
821
2.70 + j2.50
2.60 + j2.60
2.60 + j2.80
20.8
21.1
21.1
53.2
53.0
53.1
71.6
72.0
71.3
-- 2 4
-- 2 6
-- 2 4
(1) Load impedance for optimum P3dB efficiency.
Z
Z
Z
= Measured impedance presented to the input of the device at the package reference plane.
= Impedance as measured from gate contact to ground.
= Measured impedance presented to the output of the device at the package reference plane.
source
in
load
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Z
Z
in
Z
load
source
A2V09H400--04S
RF Device Data
NXP Semiconductors
5
P3dB LOAD PULL PERFORMANCE, PEAKING — 758–821 MHz
Table 9. Peaking Side Load Pull Performance — Maximum Power Tuning
V
= 48 Vdc, I
= 1000 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
DD
DQB
Max Output Power
P3dB
(1)
Z
f
Z
Z
in
()
load
()
source
()
Gain (dB)
(dBm)
D
(%)
AM/PM ()
(MHz)
758
1.90 – j4.10
2.10 – j4.30
1.90 – j4.40
2.10 – j4.40
1.90 + j3.80
1.90 – j1.02
2.00 – j0.70
1.60 – j0.60
1.70 – j0.40
18.1
56.5
60.8
62.2
59.3
59.8
-- 1 5
790
803
821
1.90 + j4.20
1.90 + j4.40
2.00 + j4.70
18.5
18.1
18.3
56.3
56.5
56.4
-- 1 6
-- 1 7
-- 1 8
(1) Load impedance for optimum P3dB power.
Z
Z
Z
= Measured impedance presented to the input of the device at the package reference plane.
= Impedance as measured from gate contact to ground.
= Measured impedance presented to the output of the device at the package reference plane.
source
in
load
Table 10. Peaking Side Load Pull Performance — Maximum Efficiency Tuning
V
= 48 Vdc, I
= 1000 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
DD
DQB
Max Drain Efficiency
P3dB
(1)
Z
f
Z
Z
in
()
load
()
source
()
Gain (dB)
(dBm)
D
(%)
AM/PM ()
(MHz)
758
1.90 – j4.10
2.10 – j4.30
1.90 – j4.40
2.10 – j4.40
1.80 + j3.80
2.10 + j0.90
2.00 + j0.41
1.80 + j0.60
1.60 + j0.70
20.4
54.9
72.2
-- 2 2
790
803
821
1.73 + j4.10
1.70 + j4.30
1.80 + j4.50
20.2
20.3
20.3
55.2
55.0
55.1
69.3
70.7
69.8
-- 2 2
-- 2 5
-- 2 5
(1) Load impedance for optimum P3dB efficiency.
Z
Z
Z
= Measured impedance presented to the input of the device at the package reference plane.
= Impedance as measured from gate contact to ground.
= Measured impedance presented to the output of the device at the package reference plane.
source
in
load
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Z
Z
in
Z
load
source
A2V09H400--04S
RF Device Data
NXP Semiconductors
6
PACKAGE DIMENSIONS
A2V09H400--04S
RF Device Data
NXP Semiconductors
7
A2V09H400--04S
RF Device Data
NXP Semiconductors
8
PRODUCT DOCUMENTATION, SOFTWARE AND TOOLS
Refer to the following resources to aid your design process.
Application Notes
AN1908: Solder Reflow Attach Method for High Power RF Devices in Air Cavity Packages
AN1955: Thermal Measurement Methodology of RF Power Amplifiers
Software
Electromigration MTTF Calculator
.s2p File
Development Tools
Printed Circuit Boards
REVISION HISTORY
The following table summarizes revisions to this document.
Revision
Date
Description
0
1
2
Sept. 2019
Jan. 2021
Feb. 2021
Initial release of data sheet
Added 700 MHz performance table with corresponding measured data, p. 1
Tables 7–10, Load Pull Performance: added Carrier Side and Peaking Side load pull performance tables
showing P3dB performance across the 758–821 MHz band, pp. 5–6
A2V09H400--04S
RF Device Data
NXP Semiconductors
9
Information in this document is provided solely to enable system and software
implementers to use NXP products. There are no express or implied copyright licenses
granted hereunder to design or fabricate any integrated circuits based on the information
in this document. NXP reserves the right to make changes without further notice to any
products herein.
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products for any particular purpose, nor does NXP assume any liability arising out of the
application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation consequential or incidental damages. “Typical” parameters
that may be provided in NXP data sheets and/or specifications can and do vary in
different applications, and actual performance may vary over time. All operating
parameters, including “typicals,” must be validated for each customer application by
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names are the property of their respective owners.
E 2019, 2021 NXP B.V.
Document Number: A2V09H400--04S
Rev. 2, 02/2021
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