74HCT583PW-T [NXP]
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| 型号： | 74HCT583PW-T |
| 厂家： | 
NXP |
| 描述： | 暂无描述 运算电路 逻辑集成电路 光电二极管 |
| 文件： | 总13页 (文件大小：72K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT583
4-bit full adder with fast carry
1998 Mar 31
Product specification
Supersedes data of December 1990
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
4-bit full adder with fast carry
74HC/HCT583
The “583” generates the decimal sum outputs (∑0 to ∑3)
FEATURES
and a carry output (Cn+4) if the sum is greater than 9.
• Adds two decimal numbers
• Full internal look-ahead
If an addition of two BCD numbers produce a number
greater than 9, a valid BCD number and a carry will result.
For input values larger than 9, the number is converted
from binary to BCD. Binary to BCD conversion occurs by
grounding one set of inputs, An or Bn and applying a 4-bit
binary number to the other set of inputs. If the input is
between 0 and 9, a BCD number occurs at the output.
If the binary input falls between 10 and 15, a carry term is
generated. Both the carry term and the sum are the BCD
equivalent of the binary input. Converting binary numbers
greater than 16 may be achieved by cascading “583s”.
• Fast ripple carry for economical expansion
• Output capability: standard driver
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT583 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JECEC
standard no. 7A.
See the “283” for the binary version.
The 74HC/HCT583 are high-speed 4-bit BCD full adders
with internal carry look-ahead. They accept two 4-bit
decimal numbers (A0 to A3 and B0 to B3) and a carry input
(CIN).
QUICK REFERENCE DATA
GND = 0 V; Tamb= 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PHL/ tPLH
PARAMETER
CONDITIONS
UNIT
HC
HCT
t
propagation delay
CL = 15 pF; VCC = 5 V
C
IN to Cn+4
20
23
ns
ns
pF
pF
An, Bn to Cn+4
23
27
CI
input capacitance
3.5
116
3.5
120
CPD
power dissipation capacitance per package
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
1998 Mar 31
2
Philips Semiconductors
Product specification
4-bit full adder with fast carry
74HC/HCT583
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
74HC583
74HC583
74HCT583
74HCT583
DIP16
SO16
DIP16
SO16
plastic dual in-line package; 16 leads (300 mil); long body
plastic small outline package; 16 leads; body width 3.9 mm
plastic dual in-line package; 16 leads (300 mil); long body
plastic small outline package; 16 leads; body width 3.9 mm
SOT38-1
SOT109-1
SOT38-1
SOT109-1
PIN DESCRIPTION
PIN NO.
SYMBOL NAME AND FUNCTION
handbook, halfpage
5
CIN
carry input
B
B
B
A
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
A
A
A
B
1
2
3
3
CC
2
6
Cn+4
carry output
8
GND
ground (0 V)
1
11, 10, 7, 9
12, 1, 2, 3
13, 14, 15, 4
16
∑0 to ∑3
B0 to B3
A0 to A3
VCC
sum outputs
B operand inputs
A operand inputs
positive supply voltage
0
583
C
IN
0
C
∑
∑
∑
n + 4
0
1
3
∑
2
GND
MGM851
Fig.1 Pin configuration.
handbook, halfpage
13
∑
0
(BCD)
14
P
15
4
11
10
7
handbook, halfpage
A
A
A
3
A
B
B
1
B
B
6
1
2
0
0
0
3
2
3
13 12 14
1
15
2
9
4
3
3
0
∑
C
C
IN
n + 4
12
1
5
9
11 10
7
Q
2
∑
∑
∑
∑
2
3
0
1
MGM852
3
3
5
6
C1
C0
MGM853
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
1998 Mar 31
3
Philips Semiconductors
Product specification
4-bit full adder with fast carry
74HC/HCT583
handbook, halfpage
A
B
A
B
A
B
2
A
4
B
3
0
0
1
1
2
2
3
3
13 12 14
1
15
C
C
5
6
IN
n + 4
11 10
7
9
∑
∑
∑
∑
0
1
2
3
MGM854
Fig.4 Functional diagram.
1998 Mar 31
4
Philips Semiconductors
Product specification
4-bit full adder with fast carry
74HC/HCT583
S
0
B
0
A
0
S
1
B
1
A
1
B
2
S
2
A
2
B
3
S
3
A
3
C
IN
C
n + 4
MGM856
Fig.5 Logic diagram.
5
1998 Mar 31
Philips Semiconductors
Product specification
4-bit full adder with fast carry
74HC/HCT583
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
T
amb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
typ.
−40 to +85 −40 to +125
min.
max.
min. max.
min.
max.
tPHL/ tPLH propagation delay
50
155
31
195
39
235
47
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.0 Fig.6
4.5
CIN to ∑0
18
14
26
33
40
6.0
t
t
t
t
t
t
PHL/ tPLH propagation delay
113 350
440
88
525
105
90
2.0 Fig.6
4.5
CIN to ∑1
41
33
70
60
75
6.0
PHL/ tPLH propagation delay
100 305
380
76
460
92
2.0 Fig.6
4.5
CIN to ∑2
36
29
61
52
65
78
6.0
PHL/ tPLH propagation delay
110 340
425
85
510
102
87
2.0 Fig.6
4.5
CIN to ∑3
40
32
50
18
14
68
58
155
31
26
72
6.0
PHL/ tPLH propagation delay
195
39
235
47
2.0 Fig.6
4.5
An or Bn to ∑0
33
40
6.0
PHL/ tPLH propagation delay
120 365
455
91
550
110
94
2.0 Fig.6
4.5
An or Bn to ∑1
43
34
73
62
77
6.0
PHL/ tPLH propagation delay
105 325
405
81
490
98
2.0 Fig.6
4.5
An or Bn to ∑2
38
30
65
55
69
83
6.0
tPHL/ tPLH propagation delay
116 355
445
89
535
107
91
2.0 Fig.6
4.5
An or Bn to ∑3
42
34
63
23
18
72
26
21
71
60
76
6.0
tPHL/ tPLH propagation delay
CIN to Cn+4
195
39
245
49
295
59
2.0 Fig.6
4.5
33
42
50
6.0
tPHL/ tPLH propagation delay
An to Cn+4
220
44
275
55
330
66
2.0 Fig.6
4.5
37
47
56
6.0
1998 Mar 31
6
Philips Semiconductors
Product specification
4-bit full adder with fast carry
74HC/HCT583
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
typ.
−40 to +85 −40 to +125
min.
max.
min. max.
min.
max.
tPHL/ tPLH propagation delay
Bn to Cn+4
74
27
230
46
39
75
15
13
290
58
49
95
19
16
345
69
ns
ns
2.0 Fig.6
4.5
22
19
7
59
6.0
tTHL/ tTLH output transition time
standard outputs
110
22
2.0 Fig.6
4.5
6
19
6.0
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
An, Bn
CIN
0.4
1.5
1998 Mar 31
7
Philips Semiconductors
Product specification
4-bit full adder with fast carry
74HC/HCT583
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
typ.
−40 to +85 −40 to +125
min.
max. min. max.
min.
max.
tPHL/ tPLH propagation delay
20
34
43
85
81
81
46
91
85
88
58
66
64
19
51
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5 Fig.6
4.5 Fig.6
4.5 Fig.6
4.5 Fig.6
4.5 Fig.6
4.5 Fig.6
4.5 Fig.6
4.5 Fig.6
4.5 Fig.6
4.5 Fig.6
4.5 Fig.6
4.5 Fig.6
CIN to ∑0
t
PHL/ tPLH propagation delay
40
38
38
22
43
40
41
27
31
30
7
68
65
65
37
73
68
70
46
53
51
15
102
98
CIN to ∑1
tPHL/ tPLH propagation delay
CIN to ∑2
t
t
t
PHL/ tPLH propagation delay
IN to ∑3
98
C
PHL/ tPLH propagation delay
56
An or Bn to ∑0
PHL/ tPLH propagation delay
110
102
105
69
An or Bn to ∑1
tPHL/ tPLH propagation delay
An or Bn to ∑2
t
PHL/ tPLH propagation delay
An or Bn to ∑3
tPHL/ tPLH propagation delay
CIN to Cn+4
t
t
t
PHL/ tPLH propagation delay
An to Cn+4
80
PHL/ tPLH propagation delay
Bn to Cn+4
77
THL/ tTLH output transition time
standard outputs
22
1998 Mar 31
8
Philips Semiconductors
Product specification
4-bit full adder with fast carry
74HC/HCT583
AC WAVEFORMS
b
C
, A , B
IN
n
n
(1)
V
M
t
INPUT
t
PHL
PLH
∑ , C
n + 4
OUTPUT
n
(1)
V
M
t
t
MGM855
THL
TLH
(1) HC: VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.6 Waveforms showing the inputs (CIN, An, Bn) to the outputs (∑n, Cn+4) propagation delays and the output
transition times.
1998 Mar 31
9
Philips Semiconductors
Product specification
4-bit full adder with fast carry
74HC/HCT583
PACKAGE OUTLINES
DIP16: plastic dual in-line package; 16 leads (300 mil); long body
SOT38-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
c
D
E
e
e
L
M
M
H
1
1
E
max.
max.
min.
max.
1.40
1.14
0.53
0.38
0.32
0.23
21.8
21.4
6.48
6.20
3.9
3.4
8.25
7.80
9.5
8.3
4.7
0.51
3.7
2.54
0.10
7.62
0.30
0.254
0.01
2.2
0.021
0.015
0.013
0.009
0.86
0.84
0.32
0.31
0.055
0.045
0.26
0.24
0.15
0.13
0.37
0.33
inches
0.19
0.020
0.15
0.087
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-10-02
95-01-19
SOT38-1
050G09
MO-001AE
1998 Mar 31
10
Philips Semiconductors
Product specification
4-bit full adder with fast carry
74HC/HCT583
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
H
v
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.050
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-01-23
97-05-22
SOT109-1
076E07S
MS-012AC
1998 Mar 31
11
Philips Semiconductors
Product specification
4-bit full adder with fast carry
74HC/HCT583
Several techniques exist for reflowing; for example,
SOLDERING
Introduction
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
WAVE SOLDERING
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(order code 9398 652 90011).
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
DIP
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
SOLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
• The package footprint must incorporate solder thieves at
the downstream end.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
REPAIRING SOLDERED JOINTS
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
SO
REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
1998 Mar 31
12
Philips Semiconductors
Product specification
4-bit full adder with fast carry
74HC/HCT583
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1998 Mar 31
13
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