933372740652 [NXP]
IC 4000/14000/40000 SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, PLASTIC, SOT-109-1, SO-16, Shift Register;
| 型号： | 933372740652 |
| 厂家： | 
NXP |
| 描述： | IC 4000/14000/40000 SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, PLASTIC, SOT-109-1, SO-16, Shift Register 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总6页 (文件大小：68K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4021B
MSI
8-bit static shift register
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4021B
MSI
8-bit static shift register
Each register stage is a D-type master-slave flip-flop with
a set direct/clear direct input. Information on P0 to P7 is
asynchronously loaded into the register while PL is HIGH,
independent of CP and DS. When PL is LOW, data on
DS is shifted into the first register position and all the data
in the register is shifted one position to the right on the
LOW to HIGH transition of CP. Schmitt-trigger action in the
clock input makes the circuit highly tolerant to slower clock
rise and fall times.
DESCRIPTION
The HEF4021B is an 8-bit static shift register
(parallel-to-serial converter) with a synchronous serial
data input (DS), a clock input (CP), an asynchronous active
HIGH parallel load input (PL), eight asynchronous parallel
data inputs (P0 to P7) and buffered parallel outputs from
the last three stages (05 to O7).
Fig.1 Functional diagram.
HEF4021BP(N):
16-lead DIL; plastic
(SOT38-1)
HEF4021BD(F):
HEF4021BT(D):
16-lead DIL; ceramic (cerdip)
(SOT74)
16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
PINNING
PL
parallel load input
P0 to P7
DS
parallel data inputs
serial data input
CP
clock input (LOW to HIGH edge-triggered)
O5 to O7
buffered parallel outputs from the last three stages
January 1995
2
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Fig.3 Logic diagram.
Philips Semiconductors
Product specification
HEF4021B
MSI
8-bit static shift register
FUNCTION TABLES
Serial operation
Parallel operation
INPUTS
OUTPUTS
INPUTS
OUTPUTS
n
1
2
3
6
7
8
CP
DS
D1
D2
D3
X
PL
L
O5
X
O6
O7
X
n
CP
DS
PL
O5
O6
O7
X
X
X
H
P5
P6
P7
L
X
X
X
Notes
L
X
X
X
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
L
D1
D2
D3
X
D1
X
X
L
X
= positive-going transition
= negative-going transition
X
L
D2
D1
Dn = either HIGH or LOW
n = number of clock pulse transitions
X
L
no change
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL MIN.
TYP.
MAX.
Propagation delays
CP → On
HIGH to LOW
5
125
55
250
110
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
98 ns
44 ns
32 ns
88 ns
39 ns
32 ns
93 ns
44 ns
32 ns
78 ns
39 ns
32 ns
10 ns
9 ns
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
(0,55 ns/pF) CL
(0,23 ns/pF) CL
(0,16 ns/pF) CL
(0,55 ns/pF) CL
(0,23 ns/pF) CL
(0,16 ns/pF) CL
(0,55 ns/pF) CL
(0,23 ns/pF) CL
(0,16 ns/pF) CL
(0,55 ns/pF) CL
(0,23 ns/pF) CL
(0,16 ns/pF) CL
(1,0 ns/pF) CL
(0,42 ns/pF) CL
(0,28 ns/pF) CL
(1,0 ns/pF) CL
(0,42 ns/pF) CL
(0,28 ns/pF) CL
10
15
5
tPHL
tPLH
tPHL
tPLH
tTHL
tTLH
40
115
50
230
100
80
LOW to HIGH
10
15
5
40
PL → On
120
55
240
110
80
HIGH to LOW
10
15
5
40
105
50
210
100
80
LOW to HIGH
10
15
5
40
Output transition
times
HIGH to LOW
60
120
60
10
15
5
30
20
40
6 ns
60
120
60
10 ns
9 ns
LOW to HIGH
10
15
30
20
40
6 ns
January 1995
4
Philips Semiconductors
Product specification
HEF4021B
MSI
8-bit static shift register
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
MIN.
TYP.
MAX.
Set-up time
5
25
25
15
50
30
20
40
20
15
15
15
15
70
30
24
70
30
24
50
40
35
6
−15
−10
−5
25
10
5
ns
DS → CP
10
15
5
tsu
ns
ns
ns
Pn → PL
10
15
5
tsu
ns
ns
Hold times
20
10
8
ns
DS → CP
10
15
5
thold
thold
tWCPL
tWPLH
tRPL
fmax
ns
ns
−10
0
ns
see also waveforms
Figs 4 and 5
Pn → PL
10
15
5
ns
0
ns
Minimum clock
35
15
12
35
15
12
10
5
ns
pulse width; LOW
10
15
5
ns
ns
Minimum PL
pulse width; HIGH
ns
10
15
5
ns
ns
Recovery time
for PL
ns
10
15
5
ns
5
ns
Maximum clock
13
30
40
MHz
MHz
MHz
pulse frequency
10
15
15
20
VDD
V
TYPICAL FORMULA FOR P (µW)
2
Dynamic power
dissipation per
package (P)
5
10
15
900 fi + ∑ (foCL) × VDD
where
2
4 300 fi + ∑ (foCL) × VDD
fi = input freq. (MHz)
2
12 000 fi + ∑ (foCL) × VDD
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
5
Philips Semiconductors
Product specification
HEF4021B
MSI
8-bit static shift register
Fig.4 Waveforms showing minimum clock pulse width, set-up time and hold time for CP and DS.
Fig.5 Waveforms showing minimum PL pulse width, recovery time for PL, and set-up and hold times for Pn to
PL. Set-up and hold times are shown as positive values but may be specified as negative values.
January 1995
6
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