935323702557 [NXP]
Microprocessor Circuit;型号: | 935323702557 |
厂家: | NXP |
描述: | Microprocessor Circuit 外围集成电路 |
文件: | 总91页 (文件大小:1259K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
NXP Semiconductors
MKW41Z512
Data Sheet: Technical Data
Rev. 4, 03/2018
MKW41Z/31Z/21Z Data Sheet
MKW41Z512
A Bluetooth® Low Energy, IEEE® Standard 802.15.4,
Generic FSK System on a Chip (SoC) Supports the
following: MKW41Z512VHT4, MKW31Z512VHT4,
MKW21Z512VHT4, MKW41Z256VHT4, MKW31Z256VHT4,
MKW21Z256VHT4,MKW41Z512CAT4,MKW31Z512CAT4
MKW31Z512
MKW21Z512
MKW41Z256
MKW31Z256
MKW21Z256
48 LQFN
7 x 7 x 0.98 mm Pitch 3.893 x 3.797 x 0.564
0.5 mm mm Pitch 0.4 mm
75 WLCSP
Multi-Standard Radio
System peripherals
• 2.4 GHz Bluetooth Low Energy ver. 4.2 compliant
supporting up to 2 simultaneous hardware connections
• IEEE Std. 802.15.4 compliant with dual-PAN support
• Generic FSK modulation
• Nine MCU low-power modes to provide power
optimization based on application requirements
• DC-DC Converter supporting Buck, Boost, and
Bypass operating modes
• Data Rate: 250, 500 and 1000 kbps
• Modulations: GFSK BT = 0.3, 0.5, 0.7; FSK/MSK
• Modulation Index: 0.32, 0.5, or 0.7
• Direct memory access(DMA) Controller
• Computer operating properly(COP) watchdog
• Serial wire debug(SWD) Interface and Micro Trace
buffer
• Typical Receiver Sensitivity (BLE) = -95 dBm
• Typical Receiver Sensitivity (802.15.4) = -100 dBm
• Typical Receiver Sensitivity (250 kbps GFSK-BT=0.5,
h=0.5) = -100 dBm
• Bit Manipulation Engine (BME)
Analog Modules
• 16-bit Analog-to-Digital Converter (ADC)
• 12-bit Digital-to-Analog Converter (DAC)
• 6-bit High Speed Analog Comparator (CMP)
• 1.2 V voltage reference (VREF)
• Prog Transmitter Output Power: -30 dBm to 3.5 dBm
• Low external component counts for low cost application
• On-chip balun with single ended bidirectional RF port
MCU and Memories
Timers
• Up to 48 MHz ARM® Cortex-M0+ core
• On-chip 512/256 KB Flash memory
• On-chip 128/64 KB SRAM
• 16-bit low-power timer (LPTMR)
• 3 Timers Modules(TPM): One 4 channel TPM and
two 2 channel TPMs
Low Power Consumption
• Programmable Interrupt Timer (PIT)
• Real-Time Clock (RTC)
• Transceiver current (DC-DC buck mode, 3.6 V supply)
• Typical Rx Current: 6.8 mA
Communication interfaces
• Typical Tx current: 6.1 mA (0 dBm output)
• Low Power Mode (VLLS0) Current: 182 nA
• 2 serial peripheral interface (SPI) modules
• 2 inter-integrated circuit (I2C) modules
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Clocks
• 26 and 32 MHz supported for BLE and FSK modes
• Low Power UART module
• Carrier Modulator Timer (CMT)
• 32 MHz supported for IEEE Standard 802.15.4
• 32.768 kHz Crystal Oscillator
Security
• AES-128 Hardware Accelerator (AESA)
• True Random Number Generator (TRNG)
• Advanced flash security
• 80-bit unique identification number per chip
• 40-bit unique media access control (MAC) sub-
address
Operating Characteristics
• Voltage range: 0.9 V to 4.2 V
• Temperature range:
• –40 to 105 °C (Laminate-QFN)
• –40 to 85 °C (WLCSP)
• Bluetooth-LE v4.2 Secure Connections
• IEEE Standard 802.15.4-2011 compliant security
Human-machine interface
• Touch sensing input
• General-purpose input/output
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MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
NXP Semiconductors
Table of Contents
1
2
3
Introduction......................................................................... 4
7.2.9 Capacitance attributes..................................... 46
7.3 Switching electrical specifications................................46
7.3.1 Device clock specifications.............................. 46
7.3.2 General switching specifications......................47
7.4 Thermal specifications................................................. 48
7.4.1 Thermal operating requirements......................48
7.4.2 Thermal attributes............................................ 48
7.5 Peripheral operating requirements and behaviors.......49
7.5.1 Core modules...................................................49
7.5.2 System modules.............................................. 51
7.5.3 Clock modules................................................. 51
7.5.4 Memories and memory interfaces....................54
7.5.5 Security and integrity modules.........................56
7.5.6 Analog..............................................................56
7.5.7 Timers.............................................................. 67
7.5.8 Communication interfaces................................67
7.5.9 Human-machine interfaces (HMI).................... 72
7.6 DC-DC Converter Operating Requirements................ 73
7.7 Ratings.........................................................................76
7.7.1 Thermal handling ratings................................. 76
7.7.2 Moisture handling ratings.................................76
7.7.3 ESD handling ratings....................................... 76
7.7.4 Voltage and current operating ratings..............77
Pin Diagrams and Pin Assignments....................................77
8.1 Pinouts.........................................................................77
8.2 Signal Multiplexing and Pin Assignments.................... 79
8.3 Module Signal Description Tables............................... 83
8.3.1 Core Modules...................................................83
8.3.2 Radio Modules................................................. 83
8.3.3 System Modules.............................................. 84
8.3.4 Clock Modules................................................. 85
8.3.5 Analog Modules............................................... 86
8.3.6 Timer Modules................................................. 87
8.3.7 Communication Interfaces............................... 87
8.3.8 Human-Machine Interfaces(HMI).....................89
Package Information........................................................... 89
9.1 Obtaining package dimensions....................................89
Ordering Information........................................................... 5
Feature Descriptions........................................................... 5
3.1 Block Diagram..............................................................5
3.2 Radio features..............................................................6
3.3 Microcontroller features............................................... 7
3.4 System features...........................................................8
3.5 Peripheral features.......................................................11
3.6 Security Features.........................................................15
Transceiver Description.......................................................17
4.1 Key Specifications........................................................17
4.2 Channel Map Frequency Plans ...................................18
4.2.1 Channel Plan for Bluetooth Low Energy.......... 18
4.2.2 Channel Plan for IEEE 802.15.4 in 2.4GHz
4
ISM and MBAN frequency bands.....................19
4.2.3 Other Channel Plans .......................................20
4.3 Transceiver Functions..................................................21
Transceiver Electrical Characteristics................................. 21
5.1 Radio operating conditions.......................................... 21
5.2 Receiver Feature Summary.........................................22
5.3 Transmit and PLL Feature Summary...........................25
System and Power Management........................................ 28
6.1 Power Management.....................................................28
6.1.1 DC-DC Converter.............................................29
6.2 Modes of Operation..................................................... 29
6.2.1 Power modes................................................... 29
MCU Electrical Characteristics............................................32
7.1 AC electrical characteristics.........................................32
7.2 Nonswitching electrical specifications..........................32
7.2.1 Voltage and current operating requirements....32
7.2.2 LVD and POR operating requirements............ 33
7.2.3 Voltage and current operating behaviors......... 34
7.2.4 Power mode transition operating behaviors.....35
7.2.5 Power consumption operating behaviors.........36
7.2.6 Diagram: Typical IDD_RUN operating
5
6
8
7
behavior........................................................... 44
9
10 Revision History.................................................................. 90
7.2.7 SoC Power Consumption.................................45
7.2.8 Designing with radiated emissions in mind...... 46
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
3
NXP Semiconductors
Introduction
1 Introduction
The KW41Z/31Z/21Z (called KW41Z throughout this document) is an ultra low-power,
highly integrated single-chip device that enables Bluetooth low energy (BLE), Generic
FSK (at 250, 500 and 1000 kbps) or IEEE Standard 802.15.4 RF connectivity for
portable, extremely low-power embedded systems. Applications include portable health
care devices, wearable sports and fitness devices, AV remote controls, computer
keyboards and mice, gaming controllers, access control, security systems, smart energy
and home area networks.
The KW41Z SoC integrates a radio transceiver operating in the 2.36 GHz to 2.48 GHz
range supporting a range of FSK/GFSK and O-QPSK modulations, an ARM Cortex-
M0+ CPU, up to 512 KB Flash and up to 128 KB SRAM, BLE Link Layer hardware,
802.15.4 packet processor hardware and peripherals optimized to meet the requirements
of the target applications.
The KW41Z SoC’s radio frequency transceiver is compliant with Bluetooth version 4.2
for Low Energy (aka Bluetooth Smart or BLE), Generic FSK and the IEEE Standard
802.15.4 using O-QPSK in the 2.4 GHz ISM band. NXP provides fully certified
Bluetooth Low Energy and IEEE Standard 802.15.4 protocol stacks, including Zigbee
3.0, Thread, and application profiles to support KW41Z.
The KW41Z SoC can be used in applications as a "BlackBox" modem by simply
adding BLE or IEEE Standard 802.15.4 connectivity to an existing embedded controller
system, or used as a stand-alone smart wireless sensor with embedded application
where no host controller is required.
KW41Z has 512/256 KB of on-chip Flash and 128/64 KB of on-chip SRAM memory
available to be used by customer applications and chosen communication protocol stack
using a choice of either NXP or 3rd party software development tools.
The RF section of the KW41Z SoC is optimized to require very few external
components, achieving the smallest RF footprint possible on a printed circuit board.
Extremely long battery life is achieved though efficiency of code execution in the
Cortex-M0+ CPU core and the multiple low power operating modes of the KW41Z
SoC. Additionally, an integrated DC-DC converter enables a wide operating range from
0.9 V to 4.2 V. The DC-DC in Buck mode enables KW41Z to operate from a single
coin cell battery with a significant reduction of peak Rx and Tx current consumption.
The DC-DC in boost mode enables a single alkaline battery to be used throughout its
entire useful voltage range of 0.9 V to 1.795 V.
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MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
NXP Semiconductors
Ordering Information
2 Ordering Information
Table 1. Orderable parts details
Memory
Configuration
Device
Part Marking
Package
Description
MKW21Z512VHT4(R)
M21W9VT4
512 KB Flash
128 KB SRAM
256 KB Flash
64 KB SRAM
512 KB Flash
128 KB SRAM
512 KB Flash
128 KB SRAM
256 KB Flash
64 KB SRAM
512 KB Flash
128 KB SRAM
48-pin Laminate IEEE 802.15.4
QFN
MKW21Z256VHT4(R)
MKW31Z512CAT4R
MKW31Z512VHT4(R)
MKW31Z256VHT4(R)
MKW41Z512CAT4R
M21W8VT4
MKW31Z512CAT4
M31W9VT4
75-pin WLCSP
Bluetooth Low Energy and
Generic FSK
48-pin Laminate Bluetooth Low Energy and
QFN
Generic FSK
M31W8VT4
MKW41Z512CAT4
75-pin WLCSP
Bluetooth Low Energy and
IEEE 802.15.4 and Generic
FSK
MKW41Z512VHT4(R)
MKW41Z256VHT4(R)
M41W9VT4
M41W8VT4
512 KB Flash
128 KB SRAM
256 KB Flash
64 KB SRAM
48-pin Laminate Bluetooth Low Energy and
QFN
IEEE 802.15.4 and Generic
FSK
3 Feature Descriptions
This section provides a simplified block diagram and highlights the KW41Z features.
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
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NXP Semiconductors
Feature Descriptions
3.1 Block Diagram
ARM Cortex M0+ Core
32K Osc
IRC
MCG
DMA MUX
4ch DMA
Serial Wire Debug
DAP MDM
NVIC
WIC
4 MHz
DWT
MTB
26M or
32M OSC
IRC
32 kHz
FLL
IOPORT
Unified Bus
AHBLite
AHBLite
M2A
M0
Crossbar-Lite Switch (XBS)
S2
S0
S1
SIM
ADC
I2C x2
BME
PIT
GPIO
Flash
128/64 KB
SRAM
Controller
SMC
RCM
PMC
CMP
TPM x3
LPTMR
RTC
LPUART
SPI x2
CMT
AIPS-Lite
Flash
512/256 KB
DAC
Radio
TRNG
TSI
IPS
VREF
IPS
APB
VDCDC_IN
DCDC
Figure 1. KW41Z Detailed Block Diagram
3.2 Radio features
Operating frequencies:
• 2.4 GHz ISM band (2400-2483.5 MHz)
• MBAN 2360-2400 MHz
Supported standards:
• Bluetooth v4.2 Low Energy compliant 1 Mbps GFSK modulation supporting up to
2 simultaneous connections in hardware (master-slave, master-master, slave-slave)
• IEEE Standard 802.15.4-2011 compliant O-QPSK modulation and security features
• Zigbee 3.0
• Thread Networking Stack
• Bluetooth Low Energy(BLE) Application Profiles
Receiver performance:
• Receive sensitivity of -95 dBm for BLE
• Receive sensitivity of -100 dBm typical for IEEE Standard 802.15.4
• Receive sensitivity of up to -100 dBm for a 250 kbps GFSK mode with a
modulation index of 0.5. Receive sensitivity in generic FSK modes depends on
mode selection and data rate.
Other features:
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MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
NXP Semiconductors
Feature Descriptions
• Programmable transmit output power from -30 dBm to 3.5 dBm
• Integrated on-chip balun
• Single ended bidirectional RF port shared by transmit and receive
• Low external component count
• Supports transceiver range extension using external PA and/or LNA
• 26 and 32 MHz supported for BLE and FSK modes
• 32 MHz supported for IEEE Standard 802.15.4
• Bluetooth Low Energy ver. 4.2 Link Layer hardware with 2 independent
hardware connection engines
• Hardware acceleration for IEEE Standard 802.15.4 packet processing/link layer
• Hardware acceleration for Generic FSK packet processing
• Supports dual PAN for IEEE Standard 802.15.4 with hardware-assisted address
matching acceleration
• Generic FSK modulation at 250, 500 and 1000 kbps
• Supports antenna diversity option for IEEE Std. 802.15.4
3.3 Microcontroller features
ARM Cortex-M0+ CPU
• Up to 48 MHz CPU
• As compared to Cortex-M0, the Cortex-M0+ uses an optimized 2-stage pipeline
microarchitecture for reduced power consumption and improved architectural
performance (cycles per instruction)
• Supports up to 32 interrupt request sources
• Binary compatible instruction set architecture with the Cortex-M0 core
• Thumb instruction set combines high code density with 32-bit performance
• Serial Wire Debug (SWD) reduces the number of pins required for debugging
• Micro Trace Buffer (MTB) provides lightweight program trace capabilities using
system RAM as the destination memory
Nested Vectored Interrupt Controller (NVIC)
• 32 vectored interrupts, 4 programmable priority levels
• Includes a single non-maskable interrupt
Wake-up Interrupt Controller (WIC)
• Supports interrupt handling when system clocking is disabled in low power
modes
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
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NXP Semiconductors
Feature Descriptions
• Takes over and emulates the NVIC behavior when correctly primed by the NVIC
on entry to very-deep-sleep
• A rudimentary interrupt masking system with no prioritization logic signals for
wake-up as soon as a non-masked interrupt is detected
Debug Controller
• Two-wire Serial Wire Debug (SWD) interface
• Hardware breakpoint unit for 2 code addresses
• Hardware watchpoint unit for 2 data items
• Micro Trace Buffer for program tracing
On-Chip Memory
• 512/256 KB
• Firmware distribution protection. Program flash can be marked execute-only
on a per-sector (8 KB) basis to prevent firmware contents from being read by
third parties
• Flash implemented as two equal blocks each of 256 KB block. Code can
execute or read from one block while the other block is being erased or
programmed.
• 128/64 KB SRAM
• Security circuitry to prevent unauthorized access to RAM and flash contents
through the debugger
3.4 System features
Power Management Control Unit (PMC)
• Programmable power saving modes
• Available wake-up from power saving modes via internal and external sources
• Integrated Power-on Reset (POR)
• Integrated Low Voltage Detect (LVD) with reset (brownout) capability
• Selectable LVD trip points
• Programmable Low Voltage Warning (LVW) interrupt capability
• Individual peripheral clocks can be gated off to reduce current consumption
• Internal Buffered bandgap reference voltage
• Factory programmed trim for bandgap and LVD
• 1 kHz Low Power Oscillator (LPO)
DC-DC Converters
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MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
NXP Semiconductors
Feature Descriptions
• Internal switched mode power supply supporting Buck, Boost, and Bypass
operating modes
• Buck operation supports external voltage sources of 2.1 V to 4.2 V. This reduces
peak current consumption during Rx and Tx by ~25%, ideal for single coin-cell
battery operation (typical CR2032 cell).
• Boost operation supports external voltage sources of 0.9 V to 1.795 V, which is
efficiently increased to the static internal core voltage level, ideal for single
battery operation (typical AA or AAA alkaline cell).
• When DC-DC is not used, the device supports an external voltage range of 1.5 V
to 3.6 V (1.5 - 3.6 V on VDD_RF1, VDD_RF2, VDD_XTAL and
VDD_1P5OUT_PMCIN pins. 1.71 - 3.6 V on VDD_0, VDD_1 and VDDA pins)
• An external inductor is required to support the Buck or Boost modes
• The DC-DC Converter 1.8 V output current drive for external devices (MCU in
RUN mode, Radio is enabled, other peripherals are disabled)
• Up to 44 mA in buck mode with VDD_1P8 = 1.8 V
• Up to 31.4 mA in buck mode with VDD_1P8 = 3.0 V
Direct Memory Access (DMA) Controller
• All data movement via dual-address transfers: read from source, write to
destination
• Programmable source and destination addresses and transfer size
• Support for enhanced addressing modes
• 4-channel implementation that performs complex data transfers with minimal
intervention from a host processor
• Internal data buffer, used as temporary storage to support 16- and 32-byte
transfers
• Connections to the crossbar switch for bus mastering the data movement
• Transfer control descriptor (TCD) organized to support two-deep, nested transfer
operations
• 32-byte TCD stored in local memory for each channel
• An inner data transfer loop defined by a minor byte transfer count
• An outer data transfer loop defined by a major iteration count
• Channel activation via one of three methods:
• Explicit software initiation
• Initiation via a channel-to-channel linking mechanism for continuous
transfers
• Peripheral-paced hardware requests, one per channel
• Fixed-priority and round-robin channel arbitration
• Channel completion reported via optional interrupt requests
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
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NXP Semiconductors
Feature Descriptions
• One interrupt per channel, optionally asserted at completion of major iteration
count
• Optional error terminations per channel and logically summed together to form one
error interrupt to the interrupt controller
• Optional support for scatter/gather DMA processing
• Support for complex data structures
DMA Channel Multiplexer (DMA MUX)
• 4 independently selectable DMA channel routers
• 2 periodic trigger sources available
• Each channel router can be assigned to 1 of the peripheral DMA sources
COP Watchdog Module
• Independent clock source input (independent from CPU/bus clock)
• Choice between two clock sources
• LPO oscillator
• Bus clock
System Clocks
• Both 26 MHz and 32 MHz crystal reference oscillator supported for BLE and FSK
radio modes
• 32 MHz crystal reference oscillator supported for IEEE 802.15.4 radio mode
• MCU can derive its clock either from the crystal reference oscillator or the
frequency locked loop (FLL)1
• 32.768 kHz crystal reference oscillator used to maintain precise Bluetooth radio
time in low power modes
• Multipurpose Clock Generator (MCG)
• Internal reference clocks — Can be used as a clock source for other on-chip
peripherals
• On-chip RC oscillator range of 31.25 kHz to 39.0625 kHz with 2% accuracy
across full temperature range
• On-chip 4MHz oscillator with 5% accuracy across full temperature range
• Frequency-locked loop (FLL) controlled by internal or external reference
• 20 MHz to 48 MHz FLL output
Unique Identifiers
• 10 bytes(or 80-bits) of the Unique ID represents a unique identifier for each chip
• 40 bits of unique media access control (MAC) address, which can be used to build
a unique 48-bit Bluetooth-LE or 64-bit IEEE 802.15.4 device address
1. Clock options can have restrictions based on the chosen SoC configuration.
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MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
NXP Semiconductors
Feature Descriptions
3.5 Peripheral features
16-bit Analog-to-Digital Converter (ADC)
• Linear successive approximation algorithm with 16-bit resolution
• Output formatted in differential-ended 16-, 13-, 11-, and 9-bit mode
• Output formatted in single-ended 16-, 12-, 10-, and 8-bit mode
• Single or continuous conversion
• Configurable sample time and conversion speed / power
• Conversion rates in 16-bit mode with no averaging up to ~500Ksamples/sec
• Input clock selection
• Operation in low power modes for lower noise operation
• Asynchronous clock source for lower noise operation
• Selectable asynchronous hardware conversion trigger
• Automatic compare with interrupt for less-than, or greater than, or equal to
programmable value
• Temperature sensor
• Battery voltage measurement
• Hardware average function
• Selectable voltage reverence
• Self-calibration mode
12-Bit Digital-to-Analog Converter (DAC)
• 12-bit resolution
• Guaranteed 6-sigma monotonicity over input word
• High- and low-speed conversions
• 1 μs conversion rate for high speed, 2 μs for low speed
• Power-down mode
• Automatic mode allows the DAC to generate its own output waveforms including
square, triangle, and sawtooth
• Automatic mode allows programmable period, update rate, and range
• DMA support with configurable watermark level
High-Speed Analog Comparator (CMP)
• 6-bit DAC programmable reference generator output
• Up to eight selectable comparator inputs; each input can be compared with any
input by any polarity sequence
• Selectable interrupt on rising edge, falling edge, or either rising or falling edges of
comparator output
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
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NXP Semiconductors
Feature Descriptions
• Two performance modes:
• Shorter propagation delay at the expense of higher power
• Low power, with longer propagation delay
• Operational in all MCU power modes except VLLS0 mode
Voltage Reference(VREF1)
• Programmable trim register with 0.5 mV steps, automatically loaded with factory
trimmed value upon reset
• Programmable buffer mode selection:
• Off
• Bandgap enabled/standby (output buffer disabled)
• High power buffer mode (output buffer enabled)
• 1.2 V output at room temperature
• VREF_OUT output signal
Low Power Timer (LPTMR)
• One channel
• Operation as timer or pulse counter
• Selectable clock for prescaler/glitch filter
• 1 kHz internal LPO
• External low power crystal oscillator
• Internal reference clock
• Configurable glitch filter or prescaler
• Interrupt generated on timer compare
• Hardware trigger generated on timer compare
• Functional in all power modes
Timer/PWM (TPM)
• TPM0: 4 channels, TPM1 and TPM2: 2 channels each
• Selectable source clock
• Programmable prescaler
• 16-bit counter supporting free-running or initial/final value, and counting is up or
up-down
• Input capture, output compare, and edge-aligned and center-aligned PWM modes
• Input capture and output compare modes
• Generation of hardware triggers
• TPM1 and TPM2: Quadrature decoder with input filters
• Global time base mode shares single time base across multiple TPM instances
Programmable Interrupt Timer (PIT)
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MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
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Feature Descriptions
• Up to 2 interrupt timers for triggering ADC conversions
• 32-bit counter resolution
• Clocked by bus clock frequency
Real-Time Clock (RTC)
• 32-bit seconds counter with 32-bit alarm
• Can be invalidated on detection of tamper detect
• 16-bit prescaler with compensation
• Register write protection
• Hard Lock requires MCU POR to enable write access
• Soft lock requires POR or software reset to enable write/read access
• Capable of waking up the system from low power modes
Inter-Integrated Circuit (I2C)
• Two channels
• Compatible with I2C bus standard and SMBus Specification Version 2 features
• Up to 400 kHz operation
• Multi-master operation
• Software programmable for one of 64 different serial clock frequencies
• Programmable slave address and glitch input filter
• Interrupt driven byte-by-byte data transfer
• Arbitration lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• Bus busy detection broadcast and 10-bit address extension
• Address matching causes wake-up when processor is in low power mode
LPUART
• One channel
• Full-duplex operation
• Standard mark/space non-return-to-zero (NRZ) format
• 13-bit baud rate selection with fractional divide of 32
• Programmable 8-bit or 9-bit data format
• Programmable 1 or 2 stop bits
• Separately enabled transmitter and receiver
• Programmable transmitter output polarity
• Programmable receive input polarity
• 13-bit break character option
• 11-bit break character detection option
• Two receiver wakeup methods:
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
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Feature Descriptions
• Idle line wakeup
• Address mark wakeup
• Address match feature in receiver to reduce address mark wakeup ISR overhead
• Interrupt or DMA driven operation
• Receiver framing error detection
• Hardware parity generation and checking
• Configurable oversampling ratio to support from 1/4 to 1/32 bit-time noise
detection
• Operation in low power modes
• Hardware Flow Control RTS\CTS
• Functional in Stop/VLPS modes
Serial Peripheral Interface (DSPI)
• Two independent SPI channels
• Master and slave mode
• Full-duplex, three-wire synchronous transfers
• Programmable transmit bit rate
• Double-buffered transmit and receive data registers
• Serial clock phase and polarity options
• Slave select output
• Control of SPI operation during wait mode
• Selectable MSB-first or LSB-first shifting
• Support for both transmit and receive by DMA
Carrier Modulator Timer (CMT)
• Four modes of operation
• Time; with independent control of high and low times
• Baseband
• Frequency shift key (FSK)
• Direct software control of CMT_IRO signal
• Extended space operation in time, baseband, and FSK modes
• Selectable input clock divider
• Interrupt on end of cycle
• Ability to disable CMT_IRO signal and use as timer interrupt
General Purpose Input/Output (GPIO)
• Hysteresis and configurable pull up device on all input pins
• Independent pin value register to read logic level on digital pin
• All GPIO pins can generate IRQ and wakeup events
• Configurable drive strength on some output pins
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MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
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Feature Descriptions
Touch Sensor Input (TSI)
• Support up to 16 external electrodes
• Automatic detection of electrode capacitance across all operational power modes
• Internal reference oscillator for high-accuracy measurement
• Configurable software or hardware scan trigger
• Capability to wake MCU from low power modes
• Compensate for temperature and supply voltage variations
• High sensitivity change with 16-bit resolution register
• Configurable up to 4096 scan times
• Support DMA data transfer
Keyboard Interface
• GPIO can be configured to function as a interrupt driven keyboard scanning
matrix
• In the 48-pin package there are a total of 26 digital pins
• These pins can be configured as needed by the application as GPIO,
LPUART, SPI, I2C, ADC, timer I/O as well as other functions
3.6 Security Features
Advanced Encryption Standard Accelerator(AES-128 Accelerator)
The advanced encryption standard accelerator (AESA) module is a standalone
hardware coprocessor capable of accelerating the 128-bit advanced encryption
standard (AES) cryptographic algorithms.
The AESA engine supports the following cryptographic features.
LTC includes the following features:
• Cryptographic authentication
• Message authentication codes (MAC)
• Cipher-based MAC (AES-CMAC)
• Extended cipher block chaining message authentication code (AES-
XCBC-MAC)
• Auto padding
• Integrity Check Value(ICV) checking
• Authenticated encryption algorithms
• Counter with CBC-MAC (AES-CCM)
• Galois counter mode (AES-GCM)
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
15
NXP Semiconductors
Feature Descriptions
• Symmetric key block ciphers
• AES (128-bit keys)
• Cipher modes:
• AES-128 modes
• Electronic codebook (ECB)
• Cipher block chaining (CBC)
• Counter (CTR)
• DES modes
• Electronic codebook (ECB)
• Cipher block chaining (CBC)
• Cipher feedback (CFB)
• Output Feedback (OFB)
• Secure scan
True Random Number Generator (TRNG)
True Random Number Generator (TRNG) is a hardware accelerator module that
constitutes a high-quality entropy source.
• TRNG generates a 512-bit (4x 128-bit) entropy as needed by an entropy-consuming
module, such as a deterministic random number generator.
• TRNG output can be read and used by a deterministic pseudo-random number
generator (PRNG) implemented in software.
• TRNG-PRNG combination achieves NIST compliant true randomness and
cryptographic-strength random numbers using the TRNG output as the entropy
source.
• A fully FIPS 180 compliant solution can be realized using the TRNG together with
a FIPS compliant deterministic random number generator and the SoC-level
security.
Flash Memory Protection
The on-chip flash memory controller enables the following useful features:
• Program flash protection scheme prevents accidental program or erase of stored
data.
• Program flash access control scheme prevents unauthorized access to selected code
segments.
• The flash can be protected from mass erase even when the MCU is not secured.
• Automated, built-in, program and erase algorithms with verify.
• Read access to one program flash block is possible while programming or erasing
data in the other program flash block.
16
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
NXP Semiconductors
Transceiver Description
4 Transceiver Description
• Direct Conversion Receiver
• Constant Envelope Transmitter
• 2.36 GHz to 2.483 GHz PLL Range
• Low Transmit and Receive Current Consumption
• Low BOM
4.1 Key Specifications
The KW41Z SoC meets or exceeds all Bluetooth Low Energy v4.2 and IEEE 802.15.4
performance specifications applicable to 2.4 GHz ISM and MBAN (Medical Band
Area Network) bands. Key specification for the KW41 are:
Frequency Band:
• ISM Band: 2400 to 2483.5MHz
• MBAN Band: 2360 to 2400MHz
Bluetooth Low Energy v4.2 modulation scheme:
• Symbol rate: 1000 kbps
• Modulation: GFSK
• Receiver sensitivity: -95 dBm, typical
• Programmable transmitter output power: -30 dBm to 3.5 dBm
IEEE Standard 802.15.4 2.4 GHz modulation scheme:
• Chip rate: 2000 kbps
• Data rate: 250 kbps
• Symbol rate: 62.5 kbps
• Modulation: OQPSK
• Receiver sensitivity: -100 dBm, typical (@1% PER for 20 byte payload packet)
• Single ended bidirectional RF input/output port with integrated transmit/receive
switch
• Programmable transmitter output power: -30 dBm to 3.5 dBm
Generic FSK modulation scheme:
• Symbol rate: 250, 500 and 1000 kbps
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
17
NXP Semiconductors
Transceiver Description
• Modulation(s): GFSK (modulation index = 0.32, 0.5, and 0.7, BT =0.5, 0.3 and
0.7), MSK
• Receiver Sensitivity: Mode and data rate dependant. -100 dBm typical for GFSK
(r=250 kbps, BT = 0.5, h = 0.5)
4.2 Channel Map Frequency Plans
4.2.1 Channel Plan for Bluetooth Low Energy
This section describes the frequency plan / channels associated with 2.4GHz ISM and
MBAN bands for Bluetooth Low Energy.
2.4 GHz ISM Channel numbering:
• Fc=2402 + k * 2 MHz, k=0,.........,39.
MBAN Channel numbering:
• Fc=2363 + 5*k in MHz, for k=0,.....,6
• Fc=2367 + 5*(k-7) in MHz, for k=7,8.....,13)
where k is the channel number.
Table 2. 2.4 GHz ISM and MBAN frequency plan and channel designations
2.4 GHz ISM1
MBAN2
2.4GHz ISM + MBAN
Channel
Freq (MHz)
2402
Channel
Freq (MHz)
2360
Channel
Freq (MHz)
2390
0
1
0
1
28
29
30
31
32
33
34
35
36
0
2404
2361
2391
2
2406
2
2362
2392
3
2408
3
2363
2393
4
2410
4
2364
2394
5
2412
5
2365
2395
6
2414
6
2366
2396
7
2416
7
2367
2397
8
2418
8
2368
2398
9
2420
9
2369
2402
10
2422
10
2370
1
2404
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18
NXP Semiconductors
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
Transceiver Description
Table 2. 2.4 GHz ISM and MBAN frequency plan and channel designations (continued)
2.4 GHz ISM1
MBAN2
2.4GHz ISM + MBAN
Channel
Channel
Freq (MHz)
2424
2426
2428
2430
2432
2434
2436
2438
2440
2442
2444
2446
2448
2450
2452
2454
2456
2458
2460
2462
2464
2466
2468
2470
2472
2474
2476
2478
2480
Channel
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
Freq (MHz)
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
Freq (MHz)
2406
2408
2410
2412
2414
2416
2418
2420
2422
2424
2426
2428
2430
2432
2434
2436
2438
2440
2442
2444
2446
2448
2450
2452
2454
2456
2476
2478
2480
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
37
38
39
1. ISM frequency of operation spans from 2400.0 MHz to 2483.5 MHz
2. Per FCC guideline rules, IEEE (R) 802.15.1 and Bluetooth Low Energy single mode operation is allowed in these
channels.
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
19
NXP Semiconductors
Transceiver Description
4.2.2 Channel Plan for IEEE 802.15.4 in 2.4GHz ISM and MBAN
frequency bands
This section describes the frequency plan / channels associated with 2.4GHz ISM and
MBAN bands for IEEE 802.15.4.
2.4GHz ISM Channel numbering:
• Fc=2405 + 5*(k-11) MHz, k=11, 12, ..,26.
MBAN Channel numbering:
• Fc=2363.0 + 5*k in MHz, for k=0,.....,6
• Fc=2367.0 + 5*(k-7) in MHz, for k=7,.....,14
where k is the channel number.
Table 3. 2.4 GHz ISM and MBAN frequency plan and channel designations
2.4 GHz ISM
MBAN1
Channel #
11
Frequency (MHz)
2405
Channel #
Frequency (MHz)
2363
0
1
12
2410
2368
13
2415
2
2373
14
2420
3
2378
15
2425
4
2383
16
2430
5
2388
17
2435
6
2393
18
2440
7
2367
19
2445
8
2372
20
2450
9
2377
21
2455
10
11
12
13
14
2382
22
2460
2387
23
2465
2392
24
2470
2397
25
2475
2395
26
2480
1. Usable channel spacing to assit in co-existence.
20
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
NXP Semiconductors
Transceiver Electrical Characteristics
4.2.3 Other Channel Plans
The RF synthesizer can be configured to use any channel frequency between 2.36 and
2.487 GHz.
4.3 Transceiver Functions
Receive
The receiver architecture is Zero IF (ZIF) where the received signal after passing
through RF front end is down-converted to a baseband signal. The signal is filtered
and amplified before it is fed to analog-to-digital converter. The digital signal is then
decimated to a baseband clock frequency before it is digitally processed, demodulated
and passed on to packet processing/link-layer processing.
Transmit
The transmitter transmits O-QPSK or GFSK/FSK modulation having power and
channel selection adjustment per user application. After the channel of operation is
determined, coarse and fine tuning is executed within the Frac-N PLL to engage
signal lock. After signal lock is established, the modulated buffered signal is then
routed to a multi-stage amplifier for transmission. The differential signals at the output
of the PA (RF_P, RF_N) are converted to a single ended(SE) output signal by an on-
chip balun.
5 Transceiver Electrical Characteristics
5.1 Radio operating conditions
Table 4. Radio operating conditions
Characteristic
Symbol
fin
Min
2.360
-40
Typ
—
Max
2.480
105
Unit
GHz
°C
Input Frequency
Ambient Temperature Range
Logic Input Voltage Low
TA
25
—
VIL
0
30%
V
VDDINT
1
Table continues on the next page...
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
21
NXP Semiconductors
Transceiver Electrical Characteristics
Table 4. Radio operating conditions (continued)
Characteristic
Symbol
Min
Typ
Max
Unit
Logic Input Voltage High
VIH
70%
—
VDDINT
V
VDDINT
SPI Clock Rate
RF Input Power
fSPI
Pmax
fref
—
—
—
—
12.0
10
MHz
dBm
Crystal Reference Oscillator Frequency ( 40 ppm
over operating conditions to meet the 802.15.4
Standard.)
26 MHz or 32 MHz
1. VDDINT is the internal LDO regulated voltage supplying various circuit blocks, VDDINT=1.2 V
5.2 Receiver Feature Summary
Table 5. Top Level Receiver Specifications (TA=25°C, nominal process unless otherwise
noted)
Characteristic1
Symbol
Ipdn
Min.
—
Typ.
200
Max.
1000
—
Unit
nA
Supply current power down on VDD_RFx supplies
Supply current Rx On with DC-DC converter enable
(Buck; VDDDCDC_in = 3.6 V) , 2
IRxon
—
6.76
mA
Supply current Rx On with DC-DC converter disabled
(Bypass) 2
IRxon
—
16.2
—
mA
Input RF Frequency
fin
2.360
—
—
-100
-95
-100
7.5
—
2.4835
GHz
dBm
dBm
dBm
dB
GFSK Rx Sensitivity(250 kbps GFSK-BT=0.5, h=0.5)
BLE Rx Sensitivity 3
IEEE 802.15.4 Rx Sensitivity 4
SENSGFSK
SENSBLE
SENS15.4
NFHG
—
—
—
—
5
—
—
Noise Figure for max gain mode @ typical sensitivity
Receiver Signal Strength Indicator Range5
Receiver Signal Strength Indicator Resolution
Typical RSSI variation over frequency
Typical RSSI variation over temperature
Narrowband RSSI accuracy6
—
RSSIRange
RSSIRes
-100
—
dBm
dBm
dB
1
—
2
-2
—
-2
—
2
dB
RSSIAcc
-3
—
3
dB
BLE Co-channel Interference (Wanted signal at -67
dBm , BER <0.1%. Measurement resolution 1 MHz).
BLEco-channel
-7
dB
IEEE 802.15.4 Co-channel Interference (Wanted signal
3 dB over reference sensitivity level)
Adjacent/Alternate Channel Performance7
15.4co-channel
—
—
-2
2
—
—
dB
dB
BLE Adjacent +/- 1 MHz Interference offset (Wanted
signal at -67 dBm , BER <0.1%. Measurement
resolution 1 MHz.)
SELBLE, 1 MHz
Table continues on the next page...
22
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
NXP Semiconductors
Transceiver Electrical Characteristics
Table 5. Top Level Receiver Specifications (TA=25°C, nominal process unless otherwise
noted) (continued)
Characteristic1
Symbol
Min.
Typ.
Max.
Unit
BLE Adjacent +/- 2 MHz Interference offset (Wanted
signal at -67 dBm , BER <0.1%. Measurement
resolution 1 MHz.)
SELBLE, 2 MHz
—
40
—
dB
BLE Alternate ≥ +/-3 MHz Interference offset (Wanted
signal at -67 dBm, BER <0.1%. Measurement resolution
1 MHz.)
SELBLE, 3 MHz
SEL15.4,5 MHz
SEL15.4,5 MHz
—
—
—
50
45
60
—
—
—
dB
dB
dB
IEEE 802.15.4 Adjacent +/- 5 MHz Interference offset
(Wanted signal 3 dB over reference sensitivity level ,
PER <1%)
IEEE 802.15.4 Alternate ≥ +/- 10 MHz Interference
offset (Wanted signal 3 dB over reference sensitivity
level , PER <1%.)
Intermodulation Performance
BLE Intermodulation with continuous wave interferer at
3MHz and modulated interferer is at 6MHz (Wanted
signal at -67 dBm , BER<0.1%.)
—
—
-42
-35
—
—
dBm
dBm
BLE Intermodulation with continuous wave interferer at
5MHz and modulated interferer is at 10MHz (Wanted
signal at -67 dBm , BER<0.1%.)
Blocking Performance7
BLE Out of band blocking from 30 MHz to 1000 MHz
and 4000 MHz to 5000 MHz (Wanted signal at -67
dBm , BER<0.1%. Interferer continuous wave signal.)8
—
—
—
—
—
—
—
—
—
-5
-12
-20
0
—
—
—
—
—
dBm
dBm
dBm
dBm
dBm
BLE Out of band blocking from 1000 MHz to 2000 MHz
and 3000 MHz to 4000MHz (Wanted signal at -67 dBm ,
BER<0.1%. Interferer continuous wave signal.)
BLE Out of band blocking from 2001 MHz to 2339MHz
and 2484 MHz to 2999 MHz (Wanted signal at -67
dBm , BER<0.1%. Interferer continuous wave signal.)
BLE Out of band blocking from 5000 MHz to 12750
MHz (Wanted signal at -67 dBm , BER<0.1%. Interferer
continuous wave signal.)8
IEEE 802.15.4 Out of band blocking for frequency
offsets > 10 MHz and <= 80 MHz(Wanted signal 3 dB
over reference sensitivity level , PER <1%. Interferer
continuous wave signal.)9
-36
IEEE 802.15.4 Out of band blocking from carrier
frequencies in 1GHz to 4GHz range excluding
frequency offsets < 80 MHz (Wanted signal 3 dB over
reference sensitivity level , PER <1%. Interferer
continuous wave signal.)
—
—
-25
-15
—
—
dBm
dBm
IEEE 802.15.4 Out of band blocking frequency from
carrier frequencies < 1 GHz and > 4 GHz (Wanted
signal 3 dB over reference sensitivity level , PER <1%.
Interferer continuous wave signal.8
Table continues on the next page...
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
23
NXP Semiconductors
Transceiver Electrical Characteristics
Table 5. Top Level Receiver Specifications (TA=25°C, nominal process unless otherwise
noted) (continued)
Characteristic1
Symbol
Min.
Typ.
Max.
Unit
Spurious Emission < 1.6 MHz offset (Measured with
100 kHz resolution and average detector. Device
transmit on RF channel with center frequency fc and
spurious power measured in 1 MHz at RF frequency f),
where |f-fc|< 1.6 MHz
—
—
-54
—
dBc
Spurious Emission > 2.5 MHz offset (Measured with
100 kHz resolution and average detector. Device
transmit on RF channel with center frequency fc and
spurious power measured in 1 MHz at RF frequency f),
where |f-fc|> 2.5 MHz10
—
—
-70
—
dBc
1. All the RX parameters are measured at the KW41 RF pins
2. Transceiver power consumption
3. Measured at 0.1% BER using 37 byte long packets in max gain mode and nominal conditions
4. In max gain mode and nominal conditions
5. RSSI performance in narrowband mode
6. With one point calibration over frequency and temperature
7. BLE Adjacent and Block parameters are measured with modulated interference signals
8. Exceptions allowed for carrier frequency harmonics.
9. Exception to the 10 MHz > freq offset <= 80 MHz out-of-band blocking limit allowed for frequency offsets of twice the
reference frequency(fref).
10. Exceptions allowed for twice the reference clock frequency(fref) multiples.
Table 6. Receiver Specifications with Generic FSK Modulations
Adjacent/Alternate Channel Selectivity (dB)1
Modulation
Type
Data
Rate
(kbps)
Channel
BW (kHz) Sensitivity
(dBm)
Typical
Desired Interferer Interferer Interferer Interferer
Co-
channel
signal
level
at -/+1*
channel
at -/+ 2*
channel
at -/+ 3*
channel
at -/+ 4*
channel
(dBm) BW offset BW offset BW offset BW offset
GFSK BT =
0.5, h=0.5
1000
500
2000
1000
500
-95
-97
-100
-89
-91
-93
-96
-98
-99
-91
-93
-95
-96
-97
-67
-85
-85
-67
-85
-85
-85
-85
-85
-85
-85
-85
-85
-85
45
33
20
30
25
25
35
32
30
35
30
20
35
30
50
44
33
36
36
25
45
44
34
40
40
32
45
45
52
49
42
41
37
37
50
47
46
45
40
32
50
48
52
51
46
42
43
37
55
50
45
50
45
40
55
50
-7
-7
250
-7
GFSK, BT =
0.5, h=0.3
1000
500
1000
800
-7
-13
-13
-7
250
500
GFSK, BT =
0.5, h=0.7
1000
500
2000
1000
600
-7
250
-7
GMSK
BT=0.3
1000
500
1600
800
-8
-7
250
500
-7
GMSK, BT =
0.7
1000
500
2000
1000
-7
-7
Table continues on the next page...
24
NXP Semiconductors
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
Transceiver Electrical Characteristics
Table 6. Receiver Specifications with Generic FSK Modulations
(continued)
Adjacent/Alternate Channel Selectivity (dB)1
Modulation
Type
Data
Rate
(kbps)
Channel
BW (kHz) Sensitivity
(dBm)
Typical
Desired Interferer Interferer Interferer Interferer
Co-
channel
signal
level
at -/+1*
channel
at -/+ 2*
channel
at -/+ 3*
channel
at -/+ 4*
channel
(dBm) BW offset BW offset BW offset BW offset
250
1000
500
600
3000
1600
800
-99
-96
-98
-99
-85
-85
-85
-85
30
39
38
30
33
50
47
46
45
58
50
45
45
63
55
50
-7
-7
-7
-7
Generic
MSK
250
1. Selectivity measured with an unmodulated blocker
5.3 Transmit and PLL Feature Summary
• Supports constant envelope modulation of 2.4 GHz ISM and 2.36 GHz MBAN
frequency bands
• Fast PLL Lock time: < 25 µs
• Reference Frequency:
• 26 and 32 MHz supported for BLE and FSK modes
• 32 MHz supported for IEEE Standard 802.15.4
Table 7. Top level Transmitter Specifications (TA=25°C, nominal process unless otherwise
noted)
Characteristic1
Symbol
Ipdn
Min.
—
Typ.
200
Max.
—
Unit
nA
Supply current power down on VDD_RFx supplies
Supply current Tx On with PRF = 0dBm and DC-DC
converter enabled (Buck; VDDDCDC_in = 3.6 V) , 2
ITxone
—
6.08
—
mA
Supply current Tx On with PRF = 0 dBm and DC-DC
converter disabled (Bypass) 2
ITxond
—
14.7
—
mA
Output Frequency
Maximum RF Output power 3
Minimum RF Output power 3
fc
2.360
—
—
2.4835
—
GHz
dBm
dBm
dB
PRF,max
PRF,min
3.5
-30
34
—
—
RF Output power control range
PRFCR
—
—
IEEE 802.15.4 Peak Frequency Deviation
IEEE 802.15.4 Error Vector Magnitude4
IEEE 802.15.4 Offset Error Vector Magnitude5
IEEE 802.15.4 TX spectrum level at 3.5MHz offset4, 6
BLE TX Output Spectrum 20dB BW
Fdev15.4
EVM15.4
OEVM15.4
TXPSD15.4
TXBWBLE
—
500
4.5
0.5
—
kHz
%
8
2
%
-40
—
dBc
MHz
1.0
Table continues on the next page...
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
25
NXP Semiconductors
Transceiver Electrical Characteristics
Table 7. Top level Transmitter Specifications (TA=25°C, nominal process unless otherwise
noted) (continued)
Characteristic1
Symbol
Min.
Typ.
Max.
Unit
BLE average frequency deviation using a 00001111
modulation sequence
Δf1avg,BLE
250
kHz
BLE average frequency deviation using a 01010101
modulation sequence
Δf2avg,BLE
220
kHz
BLE RMS FSK Error
FSKerr BLE
,
3%
10
—
BLE Maximum Deviation of the Center Frequency7
BLE Adjacent Channel Transmit Power at 2MHz offset6
Fcdev,BLE
—
—
—
—
kHz
dBm
dBm
PRF2MHz,BLE
PRF3MHz,BLE
-50
-55
BLE Adjacent Channel Transmit Power at >= 3MHz
offset6
—
BLE Frequency Hopping Support
2nd Harmonic of Transmit Carrier Frequency (Pout =
PRF,max), 8
3rd Harmonic of Transmit Carrier Frequency (Pout =
PRF,max)8
YES
-46
TXH2
TXH3
—
—
—
—
dBm/MHz
dBm/MHz
-58
1. All the TX parameters are measured at test hardware SMA connector
2. Transceiver power consumption
3. Measured at the KW41Z RF pins
4. Measured as per IEEE Standard 802.15.4
5. Offset EVM is computed at one point per symbol, by combining the I value from the beginning of each symbol and the Q
value from the middle of each symbol into a single complex value for EVM computations
6. Measured at Pout = 5dBm and recommended TX match
7. Maximum drift of carrier frequency of the PLL during a BLE packet with a nominal 32MHz reference crystal
8. Harmonic Levels based on recommended 2 component match. Transmit harmonic levels depend on the tolerances and
quality of the matching components.
Transmit PA driver output as a function of the PA_POWER[5:0] field when measured
at the IC pins is as follows:
26
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
NXP Semiconductors
Transceiver Electrical Characteristics
Table 8. Transmit Output Power as a function of PA_POWER[5:0]
TX Pout (dBm)
T = 25 °C
-31.1
PA_POWER[5:0]
T = -40 °C
-30.1
-24.0
-17.9
-14.5
-12.0
-10.1
-8.5
T = 105 °C
-32.6
-26.4
-20.4
-17.0
-14.5
-12.6
-11.0
-9.7
1
2
-25.0
4
-19.0
6
-15.6
8
-13.1
10
12
14
16
18
-11.2
-9.6
-7.2
-8.3
-6.1
-7.2
-8.6
-5.1
-6.2
-7.6
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MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
27
NXP Semiconductors
System and Power Management
Table 8. Transmit Output Power as a function of PA_POWER[5:0] (continued)
TX Pout (dBm)
PA_POWER[5:0]
T = -40 °C
-4.2
-3.4
-2.7
-2.0
-1.4
-0.8
-0.3
0.2
T = 25 °C
-5.3
-4.5
-3.8
-3.1
-2.5
-1.9
-1.4
-1.0
-0.5
-0.1
0.3
T = 105 °C
-6.7
-5.9
-5.2
-4.5
-3.9
-3.3
-2.8
-2.4
-1.9
-1.5
-1.1
-0.7
-0.3
0.0
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
0.6
1.1
1.5
1.9
0.7
2.2
1.1
2.6
1.4
2.9
1.8
0.3
3.2
2.1
0.6
3.5
2.4
0.9
3.7
2.6
1.2
3.9
2.9
1.5
4.2
3.1
1.7
4.4
3.3
1.9
4.5
3.5
2.1
6 System and Power Management
6.1 Power Management
The KW41Z includes internal power management features that can be used to control
the power usage. The power management of the KW41Z includes power management
controller (PMC) and a DC-DC converter which can operate in a buck, boost or bypass
configuration. The PMC is designed such that the RF radio will remain in state-
28
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
NXP Semiconductors
System and Power Management
retention while the core is in various stop modes. It can make sure the device can stay
in low current consumption mode while the RF radio can wakeup quick enough for
communication.
6.1.1 DC-DC Converter
The features of the DC-DC converter include the following:
• Single inductor, multiple outputs.
• Boost mode (pin selectable; CFG=GND).
• Buck mode (pin selectable; CFG=VDCDC_IN).
• Continuous or pulsed operation (hardware/software configurable).
• Power switch input to allow external control of power up, and to select bypass
mode.
• Output signal to indicate power stable. Purpose is for the rest of the chip to be
used as a POR.
• Scaled battery output voltage suitable for SAR ADC utilization.
• Internal oscillator for support when the reference oscillator is not present.
• 1.8 V output is capable of supplying the external device a maximum of 38.9 mA
(VDD_1P8OUT = 1.8 V, VDCDC_IN = 3.0 V) and 20.9 mA (VDD_1P8OUT =
3.0 V, VDCDC_IN = 3.0 V), with MCU in RUN mode, peripherals are disabled.
6.2 Modes of Operation
The ARM Cortex-M0+ core in the KW41Z has three primary modes of operation:
Run, Wait, and Stop modes. For each run mode, there is a corresponding wait and stop
mode. Wait modes are similar to ARM sleep modes. Stop modes are similar to ARM
deep sleep modes. The very low power run (VLPR) operation mode can drastically
reduce runtime power when the maximum bus frequency is not required to handle the
application needs.
The WFI instruction invokes both wait and stop modes. The primary modes are
augmented in a number of ways to provide lower power based on application needs.
6.2.1 Power modes
The power management controller (PMC) provides multiple power options to allow
the user to optimize power consumption for the level of functionality needed.
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
29
NXP Semiconductors
System and Power Management
Depending on the stop requirements of the user application, a variety of stop modes are
available that provide state retention, partial power down or full power down of certain
logic and/or memory. I/O states are held in all modes of operation. The following table
compares the various power modes available.
For each run mode there is a corresponding wait and stop mode. Wait modes are similar
to ARM sleep modes. Stop modes (VLPS, STOP) are similar to ARM sleep deep mode.
The very low power run (VLPR) operating mode can drastically reduce runtime power
when the maximum bus frequency is not required to handle the application needs.
The three primary modes of operation are run, wait and stop. The WFI instruction
invokes either wait or stop depending on the SLEEPDEEP bit in Cortex-M0+ System
Control Register. The primary modes are augmented in a number of ways to provide
lower power based on application needs.
Table 9. Power modes (At 25 deg C)
Power mode
Description
CPU
Radio
recovery
method
Normal Run (all
Allows maximum performance of chip.
—
Radio can be active
peripherals clock off)
Normal Wait - via WFI Allows peripherals to function, while allowing CPU to
go to sleep reducing power.
Interrupt
Interrupt
Interrupt
Normal Stop - via
WFI
Places chip in static state. Lowest power mode that
retains all registers while maintaining LVD protection.
PStop2 (Partial Stop Core and system clocks are gated. Bus clock
2)
remains active. Masters and slaves clocked by bus
clock remain in Run or VLPRun mode. The clock
generators in MCG and the on-chip regulator in the
PMC also remain in Run or VLPRun mode.
PStop1 (Partial Stop Core, system clocks and bus clock are gated. All bus
Interrupt
—
1)
masters and slaves enter Stop mode. The clock
generators in MCG and the on-chip regulator in the
PMC also remain in Run or VLPRun mode.
VLPR (Very Low
Power Run) (all
peripherals off)
Reduced frequency (1MHz) Flash access mode,
regulator in low power mode, LVD off. Internal
oscillator can provide low power 4 MHz source for
core. (Values @2MHz core/ 1MHz bus and flash,
module off, execution from flash).
Radio operation is possible
only when DC-DC is
configured for continuous
mode.1 However, there may
be insufficient MIPS with a
4MHz MCU to support much
in the way of radio operation.
Biasing is disabled when DC-DC is configured for
continuous mode in VLPR/W
VLPW (Very Low
Similar to VLPR, with CPU in sleep to further reduce
Interrupt
Power Wait) - via WFI power. (Values @4MHz core/ 1MHz bus, module off)
(all peripherals off)
Biasing is disabled when DC-DC is configured for
continous mode in VLPR/W
Table continues on the next page...
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System and Power Management
Table 9. Power modes (At 25 deg C) (continued)
Power mode
Description
CPU
Radio
recovery
method
VLPS (Very Low
Places MCU in static state with LVD operation off.
Interrupt
Power Stop) via WFI Lowest power mode with ADC and all pin interrupts
functional. LPTMR, RTC, CMP, TSI can be
operational.
Biasing is disabled when DC-DC is configured for
continuous mode in VLPS
LLS3 (Low Leakage State retention power mode. LLWU, LPTMR, RTC,
Wakeup
Interrupt
Radio SOG is in state
retention in LLSx. The BLE/
802.15.4/Generic FSK DSM2
logic can be active using the
32 kHz clock
Stop)
CMP, TSI can be operational. All of the radio Sea of
Gates (SOG) logic is in state retention
LLS2 (Low Leakage State retention power mode. LLWU, LPTMR, RTC,
Wakeup
Interrupt
Stop)
CMP, TSI can be operational. 16 KB or 32 KB of
programmable RAM can be powered on. All of the
radio SOG logic is in state retention
VLLS3 (Very Low
Leakage Stop3)
Full SRAM retention. LLWU, LPTMR, RTC, CMP,
TSI can be operational. All of the radio SOG logic is
in state retention
Wakeup
Reset
Radio SOG is in state
retention in VLLS3/2. The
BLE/802.15.4/Generic FSK
DSM logic can be active
using the 32 kHz clock
VLLS2 (Very Low
Leakage Stop2)
Partial SRAM retention. 16 KB or 32 KB of
programmable RAM can be powered on.. LLWU,
LPTMR, RTC, CMP, TSI can be operational.All of
the radio SOG logic is in state retention -
Wakeup
Reset
VLLS1 (Very Low
Leakage Stop1) with file remains powered for customer-critical data.
RTC + 32 kHz OSC
All SRAM powered off. The 32-byte system register
Wakeup
Reset
Radio operation not
supported. The Radio SOG is
power-gated in VLLS1/0.
Radio state is lost at VLLS1
and lower power states
LLWU, LPTMR, RTC, CMP can be operational.
Radio logic is power gated.
VLLS1 (Very Low
Leakage Stop1) with file remains powered for customer-critical data.
All SRAM powered off. The 32-byte system register
Wakeup
Reset
LPTMR + LPO
LLWU, LPTMR, RTC, CMP, TSI can be operational.
VLLS0 (Very Low
Leakage Stop0) with
Brown-out Detection
VLLS0 is not supported with DC-DC
Wakeup
Reset
Radio operation not
supported. The Radio digital
is power-gated in VLLS1/0
The 32-byte system register file remains powered for
customer-critical data. Disable all analog modules in
PMC and retains I/O state and DGO state. LPO
disabled, POR brown-out detection enabled, Pin
interrupt only. Radio logic is power gated.
VLLS0 (Very Low
Leakage Stop0)
without Brown-out
Detection
VLLS0 is not supported with DC-DC buck/boost
configuration but is supported with bypass
configuration
Wakeup
Reset
The 32-byte system register file remains powered for
customer-critical data. Disable all analog modules in
PMC and retains I/O state and DGO state. LPO
disabled, POR brown-out detection disabled, Pin
interrupt only. Radio logic is power gated.
1. Biasing is disabled, but the Flash is in a low power mode for VLPx, so this configuration can realize some power
savings over use of Run/Wait/Stop
2. DSM refers to Radio's deepsleep mode. DSM does not refer to the ARM sleep deep mode.
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
31
NXP Semiconductors
MCU Electrical Characteristics
7 MCU Electrical Characteristics
7.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
High
Low
VIH
80%
50%
20%
Input Signal
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
All digital I/O switching characteristics, unless otherwise specified, assume that the
output pins have the following characteristics.
• CL=30 pF loads
• Slew rate disabled
• Normal drive strength
7.2 Nonswitching electrical specifications
7.2.1 Voltage and current operating requirements
Table 10. Voltage and current operating requirements
Symbol
VDD
Description
Min.
1.71
1.71
–0.1
–0.1
Max.
3.6
Unit
V
Notes
Supply voltage
VDDA
Analog supply voltage
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
VSS – VSSA VSS-to-VSSA differential voltage
0.1
V
0.1
V
VIH
Input high voltage
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MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
MCU Electrical Characteristics
Table 10. Voltage and current operating requirements (continued)
Symbol
Description
• 2.7 V ≤ VDD ≤ 3.6 V
Min.
Max.
Unit
Notes
0.7 × VDD
—
V
• 1.7 V ≤ VDD ≤ 2.7 V
0.75 × VDD
—
V
VIL
Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS
IICIO
Input hysteresis
0.06 × VDD
-3
—
—
V
IO pin negative DC injection current — single pin
• VIN < VSS-0.3V
1
mA
IICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents of 16
contiguous pins
-25
—
mA
• Negative current injection
VODPU
VRAM
Open drain pullup voltage level
VDD
1.2
VDD
—
V
V
2
VDD voltage required to retain RAM
1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN
greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If
this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting
resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|.
2. Open drain outputs must be pulled to VDD
.
7.2.2 LVD and POR operating requirements
Table 11. VDD supply LVD and POR operating requirements
Symbol Description
Min.
0.8
Typ.
1.1
Max.
1.5
Unit
V
Notes
VPOR
Falling VDD POR detect voltage
VLVDH
Falling low-voltage detect threshold — high
range (LVDV = 01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV = 00)
1
VLVW1H
VLVW2H
VLVW3H
VLVW4H
2.62
2.72
2.82
2.92
—
2.70
2.80
2.90
3.00
60
2.78
2.88
2.98
3.08
—
V
V
• Level 2 falling (LVWV = 01)
• Level 3 falling (LVWV = 10)
V
• Level 4 falling (LVWV = 11)
V
VHYSH
VLVDL
Low-voltage inhibit reset/recover hysteresis —
high range
mV
Falling low-voltage detect threshold — low
range (LVDV=00)
1.54
1.60
1.66
V
Low-voltage warning thresholds — low range
1
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MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
33
NXP Semiconductors
MCU Electrical Characteristics
Table 11. VDD supply LVD and POR operating requirements (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VLVW1L
VLVW2L
VLVW3L
VLVW4L
• Level 1 falling (LVWV = 00)
1.74
1.84
1.94
1.80
1.90
2.00
1.86
1.96
2.06
V
V
V
• Level 2 falling (LVWV = 01)
• Level 3 falling (LVWV = 10)
• Level 4 falling (LVWV = 11)
2.04
—
2.10
40
2.16
—
V
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
mV
VBG
tLPO
Bandgap voltage reference
0.97
900
1.00
1.03
V
Internal low power oscillator period — factory
trimmed
1000
1100
μs
1. Rising thresholds are falling threshold + hysteresis voltage
7.2.3 Voltage and current operating behaviors
Table 12. Voltage and current operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
VOH
Output high voltage — Normal drive pad (except
RESET_b)
1, 2
VDD – 0.5
VDD – 0.5
—
—
V
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -2.5 mA
VOH
Output high voltage — High drive pad (except
RESET_b)
1, 2
VDD – 0.5
VDD – 0.5
—
—
V
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -20 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -10 mA
IOHT
VOL
Output high current total for all ports
Output low voltage — Normal drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 2.5 mA
—
100
mA
1
1
—
—
0.5
0.5
V
V
VOL
Output low voltage — High drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA
—
—
0.5
0.5
V
V
IOLT
IIN
Output low current total for all ports
—
—
100
500
mA
nA
Input leakage current (per pin) for full temperature
range
3
IIN
IIN
Input leakage current (per pin) at 25 °C
—
—
0.025
5
μA
μA
3
3
Input leakage current (total all pins) for full
temperature range
Table continues on the next page...
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
34
NXP Semiconductors
MCU Electrical Characteristics
Table 12. Voltage and current operating behaviors (continued)
Symbol
Description
Min.
Max.
Unit
Notes
RPU
Internal pullup resistors
20
50
kΩ
4
1. PTB0-1 and PTC0-3, PTC6, PTC7, PTC17, PTC18 I/O have both high drive and normal drive capability selected by
the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. The reset pin only contains an active pull up device when configured as the RESET signal or as a GPIO. When
configured as a GPIO output, it acts as a pseudo open drain output.
3. Measured at VDD = 3.6 V
4. Measured at VDD supply voltage = VDD min and Vinput = VSS
7.2.4 Power mode transition operating behaviors
All specifications except tPOR and VLLSx→RUN recovery times in the following
table assume this clock configuration:
• CPU and system clocks = 48 MHz
• Bus and flash clock = 24 MHz
• FEI clock mode
POR and VLLSx→RUN recovery use FEI clock mode at the default CPU and system
frequency of 21 MHz, and a bus and flash clock frequency of 10.5 MHz.
Table 13. Power mode transition operating behaviors
Symbol
Description
Max.
Unit
Notes
tPOR
After a POR event, amount of time from the point VDD
reaches 1.8 V to execution of the first instruction across the
operating temperature range of the chip.
300
μs
1
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• LLS2 → RUN
• LLS3 → RUN
147
144
76
μs
μs
μs
μs
μs
μs
76
5.8
5.8
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35
NXP Semiconductors
MCU Electrical Characteristics
Table 13. Power mode transition operating behaviors (continued)
Symbol
Description
• VLPS → RUN
Max.
Unit
Notes
6.2
μs
• STOP → RUN
6.2
μs
1. Normal boot (FTFA_FOPT[LPBOOT]=11). When the DC-DC converter is in bypass mode, TPOR will not meet the 300µs
spec when 1) VDD_1P5 < 1.6V at 25°C and °C. 2) 1.5V ≤ VDD_1P5 ≤ 1.8V. For the bypass mode special case where
VDD_1P5 = VDD_1P8, TPOR did not meet the 300µs maximum spec when the supply slew rate <=100V/s.
7.2.5 Power consumption operating behaviors
Table 14. Power consumption operating behaviors - Bypass Mode
Symbol
Description
Typ.
Max.
Unit
Notes
IDDA
Analog supply current
—
See note
mA
1
2
IDD_RUNCO_C Run mode current in compute operation - 48 MHz
core / 24 MHz flash / bus disabled, LPTMR running
M
using LPO clock at 1kHz, CoreMark benchmark code
executing from flash at 3.0 V
7.79
4.6
8.64
5.45
mA
mA
IDD_RUNCO Run mode current in compute operation - 48 MHz
core / 24 MHz flash / bus clock disabled, code of
while(1) loop executing from flash at 3.0 V
3
3
IDD_RUN
Run mode current - 48 MHz core / 24 MHz bus and
flash, all peripheral clocks disabled, code of while(1)
loop executing from flash at 3.0 V
5.6
6.45
mA
IDD_RUN
Run mode current - 48 MHz core / 24 MHz bus and
flash, all peripheral clocks enabled, code of while(1)
loop executing from flash at 3.0 V
3, 4
6.9
7.2
7.7
7.2
8
mA
mA
mA
at 25 °C
at 85 °C
at 105 °C
8.5
IDD_WAIT Wait mode current - core disabled / 48 MHz system /
24 MHz bus / flash disabled (flash doze enabled), all
peripheral clocks disabled at 3.0 V
3
3
4.2
3.5
5.05
4.35
mA
mA
IDD_WAIT Wait mode current - core disabled / 24 MHz system /
24 MHz bus / flash disabled (flash doze enabled), all
peripheral clocks disabled at 3.0 V
IDD_PSTOP2 Stop mode current with partial stop 2 clocking option
- core and system disabled / 10.5 MHz bus at 3.0 V
3
5
2.7
3.55
960
mA
μA
IDD_VLPRCO_ Very-low-power run mode current in compute
760
operation - 4 MHz core / 0.8 MHz flash / bus clock
CM
disabled, LPTMR running using LPO clock at 1 kHz
reference clock, CoreMark benchmark code
executing from flash at 3.0 V
Table continues on the next page...
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NXP Semiconductors
MCU Electrical Characteristics
Table 14. Power consumption operating behaviors - Bypass Mode (continued)
Symbol
Description
Typ.
Max.
Unit
Notes
IDD_VLPRCO Very-low-power run mode current in compute
operation - 4 MHz core / 0.8 MHz flash / bus clock
disabled, code of while(1) loop executing from flash
at 3.0 V
6
157
357
μA
IDD_VLPR Very-low-power run mode current - 4 MHz core / 0.8
MHz bus and flash, all peripheral clocks disabled,
6
4, 6
6
195
395
μA
code of while(1) loop executing from flash at 3.0 V
IDD_VLPR Very-low-power run mode current - 4 MHz core / 0.8
MHz bus and flash, all peripheral clocks enabled,
250
142
450
342
μA
μA
code of while(1) loop executing from flash at 3.0 V
IDD_VLPW Very-low-power wait mode current - core disabled / 4
MHz system / 0.8 MHz bus / flash disabled (flash
doze enabled), all peripheral clocks disabled at 3.0 V
IDD_STOP Stop mode current at 3.0 V
at 25 °C
at 70 °C
at 85 °C
at 105 °C
0.204
0.275
0.434
0.561
0.294
0.692
0.716
1.3
mA
mA
mA
mA
IDD_VLPS Very-low-power stop mode current at Bypass
mode(3.0 V),
4.3
17
18
42
μA
μA
μA
μA
at 25 °C
at 70 °C
at 85 °C
at 105 °C
86.2
157
166
328
IDD_LLS3
Low-leakage stop mode 3 current at Bypass
mode(3.0 V),
2.7
9
5
μA
μA
μA
μA
at 25 °C
at 70 °C
at 85 °C
at 105 °C
16.5
78.1
128
36.6
69
IDD_LLS2
Low-leakage stop mode 2 current at Bypass
mode(3.0 V),
2
3.13
10.5
45.6
65.5
μA
μA
μA
μA
at 25 °C
at 70 °C
at 85 °C
at 105 °C
3.2
20.8
39
IDD_VLLS3 Very-low-leakage stop mode 3 current at Bypass
mode(3.0 V),
2.3
15
4
μA
μA
μA
at 25 °C
at 70 °C
at 85 °C
28.5
69.3
31.8
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37
NXP Semiconductors
MCU Electrical Characteristics
Table 14. Power consumption operating behaviors - Bypass Mode (continued)
Symbol
Description
Typ.
Max.
Unit
Notes
at 105 °C
58
108
μA
IDD_VLLS2 Very-low-leakage stop mode 2 current at Bypass
mode(3.0 V),
1.5
6.3
14.5
27
2.21
11.8
33.5
42.6
μA
μA
μA
μA
at 25 °C
at 70 °C
at 85 °C
at 105 °C
IDD_VLLS1 Very-low-leakage stop mode 1 current at Bypass
mode(3.0 V),
0.56
3
1.3
9.4
μA
μA
μA
μA
at 25°C
at 70°C
at 85°C
at 105°C
8.8
16.8
23.2
27.1
IDD_VLLS0 Very-low-leakage stop mode 0 current
(SMC_STOPCTRL[PORPO] = 0) at 3.0 V
0.36
2.7
0.949
8.2
μA
μA
μA
μA
at 25 °C
at 70 °C
at 85 °C
at 105 °C
7.4
14.3
27
16.5
IDD_VLLS0 Very-low-leakage stop mode 0 current
(SMC_STOPCTRL[PORPO] = 1) at 3.0 V
7
0.182
2.5
0.765
6.7
μA
μA
μA
μA
at 25 °C
at 70 °C
at 85 °C
at 105 °C
7.2
13.3
26
16.3
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. MCG configured for FEImode. CoreMark benchmark compiled using IAR 7.70 with optimization level high, optimized for
balanced.
3. MCG configured for FEI mode.
4. Incremental current consumption from peripheral activity is not included.
5. MCG configured for BLPI mode. CoreMark benchmark compiled using IAR 7.70 with optimization level high, optimized
for balanced.
6. MCG configured for BLPI mode.
7. No brownout
Table 15. Power consumption operating behaviors - Buck Mode
Symbol
Description
Typ.
Max.
Unit
Notes
IDDA
Analog supply current
—
See note
mA
1
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NXP Semiconductors
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
MCU Electrical Characteristics
Table 15. Power consumption operating behaviors - Buck Mode (continued)
Symbol
Description
Typ.
Max.
Unit
Notes
IDD_RUNCO Run mode current in compute operation - 48 MHz
core / 24 MHz flash / bus clock disabled, code of
while(1) loop executing from flash at 3.0 V
2
3.1
—
mA
IDD_RUN
Run mode current - 48 MHz core / 24 MHz bus and
flash, all peripheral clocks disabled, code of while(1)
loop executing from flash at 3.0 V
2
3.85
—
mA
IDD_RUN
Run mode current - 48 MHz core / 24 MHz bus and
flash, all peripheral clocks enabled, code of while(1)
loop executing from flash at 3.0 V
2, 3
4.8
5.3
5.7
—
—
—
mA
mA
mA
at 25 °C
at 85 °C
at 105 °C
IDD_WAIT Wait mode current - core disabled / 48 MHz system /
24 MHz bus / flash disabled (flash doze enabled), all
peripheral clocks disabled at 3.0 V
2
2
3.1
2.9
—
—
mA
mA
IDD_WAIT Wait mode current - core disabled / 24 MHz system /
24 MHz bus / flash disabled (flash doze enabled), all
peripheral clocks disabled at 3.0 V
IDD_PSTOP2 Stop mode current with partial stop 2 clocking option
- core and system disabled / 10.5 MHz bus at 3.0 V
2
4
1.9
—
—
mA
μA
IDD_VLPRCO Very-low-power run mode current in compute
operation - 4 MHz core / 0.8 MHz flash / bus clock
disabled, code of while(1) loop executing from flash
at 3.0 V
137
IDD_VLPR Very-low-power run mode current - 4 MHz core / 0.8
MHz bus and flash, all peripheral clocks disabled,
-1
3, 4
4
154
—
μA
code of while(1) loop executing from flash at 3.0 V
IDD_VLPR Very-low-power run mode current - 4 MHz core / 0.8
MHz bus and flash, all peripheral clocks enabled,
216
131
—
—
μA
μA
code of while(1) loop executing from flash at 3.0 V
IDD_VLPW Very-low-power wait mode current - core disabled / 4
MHz system / 0.8 MHz bus / flash disabled (flash
doze enabled), all peripheral clocks disabled at 3.0 V
IDD_STOP Stop mode current at 3.0 V
at 25 °C
at 70 °C
at 105 °C
1.61
1.73
2.02
2.32
4.35
4.68
mA
mA
mA
IDD_VLPS Very-low-power stop mode current at Buck mode(3.0
V),
3.58
15.08
116.94
14.98
37.27
μA
μA
μA
at 25 °C
at 70 °C
at 105 °C
244.30
IDD_LLS3
Low-leakage stop mode 3 current at Buck mode(3.0
V),
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MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
39
NXP Semiconductors
MCU Electrical Characteristics
Table 15. Power consumption operating behaviors - Buck Mode (continued)
Symbol
Description
Typ.
Max.
Unit
Notes
at 25 °C
2.20
4.08
μA
at 70 °C
7.44
13.63
90.49
μA
μA
at 105 °C
48.78
IDD_LLS2
Low-leakage stop mode 2 current at Buck mode(3.0
V),
1.86
3.19
2.91
10.48
52.80
μA
μA
μA
at 25 °C
at 70 °C
at 105 °C
31.44
IDD_VLLS3 Very-low-leakage stop mode 3 current at Buck
mode(3.0 V),
1.79
12
3.12
22.8
μA
μA
μA
at 25 °C
at 70 °C
at 105 °C
37.49
69.81
IDD_VLLS2 Very-low-leakage stop mode 2 current at Buck
mode(3.0 V),
1.09
5.56
1.60
10.40
29.52
μA
μA
μA
at 25 °C
at 70 °C
at 105 °C
18.71
IDD_VLLS1 Very-low-leakage stop mode 1 current at Buck
mode(3.0 V),
0.46
2.17
1.07
6.8
μA
μA
μA
at 25 °C
at 70 °C
at 105 °C
14.08
22.71
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. MCG configured for FEI mode.
3. Incremental current consumption from peripheral activity is not included.
4. MCG configured for BLPI mode.
Table 16. Power consumption operating behaviors - Boost Mode
Symbol
Description
Typ.
Max.
Unit
Notes
IDDA
Analog supply current
—
See note
mA
1
2
IDD_RUNCO Run mode current in compute operation - 48 MHz
core / 24 MHz flash / bus clock disabled, code of
while(1) loop executing from flash at 1.3 V
8.1
—
—
mA
mA
IDD_RUN
Run mode current - 48 MHz core / 24 MHz bus and
flash, all peripheral clocks disabled, code of while(1)
loop executing from flash at 1.3 V
2
9.76
IDD_RUN
Run mode current - 48 MHz core / 24 MHz bus and
flash, all peripheral clocks enabled, code of while(1)
loop executing from flash at 1.3 V
2, 3
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40
NXP Semiconductors
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
MCU Electrical Characteristics
Table 16. Power consumption operating behaviors - Boost Mode (continued)
Symbol
Description
Typ.
Max.
Unit
Notes
at 25 °C
13.2
—
mA
at 85 °C
14.1
15.2
—
—
mA
mA
at 105 °C
IDD_WAIT Wait mode current - core disabled / 48 MHz system /
24 MHz bus / flash disabled (flash doze enabled), all
peripheral clocks disabled at 1.3 V
2
2
6.9
5.8
—
—
mA
mA
IDD_WAIT Wait mode current - core disabled / 24 MHz system /
24 MHz bus / flash disabled (flash doze enabled), all
peripheral clocks disabled at 1.3 V
IDD_PSTOP2 Stop mode current with partial stop 2 clocking option
- core and system disabled / 10.5 MHz bus at 1.3 V
2
4
8.3
—
—
mA
μA
IDD_VLPRCO Very-low-power run mode current in compute
operation - 4 MHz core / 0.8 MHz flash / bus clock
disabled, code of while(1) loop executing from flash
at 1.3 V
378
IDD_VLPR Very-low-power run mode current - 4 MHz core / 0.8
MHz bus and flash, all peripheral clocks disabled,
4
3, 4
4
476
—
μA
code of while(1) loop executing from flash at 1.3 V
IDD_VLPR Very-low-power run mode current - 4 MHz core / 0.8
MHz bus and flash, all peripheral clocks enabled,
606
357
—
—
μA
μA
code of while(1) loop executing from flash at 1.3 V
IDD_VLPW Very-low-power wait mode current - core disabled / 4
MHz system / 0.8 MHz bus / flash disabled (flash
doze enabled), all peripheral clocks disabled at 1.3 V
IDD_STOP Stop mode current at 1.3 V
3.22
3.56
3.74
4.64
8.96
9.73
mA
mA
mA
at 25 °C
at 70 °C
at 105 °C
IDD_VLPS Very-low-power stop mode current at Boost
mode(1.3 V),
29.89
191.62
1429.24
125.13
473.41
2985.93
μA
μA
μA
at 25 °C
at 70 °C
at 105 °C
IDD_LLS3
Low-leakage stop mode 3 current at Boost mode(1.3
V),
12.16
84.61
22.53
155.12
990.79
μA
μA
μA
at 25 °C
at 70 °C
at 105 °C
534.09
IDD_LLS2
Low-leakage stop mode 2 current at Boost mode(1.3
V),
12.05
17.36
18.86
56.96
μA
μA
at 25 °C
at 70 °C
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41
NXP Semiconductors
MCU Electrical Characteristics
Table 16. Power consumption operating behaviors - Boost Mode (continued)
Symbol
Description
Typ.
Max.
Unit
Notes
at 105 °C
221.29
371.66
μA
IDD_VLLS3 Very-low-leakage stop mode 3 current at Boost
mode(1.3 V),
7.99
88.4
13.89
167.96
534.67
μA
μA
μA
at 25 °C
at 70 °C
at 105 °C
287.14
IDD_VLLS2 Very-low-leakage stop mode 2 current at Boost
mode(1.3 V),
7.09
23.38
95.67
10.45
43.79
μA
μA
μA
at 25 °C
at 70 °C
at 105 °C
150.94
IDD_VLLS1 Very-low-leakage stop mode 1 current at Boost
mode(1.3 V),
3.63
16.23
67.77
8.44
50.86
109.32
μA
μA
μA
at 25 °C
at 70 °C
at 105 °C
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. MCG configured for FEI mode.
3. Incremental current consumption from peripheral activity is not included.
4. MCG configured for BLPI mode.
Table 17. Low power mode peripheral adders — typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
IIREFSTEN4MHz
4 MHz internal reference clock (IRC)
adder. Measured by entering STOP or
VLPS mode with 4 MHz IRC enabled.
46
46
47
47
47
µA
IIREFSTEN32KHz
32 kHz internal reference clock (IRC)
adder. Measured by entering STOP mode
with the 32 kHz IRC enabled.
88
91
90
89
88
µA
IEREFSTEN32KHz
External 32 kHz crystal clock adder by
means of the RTC bits. Measured by
entering all modes with the crystal
enabled.
1.4
1.6
2.7
1.8
2.6
1.3
1.5
1.9
1.4
1.7
1.6
1.9
2.9
1.7
2.8
2.4
4.2
7.7
4.1
7.6
4.1
7.7
15
VLLS1
VLLS2
VLLS3
LLS2
μA
8
15.2
LLS3
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42
NXP Semiconductors
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
MCU Electrical Characteristics
Table 17. Low power mode peripheral adders — typical value (continued)
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
ICMP
CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and a
single external input for compare. Includes
6-bit DAC power consumption.
22
19
20
21
21
µA
IRTC
RTC peripheral adder measured by placing
the device in VLLS1 mode with external 32
kHz crystal enabled by means of the
1.4
1.3
1.6
2.4
4.3
µA
RTC_CR[OSCE] bit and the RTC ALARM
set for 1 minute. Includes ERCLK32K (32
kHz external crystal) power consumption.
ILPUART
LPUART peripheral adder measured by
placing the device in STOP or VLPS mode
with selected clock source waiting for RX
data at 115200 baud rate. Includes
selected clock source power consumption.
MCGIRCLK (4 MHz internal reference
clock)
53
54
54
54
54
µA
ILPTMR
LPTMR peripheral adder measured by
placing the device in VLLS1 mode with
LPTMR enabled using LPO.
30
30
30
85
100
nA
ITPM
TPM peripheral adder measured by
placing the device in STOP or VLPS mode
with selected clock source configured for
output compare generating 100 Hz clock
signal. No load is placed on the I/O
generating the clock signal. Includes
selected clock source and I/O switching
currents.
58
76
59
82
59
85
59
87
59
87
µA
µA
µA
MCGIRCLK (4 MHz internal reference
clock)
IBG
Bandgap adder when BGEN bit is set and
device is placed in VLPx, LLS, or VLLSx
mode.
IADC
ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS mode.
ADC is configured for low-power mode
using the internal clock and continuous
conversions.
331
327
327
327
328
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
43
NXP Semiconductors
MCU Electrical Characteristics
7.2.6 Diagram: Typical IDD_RUN operating behavior
The following data was measured from previous devices with same MCU core (ARM®
Cortex-M0+) under these conditions:
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
Figure 3. Run mode supply current vs. core frequency
44
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
NXP Semiconductors
MCU Electrical Characteristics
Figure 4. VLPR mode current vs. core frequency
7.2.7 SoC Power Consumption
Full KW41Z/31Z/21Z system-on-chip (SoC) power consumption is a function of the
many configurations possible for the MCU platform and its peripherals including the
2.4GHz radio and the DC-DC converter. A few measured SoC configurations are as
follows:
Table 18. SoC Power Consumption
MCU State
Flash State
Radio State
DCDC State
Typical
Average IC
current
Unit
STOP
STOP
RUN
Doze
Doze
Rx
Tx(at 0 dBm)
Rx
Buck(VDDDCDC_in=3.6 V)
Buck(VDDDCDC_in=3.6 V)
Buck(VDDDCDC_in=3.6 V)
8.4
7.6
mA
mA
mA
Enabled
10.2
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45
NXP Semiconductors
MCU Electrical Characteristics
Table 18. SoC Power Consumption (continued)
MCU State
Flash State
Radio State
DCDC State
Typical
Average IC
current
Unit
RUN
STOP
STOP
RUN
Enabled
Doze
Tx(at 0 dBm)
Rx
Buck(VDDDCDC_in=3.6 V)
Disabled/Bypass
Disabled/Bypass
Disabled/Bypass
Disabled/Bypass
9.6
mA
mA
mA
mA
mA
16.6
15.2
19.7
19.2
Doze
Tx(at 0 dBm)
Rx
Enabled
Enabled
RUN
Tx(at 0 dBm)
7.2.8 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.nxp.com
2. Perform a keyword search for “EMC design.”
7.2.9 Capacitance attributes
Table 19. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN
Input capacitance
—
7
pF
7.3 Switching electrical specifications
7.3.1 Device clock specifications
Table 20. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Normal run mode
fSYS
fBUS
System and core clock
Bus clock
—
—
—
48
24
24
MHz
MHz
MHz
fFLASH
Flash clock
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46
NXP Semiconductors
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
MCU Electrical Characteristics
Table 20. Device clock specifications (continued)
Symbol
Description
Min.
Max.
Unit
fLPTMR
LPTMR clock
—
24
MHz
VLPR and VLPS modes1
fSYS
fBUS
System and core clock
Bus clock
—
—
—
—
—
—
—
—
4
1
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
fFLASH
fLPTMR
fERCLK
Flash clock
LPTMR clock2
1
24
16
16
8
External reference clock
fLPTMR_ERCLK LPTMR external reference clock
fTPM
TPM asynchronous clock
fLPUART0
LPUART0 asynchronous clock
12
1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN
or from VLPR.
2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.
7.3.2 General switching specifications
These general-purpose specifications apply to all signals configured for GPIO,
LPUART, CMT and I2C signals.
Table 21. General switching specifications
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock cycles
1, 2
NMI_b pin interrupt pulse width (analog filter enabled) —
Asynchronous path
200
20
—
—
—
ns
ns
ns
3
3
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
External RESET_b input pulse width (digital glitch filter
disabled)
100
Port rise and fall time(high drive strength)
4, 5
—
—
25
16
ns
ns
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7 V
• 2.7 ≤ VDD ≤ 3.6 V
• Slew disabled
—
—
8
6
ns
ns
• 1.71 ≤ VDD ≤ 2.7 V
• 2.7 ≤ VDD ≤ 3.6 V
Port rise and fall time(low drive strength)
• Slew enabled
6, 7
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
47
NXP Semiconductors
MCU Electrical Characteristics
Table 21. General switching specifications
Description
• 1.71 ≤ VDD ≤ 2.7 V
• 2.7 ≤ VDD ≤ 3.6 V
• Slew disabled
Min.
Max.
Unit
Notes
—
24
ns
—
16
10
6
ns
• 1.71 ≤ VDD ≤ 2.7 V
• 2.7 ≤ VDD ≤ 3.6 V
—
—
ns
ns
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry in run modes.
2. The greater of synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized.
4. PTB0, PTB1, PTC0, PTC1, PTC2, PTC3, PTC6, PTC7, PTC17, PTC18.
5. 75 pF load.
6. Ports A, B, and C.
7. 25 pF load.
7.4 Thermal specifications
7.4.1 Thermal operating requirements
Table 22. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
TJ
Die junction temperature
• For Laminate QFN package
Die junction temperature
• For WLCSP package
Ambient temperature
–40
125
°C
TJ
TA
TA
–40
–40
–40
95
105
85
°C
°C
°C
1
1
• For Laminate QFN package
Ambient temperature
• For WLCSP package
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to
determine TJ is: TJ = TA + RθJA × chip power dissipation.
48
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
NXP Semiconductors
MCU Electrical Characteristics
7.4.2 Thermal attributes
Table 23. Thermal attributes
Board type
Symbol
Description
48-pin
75-pin
Unit
Notes
Laminate WLCSP
QFN
Single-layer (1S)
RθJA
RθJA
RθJMA
RθJMA
RθJB
RθJC
ΨJT
Thermal resistance, junction to
ambient (natural convection)
59.3
42.9
51.6
38.9
37.7
0.48
0.2
106.7
57.2
88.0
51.7
24.7
4.3
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
2, 1
2, 1
2, 1
2, 1
3
Four-layer (2s2p)
Thermal resistance, junction to
ambient (natural convection)
Single-layer (1S)
Thermal resistance, junction to
ambient (200 ft./min. air speed)
Four-layer (2s2p)
Thermal resistance, junction to
ambient (200 ft./min. air speed)
—
—
—
Thermal resistance, junction to
board
Thermal resistance, junction to
case
4
Thermal characterization
0.2
5
parameter, junction to package top
outside center (natural convection)
—
RθJB_CSB Thermal characterization
parameter, junction to package
bottom outside center (natural
convection)
—
13.7
°C/W
6
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test
Method Environmental Conditions—Forced Convection (Moving Air).
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
3. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board. Board temperature is measured on the top surface of the board near the package.
4. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
5. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
6. Thermal resistance between the die and the central solder balls on the bottom of the package based on simulation.
7.5 Peripheral operating requirements and behaviors
7.5.1 Core modules
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
49
NXP Semiconductors
MCU Electrical Characteristics
7.5.1.1 SWD electricals
Table 24. SWD full voltage range electricals
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
J1
SWD_CLK frequency of operation
• Serial wire debug
0
25
—
MHz
ns
J2
J3
SWD_CLK cycle period
SWD_CLK clock pulse width
• Serial wire debug
1/J1
20
—
ns
J4
J9
SWD_CLK rise and fall times
—
10
0
3
ns
ns
ns
ns
ns
SWD_DIO input data setup time to SWD_CLK rise
SWD_DIO input data hold time after SWD_CLK rise
SWD_CLK high to SWD_DIO data valid
SWD_CLK high to SWD_DIO high-Z
—
—
32
—
J10
J11
J12
—
5
J2
J4
J3
J3
SWD_CLK (input)
J4
Figure 5. Serial wire clock input timing
50
NXP Semiconductors
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
MCU Electrical Characteristics
SWD_CLK
SWD_DIO
SWD_DIO
SWD_DIO
SWD_DIO
J9
J10
Input data valid
J11
Output data valid
J12
J11
Output data valid
Figure 6. Serial wire data timing
7.5.2 System modules
There are no specifications necessary for the device's system modules.
7.5.3 Clock modules
7.5.3.1 MCG specifications
Table 25. MCG specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fints_ft Internal reference frequency (slow clock) —
—
32.768
—
kHz
factory trimmed at nominal VDD and 25 °C
fints_t
Internal reference frequency (slow clock) —
user trimmed
31.25
—
—
39.0625
0.6
kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using C3[SCTRIM] and C4[SCFTRIM]
0.3
%fdco
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
+0.5/-0.7
3
%fdco
1, 2
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51
NXP Semiconductors
MCU Electrical Characteristics
Symbol Description
Table 25. MCG specifications (continued)
Min.
Typ.
Max.
Unit
Notes
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70 °C
—
0.4
1.5
%fdco
1, 2
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25 °C
—
—
4
—
3
MHz
Δfintf_ft
Frequency deviation of internal reference clock
(fast clock) over temperature and voltage —
factory trimmed at nominal VDD and 25 °C
+1/-2
%fintf_ft
2
fintf_t
Internal reference frequency (fast clock) —
user trimmed at nominal VDD and 25 °C
3
—
—
—
5
MHz
kHz
kHz
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
floc_high Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
FLL
FLL reference frequency range
31.25
20
—
39.0625
25
kHz
ffll_ref
fdco
DCO output
Low range (DRS = 00)
20.97
MHz
3, 4
5, 6
frequency range
640 × ffll_ref
Mid range (DRS = 01)
1280 × ffll_ref
40
—
—
—
—
41.94
23.99
47.97
180
48
—
—
—
1
MHz
MHz
MHz
ps
fdco_t_DMX3 DCO output
Low range (DRS = 00)
732 × ffll_ref
frequency
2
Mid range (DRS = 01)
1464 × ffll_ref
Jcyc_fll
FLL period jitter
• fVCO = 48 MHz
7
8
tfll_acquire FLL target frequency acquisition time
—
ms
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 °C, fints_ft
.
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0.
4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency deviation
(Δfdco_t) over voltage and temperature must be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification is based on standard deviation (RMS) of period or frequency.
8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
7.5.3.2 Reference Oscillator Specification
52
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
NXP Semiconductors
MCU Electrical Characteristics
The KW41Z has been designed to meet targeted specifications with a +/-20 ppm
frequency error over the life of the part, which includes the temperature, mechanical
and aging excursions.
The table below shows the recommended crystal specifications. Note that these are
recommendations only and deviation may be allowed. However, deviations may result
in degraded RF performance or possibly a failure to meet RF protocol certification
standards. Designers should do due diligence to ensure that the crystal(s) they use will
meet the requirements of their application.
Table 26. Recommended Crystal Specification
Symbol
Description
Comment
32M
Typ
26M
Typ
Unit
Min
Max
Min
Max
Operating
Temperature
-40
105
-40
105
℃
Faging
Frequency
accuracy over
aging
1st year
-5
5
-5
5
ppm -
1st yr
iFacc
Fstab
Initial Frequency with respect
-10
-10
10
10
-10
-10
10
10
ppm
ppm
accuracy
to XO
Frequency
stability
across
temperature,
mechanical ,
load and
voltage
changes
CL
Values of CL
supported(Integr
ated on die and
programmable)
7
10
13
7
10
13
pF
Co
Shunt parasitic
capacitance
0.469
1.435
0.67
2.05
0.871
2.665
0.42
0.6
0.78
pF
fF
Cm1
Motional
capacitance
Cm1
1.435
2.05
2.665
Lm1
TS
Motional
inductance Lm1
8.47
6.30
12.1
9.00
15.73
11.70
12.81
6.39
18.3
9.12
23.79
11.86
mH
Trim Sensitivity
(TS) for the
ppm/pF
supported
[Co,CL] values
TOSC
Rm1
Oscillator
Startup Time
—
680
25
—
60
—
680
35
—
60
μs
Ohms
μW
ESR: Maximum
value of Rm1
Maximum crystal
drive level limit
200
200
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
53
NXP Semiconductors
MCU Electrical Characteristics
Figure 7. Crystal Electrical Block Diagram
7.5.3.3 32 kHz Oscillator Frequency Specifications
Table 27. 32 kHz oscillator frequency specifications
Symbol
fosc_lo
tstart
Description
Min.
—
Typ.
32.768
1000
Max.
—
Unit
kHz
ms
Notes
Oscillator crystal
Crystal start-up
time
—
—
1
2
fec_extal32
Externally
provided input
clock frequency
—
32.678
—
—
kHz
mV
vec_extal32
Externally
700
VDD
2, 3
provided input
clock amplitude
1. Proper PC board layout procedures must be followed to acheive specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The
oscillator remains enabled and XTAL32 must be left unconnected.
3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied
clock must be within the range of VSS to VDD
.
7.5.4 Memories and memory interfaces
54
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
NXP Semiconductors
MCU Electrical Characteristics
7.5.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
7.5.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps
are active and do not include command overhead.
Table 28. NVM program/erase timing specifications
Symbol Description
Min.
—
Typ.
7.5
Max.
18
Unit
μs
Notes
thvpgm4 Longword Program high-voltage time
thversscr Sector Erase high-voltage time
thversblk256k Erase Block high-voltage time for 256 KB
—
1
—
13
113
904
ms
ms
—
104
1
1. Maximum time based on expectations at cycling end-of-life.
7.5.4.1.2 Flash timing specifications — commands
Table 29. Flash command timing specifications
Symbol Description
Read 1s Block execution time
• 256 KB program flash
Min.
Typ.
Max.
Unit
Notes
1
trd1blk256k
—
—
1.7
ms
trd1sec2k Read 1s Section execution time (flash sector)
tpgmchk Program Check execution time
—
—
—
—
—
—
—
65
60
45
μs
μs
μs
μs
1
1
trdrsrc
tpgm4
Read Resource execution time
Program Longword execution time
Erase Flash Block execution time
• 256 KB program flash
30
1
145
—
2
tersblk256k
—
250
1500
ms
tersscr
trd1all
Erase Flash Sector execution time
Read 1s All Blocks execution time
Read Once execution time
—
—
—
—
—
—
—
14
—
114
1.8
ms
ms
μs
2
1
trdonce
—
30
1
tpgmonce Program Once execution time
100
500
—
—
μs
—
2
tersall
tvfykey
tersallu
Erase All Blocks execution time
3000
30
ms
μs
Verify Backdoor Access Key execution time
Erase All Blocks Unsecure execution time
1
500
3000
ms
2
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
55
NXP Semiconductors
MCU Electrical Characteristics
7.5.4.1.3 Flash high voltage current behaviors
Table 30. Flash high voltage current behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_PGM
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
IDD_ERS
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
7.5.4.1.4 Reliability specifications
Table 31. NVM reliability specifications
Symbol Description
Min.
Program Flash
Typ.1
Max.
Unit
Notes
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
nnvmcycp Cycling endurance
5
50
—
—
—
years
years
cycles
—
—
2
20
100
50 K
10 K
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
7.5.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
7.5.6 Analog
7.5.6.1 ADC electrical specifications
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications. The following specification is defined with the DC-DC converter
operating in Bypass mode.
7.5.6.1.1 16-bit ADC operating conditions
Table 32. 16-bit ADC operating conditions
Symbol Description
VDDA Supply voltage
Conditions
Min.
Typ.1
Max.
Unit
Notes
Absolute
1.71
—
3.6
V
Table continues on the next page...
56
NXP Semiconductors
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
MCU Electrical Characteristics
Table 32. 16-bit ADC operating conditions (continued)
Symbol Description
Conditions
Min.
-100
-100
1.13
Typ.1
Max.
+100
+100
VDDA
Unit
mV
mV
V
Notes
ΔVDDA
ΔVSSA
VREFH
Supply voltage
Delta to VDD (VDD – VDDA
)
0
2
2
3
Ground voltage Delta to VSS (VSS – VSSA
)
0
ADC reference
voltage high
VDDA
VREFL
VADIN
ADC reference
voltage low
VSSA
VSSA
VSSA
V
V
3
Input voltage
• 16-bit differential mode
• All other modes
• 16-bit mode
VSSA
VSSA
—
—
31/32 ×
VREFH
VREFH
CADIN
Input
capacitance
—
—
8
4
10
5
pF
• 8-bit / 10-bit / 12-bit
modes
RADIN
RAS
Input series
resistance
—
—
2
5
5
kΩ
kΩ
Analog source
resistance
(external)
13-bit / 12-bit modes
fADCK < 4 MHz
4
—
fADCK
fADCK
Crate
ADC conversion ≤ 13-bit mode
clock frequency
1.0
2.0
—
—
18.0
12.0
MHz
MHz
5
5
6
ADC conversion 16-bit mode
clock frequency
ADC conversion ≤ 13-bit modes
rate
No ADC hardware averaging
20.000
37.037
—
—
818.330
461.467
kS/s
kS/s
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion 16-bit mode
6
rate
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied
to VSSA
.
4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
57
NXP Semiconductors
MCU Electrical Characteristics
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
ZAS
ADC SAR
ENGINE
RAS
RADIN
VADIN
CAS
VAS
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 8. ADC input impedance equivalency diagram
7.5.6.1.2 16-bit ADC electrical characteristics
Table 33. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Symbol Description
Conditions1
Min.
0.215
1.2
Typ.2
Max.
1.7
3.9
6.1
7.3
9.5
Unit
Notes
IDDA_ADC Supply current
—
mA
3
ADC asynchronous
clock source
• ADLPC=1, ADHSC=0
• ADLPC=1, ADHSC=1
• ADLPC=0, ADHSC=0
• ADLPC=0, ADHSC=1
2.4
4.0
5.2
6.2
MHz tADACK =
1/fADACK
2.4
fADACK
3.0
4.4
Sample Time
See Reference Manual chapter for sample times
TUE
DNL
Total unadjusted
error
• 12-bit modes
• <12-bit modes
—
—
4
6.8
2.1
LSB4
LSB4
5
5
1.4
Differential non-
linearity
• 12-bit mode; Buck
Mode6
—
—
—
0.7
0.5
0.5
–1.1 to +1.9
–1.1 to +1.9
–1.1 to +1.9
• 12-bit mode; Boost
Mode6
• 12-bit mode; Bypass
Mode
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58
NXP Semiconductors
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
MCU Electrical Characteristics
Table 33. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
INL
Integral non-
linearity
• 12-bit mode; Buck
Mode6
—
1.0
–2.7 to +1.9
LSB4
5
—
—
0.7
0.6
–2.7 to +1.9
–2.7 to +1.9
• 12-bit mode; Boost
Mode6
• 12-bit mode; Bypass
Mode
EFS
EQ
Full-scale error
• 12-bit modes
• <12-bit modes
• 16-bit modes
• ≤13-bit modes
—
—
—
—
–4
–1.4
–1 to 0
—
–5.4
–1.8
—
LSB4 VADIN
VDDA
=
5
Quantization error
LSB4
0.5
ENOB Effective number of 16-bit differential mode; Buck
bits
Mode6
7
12
12.75
11.75
—
—
bits
• Avg = 32
• Avg = 4
11.25
16-bit single-ended mode;
Buck Mode6
• Avg = 32
• Avg = 4
11
11.5
10.5
—
—
9.5
16-bit differential mode; Boost
Mode6
• Avg = 32
• Avg = 4
11.5
9.75
12
11
—
—
16-bit single-ended mode;
Boost Mode6
• Avg = 32
• Avg = 4
11
11.5
10.5
—
—
9.75
16-bit differential mode;
Bypass Mode
• Avg = 32
• Avg = 4
12.5
13
12
—
—
11.25
16-bit single-ended mode;
Bypass Mode
• Avg = 32
• Avg = 4
11
10
11.75
10.5
—
—
Signal-to-noise plus See ENOB
distortion
SINAD
6.02 × ENOB + 1.76
dB
THD Total harmonic
distortion
16-bit differential mode; Buck
Mode6
8
• Avg = 32
—
-90
—
dB
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NXP Semiconductors
MCU Electrical Characteristics
Table 33. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
16-bit single-ended mode;
Buck Mode6
—
-88
—
• Avg = 32
16-bit differential mode; Boost
Mode6
—
—
—
-89
-89
-89
-87
—
—
—
—
• Avg = 32
16-bit single-ended mode;
Boost Mode6
• Avg = 32
16-bit differential mode;
Bypass Mode
• Avg = 32
—
16-bit single-ended mode;
Bypass Mode
• Avg = 32
Signal-to-noise plus See ENOB
distortion
SINAD
6.02 × ENOB + 1.76
dB
dB
SFDR Spurious free
dynamic range
distortion
16-bit differential mode; Buck
Mode6
8
• Avg = 32
85
85
89
87
—
16-bit single-ended mode;
Buck Mode6
• Avg = 32
—
—
—
—
—
16-bit differential mode; Boost
Mode6
• Avg = 32
78
85
87
85
86
87
94
88
16-bit single-ended mode;
Boost Mode6
• Avg = 32
16-bit differential mode;
Bypass Mode
• Avg = 32
16-bit single-ended mode;
Bypass Mode
• Avg = 32
EIL
Input leakage error
IIn × RAS
mV
IIn =
leakage
current
Table continues on the next page...
60
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MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
MCU Electrical Characteristics
Table 33. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
(see
Voltage
and
current
operating
ratings)
Temp sensor slope Across the full temperature
range of the device
1.67
706
1.74
716
1.81
726
mV/°
C
9
VTEMP25 Temp sensor
voltage
25 °C
mV
9
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
.
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with
1 MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N.
5. ADC conversion clock < 16 MHz, maximum hardware averaging (AVGE = %1, AVGS = %11).
6. VREFH = Output of Voltage Reference(VREF).
7. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
8. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
9. ADC conversion clock < 3 MHz.
7.5.6.2 Voltage reference electrical specifications
Table 34. VREF full-range operating requirements
Symbol
VDDA
TA
Description
Min.
Max.
Unit
V
Notes
Supply voltage
Temperature
1.71
3.6
-40 to 105
100
°C
nF
CL
Output load capacitance
1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature
range of the device.
Table 35. VREF full-range operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
1.190
1.1950
1.2
V
1
nominal VDDA and temperature=25°C
Vout
Voltage reference output with user trim at
nominal VDDA and temperature=25°C
1.1945
—
1.1950
0.5
1.1955
—
V
1
1
Vstep
Voltage reference trim step
mV
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MCU Electrical Characteristics
Table 35. VREF full-range operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Vtdrift
Temperature drift (Vmax -Vmin across the full
—
—
20
mV
1
temperature range)
Ibg
Ilp
Bandgap only current
Low-power buffer current
High-power buffer current
—
—
—
—
—
—
80
360
1
µA
uA
mA
µV
1
1
Ihp
ΔVLOAD Load regulation
• current = 1.0 mA
1, 2
—
200
—
Tstup
Buffer startup time
—
—
—
—
100
35
µs
Tchop_osc_st Internal bandgap start-up delay with chop
ms
oscillator enabled
up
Vvdrift
Voltage drift (Vmax -Vmin across the full voltage
range)
—
2
—
mV
1
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 36. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
TA
Temperature
0
70
°C
Table 37. VREF limited-range operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
Vtdrift
Temperature drift (Vmax -Vmin across the limited
temperature range)
—
15
mV
7.5.6.3 CMP and 6-bit DAC electrical specifications
Table 38. Comparator and 6-bit DAC electrical specifications
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
Unit
V
Supply voltage
IDDHS
IDDLS
VAIN
Supply current, High-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
—
200
20
μA
μA
V
—
—
VSS – 0.3
—
—
VDD
20
VAIO
Analog input offset voltage
—
mV
VH
Analog comparator hysteresis1
—
5
—
mV
• CR0[HYSTCTR] = 00
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NXP Semiconductors
MCU Electrical Characteristics
Table 38. Comparator and 6-bit DAC electrical specifications (continued)
Symbol
Description
• CR0[HYSTCTR] = 01
Min.
Typ.
Max.
Unit
—
10
—
mV
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
—
—
20
30
—
—
mV
mV
VCMPOh
VCMPOl
tDHS
Output high
VDD – 0.5
—
—
—
50
250
—
7
—
0.5
200
600
40
V
V
Output low
Propagation delay, high-speed mode (EN=1, PMODE=1)
Propagation delay, low-speed mode (EN=1, PMODE=0)
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
20
ns
tDLS
80
ns
—
μs
IDAC6b
INL
—
—
μA
LSB3
LSB
–0.5
–0.3
—
—
0.5
0.3
DNL
6-bit DAC differential non-linearity
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
0.08
0.07
0.06
HYSTCTR
Setting
0.05
0.04
0.03
00
01
10
11
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 9. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
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NXP Semiconductors
MCU Electrical Characteristics
0.18
0.16
0.14
0.12
HYSTCTR
Setting
0.1
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 10. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
7.5.6.4 12-bit DAC electrical characteristics
7.5.6.4.1 12-bit DAC operating requirements
Table 39. 12-bit DAC operating requirements
Symbol
VDDA
VDACR
CL
Desciption
Min.
1.71
1.13
—
Max.
3.6
3.6
100
1
Unit
V
Notes
Supply voltage
Reference voltage
Output load capacitance
Output load current
V
1
2
pF
mA
IL
—
1. The DAC reference can be selected to be VDDA or VREF_OUT
.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
64
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
NXP Semiconductors
MCU Electrical Characteristics
7.5.6.4.2 12-bit DAC operating behaviors
Table 40. 12-bit DAC operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA_DACL Supply current — low-power mode
—
—
250
μA
P
IDDA_DACH Supply current — high-speed mode
—
—
—
—
—
100
15
900
200
30
μA
μs
μs
μs
P
tDACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
1
1
1
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08) — low-power mode and high-
speed mode
0.7
1
Vdacoutl DAC output voltage range low — high-
speed mode, no load, DAC set to 0x000
—
—
—
—
—
—
100
mV
mV
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
VDACR
INL
DNL
DNL
Integral non-linearity error — high speed
mode
—
—
—
8
1
1
LSB
LSB
LSB
2
3
4
Differential non-linearity error — VDACR > 2
V
Differential non-linearity error — VDACR
VREF_OUT
=
VOFFSET Offset error
EG Gain error
PSRR Power supply rejection ratio, VDDA ≥ 2.4 V
—
—
60
—
—
—
0.4
0.1
0.8
0.6
90
%FSR
%FSR
dB
5
5
—
TCO
TGE
Rop
SR
Temperature coefficient offset voltage
Temperature coefficient gain error
Output resistance (load = 3 kΩ)
Slew rate -80h→ F7Fh→ 80h
3.7
—
μV/C
%FSR/C
Ω
6
0.000421
—
—
250
V/μs
• High power (SPHP
)
1.2
1.7
—
—
• Low power (SPLP
3dB bandwidth
)
0.05
0.12
BW
kHz
• High power (SPHP
• Low power (SPLP
)
550
40
—
—
—
—
)
1. Settling within 1 LSB
2. The INL is measured for 0 + 100 mV to VDACR −100 mV
3. The DNL is measured for 0 + 100 mV to VDACR −100 mV
4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC
set to 0x800, temperature range is across the full range of the device
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65
NXP Semiconductors
MCU Electrical Characteristics
8
6
4
2
0
-2
-4
-6
-8
0
500
1000
1500
2000
2500
3000
3500
4000
Digital Code
Figure 11. Typical INL error vs. digital code
66
NXP Semiconductors
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
MCU Electrical Characteristics
1.499
1.4985
1.498
1.4975
1.497
1.4965
1.496
55
85
25
105
125
-40
Temperature °C
Figure 12. Offset at half scale vs. temperature
7.5.7 Timers
See General switching specifications.
7.5.8 Communication interfaces
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MCU Electrical Characteristics
7.5.8.1 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provide DSPI timing characteristics for classic SPI timing modes. See the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 41. Master mode DSPI timing (limited voltage range)
Num
Description
Min.
2.7
Max.
3.6
12
Unit
V
Notes
Operating voltage
Frequency of operation
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
2 x tBUS
—
(tSCK/2) − 2 (tSCK/2) + 2
ns
(tBUS x 2) −
2
—
ns
1
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
2
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
-2
8.5
—
—
—
ns
ns
ns
ns
16.2
0
1. The delay is programmable in SPIx_CTARn[PCSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
SPI_PCSn
DS1
DS3
DS2
DS4
SPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
SPI_SIN
DS5
DS6
First data
Data
Last data
SPI_SOUT
Figure 13. DSPI classic SPI timing — master mode
Table 42. Slave mode DSPI timing (limited voltage range)
Num
Description
Min.
Max.
3.6
6
Unit
V
Operating voltage
2.7
Frequency of operation
MHz
Table continues on the next page...
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68
NXP Semiconductors
MCU Electrical Characteristics
Table 42. Slave mode DSPI timing (limited voltage range) (continued)
Num
DS9
Description
DSPI_SCK input cycle time
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
4 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) − 2
(tSCK/2) + 2
DSPI_SCK to DSPI_SOUT valid
—
0
21.4
—
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
2.6
7.0
—
—
—
—
14
14
SPI_SS
DS10
DS9
SPI_SCK
(POL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
SPI_SOUT
Data
Data
DS13
First data
Last data
SPI_SIN
Figure 14. DSPI classic SPI timing — slave mode
7.5.8.2 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provide DSPI timing characteristics for classic SPI timing modes. See
the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 43. Master mode DSPI timing (full voltage range)
Num
Description
Min.
1.71
Max.
3.6
12
Unit
V
Notes
Operating voltage
1
Frequency of operation
—
MHz
ns
DS1
DS2
DSPI_SCK output cycle time
DSPI_SCK output high/low time
2 x tBUS
—
(tSCK/2) - 4 (tSCK/2) + 4
Table continues on the next page...
ns
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MCU Electrical Characteristics
Table 43. Master mode DSPI timing (full voltage range) (continued)
Num
Description
Min.
Max.
Unit
Notes
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2) −
4
—
ns
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
3
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
-1.2
23.3
0
10
—
—
—
ns
ns
ns
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PCSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
SPI_PCSn
DS1
DS3
DS2
DS4
SPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
SPI_SIN
DS5
DS6
First data
Data
Last data
SPI_SOUT
Figure 15. DSPI classic SPI timing — master mode
Table 44. Slave mode DSPI timing (full voltage range)
Num
Description
Min.
Max.
Unit
V
Operating voltage
1.71
3.6
Frequency of operation
—
6
MHz
ns
DS9
DSPI_SCK input cycle time
4 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
29.1
—
ns
ns
3.2
7.0
—
—
—
ns
—
ns
25
25
ns
ns
70
NXP Semiconductors
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
MCU Electrical Characteristics
SPI_SS
DS10
DS9
SPI_SCK
(POL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
SPI_SOUT
Data
Data
DS13
First data
Last data
SPI_SIN
Figure 16. DSPI classic SPI timing — slave mode
7.5.8.3 Inter-Integrated Circuit Interface (I2C) timing
Table 45. I 2C timing
Characteristic
Symbol
Standard Mode
Fast Mode
Unit
Minimum Maximum
Minimum Maximum
SCL Clock Frequency
fSCL
0
4
100
—
0
400
—
kHz
µs
Hold time (repeated) START condition. tHD; STA
After this period, the first clock pulse is
generated.
0.6
LOW period of the SCL clock
HIGH period of the SCL clock
tLOW
tHIGH
4.7
4
—
—
—
1.3
0.6
0.6
—
—
—
µs
µs
µs
Set-up time for a repeated START
condition
tSU; STA
4.7
Data hold time for I2C bus devices
tHD; DAT
tSU; DAT
tr
01
2504
—
3.452
—
03
1002, 5
20 +0.1Cb
20 +0.1Cb
0.6
0.91
—
µs
ns
ns
ns
µs
µs
Data set-up time
6
5
Rise time of SDA and SCL signals
Fall time of SDA and SCL signals
Set-up time for STOP condition
1000
300
—
300
300
—
tf
—
tSU; STO
tBUF
4
Bus free time between STOP and
START condition
4.7
—
1.3
—
Pulse width of spikes that must be
suppressed by the input filter
tSP
N/A
N/A
0
50
ns
1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and
SCL lines.
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
3. Input signal Slew = 10 ns and Output Load = 50 pF.
4. Set-up time in slave-transmitter mode is 1 IP Bus clock period, if the TX FIFO is empty.
5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
71
NXP Semiconductors
MCU Electrical Characteristics
+ tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is
released.
6. Cb = total capacitance of the one bus line in pF.
SDA
tSU; DAT
tf
tr
tBUF
tf
tr
tHD; STA
tSP
tLOW
SCL
tSU; STA
tSU; STO
HD; STA
S
SR
P
S
tHD; DAT
tHIGH
Figure 17. Timing definition for fast and standard mode devices on the I2C bus
7.5.8.4 LPUART
See General switching specifications.
7.5.9 Human-machine interfaces (HMI)
7.5.9.1 TSI electrical specifications
Table 46. TSI electrical specifications
Symbol
Ta
Description
Temperature
Min.
-30
—
Typ.
—
Max.
105
—
Unit
°C
TSI_RUNF
TSI_RUNV
Fixed power consumption in run mode
100
—
µA
Variable power consumption in run mode
(depends on oscillator's current selection)
1.0
128
µA
TSI_EN
TSI_DIS
Power consumption in enable mode
Power consumption in disable mode
TSI analog enable time
—
—
100
1.2
66
—
—
µA
µA
µs
pF
V
TSI_TEN
—
—
TSI_CREF
TSI_DVOLT
TSI reference capacitor
—
1.0
—
—
Voltage variation of VP & VM around nominal
values
0.19
1.03
7.5.9.2 GPIO
The maximum input voltage on PTC0/1/2/3 is VDD+0.3V. For rest of the GPIO
specification, see General switching specifications.
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MCU Electrical Characteristics
7.6 DC-DC Converter Operating Requirements
Table 47. DC-DC Converter Recommended operating conditions
Characteristic
Symbol
Min
Typ
Max
Unit
Bypass Mode Supply Voltage (RF and Analog)
VDDRF1
VDDRF2
,
,
1.425
—
3.6
Vdc
VDDRF3
Bypass Mode Supply Voltage (Digital)
VDDX, VDCDC_IN
,
1.71
1.12
—
—
3.6
Vdc
Vdc
VDDA
Boost Mode Supply Voltage
VDDDCDC_IN
1.795
1
Buck Mode Supply Voltage3, 1, 4
External Inductor5
VDDDCDC_IN
L_DCDC
ESR
2.1
—
10
0.2
—
4.25
Vdc
uH
Inductor Resistance in Buck Mode
Inductor Resistance in Boost Mode
—
—
0.5
0.2
Ohms
Ohms
ESR
1. VDD_1P5 is 1.8 V by default in Boost mode. VDD_1P8OUT should supply to VDD1, VDD2 and VDDA.
VDD_1P5OUT_PMCIN should supply to VDD_RF1 and VDD_RF2. VDDXTAL can be either supplied by 1.5 V or 1.8 V
2. In boost mode, DC-DC converter needs minimum 1.1 V to start, the supply can drop to 0.9 V after the DC-DC
converter settles.
3. In Buck mode, DC-DC converter needs 2.1 V min to start, the supply can drop to 1.8 V after DC-DC converter settles
4. When 3.6 V < VDDDCDC_IN / DCDC_CFG / PSWITCH <= 4.25 V, TA and TJ are constrained to a maximum of +45 °C
and +65 °C respectively (typical Li-ion maximum temperatures when charging). When VDDDCDC_IN / DCDC_CFG /
PSWITCH <= 3.6 V, TA and TJ are constrained to a maximum of +105 °C and +125 °C respectively.
5. In both Buck and Boost modes, LN and LP are connected to external inductor. In boost mode, LP is also shorted to
VDCDC_IN.
Table 48. DC-DC Converter Specifications
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
DC-DC Converter Output
Power
Total power
output of 1P8V
and 1P5V
Pdcdc_out
—
—
1251
mW
Switching Frequency2
Half FET Threshold
Double FET Threshold
Boost Mode
DCDC_FREQ
I_half_FET
—
—
—
2
5
—
—
—
MHz
mA
I_double_FET
40
mA
EN_THRESH_b
oost
Enable Threshold
-
50
-
mV
DCDC_EFF_bo
ost
DC-DC Conversion Efficiency
1.8 V Output Voltage
-
90 %
1.83
-
VDD_1P8_boos
t
1.71
3.5
Vdc
Table continues on the next page...
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MCU Electrical Characteristics
Table 48. DC-DC Converter Specifications (continued)
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
VDD_1P8 = 1.8 IDD_1P8_boost
—
—
45
mA
V, VDCDC_IN =
1.7 V
1
VDD_1P8 = 3.0 IDD_1P8_boost
—
—
—
—
—
—
27
20
10
mA
mA
mA
V, VDCDC_IN =
1.7 V
2
1.8 V Output Current4, 5
VDD_1P8 = 1.8 IDD_1P8_boost
V, VDCDC_IN =
0.9 V
3
VDD_1P8 = 3.0 IDD_1P8_boost
V, VDCDC_IN =
0.9 V
4
VDD_1P5_boos 1.4256, 7
t
1.86, 7
—
2.0
30
—
Vdc
mA
us
1.5V Output Voltage
VDD_1P5_boos
t
—
1.5 V Output Current4, 8
DCDC Transition Operating LSS➔Run
t_DCDCboost_L
—
50
Behavior
S S➔RUN
DCDC Turn on Time
TDCDC_ON_boost
—
—
2.39
—
—
ms
ms
DCDC Settling Time for
increasing voltage
TDCDC_SETTLE_bo
0.271
ost
C = capacitance TDCDC_SETTLE_bo
—
(C*(V1-V2)/I2
—
s
attached to the
DCDC V1P8
output rail.
ost
V1 = the initial
output voltage of
the DCDC.
DCDC Settling Time for
decreasing voltage
V2 = the final
output voltage of
the DCDC.
I2 = the load on
the DCDC output
expressed in
Amperes.
Buck Mode
DC-DC Conversion Efficiency
DCDC_EFF_bu
ck
—
90 %
—
—
—
VDD_1P8_buck
1.71
min(VDCDC Vdc
_IN_buck,
1.8 V Output Voltage
3.5)10, 3
VDD_1P8 = 1.8 IDD_1P8_buck1
—
—
45
mA
1.8 V Output Current4, 5 V, VDC_1P5 =
1.5 V
Table continues on the next page...
74
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MCU Electrical Characteristics
Table 48. DC-DC Converter Specifications (continued)
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
VDD_1P8 = 3.0 IDD_1P8_buck2
—
—
27
mA
V, VDC_1P5 =
1.5 V
Radio section
requires 1.5 V
VDD_1P5_buck 1.42511
1.511
1.65
Vdc
1.5 V Output Voltage
1.5 V Output Current4, 8
IDD_1P5_buck
—
—
—
30
—
mA
us
DCDC Transition Operating LSS➔Run
t_DCDCbuck_L
50
Behavior
S S➔RUN
DCDC Turn on Time
TDCDC_ON_buck
—
—
2.29
—
—
ms
ms
DCDC Settling Time for
increasing voltage
TDCDC_SETTLE_bu
0.371
ck
C = capacitance TDCDC_SETTLE_bu
—
(C*(V1-V2)/I2
—
s
attached to the
DCDC V1P8
output rail.
ck
V1 = the initial
output voltage of
the DCDC
DCDC Settling Time for
decreasing voltage
V2 = the final
output voltage of
the DCDC
I2 = the load on
the DCDC output
expressed in
Amperes.
1. This is the steady state DC output power. It requires VDCDC_IN >= 1.7V in boost mode. Excessive transient current
load from external device will cause 1p8V and 1P5 output voltage unregulated temporary.
2. This is the frequency that will be observed at LN and LP pins.
3. The voltage output level can be controlled by programming DCDC_VDD1P8CTRL_TRG field in DCDC_REG3.
4. The output current specification in both buck and boost modes represents the maximum current the DC-DC converter
can deliver. The KW41Z radio and MCU blocks current consumption is not excluded. Note that the maxium output
power of the DC-DC converter is 125mW. The available supply current for external device depends on the energy
consumed by the internal peripherals in KW41Z.
5. When using DC-DC in low power mode(pulsed mode), current load must be less than 0.5 mA.
6. The minimum VDD_1P5_boost is the maximum of either what is programmed using
DCDC_VDD1P5CTRL_TRG_BOOST field in DCDC_REG3 or VDCDC_IN_boost + 0.05V. For example, if VDCDC_IN
= 0.9V, minimum VDD_1P5 is as programmed in DCDC_VDD1P5CTRL_ TRG_BOOST. If VDCDC_IN = 1.5V,
minimum VDD_1P5 = 1.5 + 0.05V is 1.55V.
7. 1.8 V is the default value of the DC-DC 1.5 V output voltage in boost mode. The user can program
DCDC_VDD1P5CTRL_TRG_BOOST field in register DCDC_REG3 to control 1.5 V output voltage level. For reliable
radio operation, a voltage level of 1.425 V is required. VDD_1P5 must not be programmed higher than VDD_1P8.
8. 1.5 V is intended to supply power to KW41Z only. It is not designed to supply power to an external device.
9. Turn on time is measured from the application of power (to DCDC_IN) to when the
DCDC_REG0[DCDC_STS_DC_OK] bit is set. Code execution may begin before the
DCDC_REG0[DCDC_STS_DC_OK] bit is set. Full device specification is not guaranteed until the bit sets.
10. In Buck mode, the maximum VDD_1P8 output is the minimum of either VDCDC_IN_BUCK minus 50 mV or 3.5 V. For
example, if VDCDC_IN = 1.85V, maximum VDD_1P8 is 1.8V. If VDCDC_IN = 4.2V, maximum VDD_1P8 is 3V.
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75
NXP Semiconductors
MCU Electrical Characteristics
11. 1.5 V is the default value of DCDC VDD_1P5 in buck mode. The user can program DCDC_VDD1P5CTRL_TRG_BUCK
field in register DCDC_REG3 to control 1P5 output voltage level. For Radio operation, minimum 1.425 V is required.
VDD_1P5 must not be programmed higher than VDD_1P8.
7.7 Ratings
7.7.1 Thermal handling ratings
Table 49. Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
7.7.2 Moisture handling ratings
Table 50. Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
7.7.3 ESD handling ratings
Table 51. ESD handling ratings
Symbol
VHBM
Description
Min.
–2000
–500
Max.
+2000
+500
Unit
V
Notes
Electrostatic discharge voltage, human body model
1
2
VCDM
Electrostatic discharge voltage, charged-device
model
V
ILAT
Latch-up current at ambient temperature of 105 °C
–100
+100
mA
3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
76
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Pin Diagrams and Pin Assignments
7.7.4 Voltage and current operating ratings
Table 52. Voltage and current operating ratings
Symbol
VDD
IDD
Description
Min.
–0.3
—
Max.
3.8
Unit
V
Digital supply voltage
Digital supply current
IO pin input voltage
120
mA
V
VIO
–0.3
–25
VDD + 0.3
25
ID
Instantaneous maximum current single pin limit (applies to
all port pins)
mA
VDDA
Analog supply voltage
VDD – 0.3
GND
VDD + 0.3
VDCDC
V
V
VIO_DCDC
IO pins in the DCDC voltage domain (DCDC_CFG and
PSWITCH)
8 Pin Diagrams and Pin Assignments
8.1 Pinouts
Device pinout are shown in figures below.
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
77
NXP Semiconductors
Pin Diagrams and Pin Assignments
PTA0
PTA1
1
36
35
34
33
32
31
30
29
28
27
26
25
VDD_RF1
VDD_RF2
GANT
2
PTA2
3
61
57
53
49
62
58
54
50
63
59
55
51
64
60
56
52
PTA16
4
ANT
PTA17
5
VDD_RF3
XTAL
PTA18
6
PTA19
7
EXTAL
PSWITCH
DCDC_CFG
VDCDC_IN
DCDC_LP
DCDC_LN
8
XTAL_OUT
VDDA
9
10
11
12
VREFH/VREF_OUT
VSSA
ADC0_DM0
*pin 49 - 64 are ground
Figure 18. 48-pin Laminate QFN pinout diagram
78
NXP Semiconductors
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
Pin Diagrams and Pin Assignments
1
2
3
4
VSS
5
6
7
8
9
A
B
C
D
E
F
PTC3
VSS
PTC4
PTC2
PTC1
VSS
PTC7
PTC6
PTC5
VDD_1
PTA16
VSS
PTC16
PTC17
PTC19
PTA0
PTC18
PTA1
GANT
XTAL
ANT
VDD_RF3
VSS
VDD_RF2
VSS
VDD_RF1
VSS
PTC0
VSS
PTA2
EXTAL
VSS
VSS
PTA17
PTA19
PSWITCH
XTAL_OUT
VDDA
VSS
VSS
VSS
VSS
VDD_1
VSS
PTA18
VREFH_VREF
OUT
PTB18
VSS
VSS
VSS
DCDC_CFG
G
H
J
VSSA
VSSA
VSS
VSS
PTB3
VSS
PTB2
PTB1
PTB0
VDD_1P8OUT DCDC_GND VDCDC_IN
VDD_1P5_P
ADC0_DM0
ADC0_DP0
PTB17
PTB16
DCDC_LN
DCDC_LP
MCIN
VDD_1P5_C
AP
VSS
VDD_0
VSS
= No Ball
Figure 19. KW41 75-pin WLCSP Pinout Diagram
8.2 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and locations of these
pins on the packages supported by this device. The Port Control Module is responsible
for selecting which ALT functional is available on each PTxy pin.
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
79
NXP Semiconductors
Pin Diagrams and Pin Assignments
NOTE
On the 75 WLCSP, VDD_1P5_CAP and VDD_1P5_PMCIN
should be tied together external to the device.
Table 53. KW41Z Pin Assignments
KW41
Z(48 (WLCSP
KW41
Pin
Name
DEFAUL
T
ALT0
ALT1
ALT2 ALT3 ALT4 ALT AL ALT7
5
T6
LGA /
Lamin
ate
)
QFN)
1
D8
B9
C9
E7
D9
E8
E9
PTA0
SWD_DIO TSIO_CH8
PTA0
SPI0_P
CS1
TPM
1_CH
0
SWD_
DIO
2
3
4
5
6
7
PTA1
SWD_CL TSI0_CH9
K
PTA1
PTA2
SPI1_P
CS0
TPM
1_CH
1
SWD_
CLK
PTA2
RESET_b
TPM
0_CH
3
RESE
T_b
PTA16
PTA17
PTA18
PTA19
DISABLE TSI0_CH10
D
PTA16/
LLWU_P4
SPI1_S
OUT
TPM
0_CH
0
DISABLE TSI0_CH11
D
PTA17/
LLWU_P5/
RF_RESET
SPI1_SI
N
TPM
_CLK
IN1
DISABLE TSI0_CH12
D
PTA18/
LLWU_P6
SPI1_S
CK
TPM
2_CH
0
DISABLE TSI0_CH13/
PTA19/
LLWU_P7
SPI1_P
CS0
TPM
2_CH
1
D
ADC0_SE5
8
9
F9
F8
PSWITCH PSWITCH PSWITCH
DCDC_C DCDC_CF DCDC_CFG
FG
G
10
11
12
13
14
15
G9
H9
H8
G8
G7
VDCDC_I VDCDC_I VDCDC_IN
N
N
DCDC_L DCDC_LP DCDC_LP
P
DCDC_L DCDC_LN DCDC_LN
N
DCDC_G DCDC_G DCDC_GND
ND
VDD_1P8 VDD_1P8 VDD_1P8OUT
OUT OUT
ND
VDD_1P5 VDD_1P5 VDD_1P5OUT_
OUT_PM OUT_PM PMCIN
CIN
CIN
Table continues on the next page...
80
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NXP Semiconductors
Pin Diagrams and Pin Assignments
Table 53. KW41Z Pin Assignments (continued)
KW41
Z(48 (WLCSP
KW41
Pin
Name
DEFAUL
T
ALT0
ALT1
ALT2 ALT3 ALT4 ALT AL ALT7
5
T6
LGA /
Lamin
ate
)
QFN)
J8
H7
J6
VDD_1P5 VDD_1P5 VDD_1P5_CAP
_CAP _CAP
VDD_1P5 VDD_1P5 VDD_1P5_PM
_PMCIN _PMCIN CIN
16
PTB0
DISABLE
D
PTB0/
I2C0_ CMP0_ TPM
CLKO
UT
LLWU_P8/
XTAL_OUT_E
N
SCL OUT
0_CH
1
17
18
19
H6
G6
G5
PTB1
PTB2
PTB3
DISABLE ADC0_SE1/
CMP0_IN5
PTB1
PTB2
PTB3
DTM_R I2C0_ LPTM TPM
CMT_I
RO
D
X
SDA R0_AL 0_CH
T1
2
DISABLE ADC0_SE3/
CMP0_IN3
RF_NO DTM_
T_ALLO TX
WED
TPM
1_CH
0
D
DISABLE ADC0_SE2/
CLKO TPM
RTC_
CLKO
UT
D
CMP0_IN4
UT
1_CH
1
20
21
J5
VDD_0
PTB16
VDD_0
VDD_0
H4
EXTAL32 EXTAL32K
K
PTB16
PTB17
PTB18
I2C1_
SCL
TPM
2_CH
0
22
23
24
H3
F3
J1
PTB17
PTB18
XTAL32K XTAL32K
I2C1_
SDA
TPM
2_CH
1
BSM_
CLK
NMI_b
DAC0_OUT/
ADC0_SE4/
CMP0_IN2
I2C1_ TPM_ TPM
SCL CLKIN 0_CH
NMI_b
0
0
ADC0_DP ADC0_DP ADC0_DP0/
0
0/
CMP0_IN0
CMP0_IN
0
25
H1
ADC0_D ADC0_DM ADC0_DM0/
M0
0/
CMP0_IN1
CMP0_IN
1
26
27
G1, G2
F2
VSSA
VSSA
VSSA
VREFH/ VREFH/
VREFH/
VREF_O VREF_OU VREF_OUT
UT
T
28
29
F1
E1
VDDA
VDDA
VDDA
XTAL_OU XTAL_OU XTAL_OUT
T
T
Table continues on the next page...
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
81
NXP Semiconductors
Pin Diagrams and Pin Assignments
Table 53. KW41Z Pin Assignments (continued)
KW41
Z(48 (WLCSP
KW41
Pin
Name
DEFAUL
T
ALT0
ALT1
ALT2 ALT3 ALT4 ALT AL ALT7
5
T6
LGA /
Lamin
ate
)
QFN)
30
31
32
33
34
35
36
D1
C1
C2
B2
B1
B3
B4
C5
EXTAL
XTAL
EXTAL
XTAL
EXTAL
XTAL
VDD_RF3 VDD_RF3 VDD_RF3
ANT
ANT
ANT
GANT
GANT
GANT
VDD_RF2 VDD_RF2 VDD_RF2
VDD_RF1 VDD_RF1 VDD_RF1
PTC0
DISABLE
D
PTC0/
LLWU_P9
ANT_A I2C0_ LPUAR TPM
SCL T0_CT 0_CH
S_b
1
37
C6
PTC1
DISABLE
D
PTC1
ANT_B I2C0_ LPUAR TPM
SDA T0_RT 0_CH
BLE_
RF_A
CTIVE
S_b
TX_SWI I2C1_ LPUAR CMT
TCH SCL T0_RX _IRO
RX_SWI I2C1_ LPUAR TPM
2
38
39
B6
A5
PTC2
PTC3
DISABLE TSI0_CH14/
PTC2/
LLWU_P10
DTM_
RX
D
DIAG1
DISABLE TSI0_CH15/
DIAG2
PTC3/
LLWU_P11
DTM_
TX
D
TCH
SDA T0_TX 0_CH
1
40
41
42
A6
C7
B7
PTC4
PTC5
PTC6
DISABLE TSI0_CH0/
DIAG3
PTC4/
LLWU_P12
ANT_A EXTR LPUAR TPM
G_IN T0_CT 1_CH
BSM_
DATA
D
S_b
0
DISABLE TSI0_CH1/
DIAG4
PTC5/
LLWU_P13
RF_NO LPTM LPUAR TPM
T_ALLO R0_A T0_RT 1_CH
BSM_
CLK
D
WED
LT2
S_b
1
DISABLE TSI0_CH2
D
PTC6/
I2C1_ LPUAR TPM
SCL T0_RX 2_CH
0
BSM_
FRAM
E
LLWU_P14/
XTAL_OUT_E
N
43
A7
PTC7
DISABLE TSI0_CH3
D
PTC7/
LLWU_P15
SPI0_P I2C1_ LPUAR TPM
BSM_
DATA
CS2
SDA T0_TX 2_CH
1
44
45
E6, D7
A8
VDD_1
PTC16
VDD_1
VDD_1
DISABLE TSI0_CH4
D
PTC16/
LLWU_P0
SPI0_S I2C0_ LPUAR TPM
CK SDA T0_RT 0_CH
S_b
3
46
47
B8
A9
PTC17
PTC18
DISABLE TSI0_CH5
D
PTC17/
LLWU_P1
SPI0_S I2C1_ LPUAR BSM
DTM_
RX
OUT
SCL T0_RX _FRA
ME
DISABLE TSI0_CH6
D
PTC18/
LLWU_P2
SPI0_SI I2C1_ LPUAR BSM
DTM_
TX
N
SDA T0_TX _DAT
A
Table continues on the next page...
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
82
NXP Semiconductors
Pin Diagrams and Pin Assignments
Table 53. KW41Z Pin Assignments (continued)
KW41
Z(48 (WLCSP
KW41
Pin
Name
DEFAUL
T
ALT0
ALT1
ALT2 ALT3 ALT4 ALT AL ALT7
5
T6
LGA /
Lamin
ate
)
QFN)
48
C8
PTC19
Ground
DISABLE TSI0_CH7
D
PTC19/
LLWU_P3
SPI0_P I2C0_ LPUAR BSM
BLE_
RF_A
CTIVE
CS0
SCL T0_CT _CLK
S_b
49-64 A4, B5,
C3, C4,
D2, D3,
D4, D5,
D6, E2,
E3, E4,
E5, F4,
F5, F6,
F7, G3,
G4, H2,
H5, J2,
J7
NA
8.3 Module Signal Description Tables
The following sections correlate the chip-level signal name with the signal name used
in the module's chapter. They also briefly describe the signal function and direction.
8.3.1 Core Modules
This section contains tables describing the core module signal descriptions.
Table 54. SWD Module Signal Descriptions
SoC Signal Name
SWD_DIO
Module Signal Name
SWD_DIO
Description
I/O
Serial Wire Debug Data
Input/Output1
Serial Wire Clock2
I/O
I
SWD_CLK
SWD_CLK
1. Pulled up internally by default
2. Pulled down internally by default
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
83
NXP Semiconductors
Pin Diagrams and Pin Assignments
8.3.2 Radio Modules
This section contains tables describing the radio signals.
Table 55. Radio Module Signal Descriptions
SoC Signal Name
Module Signal Name
ANT
Description
I/O
ANT
Antenna
O
I
GANT
GANT
Antenna ground
BLE_RF_ACTIVE
BLE_RF_ACTIVE
Signal to indicate future BLE
activity. Refer BLE Link Layer
for more details.
O
RF_NOT_ALLOWED
RF_NOT_ALLOWED
Radio off signal, intended for
WiFi coexistence control
I
RF_RESET
DTM_RX
DTM_TX
RF_RESET
DTM_RX
DTM_TX
Radio reset signal
I
Direct Test Mode Receive
Direct Test Mode Transmit
I
O
O
BSM_CLK
BSM_CLK
Bit Streaming Mode (BSM)
Clock signal, 802.15.4 packet
data stream clock line
BSM_FRAME
BSM_DATA
BSM_FRAME
BSM_DATA
Bit Streaming Mode Frame
signal, 802.15.4 packet data
stream frame line
O
Bit Streaming Mode Data
signal, 802.15.4 packet data
stream data line
I/O
ANT_A
ANT_A
Antenna selection A for Front O
End Module support
ANT_B
ANT_B
Antenna selection B for Front O
End Module support
TX_SWITCH
RX_SWITCH
TX_SWITCH
RX_SWITCH
Front End Module Transmit
mode signal
O
Front End Module Receive
mode signal
O
8.3.3 System Modules
This section contains tables describing the system signals.
Table 56. System Module Signal Descriptions
SoC Signal Name
NMI_b
Module Signal Name
Description
Non-maskable interrupt
Reset bidirectional signal
Power supply
I/O
—
—
I
RESET_b
VDD_[1:0]
I/O
I
VDD
Table continues on the next page...
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
84
NXP Semiconductors
Pin Diagrams and Pin Assignments
Table 56. System Module Signal Descriptions (continued)
SoC Signal Name
Ground
Module Signal Name
VSS
Description
I/O
Ground
I
VDD_RF[3:1]
VDCDC_IN
VDD_RF
Radio power supply
VDCDC_IN
I
VDCDC_IN
VDD_1P8
I
VDD_1P8OUT
DCDC 1.8 V Regulated
Output / Input in bypass
I/O
VDD_1P5OUT_PMCIN
VDD_1P5_CAP1
VDD_1P5/VDD_PMC
VDD_1P5
DCDC 1.5 V Regulated
Output / PMC Input in bypass
(LQFN only)
I/O
DCDC 1.5V Regulated output O
(WLCSP Only)
VDD_1P5_PMCIN1
PSWITCH
VDD_PMC
PSWITCH
DCDC_CFG
DCDC_LP
DCDC_LN
DCDC_GND
PMC Input (WLCSP Only)
DCDC enable switch
I
I
I
DCDC_CFG
DCDC_LP
DCDC switch mode select
DCDC inductor input positive I/O
DCDC inductor input negative I/O
DCDC_LN
DCDC_GND
DCDC ground
I
1. VDD_1P5_CAP and VDD_1P5_PMCIN should always be connected together via PCB trace. System designers
should take care to ensure this connection is as short as possible.
Table 57. LLWU Module Signal Descriptions
SoC Signal Name
LLWU_P[15:0]
Module Signal Name
LLWU_P[15:0]
Description
Wakeup inputs
I/O
I
8.3.4 Clock Modules
This section contains tables for Clock signal descriptions.
Table 58. Clock Module Signal Descriptions
SoC Signal Name
EXTAL
Module Signal Name
EXTAL
Description
I/O
26 MHz/32 MHz External
clock/Oscillator input
I
XTAL
XTAL
26 MHz/32 MHz Oscillator
input
I
XTAL_OUT
XTAL_OUT_EN
XTAL_OUT
26 MHz/32 MHz Clock
output
O
I
XTAL_OUT_ENABLE
26 MHz/32 MHz Clock
output enable for XTAL_OUT
Table continues on the next page...
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
85
NXP Semiconductors
Pin Diagrams and Pin Assignments
Table 58. Clock Module Signal Descriptions (continued)
SoC Signal Name
EXTAL32K
Module Signal Name
EXTAL32K
Description
I/O
32 kHz External clock/
Oscillator input
I
XTAL32K
CLKOUT
XTAL32K
CLKOUT
32 kHz Oscillator input
Internal clocks monitor
I
O
8.3.5 Analog Modules
This section contains tables for Analog signal descriptions.
Table 59. ADC0 Signal Descriptions
SoC Signal Name
ADC0_DM0
Module Signal Name
DADM0
Description
I/O
ADC Channel 0 Differential
Input Negative
I
ADC0_DP0
ADC0_SE[5:1]
VREFH
DADP0
AD[5:1]
VREFSH
ADC Channel 0 Differential
Input Positive
I
ADC Channel 0 Single-ended I
Input n
Voltage Reference Select
High
I
VDDA
VSSA
VDDA
VSSA
Analog Power Supply
Analog Ground
I
I
Table 60. CMP0 Signal Descriptions
SoC Signal Name
Module Signal Name
IN[5:0]
CMP0
Description
Analog voltage inputs
Comparator output
I/O
CMP0_IN[5:0]
CMP0_OUT
I
O
Table 61. DAC0 Signal Descriptions
SoC Signal Name
DAC0_OUT
Module Signal Name
VOUT
Description
DAC output
I/O
I/O
O
O
Table 62. VREF Signal Descriptions
SoC Signal Name
Module Signal Name
VREF_OUT
Description
VREF_OUT
Internally generated voltage
reference output
86
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
NXP Semiconductors
Pin Diagrams and Pin Assignments
8.3.6 Timer Modules
This section contains tables describing timer module signals.
Table 63. TPM0 Module Signal Descriptions
SoC Signal Name
TPM_CLKIN[1:0]
TPM0_CH[3:0]
Module Signal Name
TPM_EXTCLK
TPM_CH[3:0]
Description
External clock
TPM channel
I/O
I/O
I/O
I
I/O
Table 64. TPM1 Module Signal Descriptions
SoC Signal Name
Module Signal Name
TPM_EXTCLK
TPM_CH[1:0]
Description
External clock
TPM channel
TPM_CLKIN[1:0]
TPM1_CH[1:0]
I
I/O
Table 65. TPM2 Module Signal Descriptions
SoC Signal Name
Module Signal Name
TPM_EXTCLK
TPM_CH[1:0]
Description
External clock
TPM channel
TPM_CLKIN[1:0]
TPM2_CH[1:0]
I
I/O
Table 66. LPTMR0 Module Signal Descriptions
SoC Signal Name
LPTMR0_ALT[2:1]
Module Signal Name
Description
I/O
I/O
LPTMR0_ALT[2:1]
Pulse counter input pin
I
Table 67. RTC Module Signal Descriptions
SoC Signal Name
RTC_CLKOUT
Module Signal Name
RTC_CLKOUT
Description
1 Hz square-wave output
O
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
87
NXP Semiconductors
Pin Diagrams and Pin Assignments
8.3.7 Communication Interfaces
This section contains tables for the signal descriptions for the communication modules.
Table 68. SPI0 Module Signal Descriptions
SoC Signal Name
SPI0_PCS0
Module Signal Name
PCS0/SS
Description
Chip Select/Slave Select
Chip Select
I/O
I/O
O
SPI0_PCS[2:1]
SPI0_SCK
PCS[2:1]
SCK
Serial Clock
I/O
I
SPI0_SIN
SIN
Data In
SPI0_SOUT
SOUT
Data Out
O
Table 69. SPI1 Module Signal Descriptions
SoC Signal Name
Module Signal Name
SPI1_PCS0
Description
Chip Select/Slave Select
Serial Clock
I/O
SPI1_PCS0
SPI1_SCK
SPI1_SIN
I/O
I/O
I
SCK
SIN
Data In
SPI1_SOUT
SOUT
Data Out
O
Table 70. I2C0 Module Signal Descriptions
SoC Signal Name
Module Signal Name
SCL
SDA
Description
I2C serial clock line
I2C serial data line
I/O
I/O
I/O
I2C0_SCL
I2C0_SDA
I/O
I/O
Table 71. I2C1 Module Signal Descriptions
SoC Signal Name
Module Signal Name
SCL
SDA
Description
I2C serial clock line
I2C serial data line
I2C1_SCL
I2C1_SDA
I/O
I/O
Table 72. LPUART0 Module Signal Descriptions
SoC Signal Name
Module Signal Name
LPUART CTS
Description
Clear To Send
LPUART0_CTS_b
LPUART0_RTS_b
LPUART0_RX
I
LPUART RTS
LPUART RxD
LPUART TxD
Request To Send
Receive Data
Transmit Data1
O
I
LPUART0_TX
I/O
1. This pin is normally an output, but is an input (tristated) in single wire mode whenever the transmitter is disabled or
transmit direction is configured for receive data
88
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
NXP Semiconductors
Package Information
8.3.8 Human-Machine Interfaces(HMI)
This section contains tables describing the HMI signals.
Table 73. GPIO Module Signal Descriptions
SoC Signal Name
PTA[19:16][2:0]
Module Signal Name
Description
I/O
PORTA19-16, 2-0
General Purpose Input/
Output
I/O
I/O
I/O
PTB[18:16][3:0]
PTC[19:16][7:1]
PORTB18-16, 3-0
PORTC19-16, 7-1
General Purpose Input/
Output
General Purpose Input/
Output
Table 74. TSI0 Module Signal Descriptions
SoC Signal Name
TSI0_CH[15:0]
Module Signal Name
TSI[15:0]
Description
I/O
Touch Sensing Input
capacitive pins
I/O
9 Package Information
9.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to nxp.com and perform a keyword search for the
drawing’s document number:
Table 75. Packaging Dimensions
If you want the drawing for this package
48-pin Laminate QFN (7x7)
Then use this document number
98ASA00694D
98ASA00956D
75-pin WLCSP (3.893x3.797)
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
89
NXP Semiconductors
Revision History
10 Revision History
Table 76. MKW41Z Revision History
Rev. No.
Date
Substantial Changes
4
03/2018
• Added Zigbee 3.0 in supported
standards
• Updated Flash memory protection
features
• Updated Table 12 Voltage and
current operating behaviors
footnotes
• Corrected Table 21 typos
• Updated Table 26 Reference
crystal specifications verbiage
• Updated Temperature sensor
slow information (Table 33 16-bit
ADC characteristics)
• Updated DCDC converter
operating requirements and
specifications
• Added DCDC pin voltage
operating range to Table 52.
Voltage and current operating
ratings
Rev 3
Rev 2
Rev 1
07/2017
07/2017
10/2016
Added "32 kHz oscillator frequency
specifications" table in Clock Modules
section.
• Added WLCSP package details
• Updated "DC-DC Converter
Specifications" table
Initial Release
90
MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018
NXP Semiconductors
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Document Number MKW41Z512
Revision 4, 03/2018
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