MPC93R52ACR2 [NXP]
93R SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, LEAD FREE, LQFP-32;
| 型号： | MPC93R52ACR2 |
| 厂家： | 
NXP |
| 描述： | 93R SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, LEAD FREE, LQFP-32 驱动 输出元件 逻辑集成电路 |
| 文件： | 总16页 (文件大小：337K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MPC93R52
Rev. 5, 1/2005
Freescale Semiconductor
Technical Data
3.3 V 1:11 LVCMOS Zero Delay
Clock Generator
MPC93R52
The MPC93R52 is a 3.3 V compatible, 1:11 PLL based clock generator
targeted for high performance clock tree applications. With output frequencies up
to 240 MHz and output skews lower than 200 ps, the device meets the needs of
most demanding clock applications.
LOW VOLTAGE
3.3 V LVCMOS 1:11
CLOCK GENERATOR
Features
•
•
•
•
Configurable 11 outputs LVCMOS PLL clock generator
Fully integrated PLL
Wide range of output clock frequency of 16.67 MHz to 240 MHz
Multiplication of the input reference clock frequency by 3, 2, 1, 3 ÷ 2, 2 ÷ 3,
1 ÷ 3, and 1 ÷ 2
•
•
•
•
3.3 V LVCMOS compatible
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
Maximum output skew of 200 ps
Supports zero-delay applications
Designed for high-performance telecom, networking and computing
applications
•
•
•
•
32-lead LQFP package
32-lead Pb-free package available
Ambient Temperature Range – 0°C to +70°C
Pin and function compatible to the MPC952
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
Functional Description
The MPC93R52 is a fully 3.3 V compatible PLL clock generator and clock driver. The device has the capability to generate
output clock signals of 16.67 to 240 MHz from external clock sources. The internal PLL is optimized for its frequency range and
does not require external look filter components. One output of the MPC93R52 has to be connected to the PLL feedback input
FB_IN to close the external PLL feedback path. The output divider of this output setting determines the PLL frequency multipli-
cation factor. This multiplication factor, F_RANGE and the reference clock frequency must be selected to situate the VCO in its
specified lock range. The frequency of the clock outputs can be configured individually for all three output banks by the FSELx
pins supporting systems with different but phase-aligned clock frequencies.
The PLL of the MPC93R52 minimizes the propagation delay and therefore supports zero-delay applications. All inputs and
outputs are LVCMOS compatible. The outputs are optimized to drive parallel terminated 50 Ω transmission lines. Alternatively,
each output can drive up to two series terminated transmission lines giving the device an effective fanout of 22.
The device also supports output high-impedance disable and a PLL bypass mode for static system test and diagnosis. The
MPC93R52 is package in a 32 ld LQFP.
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
Bank A
CCLK
VCO
QA0
÷2
1
0
1
0
÷6
÷4
÷2
1
0
QA1
QA2
CCLK
FB_IN
Ref
FB
PLL
QA3
QA4
200 - 480 MHz
PLL_EN
Bank B
QB0
1
0
F_RANGE
QB1
QB2
QB3
FSELA
FSELB
Bank C
1
0
QC0
QC1
FSELC
MR/OE
Power-On Reset
(All input resistors have a value of 25 kΩ)
Figure 1. MPC93R52 Logic Diagram
24
23
22
21
20 19
18
17
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
V
CC
V
CC
QA2
QA1
GND
QA0
QB2
QB3
GND
GND
QC0
QC1
MPC93R52
V
CC
V
CCA
V
PLL_EN
CC
1
2
3
4
5
6
7
8
It is recommended to use an external RC filter for the analog power supply pin V
. Please see application section for details.
CCA
Figure 2. Pinout: 32-Lead Package Pinout (Top View)
MPC93R52
Advanced Clock Drivers Devices
Freescale Semiconductor
2
Table 1. Pin Configuration
Pin
I/O
Type
LVCMOS
Function
CCLK
Input
Input
Input
Input
Input
Input
Input
Input
PLL reference clock signal
FB_IN
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
PLL feedback signal input, connect to an output
PLL frequency range select
F_RANGE
FSELA
FSELB
FSELC
PLL_EN
MR/OE
Frequency divider select for bank A outputs
Frequency divider select for bank B outputs
Frequency divider select for bank C outputs
PLL enable/disable
Output enable/disable (high-impedance tristate) and device reset
Clock outputs
QA0–4, QB0–3, QC0–1 Output
GND
Supply
Supply
Negative power supply
V
V
PLL positive power supply (analog power supply). It is recommended to
use an external RC filter for the analog power supply pin V
applications section for details.
CCA
CC
CC
. Please see
CCA
V
Supply
V
Positive power supply for I/O and core
CC
Table 2. Function Table
Control
Default
0
1
F_RANGE, FSELA, FSELB, and FSELC control the operating PLL frequency range and input/output frequency ratios.
See Table 7 and Table 8 for supported frequency ranges and output to input frequency ratios.
F_RANGE
FSELA
0
0
0
0
0
VCO ÷ 1 (High input frequency range)
Output divider ÷ 4
VCO ÷ 2 (Low input frequency range)
Output divider ÷ 6
FSELB
Output divider ÷ 4
Output divider ÷ 2
FSELC
MR/OE
Output divider ÷ 2
Output divider ÷ 4
Outputs enabled (active)
Outputs disabled (high-impedance state) and reset of
the device. During reset, the PLL feedback loop is open
and the VCO is operating at its lowest frequency. The
MPC93R52 requires reset after any loss of PLL lock.
Loss of PLL lock may occur when the external feedback
path is interrupted. The length of the reset pulse should
be greater than two reference clock cycles (CCLK). The
device is reset by the internal power-on reset (POR)
circuitry during power-up.
PLL_EN
0
Normal operation mode with PLL enabled.
Test mode with PLL disabled. CCLK is substituted for
the internal VCO output. MPC93R52 is fully static and
no minimum frequency limit applies. All PLL related AC
characteristics are not applicable.
MPC93R52
Advanced Clock Drivers Devices
Freescale Semiconductor
3
Table 3. General Specifications
Symbol
Characteristics
Min
Typ
÷ 2
Max
Unit
V
Condition
V
Output Termination Voltage
ESD Protection (Machine Model)
ESD Protection (Human Body Model)
Latch-Up Immunity
V
TT
CC
MM
HBM
LU
200
2000
200
V
V
mA
pF
pF
C
Power Dissipation Capacitance
Input Capacitance
10
Per output
Inputs
PD
C
4.0
IN
Table 4. Absolute Maximum Ratings(1)
Symbol
Characteristics
Min
–0.3
–0.3
–0.3
Max
Unit
V
Condition
V
Supply Voltage
3.9
CC
V
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature
V
V
+ 0.3
V
IN
CC
CC
V
+ 0.3
V
OUT
I
±20
mA
mA
°C
IN
I
±50
OUT
T
–65
125
S
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated
conditions is not implied.
Table 5. DC Characteristics (VCC = 3.3 V ± 5%, TA = 0° to 70°C)
Symbol
Characteristics
Min
Typ
Max
V + 0.3
CC
Unit
V
Condition
LVCMOS
LVCMOS
V
Input high voltage
Input low voltage
2.0
IH
V
0.8
V
IL
(1)
V
Output High Voltage
Output Low Voltage
2.4
V
I
= –24 mA
OH
OH
V
0.55
0.30
V
V
I
I
= 24 mA
= 12 mA
OL
OL
OL
Z
Output impedance
14 – 17
Ω
OUT
(2)
I
Input Current
±200
µA
V
V
= V or
= GND
IN
IN
IN
CC
I
Maximum PLL Supply Current
3.0
7.0
5.0
1.0
mA
mA
V
Pin
CCA
CCA
(3)
I
Maximum Quiescent Supply Current
All V Pins
CC
CCQ
1. The MPC93R52 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated
transmission line to a termination voltage of V . Alternatively, the device drives up to two 50 Ω series terminated transmission lines.
TT
2. Inputs have pull-down resistors affecting the input current.
3. I
is the DC current consumption of the device with all outputs open in high impedance state and the inputs in its default state or open.
CCQ
MPC93R52
Advanced Clock Drivers Devices
Freescale Semiconductor
4
Table 6. AC Characteristics (VCC = 3.3 V ± 5%, TA = 0° to 70°C)(1)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
(2) (3)
f
Input reference frequency in PLL mode
÷4 feedback
÷6 feedback
÷8 feedback
÷12 feedback
50.0
33.3
25.0
120.0
80.0
60.0
40.0
MHz
MHz
MHz
MHz
ref
16.67
(4)
Input reference frequency in PLL bypass mode
50.0
200
250.0
480
MHz
MHz
(5)
f
f
VCO lock frequency range
VCO
MAX
(6)
Output Frequency
÷2 output
100
50
33.3
25
240
120
80
60
40
MHz
MHz
MHz
MHz
MHz
÷4 output
÷6 output
÷8 output
÷12 output
16.67
t
Minimum Reference Input Pulse Width
2.0
ns
ns
ps
PWMIN
(7)
t , t
CCLK Input Rise/Fall Time
1.0
0.8 to 2.0 V
PLL locked
r
f
t
Propagation Delay CCLK to FB_IN
(static phase offset)
f
> 50 MHz
ref
–100
+200
(∅)
(8)
t
Output-to-output Skew
all outputs, any frequency
within QA output bank
within QB output bank
within QC output bank
150
100
100
50
ps
ps
ps
ps
sk(O)
DC
Output duty cycle
47
50
53
1.0
8
%
ns
ns
ns
t , t
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle-to-cycle jitter
0.1
0.55 to 2.4 V
r
f
t
PLZ, HZ
t
10
PZL, LZ
t
JIT(CC)
output frequencies mixed
all outputs same frequency
400
100
ps
ps
t
Period Jitter
output frequencies mixed
all outputs same frequency
450
100
ps
ps
JIT(PER)
(9)
t
I/O Phase Jitter
÷4 feedback divider RMS (1 σ)
÷6 feedback divider RMS (1 σ)
÷8 feedback divider RMS (1 σ)
÷12 feedback divider RMS (1 σ)
40
50
60
80
ps
ps
ps
ps
JIT(∅)
(10)
BW
PLL closed loop bandwidth
÷4 feedback
2.0 – 8.0
1.0 – 4.0
0.8 – 2.5
0.6 – 1.5
MHz
MHz
MHz
MHz
÷6 feedback
÷8 feedback
÷12 feedback
t
Maximum PLL Lock Time
10
ms
LOCK
1. AC characteristics apply for parallel output termination of 50 Ω to V
.
TT
2. PLL mode requires PLL_EN=0 to enable the PLL and zero-delay operation.
3. The PLL may be unstable with a divide by 2 feedback ratio.
4. In PLL bypass mode, the MPC93R52 divides the input reference clock.
5. The input frequency f on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: f = f ÷ FB.
ref
ref
VCO
6. See Table 7 and Table 8 for output divider configurations.
7. The MPC93R52 will operate with input rise and fall times up to 3.0 ns, but the AC characteristics, specifically t , can only be guaranteed if
(∅)
t /t are within the specified range.
r
f
8. See application section for part-to-part skew calculation.
9. See application section for jitter calculation for other confidence factors with 1 σ.
10. –3 dB point of PLL transfer characteristics.
MPC93R52
Advanced Clock Drivers Devices
Freescale Semiconductor
5
APPLICATIONS INFORMATION
desired output clock frequencies. Possible frequency ratios
Programming the MPC93R52
of the reference clock input to the outputs are 1:1, 1:2, 1:3,
3:2 as well as 2:3, 3:1, and 2:1. Table 7 and Table 8 illustrate
the various output configurations and frequency ratios
supported by the MPC93R52. See also Figure 3 to Figure 6
for further reference. A ÷2 output divider cannot be used for
feedback.
The MPC93R52 supports output clock frequencies from
16.67 to 240 MHz. Different feedback and output divider
configurations can be used to achieve the desired input to
output frequency relationship. The feedback frequency and
divider should be used to situate the VCO in the frequency
lock range between 200 and 480 MHz for stable and optimal
operation. The FSELA, FSELB, FSELC pins select the
Table 7. MPC93R52 Example Configuration (F_RANGE = 0)
(1)
PLL Feedback
FSELA
FSELB
FSELC
QA[0:4]:fref ratio
QB[0:3]:fref ratio
(50-120 MHz) fref ∗ 2 (100-240 MHz)
(50-120 MHz) fref (50-120 MHz)
(50-120 MHz) fref ∗ 2 (100-240 MHz)
(50-120 MHz) fref (50-120 MHz)
QC[0:1]:fref ratio
fref [MHz]
(2)
VCO ÷ 4
50–120
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
1
fref
fref
(50-120 MHz) fref
(50-120 MHz) fref
fref ∗ 2÷3 (33-80 MHz) fref
fref ∗ 2÷3 (33-80 MHz) fref
(3)
VCO ÷ 6
33.3–80
fref
fref
fref
fref
(33-80 MHz) fref ∗ 3÷2 (50-120 MHz) fref ∗ 3 (100-240 MHz)
(33-80 MHz) fref ∗ 3÷2 (50-120 MHz) fref ∗ 3÷2 (50-120 MHz)
(33-80 MHz) fref ∗ 3 (100-240 MHz) fref ∗ 3 (100-240 MHz)
(33-80 MHz) fref ∗ 3 (100-240 MHz) fref ∗ 3÷2 (50-120 MHz)
1. fref is the input clock reference frequency (CCLK).
2. QAx connected to FB_IN and FSELA=0.
3. QAx connected to FB_IN and FSELA=1.
Table 8. MPC93R52 Example Configurations (F_RANGE = 1)
(1)
PLL Feedback
FSELA FSELB FSELC
QA[0:4]:fref ratio
QB[0:3]:fref ratio
(25-60 MHz) fref ∗ 2 (50-120 MHz)
(25-60 MHz) fref (25-60 MHz)
(25-60 MHz) fref ∗ 2 (50-120 MHz)
(25-60 MHz) fref (25-60 MHz)
QC[0:1]:fref ratio
fref [MHz]
(2)
VCO ÷ 8
25-60
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
1
fref
fref
(25-60 MHz) fref
(25-60 MHz) fref
fref ∗ 2÷3 (16-40 MHz) fref
fref ∗ 2÷3 (16-40 MHz) fref
(3)
VCO ÷ 12
16.67–40
fref
fref
fref
fref
(16-40 MHz) fref ∗ 3÷2 (25-60 MHz) fref ∗ 3 (50-120 MHz)
(16-40 MHz) fref ∗ 3÷2 (25-60 MHz) fref ∗ 3÷2 (25-60 MHz)
(16-40 MHz) fref ∗ 3 (50-120 MHz) fref ∗ 3 (50-120 MHz)
(16-40 MHz) fref ∗ 3 (50-120 MHz) fref ∗ 3÷2 (25-60 MHz)
1. fref is the input clock reference frequency (CCLK).
2. QAx connected to FB_IN and FSELA=0.
3. QAx connected to FB_IN and FSELA=1.
MPC93R52
Advanced Clock Drivers Devices
Freescale Semiconductor
6
Example Configurations for the MPC93R52
PACKAGE DIMENSIONS
QA0
QA1
QA2
QA3
QA4
fref = 100 MHz
CCLK
QA0
QA1
QA2
QA3
QA4
fref = 62.5 MHz
CCLK
FB_IN
62.5 MHz
100 MHz
FB_IN
QB0
QB1
QB2
QB3
FSELA
FSELB
FSELC
QB0
QB1
QB2
QB3
FSELA
FSELB
FSELC
62.5 MHz
62.5 MHz
100 MHz
200 MHz
V
CC
F_RANGE
QC0
QC1
QC0
QC1
F_RANGE
MPC93R52
MPC93R52
100 MHz (Feedback)
62.5 MHz (Feedback)
MPC93R52 default configuration (feedback of QB0 =
100 MHz). All control pins are left open.
MPC93R52 zero-delay (feedback of QB0 = 62.5 MHz). All
control pins are left open except FSELC = 1. All outputs
are locked in frequency and phase to the input clock.
Frequency range
Input
Min
Max
Frequency range
Input
Min
Max
50 MHz
50 MHz
50 MHz
100 MHz
120 MHz
12 MHz
120 MHz
240 MHz
50 MHz
50 MHz
50 MHz
50 MHz
120 MHz
120 MHz
120 MHz
120 MHz
QA outputs
QB outputs
QC outputs
QA outputs
QB outputs
QC outputs
Figure 3. MPC93R52 Default Configuration
Figure 4. MPC93R52 Zero Delay Buffer Configuration
QA0
fref = 33.3 MHz
fref = 33.3 MHz
CCLK
FB_IN
QA0
QA1
QA2
QA3
QA4
CCLK
FB_IN
QA1
QA2
QA3
QQ4
33.3 MHz
33.3 MHz
QB0
QB1
QB2
QB3
V
V
CC
CC
FSELA
FSELB
FSELC
QB0
QB1
QB2
QB3
FSELA
FSELB
FSELC
33.3 MHz
33.3 MHz
V
V
50 MHz
CC
V
F_RANGE
CC
F_RANGE
QC0
QC1
CC
QC0
QC1
100 MHz
MPC93R52
MPC93R52
33.3 MHz (Feedback)
33.3 MHz (Feedback)
MPC93R52 configuration to multiply the reference
frequency by 3, 3 ÷ 2 and 1. PLL feedback of
QA4 = 33.3 MHz.
MPC93R52 zero-delay (feedback of QB0 = 33.3 MHz).
Equivalent to Table 2 except F_RANGE = 1 enabling a low-
er input and output clock frequency.
Frequency range
Input
Min
Max
Frequency range
Input
Min
Max
25 MHz
50 MHz
50 MHz
100 MHz
60 MHz
120 MHz
120 MHz
240 MHz
25 MHz
25 MHz
25 MHz
25 MHz
60 MHz
60 MHz
60 MHz
60 MHz
QA outputs
QB outputs
QC outputs
QA outputs
QB outputs
QC outputs
Figure 6. MPC93R52 Zero Delay Buffer Configuration 2
Figure 5. MPC93R52 Default Configuration
MPC93R52
Advanced Clock Drivers Devices
Freescale Semiconductor
7
Power Supply Filtering
Nested clock trees are typical applications for the
MPC93R52. Designs using the MPC93R52 as LVCMOS PLL
fanout buffer with zero insertion delay will show significantly
lower clock skew than clock distributions developed from
CMOS fanout buffers. The external feedback option of the
MPC93R52 clock driver allows for its use as a zero delay
buffer. One example configuration is to use a ÷4 output as a
feedback to the PLL and configuring all other outputs to a
divide-by-4 mode. The propagation delay through the device
is virtually eliminated. The PLL aligns the feedback clock
output edge with the clock input reference edge resulting a
near zero delay through the device. The maximum insertion
delay of the device in zero-delay applications is measured
between the reference clock input and any output. This
effective delay consists of the static phase offset, I/O jitter
(phase or long-term jitter), feedback path delay and the
output-to-output skew error relative to the feedback output.
The MPC93R52 is a mixed analog/digital product. Its
analog circuitry is naturally susceptible to random noise,
especially if this noise is seen on the power supply pins.
Random noise on the VCCA (PLL) power supply impacts the
device characteristics, for instance I/O jitter. The MPC93R52
provides separate power supplies for the output buffers (VCC
)
and the phase-locked loop (VCCA) of the device. The purpose
of this design technique is to isolate the high switching noise
digital outputs from the relatively sensitive internal analog
phase-locked loop. In a digital system environment where it
is more difficult to minimize noise on the power supplies a
second level of isolation may be required. The simple but
effective form of isolation is a power supply filter on the VCCA
pin for the MPC93R52. Figure 7 illustrates a typical power
supply filter scheme. The MPC93R52 frequency and phase
stability is most susceptible to noise with spectral content in
the 100 kHz to 20 MHz range. Therefore the filter should be
designed to target this range. The key parameter that needs
to be met in the final filter design is the DC voltage drop
across the series filter resistor RF. From the data sheet the
ICCA current (the current sourced through the VCCA pin) is
typically 3 mA (5 mA maximum), assuming that a minimum of
2.98 V must be maintained on the VCCA pin. The resistor RF
shown in Figure 7 should have a resistance of 5-25 Ω to meet
the voltage drop criteria.
Calculation of Part-to-Part Skew
The MPC93R52 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC93R52 are connected together, the maximum overall
timing uncertainty from the common CCLK input to any
output is:
tSK(PP) = t(∅) + tSK(O) + tPD, LINE(FB) + tJIT(∅) • CF
This maximum timing uncertainty consist of 4 components:
static phase offset, output skew, feedback board trace delay
and I/O (phase) jitter:
R = 5–25Ω
C = 22 µF
F
F
R
F
V
V
CCA
CC
C
10 nF
F
MPC93R52
CCLK
QFB
Common
Device 1
t
PD,LINE(FB)
V
CC
—t
(∅)
33...100 nF
t
JIT(∅)
Figure 7. VCCA Power Supply Filter
Any Q
Device 1
+t
SK(O)
The minimum values for RF and the filter capacitor CF are
defined by the required filter characteristics: the RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in Figure 7, the filter cut-off frequency is around
3-5 kHz and the noise attenuation at 100 kHz is better than
42 dB.
As the noise frequency crosses the series resonant point
of an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC93R52 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL) there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
+t
(∅)
QFB
Device2
t
JIT(∅)
Any Q
Device 2
+t
SK(O)
Max. skew
t
SK(PP)
Figure 8. MPC93R52 Max. Device-to-Device Skew
Due to the statistical nature of I/O jitter a RMS value (1 σ)
is specified. I/O jitter numbers for other confidence factors
(CF) can be derived from Table 9.
Using the MPC93R52 in Zero-Delay Applications
MPC93R52
Advanced Clock Drivers Devices
Freescale Semiconductor
8
the outputs can drive multiple series terminated lines.
Figure 10 illustrates an output driving a single series
terminated line versus two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC93R52 clock
driver is effectively doubled due to its capability to drive
multiple lines.
Table 9. Confidence Factor CF
CF
Probability of clock edge within the distribution
± 1σ
± 2σ
± 3σ
± 4σ
± 5σ
± 6σ
0.68268948
0.95449988
0.99730007
0.99993663
0.99999943
0.99999999
MPC93R52
Output
Buffer
Z
= 50Ω
O
R = 36Ω
S
14Ω
OutA
IN
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation a
I/O jitter confidence factor of 99.7% (± 3σ) is assumed,
resulting in a worst case timing uncertainty from input to any
output of –445 ps to 395 ps relative to CCLK:
MPC93R52
OUTPUT
BUFFER
Z
Z
= 50Ω
= 50Ω
R = 36Ω
O
S
OutB0
OutB1
tSK(PP) = [–200ps...150ps] + [-200ps...200ps] +
14Ω
IN
[(15ps • –3)...(15ps • 3)] + tPD, LINE(FB)
R = 36Ω
O
S
tSK(PP) = [–445ps...395ps] + tPD, LINE(FB)
Due to the frequency dependence of the I/O jitter,
Figure 9, can be used for a more precise timing performance
analysis.
Figure 10. Single versus Dual Transmission Lines
Max. I/O Jitter versus frequency
The waveform plots in Figure 11 show the simulation
results of an output driving a single line versus two lines. In
both cases the drive capability of the MPC93R52 output
buffer is more than sufficient to drive 50 Ω transmission lines
on the incident edge. Note from the delay measurements in
the simulations a delta of only 43 ps exists between the two
differently loaded outputs. This suggests the dual line driving
need not be used exclusively to maintain the tight
30
25
20
15
10
5
output-to-output skew of the MPC93R52. The output
waveform in Figure 11 shows a step in the waveform, this
step is caused by the impedance mismatch seen looking into
the driver. The parallel combination of the 36 Ω series resistor
plus the output impedance does not match the parallel
combination of the line impedances. The voltage wave
launched down the two lines will equal:
0
200
225
250
275
300 325
350
375
400
VCO frequency [MHz]
Figure 9. Max. I/O Jitter versus Frequency
Driving Transmission Lines
VL = VS (Z0 ÷ (RS+R0 +Z0))
Z0 = 50 Ω || 50 Ω
RS = 36 Ω || 36 Ω
R0 = 14 Ω
The MPC93R52 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20 Ω the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Freescale application note
AN1091. In most high performance clock networks
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50 Ω resistance to VCC÷2.
VL = 3.0 (25 ÷ (18+17+25))
= 1.31 V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6 V. It will then increment
towards the quiescent 3.0 V in steps separated by one round
trip delay (in this case 4.0 ns).
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC93R52 clock driver. For the series
terminated case however, there is no DC current draw, thus
MPC93R52
Advanced Clock Drivers Devices
Freescale Semiconductor
9
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the
situation in Figure 12 should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
3.0
2.5
2.0
1.5
1.0
0.5
0
OutA
t = 3.8956
OutB
t = 3.9386
D
D
In
MPC93R52
Output
Z
= 50Ω
= 50Ω
R = 22Ω
O
S
Buffer
14Ω
Z
R = 22Ω
O
S
2
4
6
8
10
12
14
Time (ns)
14Ω + 22Ω || 22Ω = 50Ω || 50Ω
25Ω = 25Ω
Figure 11. Single versus Dual Waveforms
Figure 12. Optimized Dual Line Termination
MPC93R52 DUT
Pulse
Generator
Z = 50Ω
Z
= 50Ω
Z = 50 Ω
O
O
R = 50Ω
R = 50 Ω
T
T
V
V
TT
TT
Figure 13. CCLK MPC93R52 AC Test Reference for VCC = 3.3 V and VCC = 2.5 V
MPC93R52
Advanced Clock Drivers Devices
Freescale Semiconductor
10
V
V
CC
÷ 2
CC
GND
V
V
CC
CC
V
V
CC
CCLK
FB_IN
÷ 2
÷ 2
CC
GND
GND
V
V
CC
CC
t
SK(O)
÷ 2
GND
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device
t
(∅)
Figure 14. Output-to-Output Skew tSK(O)
Figure 15. Propagation Delay (t(∅), static phase
offset) Test Reference
V
V
CC
÷ 2
CCLK
FB_IN
CC
GND
t
P
T
0
DC = t /T x 100%
P
0
T
= |T –T mean|
0 1
JIT(∅)
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
The deviation in t for a controlled edge with respect to a t mean
in a random sample of cycles
0
0
Figure 16. Output Duty Cycle (DC)
Figure 17. I/O Jitter
T
= |T –T
|
N+1
T
= |T –1/f |
N 0
JIT(CC)
N
JIT(PER)
T
T
N+1
T
N
0
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal
period over a random sample of cycles
Figure 18. Cycle-to-Cycle Jitter
Figure 19. Period Jitter
V
=3.3 V
2.4
CC
0.55
t
t
R
F
Figure 20. Output Transition Time Test Reference
MPC93R52
Advanced Clock Drivers Devices
Freescale Semiconductor
11
PACKAGE DIMENSIONS
4X
0.20
H
A-B D
6
D1
3
A, B, D
e/2
D1/2
32
PIN 1 INDEX
1
25
F
F
A
B
E1/2
6
E1
E
4
DETAIL G
E/2
DETAIL G
8
17
NOTES:
9
7
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
3. DATUMS A, B, AND D TO BE DETERMINED AT
DATUM PLANE H.
D
4
D/2
4X
D
4. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.
0.20
C
A-B D
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
THE MAXIMUM b DIMENSION BY MORE THAN
0.08-mm. DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSION AND ADJACENT LEAD OR
PROTRUSION: 0.07-mm.
H
28X e
32X
0.1 C
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25-mm PER SIDE. D1 AND E1 ARE MAXIMUM
PLASTIC BODY SIZE DIMENSIONS INCLUDING
MOLD MISMATCH.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.1-mm AND
0.25-mm FROM THE LEAD TIP.
SEATING
PLANE
C
DETAIL AD
BASE
METAL
PLATING
b1
c
c1
MILLIMETERS
DIM
A
A1
A2
b
b1
c
c1
D
MIN
1.40
0.05
1.35
0.30
0.30
0.09
0.09
MAX
1.60
0.15
1.45
0.45
0.40
0.20
0.16
b
5
8
8X (θ1˚)
M
0.20
C
A-B
D
R R2
SECTION F-F
R R1
9.00 BSC
D1
e
E
E1
L
L1
q
q1
R1
R2
S
7.00 BSC
0.80 BSC
9.00 BSC
7.00 BSC
A2
A
0.25
GAUGE PLANE
0.50
1.00 REF
0˚ 7˚
12 REF
0.70
(S)
A1
L
θ˚
0.08
0.08
0.20
---
(L1)
0.20 REF
DETAIL AD
CASE 873A-03
ISSUE B
32-LEAD LQFP PACKAGE
MPC93R52
Advanced Clock Drivers Devices
Freescale Semiconductor
12
NOTES
MPC93R52
Advanced Clock Drivers Devices
Freescale Semiconductor
13
NOTES
MPC93R52
Advanced Clock Drivers Devices
Freescale Semiconductor
14
NOTES
MPC93R52
Advanced Clock Drivers Devices
Freescale Semiconductor
15
How to Reach Us:
Home Page:
www.freescale.com
E-mail:
support@freescale.com
USA/Europe or Locations Not Listed:
Freescale Semiconductor
Technical Information Center, CH370
1300 N. Alma School Road
Chandler, Arizona 85224
+1-800-521-6274 or +1-480-768-2130
support@freescale.com
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
support@freescale.com
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of any
product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters that may be
provided in Freescale Semiconductor data sheets and/or specifications can and do vary
in different applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064
Japan
0120 191014 or +81 3 5437 9125
support.japan@freescale.com
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Technical Information Center
2 Dai King Street
Tai Po Industrial Estate
Tai Po, N.T., Hong Kong
+800 2666 8080
support.asia@freescale.com
For Literature Requests Only:
Freescale Semiconductor Literature Distribution Center
P.O. Box 5405
Semiconductor was negligent regarding the design or manufacture of the part.
Denver, Colorado 80217
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
All other product or service names are the property of their respective owners.
1-800-441-2447 or 303-675-2140
Fax: 303-675-2150
© Freescale Semiconductor, Inc. 2005. All rights reserved.
LDCForFreescaleSemiconductor@hibbertgroup.com
MPC93R52
Rev. 5
1/2005
相关型号：
MPC93R52FA
PLL Based Clock Driver, 11 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, PLASTIC, LQFP-32
MOTOROLA
MPC93R52FAR2
PLL Based Clock Driver, 93R Series, 11 True Output(s), 0 Inverted Output(s), PQFP32, PLASTIC, LQFP-32
IDT
MPC93R52FAR2
PLL Based Clock Driver, 11 True Output(s), 0 Inverted Output(s), PQFP32, PLASTIC, LQFP-32
MOTOROLA
MPC941AE
941 SERIES, LOW SKEW CLOCK DRIVER, 27 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48, 7 X 7 MM, PLASTIC, LQFP-48
NXP
©2020 ICPDF网 联系我们和版权申明