PCA8516T-T [NXP]
IC ON-SCREEN DISPLAY IC, PDSO24, Superimposer IC;
| 型号： | PCA8516T-T |
| 厂家： | 
NXP |
| 描述： | IC ON-SCREEN DISPLAY IC, PDSO24, Superimposer IC |
| 文件： | 总64页 (文件大小：406K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
PCA8516
Stand-alone OSD
1995 Mar 30
Preliminary specification
File under Integrated Circuits, IC14
Philips Semiconductors
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
CONTENTS
14
DEFAULT VALUES AFTER
POWER-ON-RESET
LIMITING VALUES
DC CHARACTERISTICS
AC CHARACTERISTICS
PACKAGE OUTLINES
SOLDERING
1
2
3
4
5
FEATURES
15
16
17
18
19
GENERAL DESCRIPTION
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING INFORMATION
5.1
5.2
Pinning
Pin description
19.1
19.2
19.3
Introduction
DIP
SO
6
SERIAL I/O
6.1
6.2
I2C-bus serial interface
High-speed serial interface (HIO)
20
21
22
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I2C COMPONENTS
7
CHARACTER FONTS
7.1
7.2
Character font address map
Character font ROM
8
DISPLAY RAM ORGANIZATION
8.1
8.2
8.3
Description of display RAM codes
Loading character data into display RAM
Writing character data to display RAM
9
COMMANDS
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
Command 0
Command 1
Command 2
Command 3
Command 4
Command 5
Command 6
Command 7
Command 8
Command 9
Command A
Commands B, C and D
Command E
Command F
Command G
9.9
9.10
9.11
9.12
9.13
9.14
9.15
10
MISCELLANEOUS
10.1
Space and Carriage Return Codes in different
Background/Shadowing modes
10.2
11
Combination of character font cells
OSD CLOCK
12
OSD CLOCK SELECTION FOR DIFFERENT
TV STANDARDS
12.1
12.2
12.3
OSD frequency
Maximum number of characters per row
Maximum number of rows per frame
13
OUTPUT PORTS
Mask options
13.1
1995 Mar 30
2
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
• Spacing between lines: 4 choices comprising 0, 4, 8 and
1
FEATURES
12 horizontal scan lines
• Display RAM: 256 × 13 bits
• Display character RAM address auto-post-increment
when writing data
• Fast I2C-bus serial interface (400 kbaud) or High-speed
3-wire serial interface (1 Mbaud) for data/command
transfer
• Display character fonts: 253 (fixed in ROM, mask
programmable)
• Starting position of the first character displayed:
64 vertical and 64 horizontal starting positions can be
selected by software
• ACM (Active Character Monitor) specifically for use in
camcorder applications on word basis; can also be used
as a 5th colour control with R, G, B and I signals
• Character size: 4 different character sizes on a
line-by-line basis (1 dot = 1H/1V; 2H/2V; 3H/3V and
4H/4V)
• Programmable active input polarity of HSYNC and
VSYNC
• Character matrix: 12 × 18 with no spacing between
characters and no rounding function
• Programmable output polarity of R, G, B, I and FB
• Supply voltage: 5 V ±10%
• Foreground colours: 16 combinations of Red, Green,
Blue and Intensity on character-by-character basis
• Operating temperature: −20 to +70 °C
• Package: SDIP24 or SO24.
• Background/shadowing modes: 4 modes available, No
background, Box shadowing, North-West shadowing
and Frame shadowing (raster blanking) on frame basis
• Background colours: 16 combinations of Red, Green,
Blue and Intensity on word-by-word basis. Available
when background mode is in either the Box shadowing,
North-West shadowing or Frame shadowing mode
2
GENERAL DESCRIPTION
The PCA8516 is a member of the PCA85XX CMOS family
and is an on-screen character display generator controlled
by a microcontroller via the on-chip fast I2C-bus interface
or the on-chip High-speed 3-wire serial interface. It is
suitable for use in high-end TV or camrecorder
• OSD oscillator: on-chip Phase-Locked Loop (PLL)
• Character blinking ratio: 1 : 1, 1 : 3 and 3 : 1
(programmable frequency of 1⁄16, 1⁄32, 1⁄64 or 1⁄128 of
applications and has also been designed for use in
conventional mid-end TV with advanced graphic features.
fVSYNC) on character basis
• Display format: flexible display format by using the
Carriage Return Code, maximum number of characters
per line is also flexible and depends upon the OSD clock
frequency
3
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
SOT234-1
SOT137-1
PCA8516P
PCA8516T
SDIP24
SO24
plastic shrink dual in-line package; 24 leads (400 mil)
plastic small outline package; 24 leads; body width 7.5 mm
1995 Mar 30
3
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
4
BLOCK DIAGRAM
LM3C47
1995 Mar 30
4
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
5
PINNING INFORMATION
Pinning
5.1
handbook, halfpage
AV
AV
1
2
3
4
5
6
7
8
9
I (VOW3)
24
23
DD
P04/ACM (VOB2)
TEST2
SS
22 FB (VOB)
V
21
TEST1
DD
C
20 B (VOW2)
19 P01
VSYNC
PCA8516
18
HSYNC
G (VOW1)
SDA/SIN
17 P00
SCK/SCLK
16 R (VOW0)
2
XTAL1 (IN) 10
15 HIO/I C
XTAL2 (OUT)
11
12
14
E
V
13 RESET
SS
MLC927
Fig.2 Pin configuration for SDIP24.
1995 Mar 30
5
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
5.2
Pin description
Table 1 SDIP24 and SO24 packages
SYMBOL
I (VOW3)
PIN
1
I/O
O
O
I
DESCRIPTION
Character output signal for intensity control.
P04/ACM (VOB2)
TEST2
2
Port 04 output or Active Character Monitor output (VOB2).
Test mode selection; for normal operation TEST2 is connected to VSS
Test mode selection; for normal operation TEST1 is connected to VSS
Capacitor connection for on-chip OSD PLL oscillator.
3
.
.
TEST1
4
I
C
5
I/O
I
VSYNC
HSYNC
SDA/SIN
6
Vertical synchronization input, active polarity programmable.
Horizontal synchronization input, active polarity programmable.
Data line of the I2C-bus interface or the data line for the High-speed
serial interface.
7
I
8
I/O
SCL/SCLK
9
I/O
Clock line of the I2C-bus interface or the clock line for the High-speed
serial interface.
XTAL1 (IN)
XTAL2 (OUT)
VSS
10
11
12
13
14
I
O
I
System clock input.
System clock output.
Ground, digital.
RESET
E
I
Master Reset input (active LOW).
I
Chip enable (active HIGH) for the High-speed serial interface. When the
I2C-bus interface is selected this pin should be connected to VSS
.
HIO/I2C
15
I
Serial interface selection. When this pin is LOW the High-speed serial
interface is selected; when this pin is HIGH the I2C-bus interface is
selected.
R (VOW0)
P00
16
17
18
19
20
21
22
23
24
O
I/O
O
I/O
O
I
Character output signal: VOW0 for Red.
General purpose I/O Port 00.
Character output signal: VOW1 for Green.
General purpose I/O Port 01.
Character output signal: VOW2 for Blue.
Power supply, digital.
G (VOW1)
P01
B (VOW2)
VDD
FB (VOB)
AVSS
O
I
Fast Blanking output (VOB).
Ground, analog.
AVDD
I
Power supply, analog.
1995 Mar 30
6
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
The synchronization process is carried out by on-chip
hardware and takes place during the HSYNC retrace
period when VSYNC is inactive. The I2C-bus clock is
pulled LOW if a complete display RAM data byte is
received before HSYNC becomes active. The I2C-bus
clock will be released when HSYNC becomes active and
then the contents of the shift register will be written into the
display RAM location.
6
SERIAL I/O
The PCA8516 has two means by which it can
communicate with a microcontroller: a fast I2C-bus serial
interface and a High-speed serial interface. Selection of
either interface is achieved via pin 15, HIO/I2C. When
HIO/I2C is LOW, the HIO serial interface is selected. When
HIO/I2C is HIGH, the I2C-bus serial interface is selected.
The PCA8516 is programmed by a series of commands
sent via one of these interfaces. There are 16 commands;
each command selecting different functions of the
PCA8516. The 16 commands are described in detail in
Chapter 9.
6.2
High-speed serial interface (HIO)
The High-speed serial interface is selected when pin 15
(HIO/I2C) is pulled LOW. The High-speed serial interface
has a 3-wire communication protocol; the maximum
transmission rate being 1 MHz. The interface protocol is
illustrated in Fig.4 and described below.
6.1
I2C-bus serial interface
The I2C-bus serial interface is selected by driving pin 15
(HIO/I2C) HIGH. Data transmission conforms to the fast
I2C-bus protocol; the maximum transmission rate being
400 kHz. The PCA8516 operates in the slave receiver
mode and therefore in normal operation is ‘write only’ from
the master device.
1. Pin 14 (E) the chip enable pin is driven HIGH. This
LOW-to-HIGH transition clears the shift register and
resets the serial input circuit.
2. On the first HIGH-to-LOW transition of SCLK after the
interface has been enabled, the first data bit (D0) must
be present at the SIN pin.
The format of the data streams sent via the I2C-bus
interface is shown in Fig.3. The first data byte is the slave
address 1011 101Xb. The last bit of the slave address is
always a logic 0, except in the Test mode when it could be
a logic 1. Subsequent data bytes contain the commands
for control of the device. Upon the successful reception of
a complete data byte by the shift register, an Acknowledge
bit is sent. A STOP condition terminates the data transfer
operation.
3. On the following LOW-to-HIGH transition of SCLK, the
first data bit (D0) will be latched into the shift register.
4. On the next HIGH-to-LOW transition of SCLK the
second data bit (D1) must be present at the SIN pin.
Data bit (D1) will be latched into the shift register on
the following LOW-to-HIGH transition of SCLK.
5. The operation specified in step 4 above is repeated
another 6 times, thus loading the shift register with a
complete data byte. This data byte is then transferred
to the command interpreter which takes the
appropriate action.
The I2C-bus interface is reset to its initial state (waiting for
a slave address call) by the following conditions:
• After a master reset
• After a bus error has been detected on the I2C-bus
interface.
6. Providing the chip enable signal remains HIGH, a
2nd data byte can be transferred. The 1st data bit of
the next data transfer takes place on the falling edge
of the SCLK signal.
Under both these conditions the data held in the shift
register is abandoned.
The following points should be noted:
• If the chip enable signal is pulled LOW at any time the
shift operation in progress is stopped and the HIO slave
receiver is disabled
6.1.1
MAXIMUM SPEED OF THE I2C-BUS
The maximum I2C-bus transmission rate that the
PCE8515 can receive is 400 kHz. However, if the data
byte being transmitted is for display RAM then internal
synchronization of the write operation from the shift
register to the display RAM location is necessary. This will
reduce the maximum transmission speed.
• The rising edge of the chip enable signal resets the HIO
slave receiver.
1995 Mar 30
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Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
2
I C-bus
bit stream
MSB
0
LSB
7
8
0
7
8
0
7
8
0
7
8
W
O
S
Slave address
Ack 0 1 1 1 1 0 0 BS
Ack
Ack
Ack P
1st data byte
2nd data byte
nth data byte
Command
Register data
MRA818
bit 0
bit 7
Fig.3 I2C-bus write timing diagram - data stream.
falling edge of SCLK
D
changes
SCLK
OUT
D5
D
OUT
D0
D1
D2
D3
D4
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
(from HIO master and
connected to SIN pin of
HIO slave)
E
SCLK
SIN
T
T
T
s
rising edge of SCLK
SIN sampled
s
h
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
MLB395 - 1
(1)
Ts ≥ 1 µs; Th ≥ 1 µs.
Fig.4 High-speed I/O format.
1995 Mar 30
8
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
The file format to submit to Philips for customized
7
CHARACTER FONTS
character sets is also shown in Fig.7. The following points
should be noted:
256 character fonts may be held in ROM; 253 customer
selected fonts and three reserved character font codes.
Customer selected fonts are mask programmable. Each
character font is stored in a 12 × 19 dot matrix, as shown
in Fig.5. Elements in Rows 1 to 18 can be selected as
visible dots on the screen; Row 0 is used only for the
combination of two characters in a vertical direction, when
the North-West shadowing mode is selected (see
Sections 9.9 and 10.2). Extremely high resolution can be
achieved by having no spacing between characters on the
same line and by programming the inter-line spacing to
zero. The 12 × 18 dot matrix is suitable for the display of
semigraphic patterns, Kanji, Hiragana, Katagana or even
Chinese characters.
1. Row 0 of each font is reserved for vertical combination
of two fonts.
2. When two font cells are combined in a vertical
direction Row 0 of the lower font must contain the
same bit pattern as held in Row 18 of the character
above it.
3. Binary 1 denotes visual dots; binary 0 denotes a blank
space.
4. ROM1 and ROM2 data files are in INTEL hex format
on a byte basis. Each byte is structured High nibble
followed by Low nibble.
5. The remaining unused 16 bytes (one character font) in
ROM1/ROM2 must be filled with FFH.
7.1
Character font address map
6. CS denotes Checksum.
Figure 6 shows the character font address map in ROM
and RAM. Addresses FFH and FEH hold the reserved
codes for space and carriage return functions respectively;
address FDH is reserved for testing purposes and
addresses (00H to FCH) contain the character font codes.
A software package (OSDGEM) that assists in the design
of character fonts on-screen and that also automatically
generates the bit pattern HEX files, is available on request.
The package is run under the MS-DOS environment for
IBM compatible PCs.
7.2
Character font ROM
ROM is divided into two parts: ROM1 and ROM2. The
organization of the bit patterns stored in ROM1 and ROM2
is shown in Fig.7.
0
11 10
9
8
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
Mask Programmable Font
7
8
reserved code
9
10
11
12
13
14
15
16
17
18
252 (FCH)
253 (FDH)
254 (FEH)
255 (FFH)
Test code
Carriage return code
Space code
MLB344
MLC350
Fig.5 Character dot matrix organization.
Fig.6 ROM address map.
1995 Mar 30
9
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
Column
ROM1
ROM2
1110 9 8 7 6 5 4 3 2 1
0
0
2
3
2
2
3
0
5
0
0
0
2
F
2
2
F
0
5
0
3
0
0
C
0
0
F
1
2
C
0
0 0 0 ROM1
3 F C ROM2
2 2 0 ROM1
2 2 0 ROM2
3 F C ROM1
2 2 0 ROM2
2 2 0 ROM1
3 F C ROM2
2 2 0 ROM1
2 2 0 ROM2
3 F F ROM1
0 0 1 ROM2
0 0 1 ROM1
5 5 3 ROM2
5 5 2 ROM1
0 0 6 ROM2
0 0 C ROM1
0 5 8 ROM2
0 3 0 ROM1
0
1
2
3
4
5
6
7
3
2
F
2
C
0
2
3
2
0
5
0
0
2
F
2
0
5
0
5
0
C
0
1
3
6
8
Row
8
9
10
11
12
13
14
15
16
17
18
ROM1
byte
0
#
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
__ __ __ __ __ __ __ __ __ __ __ __ __ __ __
: 1 0 0 0 0 0 0 0
00 00 22 FC 03 22 20 F2 3F 01 20 55 0C 00 03
F F C S
F F C S
F F C S
: 1 0 0 0 1 0 0 0
: 1 0 0 0 2 0 0 0
< - - -
< - - -
DATA FOR FONT 2
DATA FOR FONT 3
- - - >
- - - >
ROM2
: 1 0 0 0 0 0 0 0 FC 03 22 20 C2 3F 20 12 00 53 65 00 58
F
F
0
FF FF C S
FF FF C S
: 1 0 0 0 1 0 0 0 < - - -
: 1 0 0 0 2 0 0 0 < - - -
DATA FOR FONT 2
DATA FOR FONT 3
- - - >
- - - >
X
F
X
FF FF C S
MLB345
Fig.7 Character font pattern stored in ROM1 and ROM2.
1995 Mar 30
10
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
8
DISPLAY RAM ORGANIZATION
8.1.3
CARRIAGE RETURN CODE
The display RAM is organized as 256 × 13 bits. The
general format of each RAM location is as follows.
Bits <12-5> hold character data and allow a choice from
253 customer designed character fonts to be selected or
one of three reserved codes. Bits <4-0> contain the
attributes of the character font, for example colour,
character size etc.
If bits <12-5> hold FEH, then this is the Carriage Return
Code. A transparent pattern will be displayed on the
screen and the next character will be displayed at the
beginning of the next line. Bits <4-3> select the size of the
characters to be displayed on the next line. Bits <2-1>
determine the spacing between lines of displayed
characters. Bit <0> is the End of Display bit and indicates
the end of display of the current screen before exhaustion
of display RAM (i.e. before the 256th RAM location). The
format of the Carriage Return Code is shown in Table 3.
8.1
Description of display RAM codes
There are four data formats for display RAM code:
1. Character Font Code
2. Test Code
8.1.4
SPACE CODE
If bits <12-5> hold FFH, then this is the Space Code.
A transparent pattern, equal to one character width, will be
displayed on the screen. A mask programmable option is
available that allows the space character to be transparent
or to have a programmable background colour;
see Section 13.1. Bits <4-1> determine the background
colour of the characters that follow the Space Code in both
the Box shadowing and North-West shadowing modes.
Bit <0> is the Active Character Monitor (ACM)
enable/disable bit. The ACM signal is specifically for use in
camrecorder applications where part of the display is to be
recorded on tape and displayed on the screen, whilst the
remaining part is for display only. Figure 9 shows a typical
ACM application. During the back-tracing period R, G, B, I,
FB and ACM are inactive. The format of the Space Code
is shown in Table 4.
3. Carriage Return Code
4. Space Code.
The above data formats allow great flexibility in the
creation of On Screen Displays; see Fig.8.
8.1.1
CHARACTER FONT CODE
If bits <12-5> are in the range (00H to FCH), then this is a
Character Font Code. 1 of 253 customer designed
character fonts can be selected. Bits <4-1> determine the
colour of the character, a choice of 16 colours being
available. Bit <0> determines whether the character blinks
or not. The format of the Character Font Code is shown in
Table 2.
8.1.2
TEST CODE
If bits <12-5> hold FDH, then this is a special code
reserved for testing purposes only.
Table 2 Format of Character Font Code
12
11
10
9
8
7
6
5
4
3
2
1
0
C7
C6
C5
C4
C3
C2
C1
C0
T4
T3
T2
T1
T0
Character Font Code (00H - FCH)
Foreground colour
Blink
Table 3 Format of Carriage Return Code
12
11
10
9
8
7
6
5
4
3
2
1
0
C7
C6
C5
C4
C3
C2
C1
C0
T4
T3
T2
T1
T1
Carriage Return Code (FEH)
Character size
Line Spacing
End
Table 4 Format of Space Code
12
11
10
9
8
7
6
5
4
3
2
1
0
C7
C6
C5
C4
C3
C2
C1
C0
T4
T3
T2
T1
T0
Space Code (FFH)
Background colour
ACM
1995 Mar 30
11
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
line spacing 1 = 4H
Vstart
H
I
!
T
H
S
I
S
I
SP
SP
CR
CR
line spacing 2 = 8H
T H E
F U N C T I O N
P C A 8 5 1 0
N E W
SP
CR
line spacing 3 = 0H
CR
line spacing 4 = 0H
line spacing 4 = 4H
I
N
SP
CR
Hstart
S T A N D A L
CR
line spacing 6 = 0H
W E L C O M E
SP
CR
Volume
Channel
MRA832
Four different background colours (in box shadowing mode):
BLACK
RED
GREEN
BLUE
Fig.8 Example of On Screen Display.
1995 Mar 30
12
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
Battery Status : OK
Shutter speed : 500
Focal Length : 28 mm
Date : July 15, 1994
PHILIPS
Made by MOS IC TAIWAN, PHILIPS
MRA831
In this example, all the characters are displayed on the viewfinder.
As only the data 'Date : July 15, 1994' is to be recorded onto the tape,
only these characters' ACM attribute bit is set to a logic 1.
Fig.9 Example of ACM signal for use in camrecorder applications.
1995 Mar 30
13
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
8.2
Loading character data into display RAM
8.3
Writing character data to display RAM
Three registers are used to address and load data into the
display RAM. These registers are described below.
The procedure for writing character data to the display
RAM is as follows:
1. Select the start address in display RAM. The start
address can take any value between 0 and 255.
Command 3 is used to load the High nibble of the start
address. Command 4 is used to load the Low nibble of
the start address. The start address is stored in
DCRAR.
8.2.1
DCR ADDRESS REGISTER (DCRAR)
Table 5 DCR Address Register
7
6
5
4
3
2
1
0
A7
A6
A5
A4
A3
A2
A1
A0
2. Load the character attributes into DCRTR using
Command 2. The actual attribute selected is
dependent upon whether the Character Font Code,
Carriage Return Code or Space Code has been
selected by Command 1 (see Section 8.1).
This register holds the address of the location in display
RAM into which data is to be written. Command 3 loads
the High nibble of the address into this register;
Command 4 loads the Low nibble of the address.
If the attributes of a series of displayed characters are
the same, the contents of this register need not be
updated.
8.2.2
DCR ATTRIBUTE REGISTER (DCRTR)
3. Load the Character Font data into DCTCR using
Command 1 or Command 5. Either of these
Table 6 DCR Attribute Register
commands signal that a complete command byte is
available and the data held in registers DCRTR and
DCRCR is loaded into the RAM location pointed to by
the address stored in DCRAR. The address held in
DCRAR is then incremented by ‘1’ pointing to the next
RAM location in anticipation of the next operation.
7
6
5
4
3
2
1
0
−
−
−
T4
T3
T2
T1
T0
The Attribute Register is loaded with character font
attribute data using Command 2. The data will be loaded
into bits <4-0> of the location in RAM addressed by the
contents of DCRAR. Bits 7 to 5 are not used and are
reserved.
A description of all the Commands is given in Chapter 9.
8.2.3
DCR CHARACTER REGISTER (DCRCR)
Table 7 DCR Character Register
7
6
5
4
3
2
1
0
C7
C6
C5
C4
C3
C2
C1
C0
This register holds the character font data loaded by
Command 1. The data will be loaded into bits <12-5> of
the location in RAM addressed by the contents of DCRAR.
1995 Mar 30
14
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
9
COMMANDS
The PCA8516 is programmed by a series of commands sent by a microcontroller via the I2C-bus interface or the
High-speed serial interface. 17 commands (Commands 0 to G) are available for selecting the various functions of the
PCA8516. A command overview is shown in Table 8; full descriptions of each command are given in Sections 9.1 to 9.15.
Table 8 Command overview (note 1)
COMMAND
BS1
X
BS0
X
0
7
0
1
0
0
0
1
0
0
6
1
5
1
4
1
3
2
1
0
0
1
2
3
4
5
6
7
Command Bank selection
Character font selection - Bank 1
Character attributes
1
0
BS1 BS0
0
C6
0
C5
0
C4
T4
0
C3
T3
A7
A3
C3
D3
M1
C2
T2
A6
A2
C2
D2
M0
C1
T1
A5
A1
C1
D1
Bp
C0
T0
A4
A0
C0
D0
EN
X
0
Display Character Address High
Display Character Address Low
Character font selection - Bank 2
OSD PLL oscillator divisor
0
0
0
1
0
0
0
1
1
1
0
C6
0
C5
D5
0
C4
D4
0
0
1
Scan mode, polarity of FB, ACM, R,
G, B and I; OSD enable/disable
0
1
1
8
9
Polarity of HSYNC and VSYNC,
Display mode
0
0
1
1
0
0
1
1
0
1
1
0
Hp
Vp
S1
S0
Blinking frequency, blinking
frequency active ratio
BF1 BF0 BR1 BR0
A
B
C
I/O port selection
0
0
0
1
1
1
0
1
1
1
0
0
1
0
1
1
1
0
0
A/P
V4
0
0
Vertical start position High
V5
V1
V3
H5
V2
H4
Vertical start position Low/
Horizontal start position High
V0
D
E
F
Horizontal start position Low
0
0
0
1
1
0
1
1
0
0
1
1
1
X
0
1
P04
0
H3
X
H2
X
H1
H0
Write to ports P00, P01 and P04
P01 P00
Background colour in Frame
shadowing mode
R
G
B
I
G
Enable/disable OSD horizontal
stabilization circuit (Regen H),
selection of Half-tone background
mode and character size of first line
0
0
0
1
0
1
HM3 HT2 FS1 FS0
Note
1. ‘X’ denotes don’t care state.
1995 Mar 30
15
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
9.1
Command 0
9.3.1
CHARACTER FONT CODE ATTRIBUTES
Command 2 when used in conjunction with a Character
Font Code (80H to FCH) will select 1 of 16 foreground
colours and enables/disables the Blinking function.
Table 9 Command 0 format
7
6
5
4
3
2
1
0
0
1
1
1
1
0
BS1 BS0
Table 12 Selection of Foreground colour
Command 0 is used to select the Command Bank. Bits
BS1 and BS0 are the two flags that indicate the current
Command Bank being executed. During a master reset
these two bits are cleared (BS1 = 0, BS0 = 0). Each
command has its own associated Command Bank, this is
shown in Table 8.
T4
R
T3
G
T2
B
T1
I
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
9.2
Command 1
Table 10 Command 1 format
BS1 BS0
7
6
5
4
3
2
1
0
0
0
1
C6 C5 C4 C3 C2 C1 C0
Command 1 is used to load character data into the DCR
Character Register. The data will specify either a
Character Font Code, the Test Code, the Carriage Return
Code or the Space Code. These codes are explained in
detail in Section 8.1.
9.3
Command 2
Table 11 Command 2 format
BS1 BS0
7
6
5
4
3
2
1
0
Table 13 Selection of Blinking function
X
0
0
0
0
T4 T3 T2 T1 T0
T0
BLINKING
0
1
OFF
ON
This command writes character attribute data into the DCR
Attribute Register. The actual character attribute is
dependent upon the code selected by Command 1. See
the data formats shown in Tables 2, 3 and 4.
1995 Mar 30
16
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
9.3.2
CARRIAGE RETURN CODE ATTRIBUTES
Table 17 Selection of Background colour
Command 2 when used in conjunction with the Carriage
Return Code (FEH) determines the size of characters to be
displayed on the next line, sets the spacing between lines
of characters and enables/disables the display.
T4
R
T3
G
T2
B
T1
I
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
The character size is also a function of the TV scanning
standard being used and fOSD; this is explained in
Chapter 12.
Table 14 Selection of character size
T4
T3
CHARACTER DOT SIZE
0
0
1
1
0
1
0
1
1H/1V (the default size)
2H/2V
3H/3V
4H/4V
Table 15 Selection of line spacing
LINE SPACING
(BETWEEN TWO ROWS)
T2
T1
0
0
1
1
0
1
0
1
0H line
4H line
8H line
12H line
Table 18 ACM control
T0
ACM PIN
0
The ACM pin is inactive; this is also the
default setting.
Table 16 End of display control
T0
DISPLAY CONTROL
1
The ACM function is active for all
characters displayed following this
Space Code.
0
Continue to display next character. This
is also the default setting.
1
End of display.
9.3.3
SPACE CODE ATTRIBUTES
Command 2 when used in conjunction with the Space
Code (FFH) selects the background colour of characters in
Box shadowing or North-West shadowing modes and also
controls the Active Character Monitor pin. The ACM pin will
remain active until a Space Code is received that resets
the ACM bit to logic 0. The ACM timing diagram is shown
in Fig.10.
1995 Mar 30
17
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
0
SP code
SP code
18
R
G
B
I
FB
ACM
MRA830 - 1
'S' : Red
'I' : Green
'Z' : Green + Blue + Intensity
'E' : Blue + Intensity
1st SP code : ACM = on
2nd SP code: ACM = off
Fig.10 R, G, B, I - ACM timing.
1995 Mar 30
18
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
9.4
Command 3
9.8
Command 7
Table 19 Command 3 format
Table 23 Command 7 format
BS1 BS0
7
6
5
4
3
2
1
0
BS1 BS0
7
6
5
4
3
2
1
0
0
0
0
0
1
1
A7 A6 A5 A4
0
1
0
1
0
0
M1 M0 Bp EN
Command 3 loads the DCR Address Register with the
4 MSBs of the RAM address to which data will be written.
This command loads Control Register 1 with data that
selects the scanning mode, the output polarity of signals
FB, ACM, R, G, B and I, and also enables/disables the
OSD clock.
9.5
Command 4
With reference to the scanning modes: 1V/2V is the
conventional NTSC or PAL scanning mode; 1V/2H is the
Line Progress Scan used for the IDTV in NTSC and 2V/2H
is for the PAL system and is known as 50 Hz to 100 Hz
scan conversion.
Table 20 Command 4 format
BS1 BS0
7
6
5
4
3
2
1
0
0
0
0
0
1
1
A3 A2 A1 A0
Command 4 loads the DCR Address Register with the
4 LSBs of the RAM address to which data will be written.
Table 24 Selection of Scanning Mode
M1
M0
SCAN MODE
9.6
Command 5
0
0
1V/1H; NTSC 525LPF/60 Hz or
PAL 625LPF/50 Hz; see Fig.11. This is
the default setting.
Table 21 Command 5 format
BS1 BS0
7
6
5
4
3
2
1
0
0
1
1
0
reserved
1
0
1
C6 C5 C4 C3 C2 C1 C0
1V/2H; NTSC 1050LPF/60 Hz; see
Fig.11.
Command 5 is used to load character data into the DCR
Character Register. The data will specify either a
Character Font Code, the Test Code, the Carriage Return
Code or the Space Code. These codes are explained in
detail in Section 8.1.
1
1
2V/2H; PAL 1250LPF/100 Hz; see
Fig.12.
Table 25 Selection of output polarity (see Fig.13)
Bp
OUTPUT POLARITY (FB, ACM, R, G, B, I)
9.7
Command 6
0
1
active LOW
active HIGH (the default setting)
Table 22 Command 6 format
BS1 BS0
7
6
5
4
3
2
1
0
Table 26 OSD clock control
0
1
0
0
D5 D4 D3 D2 D1 D0
EN
OSD CLOCK
0
1
disabled (the default setting)
enabled
Command 6 loads the programmable 6-bit counter of the
OSD clock oscillator. The output frequency (fOSD) is a
function of the decimal value of the 6-bits loaded in by
Command 6; see Chapter 11.
1995 Mar 30
19
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
f
= 60 Hz
f
= 60 Hz
VSYNC
VSYNC
VSYNC
f
= 15734 Hz
HSYNC
HSYNC
262.5 lines
262.5 lines
(a) Conventional NTSC 1V/1H
f
= 60 Hz
f
= 60 Hz
VSYNC
VSYNC
VSYNC
HSYNC
f
= 31468 Hz
HSYNC
525 lines
525 lines
MRA834
(b) NTSC 1V/2H
Fig.11 NTSC scan formats.
f
= 50 Hz
f
= 50 Hz
VSYNC
VSYNC
VSYNC
f
= 15625 Hz
HSYNC
HSYNC
312.5 lines
312.5 lines
(a) Conventional PAL 1V/1H
f
= 100 Hz
f
= 100 Hz
f
= 100 Hz
f = 100 Hz
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
HSYNC
f
= 31250 Hz
HSYNC
312.5 lines
312.5 lines
312.5 lines
312.5 lines
MRA835
(b) PAL 2V/2H
Fig.12 PAL scan formats.
20
1995 Mar 30
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
FB (ACM or R, G, B or I )
Bp = 0 (active LOW)
active period
active period
FB (ACM or R, G, B or I )
Bp = 1 (active HIGH)
MRA836
Fig.13 Active levels of FB, R, G, B, and I signals.
HSYNC/VSYNC
Hp/Vp = 0 (active LOW)
active period
active period
HSYNC/VSYNC
Hp/Vp = 1 (active HIGH)
MRA837
Fig.14 Active levels of HSYNC and VSYNC signals.
21
1995 Mar 30
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
9.9
Command 8
9.10 Command 9
Table 27 Command 8 format
Table 30 Command 9 format
BS1 BS0
7
6
5
4
3
2
1
0
BS1 BS0
7
6
5
4
3
2
1
0
0
1
0
1
0
1
Hp Vp S1 S0
0
1
0
1
1
0
BF1 BF0 BR1 BR0
Command 8 loads Control Register 2 with data that
selects the input polarity of HSYNC and VSYNC (see
Fig.14) and also selects the Display modes.
This command loads Control Register 3 with data that
controls both the character blinking frequency and the
active ratio of the character blinking frequency.
Figures 25 to 29 show how blinking influences the display
in different display modes.
Table 28 Selection of input polarity of HSYNC/VSYNC
Hp/Vp
INPUT POLARITY
active LOW (the default setting)
active HIGH
Table 31 Selection of Blinking frequency
0
1
BF1
BF0
BLINKING FREQUENCY (Hz)
0
0
f
VSYNC ; this is the default setting
----------------
16
Table 29 Selection of Display Mode
0
1
1
1
0
1
f VSYNC
S1
S0
DISPLAY MODE
-----------------
32
0
0
0
1
Mode 0: this is the No background
mode. The OSD characters are
superimposed on the TV video signals
(see Fig.15).
f VSYNC
-----------------
64
f VSYNC
Mode 1: this is the North-West
-----------------
128
shadowing mode; available only with
character sizes 2V/2H or 4V/4H. The
shadows are generated as if a light
source was placed North-West of the
character (see Figs 16 to 18). The
shadows generated lie within 18 rows
in a vertical direction but can be
extended by one bit to the next
Table 32 Selection of active ratio of character blinking
BR1
BR0
ACTIVE RATIO
0
0
1
1
0
1
0
1
3 : 1 (the default setting)
1 : 1
1 : 3
characters first column, in a horizontal
direction (see Figs 19 and 20).
reserved
1
1
0
1
Mode 2: this is the Box shadowing
mode. A background dot matrix of
12 × 18 bits surrounds the character
font; see Figs 21 and 22.
Mode 3: this is the Frame shadowing
(raster blanking) mode. A background
colour fills the whole screen when no
bit patterns are being displayed (see
Fig.23). 1 of 16 background colours
can be selected using Command F;
the default background colour is Blue.
1995 Mar 30
22
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
scan
line
M O S
SP code
SP code
SP code
FB
R
G
B
I
MLB346
'M' : Red + Blue + Intensity
'O' : Blue
'S' : Red + Green + Intensity
Bp = 1
Fig.15 Mode 0: No background mode.
1995 Mar 30
23
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
scan line
: background
FB
R
G
B
I
1f
OSD
1st character: GREEN
MRA839
2nd character: GREEN + BLUE + INTENSITY
background: RED + BLUE
Bp = 1 (active HIGH)
Available only in character sizes 2V/2H or 4V/4H.
Fig.16 Mode 1: North-West shadowing mode.
1995 Mar 30
24
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
0 1 2 3
4
5 6
7
8 9 10 11
0
1
2
3
1V
4
5
6
7
8
9
10
11
12
13
14
15
16
17
MRA842
1H
Fig.17 Example of North-West shadowing mode - size 2V/2H.
1995 Mar 30
25
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
0
1
2
3
4
5
6
7
8
9
10 11
0
1
2V
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
MRA843
2H
Fig.18 Example of North-West shadowing mode - size 4V/4H.
1995 Mar 30
26
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
14
15
16
17
18
10
11
12
13
14
15
16
17
Character designed in character ROM
Character displayed on TV screen
MRA844
Fig.19 Example of North-West shadowing mode.
1995 Mar 30
27
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
0
1
2
3
4
5
6
7
8
9
10 11
0 1 2 3 4 5 6 7 8 9 10 11
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Two characters designed in character ROM separately
10 11 0 1 2 3 4 5 6 7 8 9 10 11
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
MRA846
Two characters displayed on TV screen
Fig.20 North-West shadowing.
1995 Mar 30
28
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
Column 0
Column 11
Row 0
Row 17
MRA840
background colour
Fig.21 Mode 2: Box shadowing mode.
1995 Mar 30
29
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
size = 1
size = 4
0
1
2
3
4
5
6
7
8
9
10 11
0
1
2
3
size = 2
4
size = 3
5
6
7
8
9
10
11
12
13
14
15
16
17
MRA847
Fig.22 Example of Box shadowing mode.
1995 Mar 30
30
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
MRA841
Background: BLUE
Fig.23 Mode 3: Frame shadowing mode.
1995 Mar 30
31
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
60 Hz
60 Hz
VSYNC
f
14 15 0
1
2
3
7
8
10 11
0
1
2
3
7
8
10 11
14 15
VSYNC
16
Blinking frequency:
Blinking ratio: 1 : 3
f
f
VSYNC
16
Blinking frequency:
Blinking ratio: 1 : 1
VSYNC
16
Blinking frequency:
Blinking ratio: 3 : 1
f
VSYNC
32
Blinking frequency:
Blinking ratio: 1 : 3
f
f
VSYNC
32
Blinking frequency:
Blinking ratio: 1 : 1
VSYNC
32
Blinking frequency:
Blinking ratio: 3 : 1
MRA848
Fig.24 Timing diagram of character blinking frequency and blinking ratio.
SP code
CR code
SP code
CR code
Character ON
Character OFF
MLB397
Fig.25 Blinking in No background mode.
32
1995 Mar 30
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
SP code
CR code
SP code
CR code
Character ON
Character OFF
MLB398
Fig.26 Blinking in North-West shadowing mode.
SP code
CR code
SP code
CR code
Character ON
Character OFF
MLB399
Fig.27 Blinking in Box shadowing mode (Space Code with background).
33
1995 Mar 30
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
SP code
CR code
SP code
CR code
Character ON
Character OFF
MLB400
Fig.28 Blinking in Box shadowing mode (Space Code without background).
SP code
CR code
SP code
CR code
Character ON
Character OFF
MLB401
Fig.29 Blinking in Frame shadowing mode.
34
1995 Mar 30
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
9.11 Command A
9.13 Command E
When output ports P00, P01 and P04 are enabled,
Command E is used to write data to them.
Table 33 Command A format
BS1 BS0
7
6
5
4
3
2
1
0
0
1
0
1
1
1
0
A/P
0
0
Table 38 Command E format
BS1 BS0
7
6
5
4
3
2
1
0
Command A loads Control Register 4 with data that
determines the function of pin 2 (P04/ACM(VOB2)).
0
1
1
1
X
P04
X
X
P01 P00
9.14 Command F
Table 39 Command F format
Table 34 Selection of P04 or ACM
A/P
PIN FUNCTION
BS1 BS0
7
6
5
4
3
2
1
0
0
P04 is selected as an output port. Data is
written to this port using Command E. This is
also the default setting.
0
0
0
1
0
0
R
G
B
I
1
ACM function selected; can also be used as the
5th colour signal.
This command loads Control Register 5 with data that
determines the background colour in Frame shadowing
mode.
9.12 Commands B, C and D
9.15 Command G
Table 35 Command B format
Table 40 Command G format
BS1 BS0
7
6
5
4
3
2
1
0
BS1 BS0
7
6
5
4
3
2
1
0
0
1
1
0
0
1
V5 V4 V3 V2
0
0
0
1
0
1
HM3 HT2 FS1 FS0
Table 36 Command C format
BS1 BS0
7
6
5
4
3
2
1
0
Command G is used to enable/disable the OSD horizontal
stabilization circuit, to select the Half-tone mode and to
select the character size of the first line.
0
1
1
0
1
0
V1 V0 H5 H4
Table 37 Command D format
In the Half-tone mode, excellent semi-transparent
half-tone effects can be obtained with OSD frequencies in
the range 4 to 7 MHz. This mode also enhances the
background colour with intensity output. For further details
on the half-tone effect refer to the “The programming guide
for the PCA8516” report number MICT/AN9402.
BS1 BS0
7
6
5
4
3
2
1
0
0
1
1
0
1
1
H3 H2 H1 H0
These three commands determine the vertical and
horizontal start positions of the display. 64 vertical and
64 horizontal start positions can be selected. After a
master reset, starting positions are not guaranteed and
therefore must be programmed by the user. The horizontal
start position (HP) and the vertical start position (VP) may
be calculated as follows:
Table 41 Horizontal stabilization circuit control
HM3
STATE OF STABILIZATION CIRCUIT
Stabilization circuit disabled (the default state).
Horizontal stabilization circuit enabled.
0
1
HP = [4 × (H5 → H0) + 5] × fOSD
Table 42 Selection of Half-tone mode
Where (H5 → H0) is the decimal value of these 6 bits and
(H5 → H0) ≥ 4.
HT2
0
HALF-TONE MODE
Half-tone mode not selected (the default state).
Half-tone mode available when ACM bit = 1.
VP = [4 × (V5 → V0) ] × number of scan lines
1
Where (V5 → V0) is the decimal value of these 6 bits and
(V5 → V0) ≥ 0.
1995 Mar 30
35
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
Table 43 Selection of the character size for the first line
10.2 Combination of character font cells
Two (or more) character font cells may be combined in a
horizontal or vertical direction to create a new higher
resolution pattern.
FS1
FS0
CHARACTER DOT SIZE
1H/1V (the default size)
0
0
1
1
0
1
0
1
2H/2V
3H/3V
4H/4V
The combination of two cells in a horizontal direction is
straight forward and requires no special precautions to be
taken. When combining character cells in this manner all
4 Background/Shadowing modes are available. An
example of combining two character font cells in a
horizontal direction is shown in Fig.35.
10 MISCELLANEOUS
10.1 Space and Carriage Return Codes in different
Background/Shadowing modes
However, the combination of two character font cells in a
vertical direction is more difficult and care must be taken;
otherwise, the new pattern may be created with gaps in its
shadowing. An example of a character pattern with gaps is
shown in Fig.37. Providing the steps listed below are
followed no problems with shadowing will occur.
Figures 30 to 34 show the Space Code and Carriage
Return Code in the 4 different Background/Shadowing
modes:
• Mode 0: the No background mode. Both the Space
Code and the Carriage Return Code are displayed as
transparent (no bit) patterns with the video signal as the
background. This is shown in Fig.30.
• The line spacing between two rows of characters must
be programmed to 0H. This procedure is explained in
Section 9.3.2.
• If the North-West shadowing mode is selected then
when combining two character cells in a vertical
direction Row 0 must contain the same bit pattern as
held in Row 18 of the character directly above it. This is
shown in Fig.38.
• Mode 1: the North-West shadowing mode. Both codes
are displayed in the same manner as for Mode 0. This is
shown in Fig.31.
• Mode 2: the Box shadowing mode. The Space Code is
displayed as an opaque pattern with a selected
background colour. This will also be the background
colour of the character following the Space Code. The
Carriage Return Code however, is displayed as a
transparent (no bit) pattern superimposed on the video
signal. This is shown in Fig.32.
• If North-West shadowing is not required then Row 0
should contain all zeros.
The Space Code can also be displayed as a transparent
pattern on the video signal, and this is shown in Fig.33.
The choice of whether the Space Code displays an
opaque pattern or a transparent pattern is mask
programmable.
• Mode 3: the Frame shadowing mode. The Space Code
and Carriage Return Code are displayed as transparent
patterns with background colour. This is shown in
Fig.34.
1995 Mar 30
36
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
0
1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
SP code
CR code
MRA853
RED
BLUE
Fig.30 Space Code and Carriage Return Code in No Background mode - transparent pattern.
1995 Mar 30
37
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
0
1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
SP code
CR code
MRA854
RED
BLUE
BLACK (background)
GREEN (background)
Fig.31 Space Code and Carriage Return Code in North-West shadowing mode - transparent pattern.
1995 Mar 30
38
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
0
1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
SP code
CR code
MRA855
RED
BLUE
YELLOW(background)
CYAN (background)
SP code is an opaque pattern with the background colour of the character it
intends to change or keep.
CR code is always a transparent pattern with the video signal as its background.
SP code can change the background colour of itself and the character/word next to it
(in this example: from cyan to yellow).
Fig.32 Space Code and Carriage Return Code in Box shadowing mode.
1995 Mar 30
39
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
0
1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
SP code
CR code
MED267
RED
BLUE
YELLOW (background)
CYAN (background)
SP code is an transparent pattern with no background colour.
CR code is always a transparent pattern with the video signal as its background.
SP code can change the background colour the character/word next to it
(in this example : from cyan to yellow).
Fig.33 Space Code and Carriage Return Code in Box shadowing mode.
1995 Mar 30
40
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
0
1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
SP code
CR code
MRA856
RED
BLUE
YELLOW (background)
SP and CR codes are both transparent patterns coloured the same
as the background colour.
Fig.34 Space Code and Carriage Return Code in Frame shadowing mode.
1995 Mar 30
41
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
0
1
2
3
4
5
6
7
8
9
10 11
0
1
2
3
4
5
6
7
8
9
10 11
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
14
15
16
17
10
11
12
13
14
15
16
17
MRA849
Fig.35 Combination of two character cells in a horizontal direction to create a new font.
1995 Mar 30
42
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
0
1
2
3
4
5
6
7
8
9
10 11
0
1
2
3
4
5
6
7
8
9
10 11
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
14
15
16
17
10
11
12
13
14
15
16
17
MRA850
Fig.36 Combination of two character cells in a horizontal direction to create a new font
North-West shadowing mode.
1995 Mar 30
43
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
0
1 2 3 4 5 6 7 8 9 10 11
0
1 2 3 4 5 6 7 8 9 10 11
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
0
cell boundary
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
8
If Row 0 of the lower
character does not contain
the bit pattern of Row 18
of the upper character
in North West shadowing
mode, a gap in the
8
9
shadow might occur.
10
11
12
13
14
15
16
17
9
10
11
12
13
14
15
16
17
18
0
1 2 3 4 5 6 7 8 9 10 11
MRA851
0
1 2 3 4 5 6 7 8 9 10 11
Character pattern stored in the ROM/RAM
Character pattern displayed on the screen
Fig.37 Combination of two characters in a vertical direction - with gap.
1995 Mar 30
44
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
0
1 2 3 4 5 6 7 8 9 10 11
0
1 2 3 4 5 6 7 8 9 10 11
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
0
cell boundary
1
2
0
1
2
3
4
5
6
7
8
Row 0 of the lower character
should contain the bit
pattern of Row 18
of the upper character in
North West shadowing
mode to avoid a 'break'
in the shadow
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
9
10
11
12
13
14
15
16
17
18
0
1
2
3
4
5
6
7
8
9
10 11
MRA852
0
1 2 3 4 5 6 7 8 9 10 11
Character pattern stored in the ROM/RAM
Character pattern displayed on the screen
Fig.38 Combination of two characters in a vertical direction - with no gap.
1995 Mar 30
45
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
The OSD clock is enabled/disabled using Command 7;
see Section 9.8. When the OSD clock is disabled, the
oscillator remains active, therefore the transient time from
the OSD clock start-up to locking into the external HSYNC
signal is reduced. As the on-chip oscillator is always active
after power-on, when the OSD clock is enabled no large
currents flow (as for RC or LC oscillators); therefore
radiated noise is dramatically reduced.
11 OSD CLOCK
The on-chip clock generator comprises Phase-Locked
Loop circuitry and is shown in Fig.39. The frequency of the
OSD clock is programmable and is determined by the
contents of the 6-bit counter, which is loaded using
Command 6. The OSD clock frequency is calculated as
shown below; frequencies within the range 4 to 14 MHz
can be selected.
Character width is a function of the OSD clock frequency;
decreasing fOSD increases the width of the characters.
Therefore, for optimum character display quality the
choice of the OSD clock frequency is important; this is
explained in Chapter 12.
fOSD = fHSYNC × 16 × (PLLCN)
Where: 16 < (PLLCN) < 40; (PLLCN) is the decimal value
held in the 6-bit counter.
The Voltage Controlled Oscillator (VCO) is synchronized
to the HIGH-to-LOW edge of f1 (see Fig.39) which is
always on the trailing edge of fHSYNC. The programmable
active level detector will pass the HSYNC signal if it is
programmed as active HIGH or invert the HSYNC signal if
it is programmed as active LOW. The 4-bit prescaler
increments or decrements the output of the VCO in steps
of (16 × fHSYNC).
C
HSYNC
f
1
R
1
ACTIVE
LEVEL
DETECTOR
PHASE/
FREQUENCY
DETECTOR
CHARGE PUMP
AND
LOOP FILTER
VOLTAGE
CONTROLLED
OSCILLATOR
C
1
divided by N
PROGRAMMABLE
6-BIT COUNTER
4-BIT
PRESCALER
f
PLL
f
OSD
MLC349
OSD disable
Fig.39 Block diagram of OSD oscillator.
1995 Mar 30
46
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
12 OSD CLOCK SELECTION FOR DIFFERENT TV
STANDARDS
12.2 Maximum number of characters per row
The number of characters per row is a function of the OSD
clock frequency and the TV standard used.
12.1 OSD frequency
With reference to Fig.40 the active video signal period of a
horizontal line is 53.5 µs. However, in order to reduce
jittering at the screen edge, overscan is normally applied
by the TV manufacturer and this reduces the visible video
signal period to 48.15 µs. The examples given below show
how the number of characters per row and the character
width may be obtained for the NTSC 525LPF/60 Hz
TV standard using different OSD clock frequencies.
The PCA8516 supports four different TV scanning
standards. To obtain the best quality character display,
each TV standard requires a different OSD frequency. To
cater for this requirement the PCA8516 provides a
programmable OSD clock that generates frequencies in
the range 4 to 14 MHz. The three examples given below
illustrate the OSD clock requirements for different TV
scanning standards.
12.2.1 NTSC 525LPF/60 Hz; fOSD = 6 MHz
12.1.1 NTSC 525LPF/60 Hz and PAL 625LPF/50 Hz
• As fOSD = 6 MHz: tOSD = 0.1666 µs.
The OSD clock is applied directly to the OSD circuitry and
can take any value within the 4 to 14 MHz frequency
range. The NTSC 525LPF/60 Hz standard when used with
a 19 inch screen and an OSD clock of 8 MHz, produces a
character dot width of 13.2 mm.
• The number of visible dots on one horizontal line is 290
(48.15 µs/0.1666 µs). However, as the starting position
of the first character dot is approximately 45 dots after
HSYNC, the actual visible number of dots per line is 245.
• Each character is composed of a 12 × 18 dot matrix;
therefore the maximum number of characters on one
line is 20 (245/12).
12.1.2 NTSC 1050LPF/60 Hz
With this standard, in order to obtain the same character
dot width as in the NTSC 525LPF/60 Hz standard that
uses an OSD clock of 7 MHz; the OSD clock must be
doubled to 14 MHz because the horizontal frequency is
doubled.
• If a 19 inch TV screen is used, the width of a horizontal
line is approximately 370 mm and this gives a character
width of 18.5 mm.
12.2.2 NTSC 525LPF/60 Hz; fOSD = 10 MHz
To keep the same character height as that in the
NTSC 525LPF/60 Hz standard, HSYNC is also divided by
two, internally.
• As fOSD = 10 MHz: tOSD = 0.1 µs.
• The number of visible dots on one horizontal line is 481
(48.15 µs/0.1 µs). Allowing for the initial starting position
of 45 dots, the actual number of visible dots per line is
436.
12.1.3 PAL 1250LPF/100 Hz
With this standard, in order to obtain the same character
dot width as in the PAL 625LPF/50 Hz standard; the OSD
clock must be doubled.
• Each character is composed of a 12 × 18 dot matrix;
therefore the maximum number of characters on one
line is 36.
HSYNC is applied directly to the OSD circuitry without
being divided by two as both the horizontal frequency
(1250 Hz) and the vertical frequency (100 Hz) are
doubled.
• With a 19 inch TV screen, the width of a horizontal line
is approximately 370 mm and the character width is
10.3 mm.
1995 Mar 30
47
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
12.3 Maximum number of rows per frame
The number of rows per frame is a function of the number
of active lines per display field and the number of vertical
dots in the character matrix (which is 18). The number of
rows per frame (N) is calculated as shown below.
number of active lines per field
N =
---------------------------------------------------------------------------------
18
The four examples shown below illustrate how the
maximum number of rows per frame is obtained for each
TV scanning standard.
12.3.1 NTSC 525LPF/60 HZ
The number of active lines per field for this standard is
between 241.5 and 249H (see Fig.41). If the value of 241
is used then the maximum number of rows per frame is 13.
12.3.2 PAL 625LPF/50 HZ
The number of active lines per field for this standard is 280.
Therefore, the maximum number of rows per frame is 15.
12.3.3 NTSC 1050LPF/60 HZ
For this standard the number of active lines per frame is
double that of the NTSC 525LPF/60 Hz standard.
However, as HSYNC is divided by two internally, the
maximum number of rows per frame is also 13.
12.3.4 PAL 1250LPF/100 HZ
With this standard it is not necessary to divide HSYNC by
two as both the horizontal and vertical frequency are
doubled. The maximum number of rows per frame is 15.
1995 Mar 30
48
blacker than
black, 100%
blanking level
75%
black,
67.5 2.5%
composite
video
signal
white,
12.5 2.5%
0
retrace
begins
blanking
begins
trace
RIGHT
horizontal
deflection
sawtooth
0
retrace
blanking
ends
LEFT
MRA862
retrace ends
ahdnbok,uflapegwidt
Fig.40 Composite video signal for three horizontal lines compared to three horizontal deflection sawteeth (NTSC 525LPF/60 Hz).
equalizing
pulse
interval
vertical
sync pulse
interval
equalizing
pulse
interval
blacker
than black
H
H
H
0.5 H
3H
H
0.5 H
H
100%
black
level
(75 2.5)%
3H
3H
white
level
(12.5 2.5)%
0%
zero
carrier
0.03 V
0
vertical blanking 0.05 V
bottom of
picture
start of
next field
picture
horizontal
blanking
second field, 262.5 H
16.666 s or 1/60 s
first field, 262.5 H
16.666 s or 1/60 s
µ
µ
RIGHT
horizontal
deflection
sawtooth
LEFT
vertical blanking period
13 to 21 H (825.5 to 1335.5 s)
active lines
241.5 to 249.5 H
active lines
241.5 to 249.5 H
vertical blanking period
13 to 21 H
µ
MRA863
second field
vertical deflection
sawtooth
BOTTOM
trace
retrace
vertical
deflection
sawtooth
trace
blanking
begins
retrace
500 to 750
µ
s
first field
vertical deflection
sawtooth
blanking
ends
TOP
ahdnbok,uflapegwidt
Fig.41 Vertical synchronization and blanking pulse intervals for one frame (NTSC 525LPF/60 Hz).
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
13 OUTPUT PORTS
The three output ports P00, P01 and P04 can be
configured using one of three mask options. The three
output mask options are specified below:
Option 1 Standard output with switched pull-up current
source. See Figs 42 and 45.
Option 2 Open-drain output. See Figs 43 and 46.
Option 3 Push-pull output. See Figs 44 and 47.
The state of each output port after a Power-on-reset can
also be selected using the mask options. All the available
mask options for the PCA8516 are given in Section 13.1.
Port output register
V
DD
write pulse
TR2
current
source
TR3
TR4
data bus
D
MQ
D
SQ
SQ
100 µA typical
Pin
TR1
V
SS
MBE128
read pulse (testing use only)
Fig.42 Standard output with switched pull-up current source (Option 1 - P00 and P01).
1995 Mar 30
51
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
Port output register
write pulse
data bus
V
DD
D
D
MQ
SQ
SQ
Pin
TR1
V
SS
MBE129
read pulse (testing use only)
Fig.43 Open-drain output (Option 2 - P00 and P01).
Port output register
write pulse
V
DD
TR2
TR3
TR4
current
source
data bus
D
MQ
D
SQ
SQ
100 µA typical
Pin
TR1
V
SS
MBE130
read pulse (testing use only)
Fig.44 Push-pull output (Option 3 - P00 and P01).
52
1995 Mar 30
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
ACM output from OSD circuit
ACM output enable (A/P bit)
V
DD
Port output register
write pulse
TR2
current
source
TR3
TR4
data bus
100 µA typical
D
MQ
D
SQ
SQ
Pin
TR1
V
SS
MLB353 - 1
read pulse (testing use only)
Fig.45 Standard output with switched pull-up current source (Option 1 - P04).
ACM output from OSD circuit
ACM output enable (A/P bit)
Port output register
write pulse
V
DD
data bus
D
MQ
D
SQ
Pin
TR1
V
SS
MLB354 - 1
read pulse (testing use only)
Fig.46 Open-drain output (Option 2 - P04).
53
1995 Mar 30
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
ACM output from OSD circuit
ACM output enable (A/P bit)
V
DD
Port output register
write pulse
TR2
current
source
TR3
TR4
data bus
100 µA typical
D
MQ
D
SQ
Pin
TR1
V
SS
MLB355 - 1
read pulse (testing use only)
Fig.47 Push-pull output (Option 3 - P04).
1995 Mar 30
54
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
13.1 Mask options
Table 47 Customer selected mask options
Tables 44 to 48 list the available mask options for the
PCA8516. Table 47 is intended for customer use when
ordering the device.
FEATURE
OPTION
Output port configurations
P00
P01
P04
Table 44 Port configuration options
OPTION
1, 2 or 3
1, 2 or 3
1, 2 or 3
PORT
P00
Port state after Power-on-reset
P01
P00
P01
P04
P04
Table 45 Port state after Power-on-reset
Oscillator tranconductance
OPTION
HIGH
PORT
P00
LOW
MEDIUM
HIGH
HIGH
P01
HIGH or LOW
P04
Space Code pattern
Transparent
Table 46 Space Code options
Opaque
OPTION
SHADOWING MODE
Transparent
pattern
Available in Box shadowing mode
only; see Fig.33.
Opaque pattern
Available in Box shadowing mode
only; see Fig.32.
Table 48 System oscillator transconductance options
TRANSCONDUCTANCE
(mS)
fOSC - QUARTZ CRYSTAL
(MHz)
fOSC - CERAMIC RESONATOR
(MHz)
OPTION
LOW
0.7
1 to 6
4 to 12
−
−
MEDIUM
HIGH
1.6
4.5
1 to 6
3 to 16
1995 Mar 30
55
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
14 DEFAULT VALUES AFTER POWER-ON-RESET
The default values of registers after a Power-on-reset are specified in Table 49. All other settings must be initialized by
the user after a Power-on-reset.
Table 49 Default values
STATE AFTER
REGISTER
BIT
DESCRIPTION
RESET
User directly controllable registers
Control Register 1
M1
M0
Bp
0
0
1
Scanning mode selection bits. Conventional
NTSC 525LPF/60 Hz and/or PAL 625LPF/50 Hz selected.
Polarity control bit; the output polarities of FB, ACM, R, G, B and
I are active HIGH.
EN
Hp
0
0
0
0
1
0
0
0
0
0
OSD enable/disable control bit; the OSD is disabled.
Control Register 2
Control Register 3
HSYNC input polarity control bit; the input polarity is active LOW.
VSYNC input polarity control bit; the input polarity is active LOW.
Vp
S1
Display mode selection bits; the North-West shadowing mode is
selected.
S0
BF1
BF0
BR1
BR0
A/P
Blinking frequency control bits. The blinking frequency is set to
fVSYNC/16 Hz.
Active ratio of blinking frequency control bits. The active ratio is
set to 3 : 1.
Control Register 4
Control Register 5
Port control bit. Pin 2 (P04/ACM/VOB2) is selected as an output
port pin.
R
G
0
0
1
0
0
0
Background colour selection bits in Frame shadowing mode; the
default colour is Blue.
B
I
−
BS1
BS0
Command Bank selection bits. Command Bank 00 is selected.
User indirectly controllable registers
ACM
ACM
B
0
1
0
0
0
0
0
0
The ACM output is LOW unless changed by the Space Code.
Background colour
The Background colour selected is Blue unless changed by the
Space Code.
R
G
I
Character size
End of display
T4
T3
T0
The default character size is 1V/1H. A different value can be
selected by using the Carriage Return Code.
Will continue to display next character (if the OSD clock is
enabled).
1995 Mar 30
56
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
15 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VDD
PARAMETER
MIN.
−0.5
MAX.
+7.0
UNIT
supply voltage
V
V
VI
all input voltages
−0.5
−
VDD + 0.5
−5.0
IOH
IOL
maximum source current for all port lines
maximum sink current for all port lines
total power dissipation
mA
mA
mW
°C
−
5.0
Ptot
Tstg
Tamb
−
500
storage temperature
−55
−20
+125
+70
operating ambient temperature
°C
1995 Mar 30
57
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
16 DC CHARACTERISTICS
VDD = 5 V ±10%; VSS = 0 V; Tamb = −20 to +70 °C. All voltages with respect to VSS unless otherwise specified.
SYMBOL
PARAMETER
operating supply voltage
operating supply current
CONDITIONS
MIN.
4.5
TYP. MAX. UNIT
VDD
IDD
5.0
5
5.5
10
V
VDD = 5 V; fxtal = 3 MHz;
−
−
−
mA
f
OSD = 10 MHz
DD = 5 V; fxtal = 3 MHz;
fOSD = Stop
DD = 5 V; fxtal = 3 MHz;
fOSD = Stop
RESET, TEST1, TEST2, HSYNC, VSYNC, E and HIO/ I2C inputs
V
7
1
14
2
mA
mA
V
VIL
VIH
ILI
LOW level input voltage
HIGH level input voltage
input leakage current
0
−
−
0.3VDD
VDD
V
0.7VDD
±0.01
V
VSS < VI < VDD
±0.20 ±10
µA
Ports P00 to P03 (with combined functions) inputs
VIL
VIH
ILI
LOW level input voltage
HIGH level input voltage
input leakage current
0
−
−
−
0.3VDD
V
0.7VDD
VDD
V
VSS < VI < VDD
−
±10
µA
Ports P00 to P03 (with combined functions) outputs
IOL
LOW level output sink current
VDD = 5 V; VO = 0.4 V
VDD = 5 V; VO = 0.7VDD
VDD = 5 V; VO = VSS
5.0
−40
−
12.0
−
−
mA
µA
IOH1
HIGH level pull-up output source current
−100
−140 −400
µA
IOH2
HIGH level push-pull output source current VDD = 5 V; VO = VDD − 0.4 V −3.0
−7.0
−
mA
SDA/SIN and SCK/SCLK inputs
VIL
VIH
LOW level input voltage
HIGH level input voltage
0
−
−
0.3VDD
VDD
V
V
0.7VDD
SDA/SIN and SCK/SCLK outputs
IOL
LOW level open drain sink current
VDD = 5 V; VO = 0.4 V
3.0
−
−
mA
R, G, B, I, FB and P04/ACM outputs
IOL
LOW level push-pull output sink current
HIGH level pull-up output source current
VDD = 5 V; VO = 0.4 V
VDD = 5 V; VO = 0.7VDD
3.2
−40
−
5.5
−
−
mA
µA
IOH1
−100
V
DD = 5 V; VO = VSS
−140 −400
−2.4
µA
IOH2
HIGH level push-pull output source current VDD = 5 V; VO = VDD − 0.4 V −1.6
−
mA
1995 Mar 30
58
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
17 AC CHARACTERISTICS
V
DD = 5 V ±10%, VSS= 0 V.
SYMBOL PARAMETER
fxtal
CONDITIONS
MIN.
0.5
TYP.
3.0
MAX.
6.0
UNIT
MHz
crystal oscillator frequency
OSD oscillator frequency
note 1
fOSD
1V/1H scanning mode
4.0
4.0
7.0
10.0
14.0
MHz
MHz
1V/2H and 2V/2H scanning
modes
12.0
COSD
ROSD
external capacitance at pin C
external resistance at pin C
0.4
5.0
−
−
4.0
µF
kΩ
15.0
Note
1. The minimum frequency should be 3 times greater than the maximum I2C-bus frequency or the HIO frequency used
in the system.
1995 Mar 30
59
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
18 PACKAGE OUTLINES
SDIP24: plastic shrink dual in-line package; 24 leads (400 mil)
SOT234-1
D
M
E
A
2
A
A
L
1
c
(e )
w M
e
Z
1
b
1
M
H
b
24
13
pin 1 index
E
1
12
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
max.
A
A
2
max.
1
(1)
(1)
Z
w
UNIT
b
b
c
D
E
e
e
L
M
M
1
1
E
H
min.
max.
1.3
0.8
0.53
0.40
0.32
0.23
22.3
21.4
9.1
8.7
3.2
2.8
10.7
10.2
12.2
10.5
mm
4.7
0.51
3.8
1.778
10.16
0.18
1.6
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-02-04
SOT234-1
1995 Mar 30
60
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A
X
c
H
v
M
A
E
y
Z
24
13
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
12
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.30
0.10
2.45
2.25
0.49
0.36
0.32
0.23
15.6
15.2
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
mm
2.65
0.25
0.01
1.27
0.050
1.4
0.25 0.25
0.01
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.61
0.014 0.009 0.60
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches 0.10
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-01-24
97-05-22
SOT137-1
075E05
MS-013AD
1995 Mar 30
61
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
Several techniques exist for reflowing; for example,
19 SOLDERING
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
19.1 Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
19.3.2 WAVE SOLDERING
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
19.2 DIP
19.2.1 SOLDERING BY DIPPING OR BY WAVE
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
• The package footprint must incorporate solder thieves at
the downstream end.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
19.2.2 REPAIRING SOLDERED JOINTS
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
19.3.3 REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
19.3 SO
19.3.1 REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
1995 Mar 30
62
Philips Semiconductors
Preliminary specification
Stand-alone OSD
PCA8516
20 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
21 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
22 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1995 Mar 30
63
Philips Semiconductors – a worldwide company
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For all other countries apply to: Philips Semiconductors,
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P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. +31-40-724825
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Tel. (03)3740 5028, Fax. (03)3740 0580
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SCD38
© Philips Electronics N.V. 1995
All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.
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The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
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use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.
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453061/1500/01/pp64
Date of release: 1995 Mar 30
9397 750 00024
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Tel. (022)74 8000, Fax. (022)74 8341
Document order number:
Philips Semiconductors
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