PCA9556PW [NXP]
Octal SMBus Registered Interface; 八路的SMBus接口注册
| 型号： | PCA9556PW |
| 厂家： | 
NXP |
| 描述： | Octal SMBus Registered Interface |
| 文件： | 总12页 (文件大小：115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
PCA9556
Octal SMBus Registered Interface
Product specification
1998 Dec 18
Philips
Semiconductors
Philips Semiconductors
Product specification
Octal SMBus Registered Interface
PCA9556
FEATURES
PIN CONFIGURATION
• SMBus compliance with fixed 3.3V voltage levels
V
1
16
DD
SCL
• Operating power supply voltage range of 3.0V – 3.6V
• Active high polarity inverter register
• Write protect register
SDA
2
3
4
5
6
7
8
15 RESET
I/O7
14
A0
A1
I/O6
13
• Active low reset pin
I/O5
12
A2
I/O4
11
I/O0
I/O1
• Low leakage current on power-down
• Noise filter on SCL/SDA inputs
• No glitch on power-up
I/O3
10
I/O2
9
V
SS
• Internal power-on reset
su01045
Figure 1. Pin configuration
• 8 I/O pins which default to 8 inputs
• High impedance open drain on I/O
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
Serial clock line
DESCRIPTION
1
2
SCL
SDA
A0
The PCA9556 is a silicon CMOS circuit which provides parallel
input/output expansion for SMBus applications. The PCA9556
consists of an 8-bit input port register, 8-bit output port register, and
an SMBus interface. It has low current consumption and a high
impedance open drain output pin, I/O0.
Serial data line
Address input 0
Address input 1
Address input 2
I/O0 (open drain)
I/O1
3
4
A1
5
A2
The SMBus system master can reset the PCA9556 in the event of a
timeout by asserting a LOW on the reset input. The SMBus system
master can also invert the PCA9556 inputs by writing to their active
HIGH polarity inversion bits. Finally, the SMBus system master can
enable the PCA9556’s I/Os as either inputs or outputs by writing to
their I/O configuration bits.
6
I/O0
I/O1
7
8
V
Supply GROUND
I/O2
SS
9
I/O2
I/O3
10
11
12
13
14
15
16
I/O3
The power-on reset sets the registers to their default values and
initializes the SMBus state machine. The RESET pin causes the
same reset/initialization to occur without depowering the part.
I/O4
I/O4
I/O5
I/O5
I/O6
I/O6
I/O7
I/O7
RESET
External reset (active LOW)
Supply voltage
V
DD
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
DRAWING NUMBER
16-Pin Plastic TSSOP16 Type I
0°C to +70°C
PCA9556 PW
SOT403-1
2
1998 Dec 18
853-2138 20549
Philips Semiconductors
Product specification
Octal SMBus Registered Interface
PCA9556
BLOCK DIAGRAM
A0
A1
A2
I/O0
I/O1
I/O2
I/O3
SCL
INPUT/
OUT-
PUT
INPUT
FILTER
8-BIT
SMBUS
CONTROL
SDA
I/O4
I/O5
PORTS
WRITE pulse
READ pulse
I/O6
I/O7
V
V
DD
SS
POWER-
ON
RESET
RESET
NOTE: ALL I/Os ARE SET TO INPUTS AT RESET
su01046
Figure 2. Block diagram
REGISTERS
Command Byte
Register 2 – Polarity Inversion Register
Command
Protocol
Function
bit
N7
N6
N5
N4
N3
N2
N1
0
N0
0
default
1
1
1
1
0
0
0
Read byte
Input port register
1
2
3
Read/write byte
Read/write byte
Read/write byte
Output port register
This register enables polarity inversion of pins defined as inputs by
register 3. If a bit in this register is set (written with ‘1’), the
corresponding port pin’s polarity is inverted. If a bit in this register is
cleared (written with a ‘0’), the corresponding port pin’s original
polarity is retained.
Polarity inversion register
I/O configuration register
The command byte is the first byte to follow the address byte during
a write transmission. It is used as a pointer to determine which of the
following registers will be written or read.
Register 3 – Input/Output Configuration Register
bit
C7
C6
C5
C4
C3
C2
C1
C0
Register 0 – Input Port Register
default
1
1
1
1
1
1
1
1
I7
I6
I5
I4
I3
I2
I1
I0
This register configures the directions of the I/O pins. If a bit in this
register is set (written with ‘1’), the corresponding port pin is enabled
as an input with high impedance output driver. If a bit in this register
is cleared (written with ‘0’), the corresponding port pin is enabled as
an output.
This register is an input-only port. It reflects the incoming logic levels
of the pins, regardless of whether the pin is defined as an input or an
output by register 3. Writes to this register have no effect.
Register 1 – Output Port Register
O7
O6
O5
O4
O3
O2
0
O1
0
O0
0
bit
RESET
default
0
0
0
0
0
Power-on Reset
This register is an output-only port. It reflects the outgoing logic
When power is applied to V , an internal power-on reset holds the
DD
levels of the pins defined as outputs by register 3. Bit values in this
register have no effect on pins defined as inputs. In turn, reads from
this register reflect the value that is in the flip-flop controlling the
output selection, NOT the actual pin value.
PCA9556 in a reset state until V has reached V
the reset condition is released and the PCA9556 registers and
SMBus state machine will initialize to their default states.
. At that point,
DD
POR
External Reset
A reset can be accomplished by holding the RESET pin low for a
minimum of T . The PCA9556 registers and SMBus state machine
W
will be held in their default state until the RESET input is once again
high. This input contains an internal pull-up, therefore, it may be left
open if not used.
3
1998 Dec 18
Philips Semiconductors
Product specification
Octal SMBus Registered Interface
PCA9556
SIMPLIFIED SCHEMATIC OF I/O0
DATA FROM
SHIFT REGISTER
INPUT/OUTPUT
MASK REGISTER
DATA FROM
SHIFT REGISTER
Q
D
OUTPUT PORT
REGISTER DATA
WRITE
REGISTER
FF
D
Q
Q
Q
C
WRITE MASK PULSE
WRITE PULSE
K
FF
I/O0
C
K
ESD PROTECTION DIODE
V
SS
READ
REGISTER
INPUT PORT
REGISTER DATA
D
Q
FF
Q
C
K
READ PULSE
POLARITY
REGISTER
DATA FROM
SHIFT REGISTER
POLARITY
REGISTER DATA
D
Q
FF
WRITE
POLARITY
PULSE
Q
C
K
NOTE: ON POWER-UP OR RESET, ALL REGISTERS RETURN TO DEFAULT VALUES
su01047
Figure 3. Simplified schematic of I/O0
4
1998 Dec 18
Philips Semiconductors
Product specification
Octal SMBus Registered Interface
PCA9556
SIMPLIFIED SCHEMATIC OF I/O1 TO I/O7
DATA FROM
SHIFT REGISTER
OUTPUT PORT
REGISTER DATA
INPUT/OUTPUT
MASK REGISTER
V
DD
DATA FROM
SHIFT REGISTER
Q
D
WRITE
REGISTER
ESD PROTECTION DIODE
FF
D
Q
Q
Q
C
WRITE MASK PULSE
WRITE PULSE
K
FF
I/O1 TO I/O7
C
K
ESD PROTECTION DIODE
V
SS
READ
REGISTER
INPUT PORT
REGISTER DATA
D
Q
FF
Q
C
K
READ PULSE
POLARITY
REGISTER
DATA FROM
SHIFT REGISTER
POLARITY
REGISTER DATA
D
Q
FF
WRITE
POLARITY
PULSE
Q
C
K
NOTE: ON POWER-UP OR RESET, ALL REGISTERS RETURN TO DEFAULT VALUES
su01055
Figure 4. Simplified schematic of I/O1 to I/O7
5
1998 Dec 18
Philips Semiconductors
Product specification
Octal SMBus Registered Interface
PCA9556
SMBus Address
slave address
0
0
1
1
A2 A1 A0 R/W
programmable
fixed
su01048
Figure 5. PCA9556 address
SMBus Transactions
Data is transmitted to the PCA9556 registers using Write Byte transfers (see Figures 6 and 7). Data is read from the PCA9556 registers using
Read and Receive Byte transfers (see FIgures 8 and 9).
1
2
3
4
5
6
7
8
0
9
SCL
SDA
command byte
slave address
data to port
DATA 1
0
0
1
1
A2 A1 A0
S
A
0
0
0
0
0
0
0
1
A
A
start condition
R/W acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
WRITE TO
PORT
DATA OUT
FROM PORT
DATA 1 VALID
t
pv
su01049
Figure 6. WRITE to output port register via Write Byte Protocol
1
2
3
4
5
6
7
8
0
9
SCL
SDA
command byte
slave address
data to register
DATA
0
0
1
1
A2 A1 A0
S
A
A
A
0
0
0
0
0
0
1
1/0
start condition
R/W acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
su01050
Figure 7. WRITE to I/O configuration or polarity inversion registers via Write Byte Protocol
6
1998 Dec 18
Philips Semiconductors
Product specification
Octal SMBus Registered Interface
PCA9556
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
acknowledge
from master
slave address
slave address
data from register
1
A2 A1
1
A2 A1
A0
0
0
1
A0
0
0
1
1
COMMAND BYTE
DATA
S
0
A
A
S
A
A
first byte
R/W
R/W
at this moment master-transmitter
becomes master-receiver and
slave-receiver becomes
slave-transmitter
no acknowledge
from master
data from register
NA
P
DATA
last byte
su01052
Figure 8. READ from register via Read byte protocol
slave address
data from port
DATA 1
data from port
SDA
0
0
1
1
A2 A1 A0
DATA 4
S
1
A
A
NA
P
start condition
R/W acknowledge
from slave
acknowledge
from master
no acknowledge
from master
stop
condition
READ FROM
PORT
DATA INTO
PORT
DATA 2
DATA 3
DATA 4
t
ph
t
ps
Notes:
1. This figure assumes the command byte has previously been programmed with 00h.
2. Transfer of data can be stopped at any moment by a stop condition. When this occurs,
data present at the last acknowledge phase is valid (output mode). Input data is lost.
su01051
Figure 9. READ input port register via Receive byte protocol
7
1998 Dec 18
Philips Semiconductors
Product specification
Octal SMBus Registered Interface
PCA9556
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
+4.6
+ 0.5
UNIT
V
V
DD
Supply voltage
Input voltage
–0.5
V
I
V
– 0.5
V
V
V
SS
DD
I
I
DC input current
–
± 20
+ 0.5
DD
mA
V
V
I/O
DC voltage on an I/O as an input other than I/O0
DC voltage on I/O0 as an input
V
V
– 0.5
SS
V
I/O0
– 0.5
4.6
+400
–20
V
SS
–
µA
mA
mA
mA
mA
mW
mW
°C
I
DC input current on I/O0
I/O0
–
–
–
–
–
–
I
I/O
DC output current on an I/O
Supply current
± 20
I
DD
I
SS
Supply current
P
tot
Total power dissipation
Power dissipation per output
Storage temperature range
Operating ambient temperature
P
O
T
stg
–65
0
+150
+70
T
amb
°C
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take
precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC24 under ”Handling MOS devices”.
DC CHARACTERISTICS
V
= 3.0 to 3.6 V; V = 0 V; T
= 0 to +70 °C; unless otherwise specified.
DD
SS
amb
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Supplies
V
Supply voltage
Supply current
3.0
3.6
V
DD
Operating mode; V = 3.3 V;
DD
no load; V = V or V ;
I
300
425
µA
I
DD
SS
DD
f
= 100 kHz
SCL
Standby mode; V = 3.3 V
DD
I
stb
Standby current
25
50
µA
no load; V = V or V
I
DD
SS
V
= 3.3 V
DD
V
POR
Power-on reset voltage
1.3
2.4
V
no load; V = V or V
note 1
I
DD
SS;
input SCL; input/output SDA
V
LOW level input voltage
HIGH level input voltage
LOW level output current
Leakage current
–0.5
2.1
3
0.8
V
V
IL
IH
V
V
+ 0.5
DD
I
OL
V
= 0.4V
–
mA
µA
pF
OL
I
L
V = V = V
I
–1
–
+1
10
DD
SS
C
Input capacitance
V = V
I
I
SS
I/Os
V
LOW level input voltage
HIGH level input voltage
–0.5
2.0
–
–
0.8
V
V
IL
V
IH
V
+ 0.5
DD
Maximum allowed input current through
protection diode (I/O1 – I/O7)
I
V ≥ V or V ≤ V
–
–
±400
µA
IHL(max)
I
DD
I
SS
I
LOW level output current
V
OL
V
OH
V
DD
V
DD
V
DD
= 0.55V; V = 3.3V
8
4
10
–
–
mA
mA
OL
DD
HIGH level output current except I/O0
= 2.4V; V = 3.3V
DD
= 3.6V; V = 4.6V
–
1
1
I
OH
OH
HIGH level output current on I/O0
µA
= 0V; V = 3.3V
–
OH
I
L
Input leakage current
Input capacitance
Output capacitance
= 3.6V; V = 0 or V
DD
–1
–
1
µA
pF
pF
I
C
–
–
10
10
I
C
–
O
Select Inputs A0, A1, A2, and RESET
V
LOW level input voltage
HIGH level input voltage
Input leakage current
–0.5
2.0
–1
0.8
V
V
IL
IH
LI
V
V
+ 0.5
DD
I
1
µA
NOTE:
1. The power-on reset circuit resets the SMBus logic with V < V
and sets all I/Os to their default values
DD
POR
8
1998 Dec 18
Philips Semiconductors
Product specification
Octal SMBus Registered Interface
PCA9556
AC SPECIFICATIONS
LIMITS
SYMBOL
PARAMETER
UNITS
MIN
10
MAX
F
SBM
SMB operating frequency
Bus free time between stop and start conditions
Hold time after (repeated) start condition
Repeated start condition setup time
Data hold time
100
KHz
µs
µs
µs
ns
ns
µs
µs
ns
ns
T
BUF
4.7
4.0
4.7
300
250
4.7
4.0
T
HO:STA
T
SU:STA
HO:DAT
T
T
Data setup time
SU:DAT
T
LOW
Clock LOW period
T
HIGH
Clock HIGH period
T
F
Clock/Data fall time
300
T
R
Clock/Data rise time
1000
Port Timing
T
PV
T
PS
T
PH
Output data valid
Input data setup time
Input data hold time
4
µs
µs
µs
0
4
Reset
T
W
Reset pulse width
2
ns
9
1998 Dec 18
Philips Semiconductors
Product specification
Octal SMbus Registered Interface
PCA9556
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
10
1998 Dec 18
Philips Semiconductors
Product specification
Octal SMbus Registered Interface
PCA9556
NOTES
11
1998 Dec 18
Philips Semiconductors
Product specification
Octal SMbus Registered Interface
PCA9556
2
2
Purchase of Philips I C components conveys a license under the Philips’ I C patent
2
to use the components in the I C system provided the system conforms to the
I C specifications defined by Philips. This specification can be ordered using the
2
code 9398 393 40011.
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1999
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 04-99
Document order number:
9397 750 04974
Philips
Semiconductors
相关型号：
PCA9557D
REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH RESET AND CONFIGURATION REGISTERS
TI
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