PCF8533U [NXP]
Universal LCD driver for low multiplex rates; 低复用率的通用LCD驱动器
| 型号： | PCF8533U |
| 厂家： | 
NXP |
| 描述： | Universal LCD driver for low multiplex rates |
| 文件： | 总36页 (文件大小：162K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
PCF8533
Universal LCD driver for low
multiplex rates
Product specification
1999 Jul 30
Supersedes data of 1999 Mar 12
File under Integrated Circuits, IC12
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
CONTENTS
7
CHARACTERISTICS OF THE I2C-BUS
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
Bit transfer
1
2
3
4
5
6
FEATURES
START and STOP conditions
System configuration
Acknowledge
PCF8533 I2C-bus controller
Input filters
I2C-bus protocol
Command decoder
Display controller
Cascaded operation
GENERAL DESCRIPTION
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
6.1
6.2
6.3
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.5
6.5.1
6.5.2
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
Power-on reset
LCD bias generator
LCD voltage selector
LCD drive mode waveforms
Static drive mode
1 : 2 multiplex drive mode
1 : 3 multiplex drive mode
1 : 4 multiplex drive mode
Oscillator
Internal clock
External clock
Timing
Display register
8
LIMITING VALUES
9
HANDLING
10
11
12
13
14
15
16
17
18
DC CHARACTERISTICS
AC CHARACTERISTICS
BONDING PAD LOCATIONS
DEVICE PROTECTION
TRAY INFORMATION
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I2C COMPONENTS
BARE DIE DISCLAIMER
Segment outputs
Backplane outputs
Display RAM
Data pointer
Subaddress counter
Output bank selector
Input bank selector
Blinker
1999 Jul 30
2
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
1
FEATURES
• Single-chip LCD controller/driver
• Selectable backplane drive configuration: static or 2/3/4
backplane multiplexing
• Selectable display bias configuration: static, 1⁄2 or 1⁄3
• Internal LCD bias generation with voltage-follower
buffers
2
GENERAL DESCRIPTION
The PCF8533 is a peripheral device which interfaces to
almost any Liquid Crystal Display (LCD) with low multiplex
rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up
to 80 segments and can easily be cascaded for larger LCD
applications. The PCF8533 is compatible with most
microprocessors/microcontrollers and communicates via a
two-line bidirectional I2C-bus. Communication overheads
are minimized by a display RAM with auto-incremented
addressing, by hardware subaddressing and by display
memory switching (static and duplex drive modes).
• 80 segment drives: up to forty 8-segment numeric
characters; up to twentyone 15-segment alphanumeric
characters; or any graphics of up to 320 elements
• 80 × 4-bit RAM for display data storage
• Auto-incremented display data loading across device
subaddress boundaries
• Display memory bank switching in static and duplex
drive modes
• Versatile blinking modes
• LCD and logic supplies may be separated
• Wide power supply range: from 1.8 to 5.5 V
• Wide LCD supply range: from 2.5 V for low threshold
LCDs and up to 6.5 V for guest-host LCDs and high
threshold (automobile) twisted nematic LCDs
• Low power consumption
• 400 kHz I2C-bus interface
• TTL/CMOS compatible
• Compatible with 4-bit, 8-bit or 16-bit
microprocessors/microcontrollers
• May be cascaded for large LCD applications (up to
5120 segments possible)
• No external components
• Compatible with Chip-On-Glass (COG) technology
• Manufactured in silicon gate CMOS process.
3
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
PCF8533U
−
chip with bumps in tray
−
1999 Jul 30
3
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BP0 BP1 BP2 BP3
S0 to S79
80
V
BACKPLANE
OUTPUTS
LCD
DISPLAY SEGMENT OUTPUTS
DISPLAY REGISTER
LCD
VOLTAGE
SELECTOR
OUTPUT BANK SELECT
AND BLINK CONTROL
DISPLAY
CONTROL
LCD BIAS
GENERATOR
V
SS
DISPLAY
RAM
PCF8533
CLK
BLINKER
CLOCK SELECT
TIMEBASE
AND TIMING
SYNC
COMMAND
DECODE
DATA POINTER AND
AUTO INCREMENT
WRITE DATA
CONTROL
POWER-ON
RESET
OSC
OSCILLATOR
SCL
SDA
2
INPUT
FILTERS
SUBADDRESS
COUNTER
I C-BUS
CONTROLLER
MGL743
A0 A1 A2
SA0
SDAACK
V
DD
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
5
PINNING
SYMBOL
PAD
DESCRIPTION
SDAACK
1
I2C-bus acknowledge output; note 1
I2C-bus serial data input; note 1
I2C-bus serial clock input
external clock input/output
supply voltage
SDA
SCL
CLK
VDD
2 and 3
4 and 5
6
7
SYNC
OSC
8
cascade synchronization input/output
internal oscillator enable input
subaddress inputs
9
A0, A1 and A2
10, 11 and 12
SA0
13
I2C-bus slave address input; bit 0
VSS
14
15
logic ground
VLCD
LCD supply voltage
BP0, BP1, BP2 and BP3
S0 to S79
17, 99, 16 and 98
18 to 97
LCD backplane outputs
LCD segment outputs
Note
1. For most applications SDA and SDAACK will be shorted together; see Chapter 7.
6
FUNCTIONAL DESCRIPTION
The PCF8533 is a versatile peripheral device designed to interface any microprocessor/microcontroller to a wide variety
of LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 80 segments.
The display configurations possible with the PCF8533 depend on the number of active backplane outputs required; a
selection of display configurations is given in Table 1.
All of the display configurations given in Table 1 can be implemented in the typical system shown in Fig.2.
The host microprocessor/microcontroller maintains the 2-line I2C-bus communication channel with the PCF8533.
The internal oscillator is selected by connecting pad OSC to VSS. The appropriate biasing voltages for the multiplexed
LCD waveforms are generated internally. The only other connections required to complete the system are to the power
supplies (VDD, VSS and VLCD) and the LCD panel selected for the application.
Table 1 Selection of display configurations
14-SEGMENTS
ALPHANUMERIC
NUMBER OF
7-SEGMENTS NUMERIC
DOT MATRIX
INDICATOR
DIGITS
INDICATOR
SYMBOLS
BACKPLANES SEGMENTS
CHARACTERS
SYMBOLS
4
3
2
1
320
240
160
80
40
30
20
10
40
30
20
10
20
16
10
5
40
16
20
10
320 dots (4 × 80)
240 dots (3 × 80)
160 dots (2 × 80)
80 dots (1 × 80)
1999 Jul 30
5
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
V
DD
t
r
SDAACK
R
2C
B
V
V
DD
LCD
SDA
SCL
HOST
MICRO-
PROCESSOR/
MICRO-
80 segment drives
4 backplanes
LCD PANEL
PCF8533
(up to 320
elements)
OSC
CONTROLLER
MGL744
A0 A1 A2 SA0
V
SS
V
SS
Fig.2 Typical system configuration.
1999 Jul 30
6
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
6.1
Power-on reset
The biasing configurations that apply to the preferred
modes of operation, together with the biasing
characteristics as functions of VOP and the resulting
discrimination ratios (D), are given in Table 2.
At Power-on the PCF8533 resets to a starting condition as
follows:
1. All backplane outputs are set to VLCD
.
A practical value for VOP is determined by equating Voff(rms)
with a defined LCD threshold voltage (Vth), typically when
the LCD exhibits approximately 10% contrast. In the static
drive mode a suitable choice is VOP > 3Vth.
2. All segment outputs are set to VLCD
3. The drive mode ‘1 : 4 multiplex with 1⁄3bias’ is selected.
.
4. Blinking is switched off.
Multiplex drive ratios of 1 : 3 and 1 : 4 with 1⁄2bias are
possible but the discrimination and hence the contrast
5. Input and output bank selectors are reset (as defined
in Table 5).
6. The I2C-bus interface is initialized.
ratios are smaller ( 3 = 1.732 for 1 : 3 multiplex or
21
7. The data pointer and the subaddress counter are
cleared.
= 1.528 for 1 : 4 multiplex).
----------
3
8. Display disabled.
The advantage of these modes is a reduction of the LCD
full-scale voltage VOP as follows:
Data transfers on the I2C-bus should be avoided for 1 ms
following Power-on to allow completion of the reset action.
• 1 : 3 multiplex (1⁄2bias):
6.2
LCD bias generator
V OP
=
6 × Voff(rms) = 2.449Voff(rms)
Fractional LCD biasing voltages are obtained from an
internal voltage divider of the three series resistors
connected between VLCD and VSS. The centre resistor can
be switched out of the circuit to provide a 1⁄2bias voltage
level for the 1 : 2 multiplex configuration.
• 1 : 4 multiplex (1⁄2bias):
(4 × 3)
VOP
=
= 2.309Voff(rms)
---------------------
3
These compare with VOP = 3Voff(rms) when 1⁄3bias is used.
Note: VOP = VLCD
.
6.3
LCD voltage selector
The LCD voltage selector co-ordinates the multiplexing of
the LCD in accordance with the selected LCD drive
configuration. The operation of the voltage selector is
controlled by MODE SET commands from the command
decoder.
Table 2 Preferred LCD drive modes: summary of characteristics
NUMBER OF
LCD BIAS
Voff(rms)
V on(rms)
V on(rms)
D =
-------------------
VOP
-------------------
VOP
-------------------
Voff(rms)
LCD DRIVE MODE
CONFIGURATION
BACKPLANES LEVELS
static
1 : 2
1 : 2
1 : 3
1 : 4
1
2
2
3
4
2
3
4
4
4
static
0
1
∞
1
⁄
0.354
0.333
0.333
0.333
0.791
0.745
0.638
0.577
2.236
2.236
1.915
1.732
2
1
⁄
3
1
⁄
3
1
⁄
3
1999 Jul 30
7
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
6.4
LCD drive mode waveforms
6.4.1
STATIC DRIVE MODE
The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive
waveforms for this mode are shown in Fig.3.
T
frame
LCD segments
V
LCD
BP0
V
SS
state 1
(on)
state 2
(off)
V
LCD
S
n
V
SS
V
LCD
S
+ 1
n
V
SS
(a) Waveforms at driver.
V
LCD
0 V
state 1
−V
LCD
V
LCD
state 2
0 V
−V
LCD
(b) Resultant waveforms
at LCD segment.
MGL745
Vstate1(t) = Vsn(t) − VBP0(t).
Von(rms) = VLCD
.
Vstate2(t) = Vsn + 1(t) − VBP0(t).
Voff(rms) = 0 V.
Fig.3 Static drive mode waveforms.
8
1999 Jul 30
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
6.4.2
1 : 2 MULTIPLEX DRIVE MODE
When two backplanes are provided in the LCD, the 1 : 2 multiplex mode applies. The PCF8533 allows the use of 1⁄2bias
or 1⁄3bias in this mode as shown in Figs 4 and 5.
T
frame
V
LCD
/2
LCD segments
V
V
BP0
BP1
LCD
SS
state 1
V
LCD
/2
state 2
V
V
LCD
SS
V
LCD
S
n
V
SS
V
LCD
S
+ 1
n
V
SS
(a) Waveforms at driver.
V
LCD
V
/2
LCD
0 V
state 1
−V
/2
LCD
−V
LCD
V
LCD
/2
V
LCD
0 V
state 2
−V
/2
LCD
−V
LCD
(b) Resultant waveforms
at LCD segment.
MGL746
Vstate1(t) = Vsn(t) − VBP0(t).
Von(rms) = 0.791VLCD
Vstate2(t) = Vsn(t) − VBP1(t).
Voff(rms) = 0.354VLCD
.
.
Fig.4 Waveforms for the 1 : 2 multiplex drive mode with 1⁄2bias.
1999 Jul 30
9
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
T
frame
V
LCD
LCD segments
2V
V
/3
LCD
BP0
BP1
/3
LCD
V
SS
state 1
V
LCD
state 2
2V
V
/3
LCD
/3
LCD
V
SS
V
LCD
2V
V
/3
LCD
S
n
/3
LCD
V
SS
V
LCD
2V
V
/3
LCD
S
+ 1
n
/3
LCD
V
SS
(a) Waveforms at driver.
V
LCD
2V
/3
/3
LCD
/3
V
LCD
state 1
0 V
−V
LCD
−2V
/3
LCD
−V
LCD
V
LCD
2V
/3
LCD
V
/3
LCD
0 V
−V
state 2
/3
LCD
−2V
/3
LCD
−V
LCD
(b) Resultant waveforms
at LCD segment.
MGL747
Vstate1(t) = Vsn(t) − VBP0(t).
Von(rms) = 0.745VLCD
Vstate2(t) = Vsn(t) − VBP1(t).
Voff(rms) = 0.333VLCD
.
.
Fig.5 Waveforms for the 1 : 2 multiplex drive mode with 1⁄3bias.
6.4.3
1 : 3 MULTIPLEX DRIVE MODE
When three backplanes are provided in the LCD, the 1 : 3 multiplex drive mode applies, as shown in Fig.6.
1999 Jul 30
10
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
T
frame
V
LCD
LCD segments
2V
V
/3
LCD
/3
BP0
BP1
BP2
LCD
V
SS
state 1
state 2
V
LCD
2V
V
/3
LCD
/3
LCD
V
SS
V
LCD
2V
V
/3
LCD
/3
LCD
V
SS
V
LCD
2V
V
/3
LCD
S
n
/3
LCD
V
SS
V
LCD
2V
V
/3
LCD
S
+ 1
+ 2
n
n
/3
LCD
V
SS
V
LCD
2V
V
/3
LCD
S
/3
LCD
V
SS
(a) Waveforms at driver.
V
LCD
2V
V
/3
/3
LCD
/3
LCD
state 1
0 V
−V
LCD
−2V
/3
LCD
−V
LCD
V
LCD
2V
/3
LCD
V
/3
LCD
0 V
−V
state 2
/3
LCD
−2V
−V
/3
LCD
LCD
(b) Resultant waveforms
at LCD segment.
MGL748
Vstate1(t) = Vsn(t) − VBP0(t).
Von(rms) = 0.638VLCD
Vstate2(t) = Vsn(t) − VBP1(t).
Voff(rms) = 0.333VLCD
.
.
Fig.6 Waveforms for the 1 : 3 multiplex drive mode.
6.4.4
1 : 4 MULTIPLEX DRIVE MODE
When four backplanes are provided in the LCD, the 1 : 4 multiplex drive mode applies, as shown in Fig.7.
1999 Jul 30
11
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
T
frame
V
LCD segments
LCD
2V
V
/3
LCD
BP0
BP1
BP2
BP3
/3
LCD
V
SS
state 1
state 2
V
LCD
2V
/3
LCD
V
/3
LCD
V
SS
V
LCD
2V
V
/3
LCD
/3
LCD
V
SS
V
LCD
2V
/3
LCD
V
/3
LCD
V
SS
V
LCD
2V
V
/3
LCD
S
n
/3
LCD
V
SS
V
LCD
2V
/3
LCD
S
+ 1
n
V
/3
LCD
V
SS
V
LCD
2V
V
/3
LCD
S
S
+ 2
n
/3
LCD
V
SS
V
LCD
2V
V
/3
LCD
+ 3
n
/3
LCD
V
SS
(a) Waveforms at driver.
V
LCD
2V
V
/3
/3
LCD
/3
LCD
state 1
0 V
−V
LCD
−2V
/3
LCD
−V
LCD
V
LCD
2V
/3
LCD
V
/3
LCD
0 V
−V
state 2
/3
LCD
−2V
−V
/3
LCD
LCD
(b) Resultant waveforms
at LCD segment.
MGL749
Vstate1(t) = Vsn(t) − VBP0(t): Von(rms) = 0.577VLCD
.
.
Vstate2(t) = Vsn(t) − VBP1(t): Voff(rms) = 0.333VLCD
Fig.7 Waveforms for the 1 : 4 multiplex drive mode.
12
1999 Jul 30
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
6.5
Oscillator
6.8
Segment outputs
6.5.1
INTERNAL CLOCK
The LCD drive section includes 80 segment outputs
(S0 to S79) which should be connected directly to the
LCD. The segment output signals are generated in
accordance with the multiplexed backplane signals and
with data resident in the display latch. When less than
80 segment outputs are required the unused segment
outputs should be left open-circuit.
The internal logic and the LCD drive signals of the
PCF8533 are timed either by the built-in oscillator or from
an external clock. When the internal oscillator is used, pad
OSC should be connected to VSS. In this event, the output
from pad CLK provides the clock signal for cascaded
PCF8533s in the system. After power-up, SDA must be
HIGH to guarantee that the clock starts.
6.9
Backplane outputs
6.5.2
EXTERNAL CLOCK
The LCD drive section includes four backplane outputs
BP0 to BP3 which should be connected directly to the
LCD. The backplane output signals are generated in
accordance with the selected LCD drive mode. If less than
four backplane outputs are required the unused outputs
can be left open-circuit. In the 1 : 3 multiplex drive mode
BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced
drive capabilities. In the 1 : 2 multiplex drive mode
BP0 and BP2, BP1 and BP3 respectively carry the same
signals and may also be paired to increase the drive
capabilities. In the static drive mode the same signal is
carried by all four backplane outputs and they can be
connected in parallel for very high drive requirements.
The condition for external clock is made by tying pad OSC
to VDD; pad CLK then becomes the external clock input.
The clock frequency (fCLK) determines the LCD frame
frequency.
A clock signal must always be supplied to the device;
removing the clock may freeze the LCD in a DC state.
6.6
Timing
The timing of the PCF8533 organizes the internal data flow
of the device. This includes the transfer of display data
from the display RAM to the display segment outputs.
In cascaded applications, the synchronization signal
(SYNC) maintains the correct timing relationship between
the PCF8533s in the system. The timing also generates
the LCD frame frequency which it derives as an integer
division of the clock frequency (see Table 3). The frame
frequency is a fixed division of the internal clock or of the
frequency applied to pad CLK when an external clock is
used.
6.10 Display RAM
The display RAM is a static 80 × 4-bit RAM which stores
LCD data. A logic 1 in the RAM bit map indicates the
on-state of the corresponding LCD segment; similarly, a
logic 0 indicates the off-state. There is a one-to-one
correspondence between the RAM addresses and the
segment outputs, and between the individual bits of a RAM
word and the backplane outputs. The first RAM column
corresponds to the 80 segments operated with respect to
backplane BP0 (see Fig.8). In multiplexed LCD
6.7
Display register
The display latch holds the display data while the
corresponding multiplex signals are generated. There is a
one-to-one relationship between the data in the display
latch, the LCD segment outputs and one column of the
display RAM.
applications the segment data of the second, third and
fourth column of the display RAM are time-multiplexed
with BP1, BP2 and BP3 respectively.
1999 Jul 30
13
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
When display data is transmitted to the PCF8533 the
display bytes received are stored in the display RAM in
accordance with the selected LCD drive mode. The data is
stored as it arrives and does not wait for the acknowledge
cycle as with the commands. Depending on the current
mux mode data is stored singularly, in pairs, triplets or
quadruplets. e.g. in 1 : 2 mux mode the RAM data is stored
every second bit. To illustrate the filling order, an example
of a 7-segment numeric display showing all drive modes is
given in Fig.9; the RAM filling organization depicted
applies equally to other LCD types. With reference to
Fig.9, in the static drive mode the eight transmitted data
bits are placed in bit 0 of eight successive display RAM
addresses. In the 1 : 2 multiplex drive mode the eight
transmitted data bits are placed in bits 0 and 1 of four
successive display RAM addresses.
In the 1 : 3 multiplex drive mode these bits are placed in
bits 0, 1 and 2 of three successive addresses, with bit 2 of
the third address left unchanged. This last bit may, if
necessary, be controlled by an additional transfer to this
address but care should be taken to avoid overriding
adjacent data because full bytes are always transmitted.
In the 1 : 4 multiplex drive mode the eight transmitted data
bits are placed in bits 0, 1, 2 and 3 of two successive
display RAM addresses.
Table 3 LCD frame frequencies
NOMINAL FRAME
FRAME FREQUENCY
FREQUENCY (Hz)
64
fCLK
----------
24
display RAM addresses (rows) / segment outputs (S)
h
0
1
2
3
4
75 76 77 78 79
0
1
2
3
display RAM bits
(columns) /
backplane outputs
(BP)
MGL750
Fig.8 Display RAM bit map showing direct relationship between display RAM addresses and segment outputs,
and between bits in a RAM word and backplane outputs.
1999 Jul 30
14
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
6.11 Data pointer
6.13 Output bank selector
The addressing mechanism for the display RAM is
realized using the data pointer. This allows the loading of
an individual display data byte, or a series of display data
bytes, into any location of the display RAM. The sequence
commences with the initialization of the data pointer by the
LOAD DATA POINTER command. Following this, an
arriving data byte is stored starting at the display RAM
address indicated by the data pointer thereby observing
the filling order shown in Fig.9. The data pointer is
automatically incremented in accordance with the chosen
LCD configuration. That is, after each byte is stored, the
contents of the data pointer are incremented by eight
(static drive mode), by four (1 : 2 multiplex drive mode), by
three (1 : 3 multiplex drive mode) or by two (1 : 4 multiplex
drive mode). If an I2C-bus data access is terminated early
then the state of the data pointer will be unknown. The data
The output bank selector selects one of the four bits per
display RAM address for transfer to the display latch.
The actual bit selected depends on the particular LCD
drive mode in operation and on the instant in the multiplex
sequence.
In 1 : 4 multiplex, all RAM addresses of bit 0 are selected,
these are followed by the contents of bit 1, bit 2 and then
bit 3. Similarly in 1 : 3 multiplex, bits 0, 1 and 2 are
selected sequentially. In 1 : 2 multiplex, bits 0 and 1 are
selected and, in the static mode, bit 0 is selected.
The SYNC signal will reset these sequences to the
following starting points; bit 3 for 1 : 4 multiplex, bit 2 for
1 : 3 multiplex, bit 1 for 1 : 2 multiplex and bit 0 for static
mode.
The PCF8533 includes a RAM bank switching feature in
pointer should be re-written prior to further RAM accesses. the static and 1 : 2 multiplex drive modes. In the static
drive mode, the BANK SELECT command may request
6.12 Subaddress counter
the contents of bit 2 to be selected for display instead of
the contents of bit 0. In the 1 : 2 drive mode, the contents
of bits 2 and 3 may be selected instead of bits 0 and 1.
This gives the provision for preparing display information
in an alternative bank and to be able to switch to it once it
is assembled.
The storage of display data is conditioned by the contents
of the subaddress counter. Storage is allowed to take
place only when the contents of the subaddress counter
agree with the hardware subaddress applied to
A0, A1 and A2. The subaddress counter value is defined
by the DEVICE SELECT command. If the contents of the
subaddress counter and the hardware subaddress do not
agree then data storage is inhibited but the data pointer is
incremented as if data storage had taken place.
The subaddress counter is also incremented when the
data pointer overflows.
6.14 Input bank selector
The input bank selector loads display data into the display
RAM in accordance with the selected LCD drive
configuration. Display data can be loaded in bit 2 in static
drive mode or in bits 2 and 3 in 1 : 2 drive mode by using
The storage arrangements described lead to extremely
efficient data loading in cascaded applications. When a
series of display bytes are sent to the display RAM,
automatic wrap-over to the next PCF8533 occurs when
the last RAM address is exceeded. Subaddressing across
device boundaries is successful even if the change to the
next device in the cascade occurs within a transmitted
character (such as during the 27th display data byte
transmitted in 1 : 3 multiplex mode).
The hardware subaddress should not be changed whilst
the device is being accessed on the I2C-bus interface.
1999 Jul 30
15
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
the BANK SELECT command. The input bank selector
functions independently to the output bank selector.
An additional feature is for an arbitrary selection of LCD
segments to be blinked. This applies to the static and
1 : 2 LCD drive modes and can be implemented without
any communication overheads. By means of the output
bank selector, the displayed RAM banks are exchanged
with alternate RAM banks at the blinking frequency. This
mode can also be specified by the BLINK command.
6.15 Blinker
The display blinking capabilities of the PCF8533 are very
versatile. The whole display can be blinked at frequencies
selected by the BLINK command. The blinking frequencies
are integer multiples of the clock frequency. The ratios
between the clock and blinking frequencies depend on the
mode in which the device is operating, see Table 4.
In the 1 : 3 and 1 : 4 multiplex modes, where no alternate
RAM bank is available, groups of LCD segments can be
blinked by selectively changing the display RAM data at
fixed time intervals.
If the entire display is to be blinked at a frequency other than the nominal blinking frequency, this can be effectively
performed by resetting and setting the display enable bit E at the required rate using the MODE SET command.
Table 4 Blinking frequencies
NORMAL OPERATING MODE
BLINKING MODE
NOMINAL BLINKING FREQUENCY
RATIO
Off
−
blinking off
2 Hz
2 Hz
fCLK
----------
768
1 Hz
1 Hz
f CLK
------------
1536
0.5 Hz
0.5 Hz
f CLK
------------
3072
1999 Jul 30
16
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drive mode
LCD segments
LCD backplanes
display RAM filling order
transmitted display byte
a
S
2
n
n
1
n
2
n
3
n
4
n
5
n
6
n 7
n
n
b
BP0
f
S
1
7
S
3
MSB
LSB
DP
n
n
0
1
2
3
c
x
x
x
b
x
x
x
a
x
x
x
f
g
x
x
x
e
x
x
x
d
x
x
x
DP
bit/
BP
g
4
S
S
S
n
n
x
x
x
x
x
x
c
b
a
f
g e d
static
e
S
5
6
c
n
d
DP
S
n
BP0
S
n
a
n
n
n
n
1
1
1
n
2
n 3
b
b
b
1 : 2
f
S
1
n
MSB
LSB
DP
0
1
2
3
a
b
x
x
f
e
c
x
x
d
bit/
BP
g
g
x
x
DP
x
x
a
b
f
g
e c d
BP1
S
S
e
2
3
multiplex
n
n
c
c
c
d
d
d
DP
BP0
BP1
S
1
a
n
n
n 2
S
S
2
f
1 : 3
n
n
MSB
LSB
e
0
1
2
3
b
DP
c
a
d
g
x
f
bit/
BP
g
e
x
x
BP2
b DP
c
a
d
g
f
e
multiplex
x
DP
S
n
a
n
BP2
BP3
BP0
BP1
f
1 : 4
0
1
2
3
a
c
f
bit/
BP
MSB
LSB
d
g
e
g
d
b
DP
e
multiplex
a
c
b
DP
f
e
g
S
1
DP
n
MGL751
X = data bit unchanged.
Fig.9 Relationships between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus.
ahdnbok,uflapegwidt
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
CHARACTERISTICS OF THE I2C-BUS
7.4
Acknowledge
7
The I2C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are a
Serial Data line (SDA) and a Serial Clock Line (SCL). Both
lines must be connected to a positive supply via a pull-up
resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not
busy.
The number of data bytes transferred between the START
and STOP conditions from transmitter to receiver is
unlimited. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH level
signal put on the bus by the transmitter during which time
the master generates an extra acknowledge related clock
pulse. A slave receiver which is addressed must generate
an acknowledge after the reception of each byte. Also a
master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the
slave transmitter. The device that acknowledges must
pull-down the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse (set-up and
hold times must be taken into consideration). A master
receiver must signal an end of data to the transmitter by
not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event the transmitter
must leave the data line HIGH to enable the master to
generate a STOP condition. Acknowledgement on the
I2C-bus is illustrated in Fig.13.
By connecting SDAACK to SDA on the PCF8533, the SDA
line becomes fully I2C-bus compatible. Having the
acknowledge output separated from the serial data line is
advantageous in Chip-On-Glass (COG) applications.
In COG applications where the track resistance from the
SDAACK pad to the system SDA line can be significant, a
potential divider is generated by the bus pull-up resistor
and the Indium Tin Oxide (ITO) track resistance. It is
possible that during the acknowledge cycle the PCF8533
will not be able to create a valid logic 0 level. By splitting
the SDA input from the output the device could be used in
a mode that ignores the acknowledge bit. In COG
applications where the acknowledge cycle is required, it is
necessary to minimize the track resistance from the
SDAACK pad to the system SDA line to guarantee a valid
low level.
7.5
PCF8533 I2C-bus controller
The PCF8533 acts as an I2C-bus slave receiver. It does
not initiate I2C-bus transfers or transmit data to an I2C-bus
master receiver. The only data output from the PCF8533
are the acknowledge signals of the selected devices.
Device selection depends on the I2C-bus slave address,
on the transferred command data and on the hardware
subaddress.
The following definition assumes SDA and SDAACK are
connected and refers to the pair as SDA.
7.1
Bit transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as a control signal. Bit
transfer is illustrated in Fig.10.
In single device application, the hardware subaddress
inputs A0, A1 and A2 are normally tied to VSS which
defines the hardware subaddress 0. In multiple device
applications A0, A1 and A2 are tied to VSS or VDD in
accordance with a binary coding scheme such that no two
devices with a common I2C-bus slave address have the
same hardware subaddress.
7.2
START and STOP conditions
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the STOP condition (P). The START
and STOP conditions are illustrated in Fig.11.
7.6
Input filters
To enhance noise immunity in electrically adverse
environments, RC low-pass filters are provided on the
SDA and SCL lines.
7.3
System configuration
A device generating a message is a ‘transmitter’, a device
receiving a message is the ‘receiver’. The device that
controls the message is the ‘master’ and the devices which
are controlled by the master are the ‘slaves’. The system
configuration is illustrated in Fig.12.
1999 Jul 30
18
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
I2C-bus protocol
In this way it is possible to configure the device then fill the
display RAM with little overhead.
7.7
Two I2C-bus slave addresses (01110000 and 01110010)
are reserved for the PCF8533. The least significant bit of
the slave address that a PCF8533 will respond to is
defined by the level tied at its input SA0. The PCF8533 is
a write only device and will not respond to a read access.
Therefore, two types of PCF8533 can be distinguished on
the same I2C-bus which allows:
The command bytes and control bytes are also
acknowledged by all addressed PCF8533s connected to
the bus.
The display bytes are stored in the display RAM at the
address specified by the data pointer and the subaddress
counter. Both data pointer and subaddress counter are
automatically updated and the data is directed to the
intended PCF8533 device.
1. Up to 16 PCF8533s on the same I2C-bus for very large
LCD applications
2. The use of two types of LCD multiplex on the same
I2C-bus.
The acknowledgement after each byte is made only by the
(A0, A1 and A2) addressed PCF8533. After the last
display byte, the I2C-bus master issues a STOP
condition (P). Alternatively a START may be issued to
RESTART an I2C-bus access.
The I2C-bus protocol is shown in Fig.14. The sequence is
initiated with a START condition (S) from the I2C-bus
master which is followed by one of the two PCF8533 slave
addresses available. All PCF8533s with the corresponding
SA0 level acknowledge in parallel to the slave address, but
all PCF8533s with the alternative SA0 level ignore the
whole I2C-bus transfer.
7.8
Command decoder
The command decoder identifies command bytes that
arrive on the I2C-bus. The five commands available to the
PCF8533 are defined in Table 5.
After acknowledgement, a control byte follows which
defines if the next byte is RAM or command information.
The control byte also defines if the next following byte is a
control byte or further RAM/command data.
SDA
SCL
data line
stable;
data valid
change
of data
allowed
MBA607
Fig.10 Bit transfer.
1999 Jul 30
19
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
SDA
SDA
SCL
SCL
S
P
STOP condition
START condition
MBC622
Fig.11 Definition of START and STOP conditions.
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER
SDA
SCL
MGA807
Fig.12 System configuration.
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
8
SCL FROM
MASTER
1
2
9
S
clock pulse for
acknowledgement
START
condition
MBC602
Fig.13 Acknowledgement on the I2C-bus.
20
1999 Jul 30
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R/W = 0
slave address
control byte
A CoRS
0
RAM/command byte
S
A
0
M
S
B
L
S
B
S
0
1
1
1
0
0
P
A
EXAMPLES
a) transmit two bytes of RAM data
S
A
S
0
1
1
1
0
0
0
0
1
1
0
A
0
A
A
A
RAM DATA
COMMAND
COMMAND
A
A
A
RAM DATA
A
A
A
P
b) transmit two command bytes
S
A
S
0
1
1
1
0
0
0
0
0
0
1
A
0
COMMAND
RAM DATA
A
A
P
c) transmit one command byte and two RAM bytes
S
A
1 0
S
0
1
1
1
0
0
0
A
0
RAM DATA
A P
MGL752
Fig.14 I2C-bus protocol.
MSB
Co RS
LSB
UNUSED
MGL753
Co = 0; last control byte.
Co = 1; control bytes continue.
RS = 0; data is a command byte
RS = 1; data is a display byte
Fig.15 Format of control byte.
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
Table 5 Definition of PCF8533 commands
COMMAND
OPCODE
OPTIONS
M1 M0 Table 6
DESCRIPTION
defines LCD drive mode
MODE SET
1
1
0
0
E
B
Table 7
Table 8
defines LCD bias configuration
defines display status; the possibility to
disable the display allows implementation of
blinking under external control
LOADDATA
POINTER
0
1
1
P6 P5 P4 P3 P2 P1 P0 Table 9
seven bits of immediate data, bits P6 to P0,
are transferred to the data pointer to define
one of eighty display RAM addresses
DEVICE
SELECT
1
1
1
1
0
1
0
1
A2 A1 A0 Table 10
three bits of immediate data, bits A0 to A3,
are transferred to the subaddress counter to
define one of eight hardware subaddresses
BANK
SELECT
0
I
O
Table 11
Table 12
defines input bank selection (storage of
arriving display data)
defines output bank selection (retrieval of
LCD display data); the BANK SELECT
command has no effect in 1 : 3 and 1 : 4
multiplex drive modes
BLINK
1
1
1
1
0
A
BF BF Table 13
defines the blinking frequency
1
0
Table 14
selects the blinking mode; normal operation
with frequency set by BF1, BF0 or blinking by
alternation of display RAM banks. Alternation
blinking does not apply in 1 : 3 and 1 : 4
multiplex drive modes
Table 6 Mode set option 1
LCD DRIVE MODE
BITS
DRIVE MODE
BACKPLANE
M1
M0
Static
1 : 2
1 : 3
1 : 4
1 BP
0
1
1
0
1
0
1
0
MUX (2 BP)
MUX (3 BP)
MUX (4 BP)
Table 7 Mode set option 2
LCD BIAS
BIT B
1⁄3bias
1⁄2bias
0
1
Table 8 Mode set option 3
DISPLAY STATUS
BIT E
Disabled (blank)
Enabled
0
1
1999 Jul 30
22
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
Table 9 Load data pointer option 1
7.10 Cascaded operation
In large display configurations, up to 16 PCF8533s can be
distinguished on the same I2C-bus by using the 3-bit
hardware subaddress (A0, A1 and A2) and the
DESCRIPTION
BITS
P6 P5 P4 P3 P2 P1 P0
7 bit binary value of
0 to 79
programmable I2C-bus slave address (SA0). When
cascaded PCF8533s are synchronized they can share the
backplane signals from one of the devices in the cascade.
Such an arrangement is cost-effective in large LCD
applications since the backplane outputs of only one
device need to be through-plated to the backplane
electrodes of the display. The other PCF8533s of the
cascade contribute additional segment outputs but their
backplane outputs are left open-circuit (see Fig.16).
Table 10 Device select option 1
DESCRIPTION
BITS
3 bit binary value of 0 to 7
A2
A1
A0
Table 11 Bank select option 1 (Input)
STATIC
RAM bit 0
RAM bit 2
1 : 2 MUX
BIT I
The SYNC line is provided to maintain the correct
synchronization between all cascaded PCF8533s. This
synchronization is guaranteed after the Power-on reset.
The only time that SYNC is likely to be needed is if
synchronization is accidentally lost (e.g. by noise in
adverse electrical environments, or by the definition of a
multiplex mode when PCF8533s with different SA0 levels
are cascaded). SYNC is organized as an input/output pad;
the output selection being realized as an open-drain driver
with an internal pull-up resistor. A PCF8533 asserts the
SYNC line at the onset of its last active backplane signal
and monitors the SYNC line at all other times. Should
synchronization in the cascade be lost, it will be restored
by the first PCF8533 to assert SYNC. The timing
relationship between the backplane waveforms and the
SYNC signal for the various drive modes of the PCF8533
are shown in Fig.17.
RAM bits 0 and 1
RAM bits 2 and 3
0
1
Table 12 Bank select option 2 (Output)
STATIC
RAM bit 0
RAM bit 2
1 : 2 MUX
BIT O
RAM bits 0 and 1
RAM bits 2 and 3
0
1
Table 13 Blink option 1
BLINK FREQUENCY
BITS
BF1
BF0
Off
0
0
1
1
0
1
0
1
2 Hz
1 Hz
0.5 Hz
The contact resistance between the SYNC pads of
cascaded devices must be controlled. If the resistance is
too high then the device will not be able to synchronize
properly. This is particularly applicable to COG
applications. Table 15 shows the limiting values for
contact resistance.
Table 14 Blink option 2
BLINK MODE
Normal blinking(1)
BIT A
0
1
Alternation blinking
Table 15 SYNC contact resistance
Note
MAXIMUM CONTACT
NUMBER OF DEVICES
RESISTANCE
1. Normal blinking is assumed when multiplex rates 1 : 3
or 1 : 4 are selected.
2
6000 Ω
2200 Ω
1200 Ω
700 Ω
3 to 5
7.9
Display controller
6 to 10
11 to 16
The display controller executes the commands identified
by the command decoder. It contains the status registers
of the PCF8533 and co-ordinates their effects.
The controller is also responsible for loading display data
into the display RAM as required by the filling order.
1999 Jul 30
23
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
SDAACK
V
V
LCD
DD
SDA
SCL
80 segment drives
LCD PANEL
SYNC
CLK
PCF8533
(up to 5120
elements)
OSC
BP0 to BP3
(open-circuit)
A0 A1 A2 SA0 V
SS
V
V
LCD
t
DD
SDAACK
r
R
2C
V
V
LCD
DD
B
SDA
SCL
HOST
MICRO-
PROCESSOR/
MICRO-
CONTROLLER
80 segment drives
SYNC
PCF8533
4 backplanes
BP0 to BP3
CLK
OSC
MGL754
A0 A1 A2 SA0
V
V
SS
SS
Fig.16 Cascaded PCF8533 configuration.
24
1999 Jul 30
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
1
T
= f
frame
frame
BP0
SYNC
(a) static drive mode.
BP1
(1/2 bias)
BP1
(1/3 bias)
SYNC
(b) 1 : 2 multiplex drive mode.
BP2
SYNC
(c) 1 : 3 multiplex drive mode.
BP3
SYNC
MGL755
(d) 1 : 4 multiplex drive mode.
Fig.17 Synchronization of the cascade for the various PCF8533 drive modes.
25
1999 Jul 30
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
8
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER
VDD
MIN.
−0.5
−50
MAX.
UNIT
supply voltage
+6.5
V
IDD
supply current
+50
mA
V
VLCD
ILCD
ISS
LCD supply voltage
LCD supply current
negative supply current
VSS − 0.5
+7.5
−50
−50
+50
mA
mA
V
+50
VI(n)
input voltage on pads SDA, SCL, CLK, SYNC, SA0, OSC
and A0 to A2
V
SS − 0.5
VDD + 0.5
VO(n)
II
output voltage on pads S0 to S79 and BP0 to BP3
DC input current
V
SS − 0.5
VLCD + 0.5
+10
V
−10
−10
−
mA
mA
mW
mW
°C
IO
DC output current
+10
Ptot
P/out
Tstg
total power dissipation
400
power dissipation per output
storage temperature
−
100
−65
+150
9
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices”).
1999 Jul 30
26
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
10 DC CHARACTERISTICS
VDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.5 to 6.5 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
Supplies
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDD
VLCD
IDD
supply voltage
1.8
2.5
−
−
8
5.5
V
V
LCD supply voltage
supply current
6.5
20
60
fCLK = 1536 Hz; note 1 −
fCLK = 1536 Hz; note 1 −
µA
µA
ILCD
LCD supply current
24
Logic
VIL
LOW-level input voltage
HIGH-level input voltage
VSS
0.7VDD
VOL = 0.4 V; VDD = 5 V 1
−
−
−
0.3VDD
VDD
−
V
VIH
IOL1
V
LOW-level output current on pads
CLK and SYNC
mA
IOH1
HIGH-level output current pad CLK
VOH = 4.6 V;
VDD = 5 V
−1
−
−
mA
IOL2
IL1
LOW-level output current pad SDA
VOL = 0.4 V; VDD = 5 V 3
−
−
−
mA
leakage current on pads SA0,
A0 to A2, CLK, SDA and SCL
VI = VDD or VSS
−1
+1
µA
IL2
leakage current pad OSC
Power-on reset voltage level
input capacitance
VI = VDD
−1
1.0
−
−
+1
1.6
7
µA
V
VPOR
CI
1.3
−
note 2
pF
LCD outputs
VBP
DC voltage component on pads
BP0 to BP3
CBP = 35 nF
CS = 5 nF
−100
−100
−
−
+100
+100
mV
mV
VS
DC voltage component on pads
S0 to S79
RBP
RS
output resistance at pads BP0 to BP3 VLCD = 5 V; note 3
output resistance at pads S0 to S79 VLCD = 5 V; note 3
−
−
1.5
6.0
10
kΩ
kΩ
13.5
Notes
1. LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50% duty factor; I2C-bus inactive.
2. Not tested; given by design.
3. Outputs measured one at a time.
1999 Jul 30
27
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
11 AC CHARACTERISTICS
VDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.5 to 6.5 V; Tamb = −40 to + 85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
797
TYP. MAX. UNIT
fCLK
oscillator frequency at pad CLK
input CLK HIGH time
VDD = 5 V; note 1
1536 3046 Hz
tCLKH
tCLKL
130
130
−
−
−
µs
µs
ns
µs
µs
input CLK LOW time
−
−
td(p)SYNC SYNC propagation delay time
30
−
−
tSYNCL
SYNC LOW time
1
−
td(PLCD)
driver delays with test loads
VLCD = 5 V
−
−
30
Timing characteristics: I2C-bus; note 2
fSCL
SCL clock frequency
−
−
−
−
−
−
−
−
−
−
−
−
−
−
400
−
kHz
µs
µs
µs
µs
µs
µs
µs
pF
ns
ns
µs
ns
tBUF
bus free time between a STOP and START
START condition hold time
set-up time for a repeated START condition
SCL LOW time
1.3
0.6
0.6
1.3
0.6
−
tHD;STA
tSU;STA
tLOW
tHIGH
tr
−
−
−
SCL HIGH time
−
SCL and SDA rise time
SCL and SDA fall time
0.3
0.3
400
−
tf
−
Cb
capacitive bus line load
data set-up time
−
tSU;DAT
tHD;DAT
tSU;STO
tSW
100
0
data hold time
−
set-up time for STOP condition
tolerable spike width on bus
0.6
−
−
50
Notes
1. Typical output duty cycle of 50%.
2. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to
VIL and VIH with an input voltage swing of VSS to VDD
.
6.8 Ω
SYNC
CLK
V
DD
(2%)
3.3 kΩ
1.5 kΩ
SDA,
SCL
0.5V
V
DD
DD
(2%)
(2%)
1 nF
BP0 to BP3, and
S0 to S79
V
SS
MGS120
Fig.18 Test loads.
28
1999 Jul 30
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
1/ f
CLK
t
t
CLKL
CLKH
0.7V
0.3V
DD
CLK
DD
0.7V
0.3V
DD
SYNC
DD
t
t
d(p)(SYNC)
d(p)(SYNC)
t
SYNCL
0.5 V
BP0 to BP3,
and S0 to S79
(V
= 5 V)
DD
0.5 V
t
MGL761
PLCD
Fig.19 Driver timing waveforms.
d
SDA
SCL
t
t
t
f
BUF
LOW
t
t
t
SU;DAT
t
HD;STA
r
t
HIGH
HD;DAT
SDA
t
SU;STA
MGA728
t
SU;STO
Fig.20 I2C-bus timing waveforms.
29
1999 Jul 30
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
12 BONDING PAD LOCATIONS
Bonding pad locations (dimensions in µm)
All x and y coordinates are referenced to centre of chip
(see Fig.22).
SYMBOL
PAD
x
y
SYMBOL
PAD
x
y
SDAACK
SDA
SDA
SCL
SCL
CLK
VDD
SYNC
OSC
A0
1
−1079.20
−839.20
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
S54
S55
S56
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
+1717.60
+1637.60
+1557.60
+1477.60
+1317.60
+1237.60
+1157.60
+1077.60
+997.60
+917.60
+837.60
+757.60
+677.60
+597.60
+437.60
+357.60
+277.60
+197.60
+117.60
+37.60
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
2
3
−759.20
4
−599.20
5
−519.20
6
−414.80
7
−284.80
8
+4.20
9
+119.20
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
+249.20
A1
+379.20
A2
+581.20
SA0
VSS
VLCD
BP2
BP0
S0
+711.20
+841.20
+1099.60
+1277.60
+1357.60
+1437.60
+1517.60
+1597.60
+1677.60
+1757.60
+1837.60
+1917.60
+1997.60
+2077.60
+2157.60
+2237.60
+2317.60
+2357.60
+2277.60
+2197.60
+2117.60
+2037.60
+1957.60
+1877.60
+1797.60
S1
S2
S3
−42.40
S4
−122.40
−202.40
−282.40
−362.40
−442.40
−602.40
−682.40
−762.40
−842.40
−922.40
−1002.40
−1082.40
−1162.40
−1242.40
−1322.40
−1402.40
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
1999 Jul 30
30
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
SYMBOL
PAD
x
y
SYMBOL
PAD
x
y
S57
S58
S59
S60
S61
S62
S63
S64
S65
S66
S67
S68
S69
S70
S71
S72
S73
S74
S75
S76
S77
S78
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
−1562.40
−1642.40
−1722.40
−1802.40
−1882.40
−1962.40
−2042.40
−2122.40
−2202.40
−2282.40
−2362.40
−2322.40
−2242.40
−2162.40
−2082.40
−2002.40
−1922.40
−1842.40
−1762.40
−1682.40
−1602.40
−1522.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
+594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
S79
BP3
BP1
97
98
99
−1442.40
−1362.40
−1282.40
−594.40
−594.40
−594.40
Alignment marks
C1
C2
F
−
−
−
+2300.5
−2320.2
−2208.3
+55.0
+107.0
−165.4
Dummy pads (connected to segments shown; note
D1
D2
D3
D4
D5
D6
D7
D8
(S11)
(S11)
(S12)
(S12)
(S67)
(S67)
(S68)
(S68)
+2469.70
+2549.70
+2517.60
+2437.60
−2442.30
−2522.30
−2554.40
−2474.40
−594.40
−594.40
+594.40
+594.40
+594.40
+594.40
−594.40
−594.40
Chip corners (pre-sawing)
Bottom left
Top right
−
−
−2695.00
−750.00
+2695.00
+750.00
Note
1. The dummy pads are not tested.
handbook, halfpage
REF
REF
C1
C2
MGL756
REF
F
Fig.21 Alignment markers.
31
1999 Jul 30
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PC8533-2
y
C
F
C
1
2
x
0,0
MGL759
The position of the bonding pads is not to scale.
Chip dimensions: approximately 5.40 × 1.51 mm.
Bump dimensions: 90 × 50 × 17.5 µm.
Wafer thickness: 381 µm.
Fig.22 Bonding pad locations.
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
13 DEVICE PROTECTION
V
V
V
DD
DD
SA0
V
SS
SS
V
DD
CLK
SCL
V
SS
V
DD
V
SS
OSC
V
V
SS
SDA
DD
SYNC
V
V
V
SS
SS
DD
A0, A1 A2
SDAACK
V
V
SS
LCD
V
BP0, BP1,
BP2, BP3
SS
V
V
SS
V
LCD
LCD
S0 to S79
V
V
SS
SS
MGL760
Fig.23 Device protection diagram.
33
1999 Jul 30
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
14 TRAY INFORMATION
x
A
C
y
D
B
F
E
MGL757
The dimensions are given in Table 16.
Fig.24 Tray details.
Table 16 Dimensions
DIM.
DESCRIPTION
VALUE
A
B
C
D
E
F
x
pocket pitch, x direction
pocket pitch, y direction
pocket width, x direction
pocket width, y direction
tray width, x direction
7.37 mm
3.68 mm
5.50 mm
1.60 mm
50.8 mm
50.8 mm
6
handbook, halfpage
tray width, y direction
no. pockets in x direction
no. pockets in y direction
PC8533-2
y
12
MGL758
The orientation of the IC in a pocket is indicated by the position of the
IC type name on the die surface with respect to the chamfer on the
upper left corner of the tray. Refer to the bonding pad location
diagram for the orientating and position of the type name on the die
surface.
Fig.25 Tray alignment.
1999 Jul 30
34
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
15 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
16 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
17 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
18 BARE DIE DISCLAIMER
All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of
ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately
indicated in the data sheet. There is no post waffle pack testing performed on individual die. Although the most modern
processes are utilized for wafer sawing and die pick and place into waffle pack carriers, Philips Semiconductors has no
control of third party procedures in the handling, packing or assembly of the die. Accordingly, Philips Semiconductors
assumes no liability for device functionality or performance of the die or systems after handling, packing or assembly of
the die. It is the responsibility of the customer to test and qualify their application in which the die is used.
1999 Jul 30
35
Philips Semiconductors – a worldwide company
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5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1999
SCA67
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
465006/02/pp36
Date of release: 1999 Jul 30
Document order number: 9397 750 05045
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IC LIQUID CRYSTAL DISPLAY DRIVER, PDSO80, 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80, Display Driver
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