PHK04P02T [NXP]

P-channel enhancement mode MOS transistor; P沟道增强型MOS晶体管


型号：	PHK04P02T
厂家：	NXP
描述：	P-channel enhancement mode MOS transistor P沟道增强型MOS晶体管晶体晶体管
文件：	总7页 (文件大小：111K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Philips Semiconductors

Product specification

P-channel enhancement mode

MOS transistor

PHK04P02T

FEATURES

SYMBOL

QUICK REFERENCE DATA

• Very low threshold voltage

• Fast switching

V_DS= -16 V

• Logic level compatible

• Surface mount package

I_D= -4.66 A

_DS(ON)≤ 0.15 Ω (V_GS= -2.5 V)

V_GS(TO)≥ 0.4 V

GENERAL DESCRIPTION

PINNING

SOT96-1

P-channel, enhancement mode,

logic level, field-effect power

transistor. This device has low

threshold voltage and extremely

fast switching making it ideal for

battery powered applications and

high speed digital interfacing.

DESCRIPTION

1,2,3 source

gate

5,6,7,8 drain

pin 1 index

The PHK04P02T is supplied in the

SOT96-1 (SO8) surface mounting

package.

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V_DS

V_DGR

V_GS

I_D

Drain-source voltage

-16

± 8

-4.66

-1.87

-26.4

5.0

Drain-gate voltage

Gate-source voltage

Drain current (DC)

R_GS= 20 kΩ

T_sp= 25 ˚C

T_sp= 100 ˚C

T_sp= 25 ˚C

T_sp= 100 ˚C

I_DM

P_tot

Drain current (pulse peak value)

Total power dissipation

˚C

2.0

150

T_stg, T_j

Storage & operating temperature

- 55

THERMAL RESISTANCES

SYMBOL PARAMETER

CONDITIONS

TYP.

MAX.

UNIT

R_{th j-sp}

Thermal resistance junction to mounted on metal clad substrate.

solder point

K/W

May 2002

Rev 1.000

Philips Semiconductors

Product specification

P-channel enhancement mode

MOS transistor

PHK04P02T

ELECTRICAL CHARACTERISTICS

T_j= 25˚C unless otherwise specified

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

V_(BR)DSS

V_GS(TO)

R_DS(ON)

Drain-source breakdown

voltage

Gate threshold voltage

V_GS= 0 V; I_D= -10 µA

V_DS= V_GS; I_D= -1 mA

V_GS= -4.5 V; I_D= -1 A

-16

-0.4

-0.1

-0.6

117

140

175

4.5

mΩ

T_j= 150˚C

Drain-source on-state

resistance

120

150

180

230

V_GS= -2.5 V; I_D= -1 A

V_GS= -1.8 V; I_D= -0.5 A

V_GS= -2.5 V; I_D= -1 A; T_j= 150˚C

V_DS= -12.8 V; I_D= -1 A

g_fs

Forward transconductance

1.5

I_GSS

I_DSS

Gate source leakage current V_GS= ±8 V; V_DS= 0 V

±10 ±100

µA

Zero gate voltage drain

current

V_DS= -12.8 V; V_GS= 0 V;

-50

-13

-100

T_j= 150˚C

Q_g(tot)

Q_gs

Q_gd

Total gate charge

Gate-source charge

Gate-drain (Miller) charge

I_D= -1 A; V_DD= -10 V; V_GS= -4.5 V

7.2

1.7

1.83

t_{d on}

t_r

t_{d off}

t_f

Turn-on delay time

Turn-on rise time

Turn-off delay time

Turn-off fall time

V_DD= -10 V; I_D= -1 A;

V_GS= -8 V; R_G= 6 Ω

Resistive load

4.5

C_iss

C_oss

C_rss

Input capacitance

Output capacitance

Feedback capacitance

V_GS= 0 V; V_DS= -12.8 V; f = 1 MHz

528

200

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

T_j= 25˚C unless otherwise specified

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

I_DR

Continuous reverse drain

current

T_sp= 25 ˚C, t ≤ 5 s

-4.66

I_DRM

V_SD

Pulsed reverse drain current

Diode forward voltage

-26

-1.3

I_F= -0.62 A; V_GS= 0 V

-0.62

t_rr

Q_rr

Reverse recovery time

Reverse recovery charge

I_F= -0.5 A; -dI_F/dt = 100 A/µs;

V_GS= 0 V; V_R= -12.8 V

May 2002

Rev 1.000

Philips Semiconductors

Product specification

P-channel enhancement mode

MOS transistor

PHK04P02T

Zth j-sp (K/W)

D = 0.5

Normalised Power Derating, Ptot (%)

100

D = 0.2

D = 0.1

D = 0.05

D = 0.02

0.1

D = tp/T

single pulse

0.01

1E-02 1E-01

0.001

1E-03

1E-02

1E-01

1E+00

1E+01

1E-06

1E-04

1E-05

Pulse width, tp (s)

100

120

140

160

Ambient temperature, Ta (C)

Fig.4. Transient thermal impedance. Z_{th j-sp}= f(t);

parameter D = t_p/T;;

Fig.1. Normalised power dissipation.

PD% = 100 P_D/P_{D 25 ˚C}= f(T_a)

Drain current, ID (A)

-5

-4.5 V

Tj = 25 C

-1.8 V

Normalised Current Derating, ID (%)

-4.5

-4

120

100

-2.5 V

-3.5

-3

-1.3 V

-1.2 V

-1.1 V

-2.5

-2

-1.5

-1

-1 V

-0.9 V

VGS = -0.8 V

-0.5

-1

-1.5

-2

100

120

140

160

Drain-Source Voltage, VDS (V)

Ambient temperature, Ta (C)

Fig.5. Typical output characteristics, T_j= 25 ˚C.

Fig.2. Normalised continuous drain current.

I_D= f(V_DS); parameter V_GS

ID% = 100 I_D/I_{D 25 ˚C}= f(T_a); conditions: V_GS≤ -10 V

Drain-Source On Resistance, RDS(on) (Ohms)

0.7

0.6

0.5

0.4

0.3

0.2

0.1

Peak Pulsed Drain Current, I

(A)

-1V

-1.2 V

-1.1 V

Tj = 25 C

-0.8 V

-0.9 V

-1.3 V

100

= 1ms

= V / I

10 ms

DS(on)

100 ms

-1.8 V

-2.5 V

0.1

0.01

VGS = -4.5V

-0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 -4.5 -5

Drain Current, ID (A)

0.1

Drain-Source Voltage, V

100

(V)

Fig.6. Typical on-state resistance, T_j= 25 ˚C.

Fig.3. Safe operating area. T_sp= 25 ˚C;

I_D& I_DM= f(V_DS); I_DMsingle pulse; parameter t_p.

R_DS(ON)= f(I_D); parameter V_GS

May 2002

Rev 1.000

Philips Semiconductors

Product specification

P-channel enhancement mode

MOS transistor

PHK04P02T

Drain Current, ID (A)

-5

VDS > ID X RDS(on)

Threshold Voltage, VGS(to), (V)

typical

0.7

0.6

0.5

0.4

0.3

0.2

0.1

Tj = 25

-4

-3

-2

-1

150

minimum

100

125

150

-0.5

-1

-1.5

-2

Junction Temperature, Tj (C)

Gate-Source Voltage, VGS (V)

Fig.7. Typical transfer characteristics; I_D= f(V_GS)

Fig.10. Gate threshold voltage.

_GS(TO)= f(T_j); conditions: I_D= 1 mA; V_DS= V_GS

Drain Current, ID (A)

Transconductance, gfs (S)

1E-01

1E-02

1E-03

1E-04

1E-05

1E-06

1E-07

VDS = -5 V

Tj = 25 C

VDS > ID X RDS(on)

Tj = 25 C

150 C

-0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 -2.2 -2.4 -2.6

Drain Current, ID (A)

-1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1

Gate-Source Voltage, VGS (V)

Fig.11. Sub-threshold drain current.

I_D= f(V_GS); conditions: T_j= 25 ˚C

Fig.8. Typical transconductance, T_j= 25 ˚C.

g_fs= f(I_D)

Capacitances, Ciss, Coss, Crss (pF)

Normalised Drain-Source On Resistance

1000

100

1.6

1.4

1.2

1.0

0.8

0.6

@ T

DS(on)

Ciss

-2.5 V

RDS(on) @ 25

= -4.5 V

Coss

-1.8 V

Crss

100

125

150

-0.1

-1.0

-10.0

-100.0

Junction Temperature, Tj (C)

Drain-Source Voltage, VDS (V)

Fig.9. Normalised drain-source on-state resistance.

R_DS(ON)/R_{DS(ON)25 ˚C}= f(T_j)

Fig.12. Typical capacitances, C_iss, C_oss, C_rss.

C = f(V_DS); conditions: V_GS= 0 V; f = 1 MHz

May 2002

Rev 1.000

Philips Semiconductors

Product specification

P-channel enhancement mode

MOS transistor

PHK04P02T

Source-Drain Diode Current, IF (A)

Gate-source voltage, VGS (V)

-5

= 10 V

= 10 Ohms

-4

-3

-2

-1

T = 25 C

150 C

Tj = 25

0.2

0.4

0.6

0.8

1.2

1.4

Drain-Source Voltage, VSDS (V)

Gate charge, (nC)

Fig.14. Typical reverse diode current.

I_F= f(V_SDS); conditions: V_GS= 0 V; parameter T_j

Fig.13. Typical turn-on gate-charge characteristics.

V_GS= f(Q_G)

May 2002

Rev 1.000

Philips Semiconductors

Product specification

P-channel enhancement mode

MOS transistor

PHK04P02T

MECHANICAL DATA

SO8: plastic small outline package; 8 leads; body width 3.9 mm

SOT96-1

)

pin 1 index

detail X

2.5

5 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

(1)

(2)

UNIT

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

5.0

4.8

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

1.27

0.050

1.05

0.041

0.25

0.01

0.25

0.1

1.75

0.25

0.01

8^o

0^o

0.010 0.057

0.004 0.049

0.019 0.0100 0.20

0.014 0.0075 0.19

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.024

0.028

0.012

inches 0.069

0.01 0.004

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

EIAJ

95-02-04

97-05-22

SOT96-1

076E03S

MS-012AA

Fig.15. SOT96 surface mounting package.

Notes

1. This product is supplied in anti-static packaging. The gate-source input must be protected against static

discharge during transport or handling.

2. Refer to Integrated Circuit Packages, Data Handbook IC26.

3. Epoxy meets UL94 V0 at 1/8".

May 2002

Rev 1.000

Philips Semiconductors

Product specification

P-channel enhancement mode

MOS transistor

PHK04P02T

DEFINITIONS

DATA SHEET STATUS

DATA SHEET

STATUS¹

PRODUCT

STATUS²

DEFINITIONS

Objective data

Development

This data sheet contains data from the objective specification for

product development. Philips Semiconductors reserves the right to

change the specification in any manner without notice

Preliminary data

Qualification

This data sheet contains data from the preliminary specification.

Supplementary data will be published at a later date. Philips

Semiconductors reserves the right to change the specification without

notice, in order to improve the design and supply the best possible

product

Product data

Production

This data sheet contains data from the product specification. Philips

Semiconductors reserves the right to make changes at any time in

order to improve the design, manufacturing and supply. Changes will

be communicated according to the Customer Product/Process

Change Notification (CPCN) procedure SNW-SQ-650A

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and

operation of the device at these or at any other conditions above those given in the Characteristics sections of

this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Philips Electronics N.V. 2002

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the

The information presented in this document does not form part of any quotation or contract, it is believed to be

accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under patent or other

industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these

products can be reasonably expected to result in personal injury. Philips customers using or selling these products

for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting

from such improper use or sale.

1 Please consult the most recently issued datasheet before initiating or completing a design.

2 The product status of the device(s) described in this datasheet may have changed since this datasheet was

published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

May 2002

Rev 1.000

PHK04P02T [NXP]

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