PHP50N03LT [NXP]
N-channel TrenchMOS transistor Logic level FET; N沟道晶体管的TrenchMOS逻辑电平FET
| 型号： | PHP50N03LT |
| 厂家： | 
NXP |
| 描述： | N-channel TrenchMOS transistor Logic level FET |
| 文件： | 总11页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
Logic level FET
PHP50N03LT, PHB50N03LT
PHD50N03LT
FEATURES
SYMBOL
QUICK REFERENCE DATA
d
• ’Trench’ technology
• Very low on-state resistance
• Fast switching
• High thermal cycling performance
• Low thermal resistance
• Logic level compatible
VDSS = 25 V
ID = 48 A
R
DS(ON) ≤ 16 mΩ (VGS = 10 V)
g
RDS(ON) ≤ 21 mΩ (VGS = 5 V)
s
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology.
Applications:-
• High frequency computer motherboard d.c. to d.c. converters
• High current switching
The PHP50N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB50N03LT is supplied in the SOT404 (D2PAK) surface mounting package.
The PHD50N03LT is supplied in the SOT428 (DPAK)surface mounting package.
PINNING
SOT78 (TO220AB)
SOT404 (D2PAK)
SOT428 (DPAK)
tab
tab
PIN
1
DESCRIPTION
tab
gate
2
drain 1
source
2
2
3
1 2 3
1
3
1
3
tab drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDSS
VDGR
VGS
Drain-source voltage
Tj = 25 ˚C to 175˚C
Tj = 25 ˚C to 175˚C; RGS = 20 kΩ
-
-
-
-
25
25
± 15
V
V
V
V
Drain-gate voltage
Gate-source voltage (DC)
Gate-source voltage (pulse
peak value)
VGSM
Tj ≤ 150˚C
± 20
ID
Drain current (DC)
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
-
-
-
48
34
180
A
A
A
IDM
Drain current (pulse peak
value)
Ptot
Tj, Tstg
Total power dissipation
Operating junction and
storage temperature
Tmb = 25 ˚C
-
86
175
W
˚C
- 55
1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.
October 1999
1
Rev 1.800
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
Logic level FET
PHP50N03LT, PHB50N03LT
PHD50N03LT
THERMAL RESISTANCES
SYMBOL PARAMETER
Rth j-mb Thermal resistance junction
CONDITIONS
MIN. TYP. MAX. UNIT
-
-
1.75 K/W
to mounting base
Thermal resistance junction SOT78 package, in free air
to ambient
Rth j-a
-
-
60
50
-
-
K/W
K/W
SOT404 and SOT428 packages, pcb
mounted, minimum footprint
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
60
UNIT
WDSS
Drain-source non-repetitive ID = 25 A; VDD ≤ 15 V;
unclamped inductive turn-off VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C
energy
-
mJ
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
V(BR)DSS Drain-source breakdown
CONDITIONS
MIN. TYP. MAX. UNIT
VGS = 0 V; ID = 0.25 mA;
25
-
-
-
-
V
V
voltage
Tj = -55˚C
22
VGS(TO)
Gate threshold voltage
VDS = VGS; ID = 1 mA
1
0.5
-
-
-
-
-
8
-
-
1.5
-
-
13
15
18
-
27
0.05
-
2
-
V
V
V
Tj = 175˚C
Tj = -55˚C
2.3
16
18
21
39
-
10
500
100
RDS(ON)
Drain-source on-state
resistance
VGS = 10 V; ID = 25 A
VGS = 10 V; ID = 25 A (SOT428 package)
VGS = 5 V; ID = 25 A
VGS = 5 V; ID = 25 A; Tj = 175˚C
VDS = 25 V; ID = 25 A
VDS = 25 V; VGS = 0 V;
Tj = 175˚C
mΩ
mΩ
mΩ
mΩ
S
µA
µA
nA
gfs
IDSS
Forward transconductance
Zero gate voltage drain
current
IGSS
Gate source leakage current VGS = ±5 V; VDS = 0 V
-
10
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 50 A; VDD = 15 V; VGS = 5 V
-
-
-
17
7.6
11
-
-
-
nC
nC
nC
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 15 V; ID = 25 A;
VGS = 10 V; RG = 5 Ω
Resistive load
-
-
-
-
6.4
62
50
30
12
75
75
45
ns
ns
ns
ns
Ld
Ld
Internal drain inductance
Internal drain inductance
Measured tab to centre of die
Measured from drain lead to centre of die
(SOT78 package only)
-
-
3.5
4.5
-
-
nH
nH
Ls
Internal source inductance
Measured from source lead to source
bond pad
-
7.5
-
nH
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
-
-
1050
330
220
-
-
-
pF
pF
pF
October 1999
2
Rev 1.800
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
Logic level FET
PHP50N03LT, PHB50N03LT
PHD50N03LT
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
IS
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
-
-
-
-
48
A
A
V
ISM
VSD
180
IF = 25 A; VGS = 0 V
IF = 40 A; VGS = 0 V
-
-
0.95
1.05
1.2
-
trr
Qrr
Reverse recovery time
Reverse recovery charge
IF = 20 A; -dIF/dt = 100 A/µs;
VGS = 0 V; VR = 25 V
-
-
100
0.13
-
-
ns
µC
Peak Pulsed Drain Current, IDM (A)
Normalised Power Derating, PD (%)
1000
100
10
100
90
80
70
60
50
40
30
20
10
0
RDS(on) = VDS/ ID
tp = 10 us
100 us
1 ms
10 ms
D.C.
100 ms
1
0
25
50
75
100
125
150
175
1
10
Drain-Source Voltage, VDS (V)
100
Mounting Base temperature, Tmb (C)
Fig.1. Normalised power dissipation.
PD% = 100 PD/PD 25 ˚C = f(Tmb)
Fig.3. Safe operating area
ID & IDM = f(VDS); IDM single pulse; parameter tp
Transient thermal impedance, Zth j-mb (K/W)
10
Normalised Current Derating, ID (%)
100
90
80
70
60
50
40
30
20
10
0
D = 0.5
1
0.2
0.1
P
0.05
0.02
D = tp/T
D
0.1
tp
single pulse
T
0.01
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
0
25
50
75
100
125
150
175
Pulse width, tp (s)
Mounting Base temperature, Tmb (C)
Fig.2. Normalised continuous drain current.
ID% = 100 ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
October 1999
3
Rev 1.800
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
Logic level FET
PHP50N03LT, PHB50N03LT
PHD50N03LT
Drain Current, ID (A)
50
Transconductance, gfs (S)
30
25
20
15
10
5
VGS = 10 V
5 V
Tj = 25 C
VDS > ID X RDS(ON)
4.5 V
Tj = 25 C
175 C
45
40
35
30
25
20
15
10
5
3.2 V
3 V
2.8 V
2.6 V
2.4 V
2.2 V
0
0
0
5
10
15
20
25
30
35
40
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Drain-Source Voltage, VDS (V)
Drain current, ID (A)
Fig.5. Typical output characteristics
ID = f(VDS); parameter VGS
Fig.8. Typical transconductance
gfs = f(ID)
Normalised On-state Resistance
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
Drain-Source On Resistance, RDS(on) (Ohms)
0.1
2.6 V
2.2 V
Tj = 25 C
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
2.4 V
2.8V
3 V
3.2 V
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
5 V
VGS =4.5 V
10V
45
-60
-40
-20
0
20
40
60
80
100 120 140 160 180
0
5
10
15
20
25
30
35
40
50
Drain Current, ID (A)
Junction temperature, Tj (C)
Fig.6. Typical on-state resistance
RDS(ON) = f(ID); parameter VGS
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj)
Threshold Voltage, VGS(TO) (V)
2.25
Drain current, ID (A)
VDS > ID X RDS(ON)
40
35
30
25
20
15
10
5
2
maximum
1.75
1.5
typical
1.25
1
minimum
0.75
0.5
0.25
0
175 C
Tj = 25 C
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-60
-40
-20
0
20
40
60
80
100 120 140 160 180
Gate-source voltage, VGS (V)
Junction Temperature, Tj (C)
Fig.7. Typical transfer characteristics.
ID = f(VGS)
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
October 1999
4
Rev 1.800
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
Logic level FET
PHP50N03LT, PHB50N03LT
PHD50N03LT
Drain current, ID (A)
1.0E-01
Gate-source voltage, VGS (V)
VDS = 5 V
15
14
13
12
11
10
9
ID = 50A
1.0E-02
Tj = 25 C
VDD = 15 V
1.0E-03
8
7
minimum
typical
maximum
1.0E-04
1.0E-05
1.0E-06
6
5
4
3
2
1
0
0
5
10
15
20
25
30
35
40
45
50
0
0.5
1
1.5
2
2.5
3
Gate charge, QG (nC)
Gate-source voltage, VGS (V)
Fig.11. Sub-threshold drain current.
ID = f(VGS); VDS = VGS
Fig.13. Typical turn-on gate-charge characteristics.
GS = f(QG)
V
Source-Drain Diode Current, IF (A)
VGS = 0 V
50
45
40
35
30
25
20
15
10
5
Capacitances, Ciss, Coss, Crss (pF)
10000
1000
100
175 C
Ciss
Tj = 25 C
Coss
Crss
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
1.1 1.2 1.3 1.4 1.5
0.1
1
10
100
Source-Drain Voltage, VSDS (V)
Drain-Source Voltage, VDS (V)
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); VGS = 0 V; f = 1 MHz
Fig.14. Typical reverse diode current.
IF = f(VSDS
)
October 1999
5
Rev 1.800
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
Logic level FET
PHP50N03LT, PHB50N03LT
PHD50N03LT
MECHANICAL DATA
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220
SOT78
E
P
A
A
1
q
D
1
D
(1)
L
L
2
1
Q
b
1
L
1
2
3
b
c
e
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
L
2
b
e
A
b
D
E
L
D
1
L
1
A
1
c
UNIT
P
q
Q
1
max.
4.5
4.1
1.39
1.27
0.9
0.7
1.3
1.0
0.7
0.4
15.8
15.2
6.4
5.9
10.3
9.7
15.0
13.5
3.30
2.79
3.8
3.6
3.0
2.7
2.6
2.2
mm
3.0
2.54
Note
1. Terminals in this zone are not tinned.
REFERENCES
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
JEDEC
EIAJ
97-06-11
SOT78
TO-220
Fig.15. SOT78 (TO220AB); pin 2 connected to mounting base (Net mass:2g)
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to mounting instructions for SOT78 (TO220AB) package.
3. Epoxy meets UL94 V0 at 1/8".
October 1999
6
Rev 1.800
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
Logic level FET
PHP50N03LT, PHB50N03LT
PHD50N03LT
MECHANICAL DATA
2
Plastic single-ended surface mounted package (Philips version of D -PAK); 3 leads
(one lead cropped)
SOT404
A
A
E
1
mounting
base
D
1
D
H
D
2
L
p
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
D
E
A
A
b
UNIT
c
D
e
L
H
Q
1
1
p
D
max.
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
1.60
1.20
10.30
9.70
2.90 15.40 2.60
2.10 14.80 2.20
mm
11
2.54
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
98-12-14
99-06-25
SOT404
Fig.16. SOT404 surface mounting package. Centre pin connected to mounting base.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.
3. Epoxy meets UL94 V0 at 1/8".
October 1999
7
Rev 1.800
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
Logic level FET
PHP50N03LT, PHB50N03LT
PHD50N03LT
MOUNTING INSTRUCTIONS
Dimensions in mm
11.5
9.0
17.5
2.0
3.8
5.08
Fig.17. SOT404 : soldering pattern for surface mounting.
October 1999
8
Rev 1.800
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
Logic level FET
PHP50N03LT, PHB50N03LT
PHD50N03LT
MECHANICAL DATA
Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads
(one lead cropped)
SOT428
seating plane
A
y
A
2
E
A
A
1
b
D
1
2
mounting
base
E
1
D
H
E
L
2
2
L
1
L
1
3
b
1
b
w
M
A
c
e
e
1
0
10
20 mm
scale
DIMENSIONS (mm are the original dimensions)
b
E
H
E
max.
D
L
y
1
min.
A
max.
D
max.
E
max.
1
1
(1)
1
A
b
2
A
UNIT
mm
b
c
e
e
1
L
L
w
2
1
2
max.
max.
min.
max.
0.65 0.89
0.45 0.71
0.7
0.5
2.38
2.22
0.89 1.1
0.71 0.9
5.36
5.26
0.4 6.22
0.2 5.98
6.73
6.47
2.95
2.55
10.4
9.6
4.81
4.45
4.57
0.2
0.2
4.0 2.285
0.5
Note
1. Measured from heatsink back to lead.
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
SOT428
98-04-07
Fig.18. SOT428 surface mounting package. Centre pin connected to mounting base.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.
3. Epoxy meets UL94 V0 at 1/8".
October 1999
9
Rev 1.800
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
Logic level FET
PHP50N03LT, PHB50N03LT
PHD50N03LT
MOUNTING INSTRUCTIONS
Dimensions in mm
7.0
7.0
2.15
2.5
1.5
4.57
Fig.19. SOT428 : soldering pattern for surface mounting.
October 1999
10
Rev 1.800
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
Logic level FET
PHP50N03LT, PHB50N03LT
PHD50N03LT
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
October 1999
11
Rev 1.800
相关型号：
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NXP
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