PSMN7R0-30YL_10_技术文档

PSMN7R0-30YL

N-channel TrenchMOS logic level FET

Rev. 03 — 4 January 2010

Product data sheet

1. Product profile

1.1 General description

Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic

package using TrenchMOS technology. This product is designed and qualified for use in

industrial and communications applications.

1.2 Features and benefits

High efficiency due to low switching

Suitable for logic level gate drive

and conduction losses

sources

1.3 Applications

Class-D amplifiers

DC-to-DC converter

Motor control

Server power supplies

1.4 Quick reference data

Table 1.

Quick reference

Symbol Parameter

Conditions

drain-source voltage T_j≥ 25 °C; T_j≤ 175 °C

Min

Typ

Max Unit

V_DS

I_D

-

30

76

V

A

drain current

T_mb= 25 °C; V_GS= 10 V;

see Figure 1

P_tot

total power

dissipation

T_mb= 25 °C; see Figure 2

-

51

W

Dynamic characteristics

Q_GD

gate-drain charge

total gate charge

V_GS= 4.5 V; I_D= 10 A;

V_DS= 12 V; see Figure 14 and 15

-

2.9

10

-

nC

Q_G(tot)

Static characteristics

R_DSon

drain-source

V_GS= 10 V; I_D= 15 A; T_j= 25 °C

-

4.92

7

mΩ

on-state resistance

PSMN7R0-30YL

NXP Semiconductors

N-channel TrenchMOS logic level FET

2. Pinning information

Table 2.

Pinning information

1

Symbol Description

Simplified outline

Graphic symbol

S

G

D

source

gate

mb

D

2

3

G

4

mbb076

S

mb

mounting base; connected to

drain

1

2 3 4

SOT669 (LFPAK)

3. Ordering information

Table 3.

Ordering information

Type number

Package

Name

Description

plastic single-ended surface-mounted package (LFPAK); 4 leads

Version

PSMN7R0-30YL

LFPAK

SOT669

4. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DS

Parameter

Conditions

Min

Max

30

Unit

drain-source voltage

drain-gate voltage

gate-source voltage

drain current

T_j≥ 25 °C; T_j≤ 175 °C

T_j≥ 25 °C; T_j≤ 175 °C; R_GS= 20 kΩ

-

V

V_DGR

V_GS

-

30

V

-20

20

V

I_D

V_GS= 10 V; T_mb= 100 °C; see Figure 1

V_GS= 10 V; T_mb= 25 °C; see Figure 1

t_p≤ 10 µs; pulsed; T_mb= 25 °C; see Figure 3

-

53

A

-

76

A

I_DM

P_tot

T_stg

T_j

peak drain current

-

260

51

A

total power dissipation T_mb= 25 °C; see Figure 2

storage temperature

-

W

°C

-55

175

junction temperature

Source-drain diode

I_S

source current

peak source current

T_mb= 25 °C

-

65

A

I_SM

t_p≤ 10 µs; pulsed; T_mb= 25 °C

260

Avalanche ruggedness

E_DS(AL)S

non-repetitive

V_GS= 10 V; T_j(init)= 25 °C; I_D= 65 A; V_sup≤ 30 V;

-

21

mJ

drain-source avalanche R_GS= 50 Ω; unclamped

energy

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Product data sheet

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N-channel TrenchMOS logic level FET

003aac720

03aa16

120

100

I_D

(A)

P

der

(%)

80

60

40

20

0

40

0

50

100

150

200

0

50

100

150

200

T_mb(°C)

T

mb

(°C)

Fig 2. Normalized total power dissipation as a

function of mounting base temperature

Fig 1. Continuous drain current as a function of

mounting base temperature

003aac732

10³

I_D

Limit R_DSon= V_DS/ I_D

(A)

10²

10

s

μ

100

s

μ

10

1

DC

1 ms

10 ms

100 ms

10^-1

1

10

10²

V_DS(V)

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage

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Product data sheet

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N-channel TrenchMOS logic level FET

5. Thermal characteristics

Table 5.

Symbol

R_th(j-mb)

Thermal characteristics

Parameter

Conditions

Min

Typ

Max

Unit

thermal resistance from junction to mounting see Figure 4

base

-

1.4

2.45

K/W

003aac721

10

Z_th(j-mb)

(K/W)

δ = 0.5

1

10^-1

10^-2

0.2

0.1

0.05

t_p

δ =

P

0.02

T

t

t_p

single shot

T

10^-6

10^-5

10^-4

10^-3

10^-2

10^-1

t_p(s)

1

Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration

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Product data sheet

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N-channel TrenchMOS logic level FET

6. Characteristics

Table 6.

Symbol

Characteristics

Parameter

Conditions

Min

Typ

Max

Unit

Static characteristics

V_(BR)DSS

drain-source

breakdown voltage

I_D= 20 A; V_GS= 0 V; T_j= 25 °C; t_av= 100 ns

I_D= 250 µA; V_GS= 0 V; T_j= 25 °C

35

30

27

1.3

-

V

-

I_D= 250 µA; V_GS= 0 V; T_j= -55 °C

-

V_GS(th)

gate-source threshold I_D= 1 mA; V_DS= V_GS; T_j= 25 °C; see Figure 11

1.7

2.15

voltage

and 12

I_D= 1 mA; V_DS= V_GS; T_j= 150 °C; see Figure 12 0.65

-

V

I_D= 1 mA; V_DS= V_GS; T_j= -55 °C; see Figure 12

V_DS= 30 V; V_GS= 0 V; T_j= 25 °C

V_DS= 30 V; V_GS= 0 V; T_j= 150 °C

V_GS= 16 V; V_DS= 0 V; T_j= 25 °C

V_GS= -16 V; V_DS= 0 V; T_j= 25 °C

V_GS= 4.5 V; I_D= 15 A; T_j= 25 °C

-

2.45

1

V

I_DSS

drain leakage current

gate leakage current

-

µA

nA

mΩ

-

100

9.1

12.2

I_GSS

-

R_DSon

drain-source on-state

resistance

6.97

-

V_GS= 10 V; I_D= 15 A; T_j= 150 °C;

see Figure 13

V

_GS= 10 V; I_D= 15 A; T_j= 25 °C

-

4.92

0.6

7

mΩ

R_G

gate resistance

f = 1 MHz

1.5

Ω

Dynamic characteristics

Q_G(tot)

total gate charge

I_D= 10 A; V_DS= 12 V; V_GS= 4.5 V;

see Figure 14 and 15

-

10

-

nC

I_D= 0 A; V_DS= 0 V; V_GS= 10 V

-

20

22

-

nC

I_D= 10 A; V_DS= 12 V; V_GS= 10 V; see Figure 14

and 15

Q_GS

gate-source charge

I_D= 10 A; V_DS= 12 V; V_GS= 4.5 V;

see Figure 14 and 15

-

3.7

2.1

-

nC

Q_GS(th)

pre-threshold

gate-source charge

Q_GS(th-pl)

post-threshold

-

1.6

-

nC

gate-source charge

Q_GD

gate-drain charge

-

2.9

2.6

-

nC

V

V_GS(pl)

gate-source plateau

voltage

V_DS= 12 V; see Figure 14 and 15

C_iss

C_oss

C_rss

input capacitance

output capacitance

V_DS= 12 V; V_GS= 0 V; f = 1 MHz; T_j= 25 °C;

see Figure 16

-

1270

255

-

pF

reverse transfer

capacitance

145

t_d(on)

t_r

t_d(off)

t_f

turn-on delay time

rise time

V_DS= 12 V; R_L= 0.5 Ω; V_GS= 4.5 V;

R_G(ext)= 4.7 Ω

-

24

39

30

11

-

ns

turn-off delay time

fall time

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Table 6.

Symbol

Characteristics …continued

Parameter

Conditions

Min

Typ

Max

Unit

Source-drain diode

V_SD

t_rr

source-drain voltage

I_S= 25 A; V_GS= 0 V; T_j= 25 °C; see Figure 17

-

0.88

30

1.2

V

reverse recovery time

recovered charge

I_S= 20 A; dI_S/dt = -100 A/µs; V_GS= 0 V;

V_DS= 20 V

-

ns

nC

Q_r

22

[1] Tested to JEDEC standards where applicable.

003aac729

003aac728

80

60

I_D

g_fs

(S)

(A)

60

40

20

0

50

40

30

T_j= 150 °C

25 °C

0

1

2

3

4

0

10

20

30

40

V_GS(V)

I_D(A)

Fig 6. Forward transconductance as a function of

drain current; typical values

Fig 5. Transfer characteristics: drain current as a

function of gate-source voltage; typical values

003aac727

003aac726

100

14

10

I_D

R_DSon

(A)

(mΩ)

V_GS(V) = 4.5

80

12

10

8

60

3.2

3

40

2.8

6

20

2.6

2.4

2.2

4

0

2

4

6

8

10

0

2

4

6

8

10

V_GS(V)

V

_DS(V)

Fig 7. Drain-source on-state resistance as a function

of gate-source voltage; typical values

Fig 8. Output characteristics: drain current as a

function of drain-source voltage; typical values

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Product data sheet

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NXP Semiconductors

N-channel TrenchMOS logic level FET

003aac724

003aac722

2500

C

(pF)

16

R_DSon

(mΩ)

14

3.2

C_iss

2000

12

10

8

C_rss

1500

1000

500

0

V_GS(V) = 4.5

6

10

4

0

2

4

6

8

10

V_GS(V)

0

20

40

60

80

100

I_D(A)

Fig 10. Drain-source on-state resistance as a function

of drain current; typical values

Fig 9. Input and reverse transfer capacitances as a

function of gate-source voltage; typical values

003aab271

003aac337

10^-1

3

I_D

(A)

10^-2

V_GS(th)

(V)

max

min

typ

max

2

10^-3

10^-4

10^-5

10^-6

typ

min

1

0

-60

0

1

2

V

_GS(V)

3

0

60

120

180

T_j(°C)

Fig 11. Sub-threshold drain current as a function of

gate-source voltage

Fig 12. Gate-source threshold voltage as a function of

junction temperature

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Product data sheet

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N-channel TrenchMOS logic level FET

03aa27

2

V

DS

a

I

D

1.5

V

GS(pl)

V

GS(th)

1

V

GS

Q

GS1

Q

GS2

0.5

0

Q

GS

Q

GD

Q

G(tot)

003aaa508

−60

0

60

120

180

T ( C)

°

j

Fig 13. Normalized drain-source on-state resistance

factor as a function of junction temperature

Fig 14. Gate charge waveform definitions

003aac725

003aac723

10

1600

V_GS

(V)

C_iss

C

(pF)

8

V_DS= 12 (V)

1200

800

400

0

C_oss

6

V_DS= 19 (V)

4

2

0

C_rss

0

5

10

15

20

25

_G(nC)

10^-1

1

10

10²

V_DS(V)

Q

Fig 15. Gate-source voltage as a function of gate

charge; typical values

Fig 16. Input, output and reverse transfer capacitances

as a function of drain-source voltage; typical

values

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Product data sheet

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N-channel TrenchMOS logic level FET

003aac730

80

I_S

(A)

60

40

20

0

T_j= 150 °C

25 °C

0.0

0.2

0.4

0.6

0.8

1.0

_SD(V)

V

Fig 17. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values

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N-channel TrenchMOS logic level FET

7. Package outline

Plastic single-ended surface-mounted package (LFPAK); 4 leads

SOT669

A

2

E

A

C

c

E

1

b

2

b

3

L

1

mounting

base

b

4

D

1

D

H

L

2

1

2

3

4

X

e

w

M

c

A

b

1/2 e

A

(A )

3

C

A

1

θ

L

detail X

y

C

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

D

(1)

D

(1)

1

A

H

L

2

w

y

θ

UNIT

A

b

c

E

1

e

1

2

3

1

2

3

4

2

max

1.20 0.15 1.10

1.01 0.00 0.95

0.50 4.41 2.2 0.9 0.25 0.30 4.10

0.35 3.62 2.0 0.7 0.19 0.24 3.80

5.0 3.3

4.8 3.1

6.2 0.85 1.3 1.3

5.8 0.40 0.8 0.8

8°

0°

mm

0.25

4.20

1.27

0.25 0.1

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

04-10-13

06-03-16

SOT669

MO-235

Fig 18. Package outline SOT669 (LFPAK)

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N-channel TrenchMOS logic level FET

8. Revision history

Table 7.

Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

PSMN7R0-30YL_3

Modifications:

20100104

Product data sheet

-

PSMN7R0-30YL_2

• Various changes to content.

PSMN7R0-30YL_2

PSMN7R0-30YL_1

20090105

Product data sheet

-

PSMN7R0-30YL_1

-

20081015

Preliminary data sheet

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N-channel TrenchMOS logic level FET

9. Legal information

9.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term 'short data sheet' is explained in section "Definitions".

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product

status information is available on the Internet at URLhttp://www.nxp.com.

Suitability for use— NXP Semiconductors products are not designed,

9.2 Definitions

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft— The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications— Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Short data sheet— A short data sheet is an extract from a full data sheet with

the same product type number(s) and title. A short data sheet is intended for

quick reference only and should not be relied upon to contain detailed and full

information. For detailed and full information see the relevant full data sheet,

which is available on request via the local NXP Semiconductors sales office.

In case of any inconsistency or conflict with the short data sheet, the full data

sheet shall prevail.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on a weakness or default in the

customer application/use or the application/use of customer’s third party

customer(s) (hereinafter both referred to as “Application”). It is customer’s

sole responsibility to check whether the NXP Semiconductors product is

suitable and fit for the Application planned. Customer has to do all necessary

testing for the Application in order to avoid a default of the Application and the

product. NXP Semiconductors does not accept any liability in this respect.

Product specification— The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

Quick reference data— The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

9.3 Disclaimers

Limiting values— Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Limited warranty and liability— Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale— NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published athttp://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with theTerms and conditions of commercial saleof NXP Semiconductors.

No offer to sell or license— Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Right to make changes— NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

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Export control— This document as well as the item(s) described herein may

be subject to export control regulations. Export might require a prior

authorization from national authorities.

customer uses the product for automotive applications beyond NXP

Semiconductors’ specifications such use shall be solely at customer’s own

risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,

damages or failed product claims resulting from customer design and use of

the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products— Unless the data sheet of an NXP

Semiconductors product expressly states that the product is automotive

qualified, the product is not suitable for automotive use. It is neither qualified

nor tested in accordance with automotive testing or application requirements.

NXP Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications. In

the event that customer uses the product for design-in and use in automotive

applications to automotive specifications and standards, customer (a) shall

use the product without NXP Semiconductors’ warranty of the product for

such automotive applications, use and specifications, and (b) whenever

9.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

TrenchMOS— is a trademark of NXP B.V.

10. Contact information

For more information, please visit:http://www.nxp.com

For sales office addresses, please send an email to:salesaddresses@nxp.com

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N-channel TrenchMOS logic level FET

11. Contents

1

Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.1

1.2

1.3

1.4

General description . . . . . . . . . . . . . . . . . . . . . .1

Features and benefits. . . . . . . . . . . . . . . . . . . . .1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Quick reference data . . . . . . . . . . . . . . . . . . . . .1

2

3

4

5

6

7

8

Pinning information. . . . . . . . . . . . . . . . . . . . . . .2

Ordering information. . . . . . . . . . . . . . . . . . . . . .2

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2

Thermal characteristics . . . . . . . . . . . . . . . . . . .4

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5

Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10

Revision history. . . . . . . . . . . . . . . . . . . . . . . . .11

9

Legal information. . . . . . . . . . . . . . . . . . . . . . . .12

Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .13

9.1

9.2

9.3

9.4

10

Contact information. . . . . . . . . . . . . . . . . . . . . .13

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 4 January 2010

Document identifier: PSMN7R0-30YL_3


型号：	PSMN7R0-30YL_10
厂家：	NXP
描述：	N-channel TrenchMOS logic level FET N沟道的TrenchMOS逻辑电平FET
文件：	总14页 (文件大小：222K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PSMN7R0-30YL_10 [NXP]

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